diff options
author | Johannes Berg <johannes.berg@intel.com> | 2012-10-31 15:49:32 -0400 |
---|---|---|
committer | Johannes Berg <johannes.berg@intel.com> | 2012-11-05 09:59:58 -0500 |
commit | 37c477dc1c6cad4a36049a9a10e4aa3dbf450c0f (patch) | |
tree | a837e648d7789da581d15515a1de04d4612f3d91 /drivers/net/wireless/iwlwifi/dvm/lib.c | |
parent | 0daf7d9605352d4f0c5575a897dd71787ea92b9c (diff) |
iwlwifi: fix flush command
The flush command really flushes queues, not
FIFOs, and the first 32 bits indicate the
queues to flush, not FIFOs. Change the command
accordingly.
Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/dvm/lib.c')
-rw-r--r-- | drivers/net/wireless/iwlwifi/dvm/lib.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/wireless/iwlwifi/dvm/lib.c b/drivers/net/wireless/iwlwifi/dvm/lib.c index bef88c1a2c9b..01ff55faf2ab 100644 --- a/drivers/net/wireless/iwlwifi/dvm/lib.c +++ b/drivers/net/wireless/iwlwifi/dvm/lib.c | |||
@@ -150,21 +150,21 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control) | |||
150 | 150 | ||
151 | memset(&flush_cmd, 0, sizeof(flush_cmd)); | 151 | memset(&flush_cmd, 0, sizeof(flush_cmd)); |
152 | if (flush_control & BIT(IWL_RXON_CTX_BSS)) | 152 | if (flush_control & BIT(IWL_RXON_CTX_BSS)) |
153 | flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK | | 153 | flush_cmd.queue_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK | |
154 | IWL_SCD_BE_MSK | IWL_SCD_BK_MSK | | 154 | IWL_SCD_BE_MSK | IWL_SCD_BK_MSK | |
155 | IWL_SCD_MGMT_MSK; | 155 | IWL_SCD_MGMT_MSK; |
156 | if ((flush_control & BIT(IWL_RXON_CTX_PAN)) && | 156 | if ((flush_control & BIT(IWL_RXON_CTX_PAN)) && |
157 | (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))) | 157 | (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))) |
158 | flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK | | 158 | flush_cmd.queue_control |= IWL_PAN_SCD_VO_MSK | |
159 | IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK | | 159 | IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK | |
160 | IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK | | 160 | IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK | |
161 | IWL_PAN_SCD_MULTICAST_MSK; | 161 | IWL_PAN_SCD_MULTICAST_MSK; |
162 | 162 | ||
163 | if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE) | 163 | if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE) |
164 | flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK; | 164 | flush_cmd.queue_control |= IWL_AGG_TX_QUEUE_MSK; |
165 | 165 | ||
166 | IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n", | 166 | IWL_DEBUG_INFO(priv, "queue control: 0x%x\n", |
167 | flush_cmd.fifo_control); | 167 | flush_cmd.queue_control); |
168 | flush_cmd.flush_control = cpu_to_le16(flush_control); | 168 | flush_cmd.flush_control = cpu_to_le16(flush_control); |
169 | 169 | ||
170 | return iwl_dvm_send_cmd(priv, &cmd); | 170 | return iwl_dvm_send_cmd(priv, &cmd); |