aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/iwlegacy/common.h
diff options
context:
space:
mode:
authorStanislaw Gruszka <sgruszka@redhat.com>2011-08-31 07:23:20 -0400
committerStanislaw Gruszka <sgruszka@redhat.com>2011-11-15 08:20:09 -0500
commite94a4099adb2ec148776975bcd953a01c6bec992 (patch)
tree45264af5a425af0d113c764512fc4da2e01d1906 /drivers/net/wireless/iwlegacy/common.h
parent98613be06e9de8acd20841d2d85b99c39b3b7814 (diff)
iwlegacy: merge common header files
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Diffstat (limited to 'drivers/net/wireless/iwlegacy/common.h')
-rw-r--r--drivers/net/wireless/iwlegacy/common.h2044
1 files changed, 1992 insertions, 52 deletions
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index 5de742c6ce40..e83c6ab39fcf 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1,74 +1,1358 @@
1/****************************************************************************** 1/******************************************************************************
2 * 2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 * redistributing this file, you may do so under either license.
5 * 4 *
6 * GPL LICENSE SUMMARY 5 * This program is free software; you can redistribute it and/or modify it
7 * 6 * under the terms of version 2 of the GNU General Public License as
8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
13 * 8 *
14 * This program is distributed in the hope that it will be useful, but 9 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * General Public License for more details. 12 * more details.
18 * 13 *
19 * You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License along with
20 * along with this program; if not, write to the Free Software 15 * this program; if not, write to the Free Software Foundation, Inc.,
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * USA
23 * 17 *
24 * The full GNU General Public License is included in this distribution 18 * The full GNU General Public License is included in this distribution in the
25 * in the file called LICENSE.GPL. 19 * file called LICENSE.
26 * 20 *
27 * Contact Information: 21 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com> 22 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * 24 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/ 25 *****************************************************************************/
62
63#ifndef __il_core_h__ 26#ifndef __il_core_h__
64#define __il_core_h__ 27#define __il_core_h__
65 28
66/************************ 29#include <linux/interrupt.h>
67 * forward declarations * 30#include <linux/pci.h> /* for struct pci_device_id */
68 ************************/ 31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
34#include <net/ieee80211_radiotap.h>
35
36#include "iwl-eeprom.h"
37#include "csr.h"
38#include "iwl-prph.h"
39#include "iwl-debug.h"
40#include "iwl-led.h"
41#include "iwl-power.h"
42#include "iwl-legacy-rs.h"
43
69struct il_host_cmd; 44struct il_host_cmd;
70struct il_cmd; 45struct il_cmd;
46struct il_tx_queue;
47
48#define RX_QUEUE_SIZE 256
49#define RX_QUEUE_MASK 255
50#define RX_QUEUE_SIZE_LOG 8
51
52/*
53 * RX related structures and functions
54 */
55#define RX_FREE_BUFFERS 64
56#define RX_LOW_WATERMARK 8
57
58#define U32_PAD(n) ((4-(n))&0x3)
59
60/* CT-KILL constants */
61#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
62
63/* Default noise level to report when noise measurement is not available.
64 * This may be because we're:
65 * 1) Not associated (4965, no beacon stats being sent to driver)
66 * 2) Scanning (noise measurement does not apply to associated channel)
67 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
68 * Use default noise value of -127 ... this is below the range of measurable
69 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
70 * Also, -127 works better than 0 when averaging frames with/without
71 * noise info (e.g. averaging might be done in app); measured dBm values are
72 * always negative ... using a negative value as the default keeps all
73 * averages within an s8's (used in some apps) range of negative values. */
74#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
75
76/*
77 * RTS threshold here is total size [2347] minus 4 FCS bytes
78 * Per spec:
79 * a value of 0 means RTS on all data/management packets
80 * a value > max MSDU size means no RTS
81 * else RTS for data/management frames where MPDU is larger
82 * than RTS value.
83 */
84#define DEFAULT_RTS_THRESHOLD 2347U
85#define MIN_RTS_THRESHOLD 0U
86#define MAX_RTS_THRESHOLD 2347U
87#define MAX_MSDU_SIZE 2304U
88#define MAX_MPDU_SIZE 2346U
89#define DEFAULT_BEACON_INTERVAL 100U
90#define DEFAULT_SHORT_RETRY_LIMIT 7U
91#define DEFAULT_LONG_RETRY_LIMIT 4U
92
93struct il_rx_buf {
94 dma_addr_t page_dma;
95 struct page *page;
96 struct list_head list;
97};
98
99#define rxb_addr(r) page_address(r->page)
100
101/* defined below */
102struct il_device_cmd;
103
104struct il_cmd_meta {
105 /* only for SYNC commands, iff the reply skb is wanted */
106 struct il_host_cmd *source;
107 /*
108 * only for ASYNC commands
109 * (which is somewhat stupid -- look at common.c for instance
110 * which duplicates a bunch of code because the callback isn't
111 * invoked for SYNC commands, if it were and its result passed
112 * through it would be simpler...)
113 */
114 void (*callback)(struct il_priv *il,
115 struct il_device_cmd *cmd,
116 struct il_rx_pkt *pkt);
117
118 /* The CMD_SIZE_HUGE flag bit indicates that the command
119 * structure is stored at the end of the shared queue memory. */
120 u32 flags;
121
122 DEFINE_DMA_UNMAP_ADDR(mapping);
123 DEFINE_DMA_UNMAP_LEN(len);
124};
125
126/*
127 * Generic queue structure
128 *
129 * Contains common data for Rx and Tx queues
130 */
131struct il_queue {
132 int n_bd; /* number of BDs in this queue */
133 int write_ptr; /* 1-st empty entry (idx) host_w*/
134 int read_ptr; /* last used entry (idx) host_r*/
135 /* use for monitoring and recovering the stuck queue */
136 dma_addr_t dma_addr; /* physical addr for BD's */
137 int n_win; /* safe queue win */
138 u32 id;
139 int low_mark; /* low watermark, resume queue if free
140 * space more than this */
141 int high_mark; /* high watermark, stop queue if free
142 * space less than this */
143};
144
145/* One for each TFD */
146struct il_tx_info {
147 struct sk_buff *skb;
148 struct il_rxon_context *ctx;
149};
150
151/**
152 * struct il_tx_queue - Tx Queue for DMA
153 * @q: generic Rx/Tx queue descriptor
154 * @bd: base of circular buffer of TFDs
155 * @cmd: array of command/TX buffer pointers
156 * @meta: array of meta data for each command/tx buffer
157 * @dma_addr_cmd: physical address of cmd/tx buffer array
158 * @txb: array of per-TFD driver data
159 * @time_stamp: time (in jiffies) of last read_ptr change
160 * @need_update: indicates need to update read/write idx
161 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
162 *
163 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
164 * descriptors) and required locking structures.
165 */
166#define TFD_TX_CMD_SLOTS 256
167#define TFD_CMD_SLOTS 32
168
169struct il_tx_queue {
170 struct il_queue q;
171 void *tfds;
172 struct il_device_cmd **cmd;
173 struct il_cmd_meta *meta;
174 struct il_tx_info *txb;
175 unsigned long time_stamp;
176 u8 need_update;
177 u8 sched_retry;
178 u8 active;
179 u8 swq_id;
180};
181
182#define IL_NUM_SCAN_RATES (2)
183
184struct il4965_channel_tgd_info {
185 u8 type;
186 s8 max_power;
187};
188
189struct il4965_channel_tgh_info {
190 s64 last_radar_time;
191};
192
193#define IL4965_MAX_RATE (33)
194
195struct il3945_clip_group {
196 /* maximum power level to prevent clipping for each rate, derived by
197 * us from this band's saturation power in EEPROM */
198 const s8 clip_powers[IL_MAX_RATES];
199};
200
201/* current Tx power values to use, one for each rate for each channel.
202 * requested power is limited by:
203 * -- regulatory EEPROM limits for this channel
204 * -- hardware capabilities (clip-powers)
205 * -- spectrum management
206 * -- user preference (e.g. iwconfig)
207 * when requested power is set, base power idx must also be set. */
208struct il3945_channel_power_info {
209 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
210 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
211 s8 base_power_idx; /* gain idx for power at factory temp. */
212 s8 requested_power; /* power (dBm) requested for this chnl/rate */
213};
214
215/* current scan Tx power values to use, one for each scan rate for each
216 * channel. */
217struct il3945_scan_power_info {
218 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
219 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
220 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
221};
222
223/*
224 * One for each channel, holds all channel setup data
225 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
226 * with one another!
227 */
228struct il_channel_info {
229 struct il4965_channel_tgd_info tgd;
230 struct il4965_channel_tgh_info tgh;
231 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
232 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
233 * HT40 channel */
234
235 u8 channel; /* channel number */
236 u8 flags; /* flags copied from EEPROM */
237 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
238 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
239 s8 min_power; /* always 0 */
240 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
241
242 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
243 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
244 enum ieee80211_band band;
245
246 /* HT40 channel info */
247 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
248 u8 ht40_flags; /* flags copied from EEPROM */
249 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
250
251 /* Radio/DSP gain settings for each "normal" data Tx rate.
252 * These include, in addition to RF and DSP gain, a few fields for
253 * remembering/modifying gain settings (idxes). */
254 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
255
256 /* Radio/DSP gain settings for each scan rate, for directed scans. */
257 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
258};
259
260#define IL_TX_FIFO_BK 0 /* shared */
261#define IL_TX_FIFO_BE 1
262#define IL_TX_FIFO_VI 2 /* shared */
263#define IL_TX_FIFO_VO 3
264#define IL_TX_FIFO_UNUSED -1
265
266/* Minimum number of queues. MAX_NUM is defined in hw specific files.
267 * Set the minimum to accommodate the 4 standard TX queues, 1 command
268 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
269#define IL_MIN_NUM_QUEUES 10
270
271#define IL_DEFAULT_CMD_QUEUE_NUM 4
272
273#define IEEE80211_DATA_LEN 2304
274#define IEEE80211_4ADDR_LEN 30
275#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
276#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
277
278struct il_frame {
279 union {
280 struct ieee80211_hdr frame;
281 struct il_tx_beacon_cmd beacon;
282 u8 raw[IEEE80211_FRAME_LEN];
283 u8 cmd[360];
284 } u;
285 struct list_head list;
286};
287
288#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
289#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
290#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
291
292enum {
293 CMD_SYNC = 0,
294 CMD_SIZE_NORMAL = 0,
295 CMD_NO_SKB = 0,
296 CMD_SIZE_HUGE = (1 << 0),
297 CMD_ASYNC = (1 << 1),
298 CMD_WANT_SKB = (1 << 2),
299 CMD_MAPPED = (1 << 3),
300};
301
302#define DEF_CMD_PAYLOAD_SIZE 320
303
304/**
305 * struct il_device_cmd
306 *
307 * For allocation of the command and tx queues, this establishes the overall
308 * size of the largest command we send to uCode, except for a scan command
309 * (which is relatively huge; space is allocated separately).
310 */
311struct il_device_cmd {
312 struct il_cmd_header hdr; /* uCode API */
313 union {
314 u32 flags;
315 u8 val8;
316 u16 val16;
317 u32 val32;
318 struct il_tx_cmd tx;
319 u8 payload[DEF_CMD_PAYLOAD_SIZE];
320 } __packed cmd;
321} __packed;
322
323#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
324
325
326struct il_host_cmd {
327 const void *data;
328 unsigned long reply_page;
329 void (*callback)(struct il_priv *il,
330 struct il_device_cmd *cmd,
331 struct il_rx_pkt *pkt);
332 u32 flags;
333 u16 len;
334 u8 id;
335};
336
337#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
338#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
339#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
340
341/**
342 * struct il_rx_queue - Rx queue
343 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
344 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
345 * @read: Shared idx to newest available Rx buffer
346 * @write: Shared idx to oldest written Rx packet
347 * @free_count: Number of pre-allocated buffers in rx_free
348 * @rx_free: list of free SKBs for use
349 * @rx_used: List of Rx buffers with no SKB
350 * @need_update: flag to indicate we need to update read/write idx
351 * @rb_stts: driver's pointer to receive buffer status
352 * @rb_stts_dma: bus address of receive buffer status
353 *
354 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
355 */
356struct il_rx_queue {
357 __le32 *bd;
358 dma_addr_t bd_dma;
359 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
360 struct il_rx_buf *queue[RX_QUEUE_SIZE];
361 u32 read;
362 u32 write;
363 u32 free_count;
364 u32 write_actual;
365 struct list_head rx_free;
366 struct list_head rx_used;
367 int need_update;
368 struct il_rb_status *rb_stts;
369 dma_addr_t rb_stts_dma;
370 spinlock_t lock;
371};
372
373#define IL_SUPPORTED_RATES_IE_LEN 8
374
375#define MAX_TID_COUNT 9
376
377#define IL_INVALID_RATE 0xFF
378#define IL_INVALID_VALUE -1
379
380/**
381 * struct il_ht_agg -- aggregation status while waiting for block-ack
382 * @txq_id: Tx queue used for Tx attempt
383 * @frame_count: # frames attempted by Tx command
384 * @wait_for_ba: Expect block-ack before next Tx reply
385 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
386 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
387 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
388 * @rate_n_flags: Rate at which Tx was attempted
389 *
390 * If C_TX indicates that aggregation was attempted, driver must wait
391 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
392 * until block ack arrives.
393 */
394struct il_ht_agg {
395 u16 txq_id;
396 u16 frame_count;
397 u16 wait_for_ba;
398 u16 start_idx;
399 u64 bitmap;
400 u32 rate_n_flags;
401#define IL_AGG_OFF 0
402#define IL_AGG_ON 1
403#define IL_EMPTYING_HW_QUEUE_ADDBA 2
404#define IL_EMPTYING_HW_QUEUE_DELBA 3
405 u8 state;
406};
407
408
409struct il_tid_data {
410 u16 seq_number; /* 4965 only */
411 u16 tfds_in_queue;
412 struct il_ht_agg agg;
413};
414
415struct il_hw_key {
416 u32 cipher;
417 int keylen;
418 u8 keyidx;
419 u8 key[32];
420};
421
422union il_ht_rate_supp {
423 u16 rates;
424 struct {
425 u8 siso_rate;
426 u8 mimo_rate;
427 };
428};
429
430#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
431#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
432#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
433#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
434#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
435#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
436#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
437
438/*
439 * Maximal MPDU density for TX aggregation
440 * 4 - 2us density
441 * 5 - 4us density
442 * 6 - 8us density
443 * 7 - 16us density
444 */
445#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
446#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
447#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
448#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
449#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
450#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
451#define CFG_HT_MPDU_DENSITY_MIN (0x1)
452
453struct il_ht_config {
454 bool single_chain_sufficient;
455 enum ieee80211_smps_mode smps; /* current smps mode */
456};
457
458/* QoS structures */
459struct il_qos_info {
460 int qos_active;
461 struct il_qosparam_cmd def_qos_parm;
462};
463
464/*
465 * Structure should be accessed with sta_lock held. When station addition
466 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
467 * the commands (il_addsta_cmd and il_link_quality_cmd) without
468 * sta_lock held.
469 */
470struct il_station_entry {
471 struct il_addsta_cmd sta;
472 struct il_tid_data tid[MAX_TID_COUNT];
473 u8 used, ctxid;
474 struct il_hw_key keyinfo;
475 struct il_link_quality_cmd *lq;
476};
477
478struct il_station_priv_common {
479 struct il_rxon_context *ctx;
480 u8 sta_id;
481};
482
483/*
484 * il_station_priv: Driver's ilate station information
485 *
486 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
487 * in the structure for use by driver. This structure is places in that
488 * space.
489 *
490 * The common struct MUST be first because it is shared between
491 * 3945 and 4965!
492 */
493struct il_station_priv {
494 struct il_station_priv_common common;
495 struct il_lq_sta lq_sta;
496 atomic_t pending_frames;
497 bool client;
498 bool asleep;
499};
500
501/**
502 * struct il_vif_priv - driver's ilate per-interface information
503 *
504 * When mac80211 allocates a virtual interface, it can allocate
505 * space for us to put data into.
506 */
507struct il_vif_priv {
508 struct il_rxon_context *ctx;
509 u8 ibss_bssid_sta_id;
510};
511
512/* one for each uCode image (inst/data, boot/init/runtime) */
513struct fw_desc {
514 void *v_addr; /* access by driver */
515 dma_addr_t p_addr; /* access by card's busmaster DMA */
516 u32 len; /* bytes */
517};
518
519/* uCode file layout */
520struct il_ucode_header {
521 __le32 ver; /* major/minor/API/serial */
522 struct {
523 __le32 inst_size; /* bytes of runtime code */
524 __le32 data_size; /* bytes of runtime data */
525 __le32 init_size; /* bytes of init code */
526 __le32 init_data_size; /* bytes of init data */
527 __le32 boot_size; /* bytes of bootstrap code */
528 u8 data[0]; /* in same order as sizes */
529 } v1;
530};
531
532struct il4965_ibss_seq {
533 u8 mac[ETH_ALEN];
534 u16 seq_num;
535 u16 frag_num;
536 unsigned long packet_time;
537 struct list_head list;
538};
539
540struct il_sensitivity_ranges {
541 u16 min_nrg_cck;
542 u16 max_nrg_cck;
543
544 u16 nrg_th_cck;
545 u16 nrg_th_ofdm;
546
547 u16 auto_corr_min_ofdm;
548 u16 auto_corr_min_ofdm_mrc;
549 u16 auto_corr_min_ofdm_x1;
550 u16 auto_corr_min_ofdm_mrc_x1;
551
552 u16 auto_corr_max_ofdm;
553 u16 auto_corr_max_ofdm_mrc;
554 u16 auto_corr_max_ofdm_x1;
555 u16 auto_corr_max_ofdm_mrc_x1;
556
557 u16 auto_corr_max_cck;
558 u16 auto_corr_max_cck_mrc;
559 u16 auto_corr_min_cck;
560 u16 auto_corr_min_cck_mrc;
561
562 u16 barker_corr_th_min;
563 u16 barker_corr_th_min_mrc;
564 u16 nrg_th_cca;
565};
566
567
568#define KELVIN_TO_CELSIUS(x) ((x)-273)
569#define CELSIUS_TO_KELVIN(x) ((x)+273)
570
571
572/**
573 * struct il_hw_params
574 * @max_txq_num: Max # Tx queues supported
575 * @dma_chnl_num: Number of Tx DMA/FIFO channels
576 * @scd_bc_tbls_size: size of scheduler byte count tables
577 * @tfd_size: TFD size
578 * @tx/rx_chains_num: Number of TX/RX chains
579 * @valid_tx/rx_ant: usable antennas
580 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
581 * @max_rxq_log: Log-base-2 of max_rxq_size
582 * @rx_page_order: Rx buffer page order
583 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
584 * @max_stations:
585 * @ht40_channel: is 40MHz width possible in band 2.4
586 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
587 * @sw_crypto: 0 for hw, 1 for sw
588 * @max_xxx_size: for ucode uses
589 * @ct_kill_threshold: temperature threshold
590 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
591 * @struct il_sensitivity_ranges: range of sensitivity values
592 */
593struct il_hw_params {
594 u8 max_txq_num;
595 u8 dma_chnl_num;
596 u16 scd_bc_tbls_size;
597 u32 tfd_size;
598 u8 tx_chains_num;
599 u8 rx_chains_num;
600 u8 valid_tx_ant;
601 u8 valid_rx_ant;
602 u16 max_rxq_size;
603 u16 max_rxq_log;
604 u32 rx_page_order;
605 u32 rx_wrt_ptr_reg;
606 u8 max_stations;
607 u8 ht40_channel;
608 u8 max_beacon_itrvl; /* in 1024 ms */
609 u32 max_inst_size;
610 u32 max_data_size;
611 u32 max_bsm_size;
612 u32 ct_kill_threshold; /* value in hw-dependent units */
613 u16 beacon_time_tsf_bits;
614 const struct il_sensitivity_ranges *sens;
615};
616
617
618/******************************************************************************
619 *
620 * Functions implemented in core module which are forward declared here
621 * for use by iwl-[4-5].c
622 *
623 * NOTE: The implementation of these functions are not hardware specific
624 * which is why they are in the core module files.
625 *
626 * Naming convention --
627 * il_ <-- Is part of iwlwifi
628 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
629 * il4965_bg_ <-- Called from work queue context
630 * il4965_mac_ <-- mac80211 callback
631 *
632 ****************************************************************************/
633extern void il4965_update_chain_flags(struct il_priv *il);
634extern const u8 il_bcast_addr[ETH_ALEN];
635extern int il_queue_space(const struct il_queue *q);
636static inline int il_queue_used(const struct il_queue *q, int i)
637{
638 return q->write_ptr >= q->read_ptr ?
639 (i >= q->read_ptr && i < q->write_ptr) :
640 !(i < q->read_ptr && i >= q->write_ptr);
641}
642
643
644static inline u8 il_get_cmd_idx(struct il_queue *q, u32 idx,
645 int is_huge)
646{
647 /*
648 * This is for init calibration result and scan command which
649 * required buffer > TFD_MAX_PAYLOAD_SIZE,
650 * the big buffer at end of command array
651 */
652 if (is_huge)
653 return q->n_win; /* must be power of 2 */
654
655 /* Otherwise, use normal size buffers */
656 return idx & (q->n_win - 1);
657}
658
659
660struct il_dma_ptr {
661 dma_addr_t dma;
662 void *addr;
663 size_t size;
664};
665
666#define IL_OPERATION_MODE_AUTO 0
667#define IL_OPERATION_MODE_HT_ONLY 1
668#define IL_OPERATION_MODE_MIXED 2
669#define IL_OPERATION_MODE_20MHZ 3
670
671#define IL_TX_CRC_SIZE 4
672#define IL_TX_DELIMITER_SIZE 4
673
674#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
675
676/* Sensitivity and chain noise calibration */
677#define INITIALIZATION_VALUE 0xFFFF
678#define IL4965_CAL_NUM_BEACONS 20
679#define IL_CAL_NUM_BEACONS 16
680#define MAXIMUM_ALLOWED_PATHLOSS 15
681
682#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
683
684#define MAX_FA_OFDM 50
685#define MIN_FA_OFDM 5
686#define MAX_FA_CCK 50
687#define MIN_FA_CCK 5
688
689#define AUTO_CORR_STEP_OFDM 1
690
691#define AUTO_CORR_STEP_CCK 3
692#define AUTO_CORR_MAX_TH_CCK 160
693
694#define NRG_DIFF 2
695#define NRG_STEP_CCK 2
696#define NRG_MARGIN 8
697#define MAX_NUMBER_CCK_NO_FA 100
698
699#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
700
701#define CHAIN_A 0
702#define CHAIN_B 1
703#define CHAIN_C 2
704#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
705#define ALL_BAND_FILTER 0xFF00
706#define IN_BAND_FILTER 0xFF
707#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
708
709#define NRG_NUM_PREV_STAT_L 20
710#define NUM_RX_CHAINS 3
711
712enum il4965_false_alarm_state {
713 IL_FA_TOO_MANY = 0,
714 IL_FA_TOO_FEW = 1,
715 IL_FA_GOOD_RANGE = 2,
716};
717
718enum il4965_chain_noise_state {
719 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
720 IL_CHAIN_NOISE_ACCUMULATE,
721 IL_CHAIN_NOISE_CALIBRATED,
722 IL_CHAIN_NOISE_DONE,
723};
724
725enum il4965_calib_enabled_state {
726 IL_CALIB_DISABLED = 0, /* must be 0 */
727 IL_CALIB_ENABLED = 1,
728};
729
730/*
731 * enum il_calib
732 * defines the order in which results of initial calibrations
733 * should be sent to the runtime uCode
734 */
735enum il_calib {
736 IL_CALIB_MAX,
737};
738
739/* Opaque calibration results */
740struct il_calib_result {
741 void *buf;
742 size_t buf_len;
743};
744
745enum ucode_type {
746 UCODE_NONE = 0,
747 UCODE_INIT,
748 UCODE_RT
749};
750
751/* Sensitivity calib data */
752struct il_sensitivity_data {
753 u32 auto_corr_ofdm;
754 u32 auto_corr_ofdm_mrc;
755 u32 auto_corr_ofdm_x1;
756 u32 auto_corr_ofdm_mrc_x1;
757 u32 auto_corr_cck;
758 u32 auto_corr_cck_mrc;
759
760 u32 last_bad_plcp_cnt_ofdm;
761 u32 last_fa_cnt_ofdm;
762 u32 last_bad_plcp_cnt_cck;
763 u32 last_fa_cnt_cck;
764
765 u32 nrg_curr_state;
766 u32 nrg_prev_state;
767 u32 nrg_value[10];
768 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
769 u32 nrg_silence_ref;
770 u32 nrg_energy_idx;
771 u32 nrg_silence_idx;
772 u32 nrg_th_cck;
773 s32 nrg_auto_corr_silence_diff;
774 u32 num_in_cck_no_fa;
775 u32 nrg_th_ofdm;
776
777 u16 barker_corr_th_min;
778 u16 barker_corr_th_min_mrc;
779 u16 nrg_th_cca;
780};
781
782/* Chain noise (differential Rx gain) calib data */
783struct il_chain_noise_data {
784 u32 active_chains;
785 u32 chain_noise_a;
786 u32 chain_noise_b;
787 u32 chain_noise_c;
788 u32 chain_signal_a;
789 u32 chain_signal_b;
790 u32 chain_signal_c;
791 u16 beacon_count;
792 u8 disconn_array[NUM_RX_CHAINS];
793 u8 delta_gain_code[NUM_RX_CHAINS];
794 u8 radio_write;
795 u8 state;
796};
797
798#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
799#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
800
801#define IL_TRAFFIC_ENTRIES (256)
802#define IL_TRAFFIC_ENTRY_SIZE (64)
803
804enum {
805 MEASUREMENT_READY = (1 << 0),
806 MEASUREMENT_ACTIVE = (1 << 1),
807};
808
809/* interrupt stats */
810struct isr_stats {
811 u32 hw;
812 u32 sw;
813 u32 err_code;
814 u32 sch;
815 u32 alive;
816 u32 rfkill;
817 u32 ctkill;
818 u32 wakeup;
819 u32 rx;
820 u32 handlers[IL_CN_MAX];
821 u32 tx;
822 u32 unhandled;
823};
824
825/* management stats */
826enum il_mgmt_stats {
827 MANAGEMENT_ASSOC_REQ = 0,
828 MANAGEMENT_ASSOC_RESP,
829 MANAGEMENT_REASSOC_REQ,
830 MANAGEMENT_REASSOC_RESP,
831 MANAGEMENT_PROBE_REQ,
832 MANAGEMENT_PROBE_RESP,
833 MANAGEMENT_BEACON,
834 MANAGEMENT_ATIM,
835 MANAGEMENT_DISASSOC,
836 MANAGEMENT_AUTH,
837 MANAGEMENT_DEAUTH,
838 MANAGEMENT_ACTION,
839 MANAGEMENT_MAX,
840};
841/* control stats */
842enum il_ctrl_stats {
843 CONTROL_BACK_REQ = 0,
844 CONTROL_BACK,
845 CONTROL_PSPOLL,
846 CONTROL_RTS,
847 CONTROL_CTS,
848 CONTROL_ACK,
849 CONTROL_CFEND,
850 CONTROL_CFENDACK,
851 CONTROL_MAX,
852};
853
854struct traffic_stats {
855#ifdef CONFIG_IWLEGACY_DEBUGFS
856 u32 mgmt[MANAGEMENT_MAX];
857 u32 ctrl[CONTROL_MAX];
858 u32 data_cnt;
859 u64 data_bytes;
860#endif
861};
862
863/*
864 * host interrupt timeout value
865 * used with setting interrupt coalescing timer
866 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
867 *
868 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
869 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
870 */
871#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
872#define IL_HOST_INT_TIMEOUT_DEF (0x40)
873#define IL_HOST_INT_TIMEOUT_MIN (0x0)
874#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
875#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
876#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
877
878#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
879
880/* TX queue watchdog timeouts in mSecs */
881#define IL_DEF_WD_TIMEOUT (2000)
882#define IL_LONG_WD_TIMEOUT (10000)
883#define IL_MAX_WD_TIMEOUT (120000)
884
885struct il_force_reset {
886 int reset_request_count;
887 int reset_success_count;
888 int reset_reject_count;
889 unsigned long reset_duration;
890 unsigned long last_force_reset_jiffies;
891};
892
893/* extend beacon time format bit shifting */
894/*
895 * for _3945 devices
896 * bits 31:24 - extended
897 * bits 23:0 - interval
898 */
899#define IL3945_EXT_BEACON_TIME_POS 24
900/*
901 * for _4965 devices
902 * bits 31:22 - extended
903 * bits 21:0 - interval
904 */
905#define IL4965_EXT_BEACON_TIME_POS 22
906
907struct il_rxon_context {
908 struct ieee80211_vif *vif;
909
910 const u8 *ac_to_fifo;
911 const u8 *ac_to_queue;
912 u8 mcast_queue;
913
914 /*
915 * We could use the vif to indicate active, but we
916 * also need it to be active during disabling when
917 * we already removed the vif for type setting.
918 */
919 bool always_active, is_active;
920
921 bool ht_need_multiple_chains;
922
923 int ctxid;
924
925 u32 interface_modes, exclusive_interface_modes;
926 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
927
928 /*
929 * We declare this const so it can only be
930 * changed via explicit cast within the
931 * routines that actually update the physical
932 * hardware.
933 */
934 const struct il_rxon_cmd active;
935 struct il_rxon_cmd staging;
936
937 struct il_rxon_time_cmd timing;
938
939 struct il_qos_info qos_data;
940
941 u8 bcast_sta_id, ap_sta_id;
942
943 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
944 u8 qos_cmd;
945 u8 wep_key_cmd;
946
947 struct il_wep_key wep_keys[WEP_KEYS_MAX];
948 u8 key_mapping_keys;
949
950 __le32 station_flags;
951
952 struct {
953 bool non_gf_sta_present;
954 u8 protection;
955 bool enabled, is_40mhz;
956 u8 extension_chan_offset;
957 } ht;
958};
959
960struct il_priv {
961
962 /* ieee device used by generic ieee processing code */
963 struct ieee80211_hw *hw;
964 struct ieee80211_channel *ieee_channels;
965 struct ieee80211_rate *ieee_rates;
966 struct il_cfg *cfg;
967
968 /* temporary frame storage list */
969 struct list_head free_frames;
970 int frames_count;
971
972 enum ieee80211_band band;
973 int alloc_rxb_page;
974
975 void (*handlers[IL_CN_MAX])(struct il_priv *il,
976 struct il_rx_buf *rxb);
977
978 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
979
980 /* spectrum measurement report caching */
981 struct il_spectrum_notification measure_report;
982 u8 measurement_status;
983
984 /* ucode beacon time */
985 u32 ucode_beacon_time;
986 int missed_beacon_threshold;
987
988 /* track IBSS manager (last beacon) status */
989 u32 ibss_manager;
990
991 /* force reset */
992 struct il_force_reset force_reset;
993
994 /* we allocate array of il_channel_info for NIC's valid channels.
995 * Access via channel # using indirect idx array */
996 struct il_channel_info *channel_info; /* channel info array */
997 u8 channel_count; /* # of channels */
998
999 /* thermal calibration */
1000 s32 temperature; /* degrees Kelvin */
1001 s32 last_temperature;
1002
1003 /* init calibration results */
1004 struct il_calib_result calib_results[IL_CALIB_MAX];
1005
1006 /* Scan related variables */
1007 unsigned long scan_start;
1008 unsigned long scan_start_tsf;
1009 void *scan_cmd;
1010 enum ieee80211_band scan_band;
1011 struct cfg80211_scan_request *scan_request;
1012 struct ieee80211_vif *scan_vif;
1013 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1014 u8 mgmt_tx_ant;
1015
1016 /* spinlock */
1017 spinlock_t lock; /* protect general shared data */
1018 spinlock_t hcmd_lock; /* protect hcmd */
1019 spinlock_t reg_lock; /* protect hw register access */
1020 struct mutex mutex;
1021
1022 /* basic pci-network driver stuff */
1023 struct pci_dev *pci_dev;
1024
1025 /* pci hardware address support */
1026 void __iomem *hw_base;
1027 u32 hw_rev;
1028 u32 hw_wa_rev;
1029 u8 rev_id;
1030
1031 /* command queue number */
1032 u8 cmd_queue;
1033
1034 /* max number of station keys */
1035 u8 sta_key_max_num;
1036
1037 /* EEPROM MAC addresses */
1038 struct mac_address addresses[1];
1039
1040 /* uCode images, save to reload in case of failure */
1041 int fw_idx; /* firmware we're trying to load */
1042 u32 ucode_ver; /* version of ucode, copy of
1043 il_ucode.ver */
1044 struct fw_desc ucode_code; /* runtime inst */
1045 struct fw_desc ucode_data; /* runtime data original */
1046 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1047 struct fw_desc ucode_init; /* initialization inst */
1048 struct fw_desc ucode_init_data; /* initialization data */
1049 struct fw_desc ucode_boot; /* bootstrap inst */
1050 enum ucode_type ucode_type;
1051 u8 ucode_write_complete; /* the image write is complete */
1052 char firmware_name[25];
1053
1054 struct il_rxon_context ctx;
1055
1056 __le16 switch_channel;
1057
1058 /* 1st responses from initialize and runtime uCode images.
1059 * _4965's initialize alive response contains some calibration data. */
1060 struct il_init_alive_resp card_alive_init;
1061 struct il_alive_resp card_alive;
1062
1063 u16 active_rate;
1064
1065 u8 start_calib;
1066 struct il_sensitivity_data sensitivity_data;
1067 struct il_chain_noise_data chain_noise_data;
1068 __le16 sensitivity_tbl[HD_TBL_SIZE];
1069
1070 struct il_ht_config current_ht_config;
1071
1072 /* Rate scaling data */
1073 u8 retry_rate;
1074
1075 wait_queue_head_t wait_command_queue;
1076
1077 int activity_timer_active;
1078
1079 /* Rx and Tx DMA processing queues */
1080 struct il_rx_queue rxq;
1081 struct il_tx_queue *txq;
1082 unsigned long txq_ctx_active_msk;
1083 struct il_dma_ptr kw; /* keep warm address */
1084 struct il_dma_ptr scd_bc_tbls;
1085
1086 u32 scd_base_addr; /* scheduler sram base address */
1087
1088 unsigned long status;
1089
1090 /* counts mgmt, ctl, and data packets */
1091 struct traffic_stats tx_stats;
1092 struct traffic_stats rx_stats;
1093
1094 /* counts interrupts */
1095 struct isr_stats isr_stats;
1096
1097 struct il_power_mgr power_data;
1098
1099 /* context information */
1100 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
1101
1102 /* station table variables */
1103
1104 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1105 spinlock_t sta_lock;
1106 int num_stations;
1107 struct il_station_entry stations[IL_STATION_COUNT];
1108 unsigned long ucode_key_table;
1109
1110 /* queue refcounts */
1111#define IL_MAX_HW_QUEUES 32
1112 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1113 /* for each AC */
1114 atomic_t queue_stop_count[4];
1115
1116 /* Indication if ieee80211_ops->open has been called */
1117 u8 is_open;
1118
1119 u8 mac80211_registered;
1120
1121 /* eeprom -- this is in the card's little endian byte order */
1122 u8 *eeprom;
1123 struct il_eeprom_calib_info *calib_info;
1124
1125 enum nl80211_iftype iw_mode;
1126
1127 /* Last Rx'd beacon timestamp */
1128 u64 timestamp;
1129
1130 union {
1131#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1132 struct {
1133 void *shared_virt;
1134 dma_addr_t shared_phys;
1135
1136 struct delayed_work thermal_periodic;
1137 struct delayed_work rfkill_poll;
1138
1139 struct il3945_notif_stats stats;
1140#ifdef CONFIG_IWLEGACY_DEBUGFS
1141 struct il3945_notif_stats accum_stats;
1142 struct il3945_notif_stats delta_stats;
1143 struct il3945_notif_stats max_delta;
1144#endif
1145
1146 u32 sta_supp_rates;
1147 int last_rx_rssi; /* From Rx packet stats */
1148
1149 /* Rx'd packet timing information */
1150 u32 last_beacon_time;
1151 u64 last_tsf;
1152
1153 /*
1154 * each calibration channel group in the
1155 * EEPROM has a derived clip setting for
1156 * each rate.
1157 */
1158 const struct il3945_clip_group clip_groups[5];
1159
1160 } _3945;
1161#endif
1162#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1163 struct {
1164 struct il_rx_phy_res last_phy_res;
1165 bool last_phy_res_valid;
1166
1167 struct completion firmware_loading_complete;
1168
1169 /*
1170 * chain noise reset and gain commands are the
1171 * two extra calibration commands follows the standard
1172 * phy calibration commands
1173 */
1174 u8 phy_calib_chain_noise_reset_cmd;
1175 u8 phy_calib_chain_noise_gain_cmd;
1176
1177 struct il_notif_stats stats;
1178#ifdef CONFIG_IWLEGACY_DEBUGFS
1179 struct il_notif_stats accum_stats;
1180 struct il_notif_stats delta_stats;
1181 struct il_notif_stats max_delta;
1182#endif
1183
1184 } _4965;
1185#endif
1186 };
1187
1188 struct il_hw_params hw_params;
1189
1190 u32 inta_mask;
1191
1192 struct workqueue_struct *workqueue;
1193
1194 struct work_struct restart;
1195 struct work_struct scan_completed;
1196 struct work_struct rx_replenish;
1197 struct work_struct abort_scan;
1198
1199 struct il_rxon_context *beacon_ctx;
1200 struct sk_buff *beacon_skb;
71 1201
1202 struct work_struct tx_flush;
1203
1204 struct tasklet_struct irq_tasklet;
1205
1206 struct delayed_work init_alive_start;
1207 struct delayed_work alive_start;
1208 struct delayed_work scan_check;
1209
1210 /* TX Power */
1211 s8 tx_power_user_lmt;
1212 s8 tx_power_device_lmt;
1213 s8 tx_power_next;
1214
1215
1216#ifdef CONFIG_IWLEGACY_DEBUG
1217 /* debugging info */
1218 u32 debug_level; /* per device debugging will override global
1219 il_debug_level if set */
1220#endif /* CONFIG_IWLEGACY_DEBUG */
1221#ifdef CONFIG_IWLEGACY_DEBUGFS
1222 /* debugfs */
1223 u16 tx_traffic_idx;
1224 u16 rx_traffic_idx;
1225 u8 *tx_traffic;
1226 u8 *rx_traffic;
1227 struct dentry *debugfs_dir;
1228 u32 dbgfs_sram_offset, dbgfs_sram_len;
1229 bool disable_ht40;
1230#endif /* CONFIG_IWLEGACY_DEBUGFS */
1231
1232 struct work_struct txpower_work;
1233 u32 disable_sens_cal;
1234 u32 disable_chain_noise_cal;
1235 u32 disable_tx_power_cal;
1236 struct work_struct run_time_calib_work;
1237 struct timer_list stats_periodic;
1238 struct timer_list watchdog;
1239 bool hw_ready;
1240
1241 struct led_classdev led;
1242 unsigned long blink_on, blink_off;
1243 bool led_registered;
1244}; /*il_priv */
1245
1246static inline void il_txq_ctx_activate(struct il_priv *il, int txq_id)
1247{
1248 set_bit(txq_id, &il->txq_ctx_active_msk);
1249}
1250
1251static inline void il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1252{
1253 clear_bit(txq_id, &il->txq_ctx_active_msk);
1254}
1255
1256#ifdef CONFIG_IWLEGACY_DEBUG
1257/*
1258 * il_get_debug_level: Return active debug level for device
1259 *
1260 * Using sysfs it is possible to set per device debug level. This debug
1261 * level will be used if set, otherwise the global debug level which can be
1262 * set via module parameter is used.
1263 */
1264static inline u32 il_get_debug_level(struct il_priv *il)
1265{
1266 if (il->debug_level)
1267 return il->debug_level;
1268 else
1269 return il_debug_level;
1270}
1271#else
1272static inline u32 il_get_debug_level(struct il_priv *il)
1273{
1274 return il_debug_level;
1275}
1276#endif
1277
1278
1279static inline struct ieee80211_hdr *
1280il_tx_queue_get_hdr(struct il_priv *il,
1281 int txq_id, int idx)
1282{
1283 if (il->txq[txq_id].txb[idx].skb)
1284 return (struct ieee80211_hdr *)il->txq[txq_id].
1285 txb[idx].skb->data;
1286 return NULL;
1287}
1288
1289static inline struct il_rxon_context *
1290il_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1291{
1292 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1293
1294 return vif_priv->ctx;
1295}
1296
1297#define for_each_context(il, _ctx) \
1298 for (_ctx = &il->ctx; _ctx == &il->ctx; _ctx++)
1299
1300static inline int il_is_associated(struct il_priv *il)
1301{
1302 return (il->ctx.active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1303}
1304
1305static inline int il_is_any_associated(struct il_priv *il)
1306{
1307 return il_is_associated(il);
1308}
1309
1310static inline int il_is_associated_ctx(struct il_rxon_context *ctx)
1311{
1312 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1313}
1314
1315static inline int il_is_channel_valid(const struct il_channel_info *ch_info)
1316{
1317 if (ch_info == NULL)
1318 return 0;
1319 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1320}
1321
1322static inline int il_is_channel_radar(const struct il_channel_info *ch_info)
1323{
1324 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1325}
1326
1327static inline u8 il_is_channel_a_band(const struct il_channel_info *ch_info)
1328{
1329 return ch_info->band == IEEE80211_BAND_5GHZ;
1330}
1331
1332static inline int
1333il_is_channel_passive(const struct il_channel_info *ch)
1334{
1335 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1336}
1337
1338static inline int
1339il_is_channel_ibss(const struct il_channel_info *ch)
1340{
1341 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1342}
1343
1344static inline void
1345__il_free_pages(struct il_priv *il, struct page *page)
1346{
1347 __free_pages(page, il->hw_params.rx_page_order);
1348 il->alloc_rxb_page--;
1349}
1350
1351static inline void il_free_pages(struct il_priv *il, unsigned long page)
1352{
1353 free_pages(page, il->hw_params.rx_page_order);
1354 il->alloc_rxb_page--;
1355}
72 1356
73#define IWLWIFI_VERSION "in-tree:" 1357#define IWLWIFI_VERSION "in-tree:"
74#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation" 1358#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
@@ -87,6 +1371,11 @@ struct il_cmd;
87 1371
88#define IL_CMD(x) case x: return #x 1372#define IL_CMD(x) case x: return #x
89 1373
1374/* Size of one Rx buffer in host DRAM */
1375#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
1376#define IL_RX_BUF_SIZE_4K (4 * 1024)
1377#define IL_RX_BUF_SIZE_8K (8 * 1024)
1378
90struct il_hcmd_ops { 1379struct il_hcmd_ops {
91 int (*rxon_assoc)(struct il_priv *il, struct il_rxon_context *ctx); 1380 int (*rxon_assoc)(struct il_priv *il, struct il_rxon_context *ctx);
92 int (*commit_rxon)(struct il_priv *il, struct il_rxon_context *ctx); 1381 int (*commit_rxon)(struct il_priv *il, struct il_rxon_context *ctx);
@@ -633,4 +1922,655 @@ void il_tx_cmd_protection(struct il_priv *il,
633 1922
634irqreturn_t il_isr(int irq, void *data); 1923irqreturn_t il_isr(int irq, void *data);
635 1924
1925
1926#include <linux/io.h>
1927
1928static inline void _il_write8(struct il_priv *il, u32 ofs, u8 val)
1929{
1930 iowrite8(val, il->hw_base + ofs);
1931}
1932#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1933
1934static inline void _il_wr(struct il_priv *il, u32 ofs, u32 val)
1935{
1936 iowrite32(val, il->hw_base + ofs);
1937}
1938
1939static inline u32 _il_rd(struct il_priv *il, u32 ofs)
1940{
1941 return ioread32(il->hw_base + ofs);
1942}
1943
1944#define IL_POLL_INTERVAL 10 /* microseconds */
1945static inline int
1946_il_poll_bit(struct il_priv *il, u32 addr,
1947 u32 bits, u32 mask, int timeout)
1948{
1949 int t = 0;
1950
1951 do {
1952 if ((_il_rd(il, addr) & mask) == (bits & mask))
1953 return t;
1954 udelay(IL_POLL_INTERVAL);
1955 t += IL_POLL_INTERVAL;
1956 } while (t < timeout);
1957
1958 return -ETIMEDOUT;
1959}
1960
1961static inline void _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
1962{
1963 _il_wr(il, reg, _il_rd(il, reg) | mask);
1964}
1965
1966static inline void il_set_bit(struct il_priv *p, u32 r, u32 m)
1967{
1968 unsigned long reg_flags;
1969
1970 spin_lock_irqsave(&p->reg_lock, reg_flags);
1971 _il_set_bit(p, r, m);
1972 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
1973}
1974
1975static inline void
1976_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
1977{
1978 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
1979}
1980
1981static inline void il_clear_bit(struct il_priv *p, u32 r, u32 m)
1982{
1983 unsigned long reg_flags;
1984
1985 spin_lock_irqsave(&p->reg_lock, reg_flags);
1986 _il_clear_bit(p, r, m);
1987 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
1988}
1989
1990static inline int _il_grab_nic_access(struct il_priv *il)
1991{
1992 int ret;
1993 u32 val;
1994
1995 /* this bit wakes up the NIC */
1996 _il_set_bit(il, CSR_GP_CNTRL,
1997 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1998
1999 /*
2000 * These bits say the device is running, and should keep running for
2001 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2002 * but they do not indicate that embedded SRAM is restored yet;
2003 * 3945 and 4965 have volatile SRAM, and must save/restore contents
2004 * to/from host DRAM when sleeping/waking for power-saving.
2005 * Each direction takes approximately 1/4 millisecond; with this
2006 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2007 * series of register accesses are expected (e.g. reading Event Log),
2008 * to keep device from sleeping.
2009 *
2010 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2011 * SRAM is okay/restored. We don't check that here because this call
2012 * is just for hardware register access; but GP1 MAC_SLEEP check is a
2013 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
2014 *
2015 */
2016 ret = _il_poll_bit(il, CSR_GP_CNTRL,
2017 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2018 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2019 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2020 if (ret < 0) {
2021 val = _il_rd(il, CSR_GP_CNTRL);
2022 IL_ERR(
2023 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
2024 _il_wr(il, CSR_RESET,
2025 CSR_RESET_REG_FLAG_FORCE_NMI);
2026 return -EIO;
2027 }
2028
2029 return 0;
2030}
2031
2032static inline void _il_release_nic_access(struct il_priv *il)
2033{
2034 _il_clear_bit(il, CSR_GP_CNTRL,
2035 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2036}
2037
2038static inline u32 il_rd(struct il_priv *il, u32 reg)
2039{
2040 u32 value;
2041 unsigned long reg_flags;
2042
2043 spin_lock_irqsave(&il->reg_lock, reg_flags);
2044 _il_grab_nic_access(il);
2045 value = _il_rd(il, reg);
2046 _il_release_nic_access(il);
2047 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2048 return value;
2049
2050}
2051
2052static inline void
2053il_wr(struct il_priv *il, u32 reg, u32 value)
2054{
2055 unsigned long reg_flags;
2056
2057 spin_lock_irqsave(&il->reg_lock, reg_flags);
2058 if (!_il_grab_nic_access(il)) {
2059 _il_wr(il, reg, value);
2060 _il_release_nic_access(il);
2061 }
2062 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2063}
2064
2065static inline void il_write_reg_buf(struct il_priv *il,
2066 u32 reg, u32 len, u32 *values)
2067{
2068 u32 count = sizeof(u32);
2069
2070 if (il != NULL && values != NULL) {
2071 for (; 0 < len; len -= count, reg += count, values++)
2072 il_wr(il, reg, *values);
2073 }
2074}
2075
2076static inline int il_poll_bit(struct il_priv *il, u32 addr,
2077 u32 mask, int timeout)
2078{
2079 int t = 0;
2080
2081 do {
2082 if ((il_rd(il, addr) & mask) == mask)
2083 return t;
2084 udelay(IL_POLL_INTERVAL);
2085 t += IL_POLL_INTERVAL;
2086 } while (t < timeout);
2087
2088 return -ETIMEDOUT;
2089}
2090
2091static inline u32 _il_rd_prph(struct il_priv *il, u32 reg)
2092{
2093 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2094 rmb();
2095 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2096}
2097
2098static inline u32 il_rd_prph(struct il_priv *il, u32 reg)
2099{
2100 unsigned long reg_flags;
2101 u32 val;
2102
2103 spin_lock_irqsave(&il->reg_lock, reg_flags);
2104 _il_grab_nic_access(il);
2105 val = _il_rd_prph(il, reg);
2106 _il_release_nic_access(il);
2107 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2108 return val;
2109}
2110
2111static inline void _il_wr_prph(struct il_priv *il,
2112 u32 addr, u32 val)
2113{
2114 _il_wr(il, HBUS_TARG_PRPH_WADDR,
2115 ((addr & 0x0000FFFF) | (3 << 24)));
2116 wmb();
2117 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2118}
2119
2120static inline void
2121il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2122{
2123 unsigned long reg_flags;
2124
2125 spin_lock_irqsave(&il->reg_lock, reg_flags);
2126 if (!_il_grab_nic_access(il)) {
2127 _il_wr_prph(il, addr, val);
2128 _il_release_nic_access(il);
2129 }
2130 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2131}
2132
2133#define _il_set_bits_prph(il, reg, mask) \
2134_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))
2135
2136static inline void
2137il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2138{
2139 unsigned long reg_flags;
2140
2141 spin_lock_irqsave(&il->reg_lock, reg_flags);
2142 _il_grab_nic_access(il);
2143 _il_set_bits_prph(il, reg, mask);
2144 _il_release_nic_access(il);
2145 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2146}
2147
2148#define _il_set_bits_mask_prph(il, reg, bits, mask) \
2149_il_wr_prph(il, reg, \
2150 ((_il_rd_prph(il, reg) & mask) | bits))
2151
2152static inline void il_set_bits_mask_prph(struct il_priv *il, u32 reg,
2153 u32 bits, u32 mask)
2154{
2155 unsigned long reg_flags;
2156
2157 spin_lock_irqsave(&il->reg_lock, reg_flags);
2158 _il_grab_nic_access(il);
2159 _il_set_bits_mask_prph(il, reg, bits, mask);
2160 _il_release_nic_access(il);
2161 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2162}
2163
2164static inline void il_clear_bits_prph(struct il_priv
2165 *il, u32 reg, u32 mask)
2166{
2167 unsigned long reg_flags;
2168 u32 val;
2169
2170 spin_lock_irqsave(&il->reg_lock, reg_flags);
2171 _il_grab_nic_access(il);
2172 val = _il_rd_prph(il, reg);
2173 _il_wr_prph(il, reg, (val & ~mask));
2174 _il_release_nic_access(il);
2175 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2176}
2177
2178static inline u32 il_read_targ_mem(struct il_priv *il, u32 addr)
2179{
2180 unsigned long reg_flags;
2181 u32 value;
2182
2183 spin_lock_irqsave(&il->reg_lock, reg_flags);
2184 _il_grab_nic_access(il);
2185
2186 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
2187 rmb();
2188 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
2189
2190 _il_release_nic_access(il);
2191 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2192 return value;
2193}
2194
2195static inline void
2196il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
2197{
2198 unsigned long reg_flags;
2199
2200 spin_lock_irqsave(&il->reg_lock, reg_flags);
2201 if (!_il_grab_nic_access(il)) {
2202 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
2203 wmb();
2204 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
2205 _il_release_nic_access(il);
2206 }
2207 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2208}
2209
2210static inline void
2211il_write_targ_mem_buf(struct il_priv *il, u32 addr,
2212 u32 len, u32 *values)
2213{
2214 unsigned long reg_flags;
2215
2216 spin_lock_irqsave(&il->reg_lock, reg_flags);
2217 if (!_il_grab_nic_access(il)) {
2218 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
2219 wmb();
2220 for (; 0 < len; len -= sizeof(u32), values++)
2221 _il_wr(il,
2222 HBUS_TARG_MEM_WDAT, *values);
2223
2224 _il_release_nic_access(il);
2225 }
2226 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2227}
2228
2229#define HW_KEY_DYNAMIC 0
2230#define HW_KEY_DEFAULT 1
2231
2232#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2233#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2234#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2235 being activated */
2236#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2237 (this is for the IBSS BSSID stations) */
2238#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
2239
2240
2241void il_restore_stations(struct il_priv *il,
2242 struct il_rxon_context *ctx);
2243void il_clear_ucode_stations(struct il_priv *il,
2244 struct il_rxon_context *ctx);
2245void il_dealloc_bcast_stations(struct il_priv *il);
2246int il_get_free_ucode_key_idx(struct il_priv *il);
2247int il_send_add_sta(struct il_priv *il,
2248 struct il_addsta_cmd *sta, u8 flags);
2249int il_add_station_common(struct il_priv *il,
2250 struct il_rxon_context *ctx,
2251 const u8 *addr, bool is_ap,
2252 struct ieee80211_sta *sta, u8 *sta_id_r);
2253int il_remove_station(struct il_priv *il,
2254 const u8 sta_id,
2255 const u8 *addr);
2256int il_mac_sta_remove(struct ieee80211_hw *hw,
2257 struct ieee80211_vif *vif,
2258 struct ieee80211_sta *sta);
2259
2260u8 il_prep_station(struct il_priv *il,
2261 struct il_rxon_context *ctx,
2262 const u8 *addr, bool is_ap,
2263 struct ieee80211_sta *sta);
2264
2265int il_send_lq_cmd(struct il_priv *il,
2266 struct il_rxon_context *ctx,
2267 struct il_link_quality_cmd *lq,
2268 u8 flags, bool init);
2269
2270/**
2271 * il_clear_driver_stations - clear knowledge of all stations from driver
2272 * @il: iwl il struct
2273 *
2274 * This is called during il_down() to make sure that in the case
2275 * we're coming there from a hardware restart mac80211 will be
2276 * able to reconfigure stations -- if we're getting there in the
2277 * normal down flow then the stations will already be cleared.
2278 */
2279static inline void il_clear_driver_stations(struct il_priv *il)
2280{
2281 unsigned long flags;
2282 struct il_rxon_context *ctx = &il->ctx;
2283
2284 spin_lock_irqsave(&il->sta_lock, flags);
2285 memset(il->stations, 0, sizeof(il->stations));
2286 il->num_stations = 0;
2287
2288 il->ucode_key_table = 0;
2289
2290 /*
2291 * Remove all key information that is not stored as part
2292 * of station information since mac80211 may not have had
2293 * a chance to remove all the keys. When device is
2294 * reconfigured by mac80211 after an error all keys will
2295 * be reconfigured.
2296 */
2297 memset(ctx->wep_keys, 0, sizeof(ctx->wep_keys));
2298 ctx->key_mapping_keys = 0;
2299
2300 spin_unlock_irqrestore(&il->sta_lock, flags);
2301}
2302
2303static inline int il_sta_id(struct ieee80211_sta *sta)
2304{
2305 if (WARN_ON(!sta))
2306 return IL_INVALID_STATION;
2307
2308 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2309}
2310
2311/**
2312 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2313 * @il: iwl il
2314 * @context: the current context
2315 * @sta: mac80211 station
2316 *
2317 * In certain circumstances mac80211 passes a station pointer
2318 * that may be %NULL, for example during TX or key setup. In
2319 * that case, we need to use the broadcast station, so this
2320 * inline wraps that pattern.
2321 */
2322static inline int il_sta_id_or_broadcast(struct il_priv *il,
2323 struct il_rxon_context *context,
2324 struct ieee80211_sta *sta)
2325{
2326 int sta_id;
2327
2328 if (!sta)
2329 return context->bcast_sta_id;
2330
2331 sta_id = il_sta_id(sta);
2332
2333 /*
2334 * mac80211 should not be passing a partially
2335 * initialised station!
2336 */
2337 WARN_ON(sta_id == IL_INVALID_STATION);
2338
2339 return sta_id;
2340}
2341
2342/**
2343 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2344 * @idx -- current idx
2345 * @n_bd -- total number of entries in queue (must be power of 2)
2346 */
2347static inline int il_queue_inc_wrap(int idx, int n_bd)
2348{
2349 return ++idx & (n_bd - 1);
2350}
2351
2352/**
2353 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2354 * @idx -- current idx
2355 * @n_bd -- total number of entries in queue (must be power of 2)
2356 */
2357static inline int il_queue_dec_wrap(int idx, int n_bd)
2358{
2359 return --idx & (n_bd - 1);
2360}
2361
2362/* TODO: Move fw_desc functions to iwl-pci.ko */
2363static inline void il_free_fw_desc(struct pci_dev *pci_dev,
2364 struct fw_desc *desc)
2365{
2366 if (desc->v_addr)
2367 dma_free_coherent(&pci_dev->dev, desc->len,
2368 desc->v_addr, desc->p_addr);
2369 desc->v_addr = NULL;
2370 desc->len = 0;
2371}
2372
2373static inline int il_alloc_fw_desc(struct pci_dev *pci_dev,
2374 struct fw_desc *desc)
2375{
2376 if (!desc->len) {
2377 desc->v_addr = NULL;
2378 return -EINVAL;
2379 }
2380
2381 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2382 &desc->p_addr, GFP_KERNEL);
2383 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2384}
2385
2386/*
2387 * we have 8 bits used like this:
2388 *
2389 * 7 6 5 4 3 2 1 0
2390 * | | | | | | | |
2391 * | | | | | | +-+-------- AC queue (0-3)
2392 * | | | | | |
2393 * | +-+-+-+-+------------ HW queue ID
2394 * |
2395 * +---------------------- unused
2396 */
2397static inline void
2398il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2399{
2400 BUG_ON(ac > 3); /* only have 2 bits */
2401 BUG_ON(hwq > 31); /* only use 5 bits */
2402
2403 txq->swq_id = (hwq << 2) | ac;
2404}
2405
2406static inline void il_wake_queue(struct il_priv *il,
2407 struct il_tx_queue *txq)
2408{
2409 u8 queue = txq->swq_id;
2410 u8 ac = queue & 3;
2411 u8 hwq = (queue >> 2) & 0x1f;
2412
2413 if (test_and_clear_bit(hwq, il->queue_stopped))
2414 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2415 ieee80211_wake_queue(il->hw, ac);
2416}
2417
2418static inline void il_stop_queue(struct il_priv *il,
2419 struct il_tx_queue *txq)
2420{
2421 u8 queue = txq->swq_id;
2422 u8 ac = queue & 3;
2423 u8 hwq = (queue >> 2) & 0x1f;
2424
2425 if (!test_and_set_bit(hwq, il->queue_stopped))
2426 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2427 ieee80211_stop_queue(il->hw, ac);
2428}
2429
2430#ifdef ieee80211_stop_queue
2431#undef ieee80211_stop_queue
2432#endif
2433
2434#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2435
2436#ifdef ieee80211_wake_queue
2437#undef ieee80211_wake_queue
2438#endif
2439
2440#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2441
2442static inline void il_disable_interrupts(struct il_priv *il)
2443{
2444 clear_bit(S_INT_ENABLED, &il->status);
2445
2446 /* disable interrupts from uCode/NIC to host */
2447 _il_wr(il, CSR_INT_MASK, 0x00000000);
2448
2449 /* acknowledge/clear/reset any interrupts still pending
2450 * from uCode or flow handler (Rx/Tx DMA) */
2451 _il_wr(il, CSR_INT, 0xffffffff);
2452 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2453 D_ISR("Disabled interrupts\n");
2454}
2455
2456static inline void il_enable_rfkill_int(struct il_priv *il)
2457{
2458 D_ISR("Enabling rfkill interrupt\n");
2459 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2460}
2461
2462static inline void il_enable_interrupts(struct il_priv *il)
2463{
2464 D_ISR("Enabling interrupts\n");
2465 set_bit(S_INT_ENABLED, &il->status);
2466 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2467}
2468
2469/**
2470 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2471 * @il -- pointer to il_priv data structure
2472 * @tsf_bits -- number of bits need to shift for masking)
2473 */
2474static inline u32 il_beacon_time_mask_low(struct il_priv *il,
2475 u16 tsf_bits)
2476{
2477 return (1 << tsf_bits) - 1;
2478}
2479
2480/**
2481 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2482 * @il -- pointer to il_priv data structure
2483 * @tsf_bits -- number of bits need to shift for masking)
2484 */
2485static inline u32 il_beacon_time_mask_high(struct il_priv *il,
2486 u16 tsf_bits)
2487{
2488 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2489}
2490
2491/**
2492 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2493 *
2494 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2495 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2496 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2497 * in which the last frame was written to
2498 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2499 * which was transferred
2500 */
2501struct il_rb_status {
2502 __le16 closed_rb_num;
2503 __le16 closed_fr_num;
2504 __le16 finished_rb_num;
2505 __le16 finished_fr_nam;
2506 __le32 __unused; /* 3945 only */
2507} __packed;
2508
2509
2510#define TFD_QUEUE_SIZE_MAX (256)
2511#define TFD_QUEUE_SIZE_BC_DUP (64)
2512#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2513#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2514#define IL_NUM_OF_TBS 20
2515
2516static inline u8 il_get_dma_hi_addr(dma_addr_t addr)
2517{
2518 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2519}
2520/**
2521 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2522 *
2523 * This structure contains dma address and length of transmission address
2524 *
2525 * @lo: low [31:0] portion of the dma address of TX buffer
2526 * every even is unaligned on 16 bit boundary
2527 * @hi_n_len 0-3 [35:32] portion of dma
2528 * 4-15 length of the tx buffer
2529 */
2530struct il_tfd_tb {
2531 __le32 lo;
2532 __le16 hi_n_len;
2533} __packed;
2534
2535/**
2536 * struct il_tfd
2537 *
2538 * Transmit Frame Descriptor (TFD)
2539 *
2540 * @ __reserved1[3] reserved
2541 * @ num_tbs 0-4 number of active tbs
2542 * 5 reserved
2543 * 6-7 padding (not used)
2544 * @ tbs[20] transmit frame buffer descriptors
2545 * @ __pad padding
2546 *
2547 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2548 * Both driver and device share these circular buffers, each of which must be
2549 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2550 *
2551 * Driver must indicate the physical address of the base of each
2552 * circular buffer via the FH_MEM_CBBC_QUEUE registers.
2553 *
2554 * Each TFD contains pointer/size information for up to 20 data buffers
2555 * in host DRAM. These buffers collectively contain the (one) frame described
2556 * by the TFD. Each buffer must be a single contiguous block of memory within
2557 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2558 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2559 * Tx frame, up to 8 KBytes in size.
2560 *
2561 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2562 */
2563struct il_tfd {
2564 u8 __reserved1[3];
2565 u8 num_tbs;
2566 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2567 __le32 __pad;
2568} __packed;
2569/* PCI registers */
2570#define PCI_CFG_RETRY_TIMEOUT 0x041
2571
2572/* PCI register values */
2573#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2574#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2575
636#endif /* __il_core_h__ */ 2576#endif /* __il_core_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 18:03:53 -0500