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authorFranky Lin <frankyl@broadcom.com>2011-11-04 17:23:41 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-11-09 16:14:06 -0500
commit61213be4cc2201b58786464000113ecbfc9d2c99 (patch)
tree516ab27ba536c47b108924852a1b911edd072508 /drivers/net/wireless/brcm80211
parente12afb6c5d13ebff64d4a2feb97cce0c2d7e1128 (diff)
brcm80211: fmac: replace private SB macros with ssb_regs version
Use SSB macros in order to clean up brcmfmac code Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/brcm80211')
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c66
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h25
2 files changed, 28 insertions, 63 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
index e068107f5fae..62c462181455 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
@@ -18,6 +18,8 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/netdevice.h> 19#include <linux/netdevice.h>
20#include <linux/mmc/card.h> 20#include <linux/mmc/card.h>
21#include <linux/ssb/ssb_regs.h>
22
21#include <chipcommon.h> 23#include <chipcommon.h>
22#include <brcm_hw_ids.h> 24#include <brcm_hw_ids.h>
23#include <brcmu_wifi.h> 25#include <brcmu_wifi.h>
@@ -38,19 +40,9 @@
38#define BCM4329_CORE_ARM_BASE 0x18002000 40#define BCM4329_CORE_ARM_BASE 0x18002000
39#define BCM4329_RAMSIZE 0x48000 41#define BCM4329_RAMSIZE 0x48000
40 42
41
42/* SB regs */
43/* sbidhigh */
44#define SBIDH_RC_MASK 0x000f /* revision code */
45#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
46#define SBIDH_RCE_SHIFT 8
47#define SBCOREREV(sbidh) \ 43#define SBCOREREV(sbidh) \
48 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \ 44 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
49 ((sbidh) & SBIDH_RC_MASK)) 45 ((sbidh) & SSB_IDHIGH_RCLO))
50#define SBIDH_CC_MASK 0x8ff0 /* core code */
51#define SBIDH_CC_SHIFT 4
52#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
53#define SBIDH_VC_SHIFT 16
54 46
55#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) 47#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
56/* SDIO Pad drive strength to select value mappings */ 48/* SDIO Pad drive strength to select value mappings */
@@ -109,9 +101,9 @@ brcmf_sdio_chip_iscoreup(struct brcmf_sdio_dev *sdiodev,
109 101
110 regdata = brcmf_sdcard_reg_read(sdiodev, 102 regdata = brcmf_sdcard_reg_read(sdiodev,
111 CORE_SB(corebase, sbtmstatelow), 4); 103 CORE_SB(corebase, sbtmstatelow), 4);
112 regdata &= (SBTML_RESET | SBTML_REJ_MASK | 104 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
113 (SICF_CLOCK_EN << SBTML_SICF_SHIFT)); 105 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
114 return ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) == regdata); 106 return (SSB_TMSLOW_CLOCK == regdata);
115} 107}
116 108
117void 109void
@@ -121,12 +113,12 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
121 113
122 regdata = brcmf_sdcard_reg_read(sdiodev, 114 regdata = brcmf_sdcard_reg_read(sdiodev,
123 CORE_SB(corebase, sbtmstatelow), 4); 115 CORE_SB(corebase, sbtmstatelow), 4);
124 if (regdata & SBTML_RESET) 116 if (regdata & SSB_TMSLOW_RESET)
125 return; 117 return;
126 118
127 regdata = brcmf_sdcard_reg_read(sdiodev, 119 regdata = brcmf_sdcard_reg_read(sdiodev,
128 CORE_SB(corebase, sbtmstatelow), 4); 120 CORE_SB(corebase, sbtmstatelow), 4);
129 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) { 121 if ((regdata & SSB_TMSLOW_CLOCK) != 0) {
130 /* 122 /*
131 * set target reject and spin until busy is clear 123 * set target reject and spin until busy is clear
132 * (preserve core-specific bits) 124 * (preserve core-specific bits)
@@ -134,26 +126,26 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
134 regdata = brcmf_sdcard_reg_read(sdiodev, 126 regdata = brcmf_sdcard_reg_read(sdiodev,
135 CORE_SB(corebase, sbtmstatelow), 4); 127 CORE_SB(corebase, sbtmstatelow), 4);
136 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 128 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
137 4, regdata | SBTML_REJ); 129 4, regdata | SSB_TMSLOW_REJECT);
138 130
139 regdata = brcmf_sdcard_reg_read(sdiodev, 131 regdata = brcmf_sdcard_reg_read(sdiodev,
140 CORE_SB(corebase, sbtmstatelow), 4); 132 CORE_SB(corebase, sbtmstatelow), 4);
141 udelay(1); 133 udelay(1);
142 SPINWAIT((brcmf_sdcard_reg_read(sdiodev, 134 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
143 CORE_SB(corebase, sbtmstatehigh), 4) & 135 CORE_SB(corebase, sbtmstatehigh), 4) &
144 SBTMH_BUSY), 100000); 136 SSB_TMSHIGH_BUSY), 100000);
145 137
146 regdata = brcmf_sdcard_reg_read(sdiodev, 138 regdata = brcmf_sdcard_reg_read(sdiodev,
147 CORE_SB(corebase, sbtmstatehigh), 4); 139 CORE_SB(corebase, sbtmstatehigh), 4);
148 if (regdata & SBTMH_BUSY) 140 if (regdata & SSB_TMSHIGH_BUSY)
149 brcmf_dbg(ERROR, "core state still busy\n"); 141 brcmf_dbg(ERROR, "core state still busy\n");
150 142
151 regdata = brcmf_sdcard_reg_read(sdiodev, 143 regdata = brcmf_sdcard_reg_read(sdiodev,
152 CORE_SB(corebase, sbidlow), 4); 144 CORE_SB(corebase, sbidlow), 4);
153 if (regdata & SBIDL_INIT) { 145 if (regdata & SSB_IDLOW_INITIATOR) {
154 regdata = brcmf_sdcard_reg_read(sdiodev, 146 regdata = brcmf_sdcard_reg_read(sdiodev,
155 CORE_SB(corebase, sbimstate), 4) | 147 CORE_SB(corebase, sbimstate), 4) |
156 SBIM_RJ; 148 SSB_IMSTATE_REJECT;
157 brcmf_sdcard_reg_write(sdiodev, 149 brcmf_sdcard_reg_write(sdiodev,
158 CORE_SB(corebase, sbimstate), 4, 150 CORE_SB(corebase, sbimstate), 4,
159 regdata); 151 regdata);
@@ -162,14 +154,14 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
162 udelay(1); 154 udelay(1);
163 SPINWAIT((brcmf_sdcard_reg_read(sdiodev, 155 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
164 CORE_SB(corebase, sbimstate), 4) & 156 CORE_SB(corebase, sbimstate), 4) &
165 SBIM_BY), 100000); 157 SSB_IMSTATE_BUSY), 100000);
166 } 158 }
167 159
168 /* set reset and reject while enabling the clocks */ 160 /* set reset and reject while enabling the clocks */
169 brcmf_sdcard_reg_write(sdiodev, 161 brcmf_sdcard_reg_write(sdiodev,
170 CORE_SB(corebase, sbtmstatelow), 4, 162 CORE_SB(corebase, sbtmstatelow), 4,
171 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) | 163 (SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
172 SBTML_REJ | SBTML_RESET)); 164 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
173 regdata = brcmf_sdcard_reg_read(sdiodev, 165 regdata = brcmf_sdcard_reg_read(sdiodev,
174 CORE_SB(corebase, sbtmstatelow), 4); 166 CORE_SB(corebase, sbtmstatelow), 4);
175 udelay(10); 167 udelay(10);
@@ -177,10 +169,10 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
177 /* clear the initiator reject bit */ 169 /* clear the initiator reject bit */
178 regdata = brcmf_sdcard_reg_read(sdiodev, 170 regdata = brcmf_sdcard_reg_read(sdiodev,
179 CORE_SB(corebase, sbidlow), 4); 171 CORE_SB(corebase, sbidlow), 4);
180 if (regdata & SBIDL_INIT) { 172 if (regdata & SSB_IDLOW_INITIATOR) {
181 regdata = brcmf_sdcard_reg_read(sdiodev, 173 regdata = brcmf_sdcard_reg_read(sdiodev,
182 CORE_SB(corebase, sbimstate), 4) & 174 CORE_SB(corebase, sbimstate), 4) &
183 ~SBIM_RJ; 175 ~SSB_IMSTATE_REJECT;
184 brcmf_sdcard_reg_write(sdiodev, 176 brcmf_sdcard_reg_write(sdiodev,
185 CORE_SB(corebase, sbimstate), 4, 177 CORE_SB(corebase, sbimstate), 4,
186 regdata); 178 regdata);
@@ -189,7 +181,7 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
189 181
190 /* leave reset and reject asserted */ 182 /* leave reset and reject asserted */
191 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, 183 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
192 (SBTML_REJ | SBTML_RESET)); 184 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
193 udelay(1); 185 udelay(1);
194} 186}
195 187
@@ -210,31 +202,29 @@ brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
210 * forcing them on throughout the core 202 * forcing them on throughout the core
211 */ 203 */
212 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, 204 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
213 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) | 205 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET);
214 SBTML_RESET);
215 udelay(1); 206 udelay(1);
216 207
217 regdata = brcmf_sdcard_reg_read(sdiodev, 208 regdata = brcmf_sdcard_reg_read(sdiodev,
218 CORE_SB(corebase, sbtmstatehigh), 4); 209 CORE_SB(corebase, sbtmstatehigh), 4);
219 if (regdata & SBTMH_SERR) 210 if (regdata & SSB_TMSHIGH_SERR)
220 brcmf_sdcard_reg_write(sdiodev, 211 brcmf_sdcard_reg_write(sdiodev,
221 CORE_SB(corebase, sbtmstatehigh), 4, 0); 212 CORE_SB(corebase, sbtmstatehigh), 4, 0);
222 213
223 regdata = brcmf_sdcard_reg_read(sdiodev, 214 regdata = brcmf_sdcard_reg_read(sdiodev,
224 CORE_SB(corebase, sbimstate), 4); 215 CORE_SB(corebase, sbimstate), 4);
225 if (regdata & (SBIM_IBE | SBIM_TO)) 216 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO))
226 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4, 217 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
227 regdata & ~(SBIM_IBE | SBIM_TO)); 218 regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO));
228 219
229 /* clear reset and allow it to propagate throughout the core */ 220 /* clear reset and allow it to propagate throughout the core */
230 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, 221 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
231 (SICF_FGC << SBTML_SICF_SHIFT) | 222 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
232 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
233 udelay(1); 223 udelay(1);
234 224
235 /* leave clock enabled */ 225 /* leave clock enabled */
236 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, 226 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
237 (SICF_CLOCK_EN << SBTML_SICF_SHIFT)); 227 4, SSB_TMSLOW_CLOCK);
238 udelay(1); 228 udelay(1);
239} 229}
240 230
@@ -345,7 +335,7 @@ brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
345 ci->buscorerev = brcmf_sdio_chip_corerev(sdiodev, ci->buscorebase); 335 ci->buscorerev = brcmf_sdio_chip_corerev(sdiodev, ci->buscorebase);
346 regdata = brcmf_sdcard_reg_read(sdiodev, 336 regdata = brcmf_sdcard_reg_read(sdiodev,
347 CORE_SB(ci->buscorebase, sbidhigh), 4); 337 CORE_SB(ci->buscorebase, sbidhigh), 4);
348 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT; 338 ci->buscoretype = (regdata & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
349 339
350 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n", 340 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
351 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype); 341 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
index e816bb69959c..638374645198 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
@@ -52,31 +52,6 @@
52#define SBSDIO_CLKAV(regval, alponly) \ 52#define SBSDIO_CLKAV(regval, alponly) \
53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
54 54
55/* sbimstate */
56#define SBIM_IBE 0x20000 /* inbanderror */
57#define SBIM_TO 0x40000 /* timeout */
58#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
59#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
60
61/* sbtmstatelow */
62#define SBTML_RESET 0x0001 /* reset */
63#define SBTML_REJ_MASK 0x0006 /* reject field */
64#define SBTML_REJ 0x0002 /* reject */
65#define SBTML_TMPREJ 0x0004 /* temporary reject(error recovery) */
66/* Shift to locate the SI control flags in sbtml */
67#define SBTML_SICF_SHIFT 16
68
69/* sbtmstatehigh */
70#define SBTMH_SERR 0x0001 /* serror */
71#define SBTMH_INT 0x0002 /* interrupt */
72#define SBTMH_BUSY 0x0004 /* busy */
73#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
74/* Shift to locate the SI status flags in sbtmh */
75#define SBTMH_SISF_SHIFT 16
76
77/* sbidlow */
78#define SBIDL_INIT 0x80 /* initiator */
79
80struct chip_info { 55struct chip_info {
81 u32 chip; 56 u32 chip;
82 u32 chiprev; 57 u32 chiprev;