diff options
author | John W. Linville <linville@tuxdriver.com> | 2012-05-22 15:18:06 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2012-05-22 15:18:06 -0400 |
commit | a0d0d1685f9763ab26a394df3ab84026b39a06a7 (patch) | |
tree | 4165dc6fd3266977ab4b3fa3b379c47597f97d88 /drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c | |
parent | 31a67102f4762df5544bc2dfb34a931233d2a5b2 (diff) | |
parent | 05f8f25276ea8c7d41b3649890d6eaf179e67a81 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next
Diffstat (limited to 'drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c')
-rw-r--r-- | drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c | 265 |
1 files changed, 138 insertions, 127 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c index 1534efc21631..f8e1f1c84d08 100644 --- a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c +++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c | |||
@@ -93,8 +93,9 @@ brcmf_sdio_sb_corerev(struct brcmf_sdio_dev *sdiodev, | |||
93 | 93 | ||
94 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); | 94 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
95 | 95 | ||
96 | regdata = brcmf_sdcard_reg_read(sdiodev, | 96 | regdata = brcmf_sdio_regrl(sdiodev, |
97 | CORE_SB(ci->c_inf[idx].base, sbidhigh), 4); | 97 | CORE_SB(ci->c_inf[idx].base, sbidhigh), |
98 | NULL); | ||
98 | return SBCOREREV(regdata); | 99 | return SBCOREREV(regdata); |
99 | } | 100 | } |
100 | 101 | ||
@@ -118,8 +119,9 @@ brcmf_sdio_sb_iscoreup(struct brcmf_sdio_dev *sdiodev, | |||
118 | 119 | ||
119 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); | 120 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
120 | 121 | ||
121 | regdata = brcmf_sdcard_reg_read(sdiodev, | 122 | regdata = brcmf_sdio_regrl(sdiodev, |
122 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | 123 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
124 | NULL); | ||
123 | regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT | | 125 | regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT | |
124 | SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK); | 126 | SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK); |
125 | return (SSB_TMSLOW_CLOCK == regdata); | 127 | return (SSB_TMSLOW_CLOCK == regdata); |
@@ -135,13 +137,13 @@ brcmf_sdio_ai_iscoreup(struct brcmf_sdio_dev *sdiodev, | |||
135 | 137 | ||
136 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); | 138 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
137 | 139 | ||
138 | regdata = brcmf_sdcard_reg_read(sdiodev, | 140 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
139 | ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4); | 141 | NULL); |
140 | ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK; | 142 | ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK; |
141 | 143 | ||
142 | regdata = brcmf_sdcard_reg_read(sdiodev, | 144 | regdata = brcmf_sdio_regrl(sdiodev, |
143 | ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, | 145 | ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
144 | 4); | 146 | NULL); |
145 | ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0); | 147 | ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0); |
146 | 148 | ||
147 | return ret; | 149 | return ret; |
@@ -151,84 +153,85 @@ static void | |||
151 | brcmf_sdio_sb_coredisable(struct brcmf_sdio_dev *sdiodev, | 153 | brcmf_sdio_sb_coredisable(struct brcmf_sdio_dev *sdiodev, |
152 | struct chip_info *ci, u16 coreid) | 154 | struct chip_info *ci, u16 coreid) |
153 | { | 155 | { |
154 | u32 regdata; | 156 | u32 regdata, base; |
155 | u8 idx; | 157 | u8 idx; |
156 | 158 | ||
157 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); | 159 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
160 | base = ci->c_inf[idx].base; | ||
158 | 161 | ||
159 | regdata = brcmf_sdcard_reg_read(sdiodev, | 162 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL); |
160 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | ||
161 | if (regdata & SSB_TMSLOW_RESET) | 163 | if (regdata & SSB_TMSLOW_RESET) |
162 | return; | 164 | return; |
163 | 165 | ||
164 | regdata = brcmf_sdcard_reg_read(sdiodev, | 166 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL); |
165 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | ||
166 | if ((regdata & SSB_TMSLOW_CLOCK) != 0) { | 167 | if ((regdata & SSB_TMSLOW_CLOCK) != 0) { |
167 | /* | 168 | /* |
168 | * set target reject and spin until busy is clear | 169 | * set target reject and spin until busy is clear |
169 | * (preserve core-specific bits) | 170 | * (preserve core-specific bits) |
170 | */ | 171 | */ |
171 | regdata = brcmf_sdcard_reg_read(sdiodev, | 172 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), |
172 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | 173 | NULL); |
173 | brcmf_sdcard_reg_write(sdiodev, | 174 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow), |
174 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), | 175 | regdata | SSB_TMSLOW_REJECT, NULL); |
175 | 4, regdata | SSB_TMSLOW_REJECT); | 176 | |
176 | 177 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), | |
177 | regdata = brcmf_sdcard_reg_read(sdiodev, | 178 | NULL); |
178 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | ||
179 | udelay(1); | 179 | udelay(1); |
180 | SPINWAIT((brcmf_sdcard_reg_read(sdiodev, | 180 | SPINWAIT((brcmf_sdio_regrl(sdiodev, |
181 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4) & | 181 | CORE_SB(base, sbtmstatehigh), |
182 | NULL) & | ||
182 | SSB_TMSHIGH_BUSY), 100000); | 183 | SSB_TMSHIGH_BUSY), 100000); |
183 | 184 | ||
184 | regdata = brcmf_sdcard_reg_read(sdiodev, | 185 | regdata = brcmf_sdio_regrl(sdiodev, |
185 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4); | 186 | CORE_SB(base, sbtmstatehigh), |
187 | NULL); | ||
186 | if (regdata & SSB_TMSHIGH_BUSY) | 188 | if (regdata & SSB_TMSHIGH_BUSY) |
187 | brcmf_dbg(ERROR, "core state still busy\n"); | 189 | brcmf_dbg(ERROR, "core state still busy\n"); |
188 | 190 | ||
189 | regdata = brcmf_sdcard_reg_read(sdiodev, | 191 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbidlow), |
190 | CORE_SB(ci->c_inf[idx].base, sbidlow), 4); | 192 | NULL); |
191 | if (regdata & SSB_IDLOW_INITIATOR) { | 193 | if (regdata & SSB_IDLOW_INITIATOR) { |
192 | regdata = brcmf_sdcard_reg_read(sdiodev, | 194 | regdata = brcmf_sdio_regrl(sdiodev, |
193 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4) | | 195 | CORE_SB(base, sbimstate), |
194 | SSB_IMSTATE_REJECT; | 196 | NULL); |
195 | brcmf_sdcard_reg_write(sdiodev, | 197 | regdata |= SSB_IMSTATE_REJECT; |
196 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4, | 198 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbimstate), |
197 | regdata); | 199 | regdata, NULL); |
198 | regdata = brcmf_sdcard_reg_read(sdiodev, | 200 | regdata = brcmf_sdio_regrl(sdiodev, |
199 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4); | 201 | CORE_SB(base, sbimstate), |
202 | NULL); | ||
200 | udelay(1); | 203 | udelay(1); |
201 | SPINWAIT((brcmf_sdcard_reg_read(sdiodev, | 204 | SPINWAIT((brcmf_sdio_regrl(sdiodev, |
202 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4) & | 205 | CORE_SB(base, sbimstate), |
206 | NULL) & | ||
203 | SSB_IMSTATE_BUSY), 100000); | 207 | SSB_IMSTATE_BUSY), 100000); |
204 | } | 208 | } |
205 | 209 | ||
206 | /* set reset and reject while enabling the clocks */ | 210 | /* set reset and reject while enabling the clocks */ |
207 | brcmf_sdcard_reg_write(sdiodev, | 211 | regdata = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
208 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4, | 212 | SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET; |
209 | (SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | | 213 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow), |
210 | SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET)); | 214 | regdata, NULL); |
211 | regdata = brcmf_sdcard_reg_read(sdiodev, | 215 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), |
212 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | 216 | NULL); |
213 | udelay(10); | 217 | udelay(10); |
214 | 218 | ||
215 | /* clear the initiator reject bit */ | 219 | /* clear the initiator reject bit */ |
216 | regdata = brcmf_sdcard_reg_read(sdiodev, | 220 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbidlow), |
217 | CORE_SB(ci->c_inf[idx].base, sbidlow), 4); | 221 | NULL); |
218 | if (regdata & SSB_IDLOW_INITIATOR) { | 222 | if (regdata & SSB_IDLOW_INITIATOR) { |
219 | regdata = brcmf_sdcard_reg_read(sdiodev, | 223 | regdata = brcmf_sdio_regrl(sdiodev, |
220 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4) & | 224 | CORE_SB(base, sbimstate), |
221 | ~SSB_IMSTATE_REJECT; | 225 | NULL); |
222 | brcmf_sdcard_reg_write(sdiodev, | 226 | regdata &= ~SSB_IMSTATE_REJECT; |
223 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4, | 227 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbimstate), |
224 | regdata); | 228 | regdata, NULL); |
225 | } | 229 | } |
226 | } | 230 | } |
227 | 231 | ||
228 | /* leave reset and reject asserted */ | 232 | /* leave reset and reject asserted */ |
229 | brcmf_sdcard_reg_write(sdiodev, | 233 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow), |
230 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4, | 234 | (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET), NULL); |
231 | (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET)); | ||
232 | udelay(1); | 235 | udelay(1); |
233 | } | 236 | } |
234 | 237 | ||
@@ -242,20 +245,19 @@ brcmf_sdio_ai_coredisable(struct brcmf_sdio_dev *sdiodev, | |||
242 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); | 245 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
243 | 246 | ||
244 | /* if core is already in reset, just return */ | 247 | /* if core is already in reset, just return */ |
245 | regdata = brcmf_sdcard_reg_read(sdiodev, | 248 | regdata = brcmf_sdio_regrl(sdiodev, |
246 | ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, | 249 | ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
247 | 4); | 250 | NULL); |
248 | if ((regdata & BCMA_RESET_CTL_RESET) != 0) | 251 | if ((regdata & BCMA_RESET_CTL_RESET) != 0) |
249 | return; | 252 | return; |
250 | 253 | ||
251 | brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, | 254 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, 0, NULL); |
252 | 4, 0); | 255 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
253 | regdata = brcmf_sdcard_reg_read(sdiodev, | 256 | NULL); |
254 | ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4); | ||
255 | udelay(10); | 257 | udelay(10); |
256 | 258 | ||
257 | brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, | 259 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
258 | 4, BCMA_RESET_CTL_RESET); | 260 | BCMA_RESET_CTL_RESET, NULL); |
259 | udelay(1); | 261 | udelay(1); |
260 | } | 262 | } |
261 | 263 | ||
@@ -279,41 +281,47 @@ brcmf_sdio_sb_resetcore(struct brcmf_sdio_dev *sdiodev, | |||
279 | * set reset while enabling the clock and | 281 | * set reset while enabling the clock and |
280 | * forcing them on throughout the core | 282 | * forcing them on throughout the core |
281 | */ | 283 | */ |
282 | brcmf_sdcard_reg_write(sdiodev, | 284 | brcmf_sdio_regwl(sdiodev, |
283 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4, | 285 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
284 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET); | 286 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET, |
285 | regdata = brcmf_sdcard_reg_read(sdiodev, | 287 | NULL); |
286 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | 288 | regdata = brcmf_sdio_regrl(sdiodev, |
289 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), | ||
290 | NULL); | ||
287 | udelay(1); | 291 | udelay(1); |
288 | 292 | ||
289 | /* clear any serror */ | 293 | /* clear any serror */ |
290 | regdata = brcmf_sdcard_reg_read(sdiodev, | 294 | regdata = brcmf_sdio_regrl(sdiodev, |
291 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4); | 295 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), |
296 | NULL); | ||
292 | if (regdata & SSB_TMSHIGH_SERR) | 297 | if (regdata & SSB_TMSHIGH_SERR) |
293 | brcmf_sdcard_reg_write(sdiodev, | 298 | brcmf_sdio_regwl(sdiodev, |
294 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4, 0); | 299 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), |
300 | 0, NULL); | ||
295 | 301 | ||
296 | regdata = brcmf_sdcard_reg_read(sdiodev, | 302 | regdata = brcmf_sdio_regrl(sdiodev, |
297 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4); | 303 | CORE_SB(ci->c_inf[idx].base, sbimstate), |
304 | NULL); | ||
298 | if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) | 305 | if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) |
299 | brcmf_sdcard_reg_write(sdiodev, | 306 | brcmf_sdio_regwl(sdiodev, |
300 | CORE_SB(ci->c_inf[idx].base, sbimstate), 4, | 307 | CORE_SB(ci->c_inf[idx].base, sbimstate), |
301 | regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO)); | 308 | regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO), |
309 | NULL); | ||
302 | 310 | ||
303 | /* clear reset and allow it to propagate throughout the core */ | 311 | /* clear reset and allow it to propagate throughout the core */ |
304 | brcmf_sdcard_reg_write(sdiodev, | 312 | brcmf_sdio_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
305 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4, | 313 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK, NULL); |
306 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK); | 314 | regdata = brcmf_sdio_regrl(sdiodev, |
307 | regdata = brcmf_sdcard_reg_read(sdiodev, | 315 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
308 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | 316 | NULL); |
309 | udelay(1); | 317 | udelay(1); |
310 | 318 | ||
311 | /* leave clock enabled */ | 319 | /* leave clock enabled */ |
312 | brcmf_sdcard_reg_write(sdiodev, | 320 | brcmf_sdio_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
313 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), | 321 | SSB_TMSLOW_CLOCK, NULL); |
314 | 4, SSB_TMSLOW_CLOCK); | 322 | regdata = brcmf_sdio_regrl(sdiodev, |
315 | regdata = brcmf_sdcard_reg_read(sdiodev, | 323 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
316 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4); | 324 | NULL); |
317 | udelay(1); | 325 | udelay(1); |
318 | } | 326 | } |
319 | 327 | ||
@@ -330,18 +338,18 @@ brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev, | |||
330 | brcmf_sdio_ai_coredisable(sdiodev, ci, coreid); | 338 | brcmf_sdio_ai_coredisable(sdiodev, ci, coreid); |
331 | 339 | ||
332 | /* now do initialization sequence */ | 340 | /* now do initialization sequence */ |
333 | brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, | 341 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
334 | 4, BCMA_IOCTL_FGC | BCMA_IOCTL_CLK); | 342 | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK, NULL); |
335 | regdata = brcmf_sdcard_reg_read(sdiodev, | 343 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
336 | ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4); | 344 | NULL); |
337 | brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, | 345 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
338 | 4, 0); | 346 | 0, NULL); |
339 | udelay(1); | 347 | udelay(1); |
340 | 348 | ||
341 | brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, | 349 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
342 | 4, BCMA_IOCTL_CLK); | 350 | BCMA_IOCTL_CLK, NULL); |
343 | regdata = brcmf_sdcard_reg_read(sdiodev, | 351 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
344 | ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4); | 352 | NULL); |
345 | udelay(1); | 353 | udelay(1); |
346 | } | 354 | } |
347 | 355 | ||
@@ -358,8 +366,9 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev, | |||
358 | */ | 366 | */ |
359 | ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON; | 367 | ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON; |
360 | ci->c_inf[0].base = regs; | 368 | ci->c_inf[0].base = regs; |
361 | regdata = brcmf_sdcard_reg_read(sdiodev, | 369 | regdata = brcmf_sdio_regrl(sdiodev, |
362 | CORE_CC_REG(ci->c_inf[0].base, chipid), 4); | 370 | CORE_CC_REG(ci->c_inf[0].base, chipid), |
371 | NULL); | ||
363 | ci->chip = regdata & CID_ID_MASK; | 372 | ci->chip = regdata & CID_ID_MASK; |
364 | ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; | 373 | ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; |
365 | ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT; | 374 | ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT; |
@@ -428,8 +437,7 @@ brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev) | |||
428 | 437 | ||
429 | /* Try forcing SDIO core to do ALPAvail request only */ | 438 | /* Try forcing SDIO core to do ALPAvail request only */ |
430 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | 439 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; |
431 | brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1, | 440 | brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); |
432 | SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | ||
433 | if (err) { | 441 | if (err) { |
434 | brcmf_dbg(ERROR, "error writing for HT off\n"); | 442 | brcmf_dbg(ERROR, "error writing for HT off\n"); |
435 | return err; | 443 | return err; |
@@ -437,8 +445,8 @@ brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev) | |||
437 | 445 | ||
438 | /* If register supported, wait for ALPAvail and then force ALP */ | 446 | /* If register supported, wait for ALPAvail and then force ALP */ |
439 | /* This may take up to 15 milliseconds */ | 447 | /* This may take up to 15 milliseconds */ |
440 | clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1, | 448 | clkval = brcmf_sdio_regrb(sdiodev, |
441 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | 449 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); |
442 | 450 | ||
443 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { | 451 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { |
444 | brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n", | 452 | brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n", |
@@ -446,8 +454,8 @@ brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev) | |||
446 | return -EACCES; | 454 | return -EACCES; |
447 | } | 455 | } |
448 | 456 | ||
449 | SPINWAIT(((clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1, | 457 | SPINWAIT(((clkval = brcmf_sdio_regrb(sdiodev, |
450 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), | 458 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), |
451 | !SBSDIO_ALPAV(clkval)), | 459 | !SBSDIO_ALPAV(clkval)), |
452 | PMU_MAX_TRANSITION_DLY); | 460 | PMU_MAX_TRANSITION_DLY); |
453 | if (!SBSDIO_ALPAV(clkval)) { | 461 | if (!SBSDIO_ALPAV(clkval)) { |
@@ -457,13 +465,11 @@ brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev) | |||
457 | } | 465 | } |
458 | 466 | ||
459 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; | 467 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; |
460 | brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1, | 468 | brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); |
461 | SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | ||
462 | udelay(65); | 469 | udelay(65); |
463 | 470 | ||
464 | /* Also, disable the extra SDIO pull-ups */ | 471 | /* Also, disable the extra SDIO pull-ups */ |
465 | brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1, | 472 | brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); |
466 | SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); | ||
467 | 473 | ||
468 | return 0; | 474 | return 0; |
469 | } | 475 | } |
@@ -472,18 +478,22 @@ static void | |||
472 | brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev, | 478 | brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev, |
473 | struct chip_info *ci) | 479 | struct chip_info *ci) |
474 | { | 480 | { |
481 | u32 base = ci->c_inf[0].base; | ||
482 | |||
475 | /* get chipcommon rev */ | 483 | /* get chipcommon rev */ |
476 | ci->c_inf[0].rev = ci->corerev(sdiodev, ci, ci->c_inf[0].id); | 484 | ci->c_inf[0].rev = ci->corerev(sdiodev, ci, ci->c_inf[0].id); |
477 | 485 | ||
478 | /* get chipcommon capabilites */ | 486 | /* get chipcommon capabilites */ |
479 | ci->c_inf[0].caps = | 487 | ci->c_inf[0].caps = brcmf_sdio_regrl(sdiodev, |
480 | brcmf_sdcard_reg_read(sdiodev, | 488 | CORE_CC_REG(base, capabilities), |
481 | CORE_CC_REG(ci->c_inf[0].base, capabilities), 4); | 489 | NULL); |
482 | 490 | ||
483 | /* get pmu caps & rev */ | 491 | /* get pmu caps & rev */ |
484 | if (ci->c_inf[0].caps & CC_CAP_PMU) { | 492 | if (ci->c_inf[0].caps & CC_CAP_PMU) { |
485 | ci->pmucaps = brcmf_sdcard_reg_read(sdiodev, | 493 | ci->pmucaps = |
486 | CORE_CC_REG(ci->c_inf[0].base, pmucapabilities), 4); | 494 | brcmf_sdio_regrl(sdiodev, |
495 | CORE_CC_REG(base, pmucapabilities), | ||
496 | NULL); | ||
487 | ci->pmurev = ci->pmucaps & PCAP_REV_MASK; | 497 | ci->pmurev = ci->pmucaps & PCAP_REV_MASK; |
488 | } | 498 | } |
489 | 499 | ||
@@ -523,10 +533,10 @@ int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev, | |||
523 | 533 | ||
524 | brcmf_sdio_chip_buscoresetup(sdiodev, ci); | 534 | brcmf_sdio_chip_buscoresetup(sdiodev, ci); |
525 | 535 | ||
526 | brcmf_sdcard_reg_write(sdiodev, | 536 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopullup), |
527 | CORE_CC_REG(ci->c_inf[0].base, gpiopullup), 4, 0); | 537 | 0, NULL); |
528 | brcmf_sdcard_reg_write(sdiodev, | 538 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopulldown), |
529 | CORE_CC_REG(ci->c_inf[0].base, gpiopulldown), 4, 0); | 539 | 0, NULL); |
530 | 540 | ||
531 | *ci_ptr = ci; | 541 | *ci_ptr = ci; |
532 | return 0; | 542 | return 0; |
@@ -562,6 +572,7 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, | |||
562 | u32 str_mask = 0; | 572 | u32 str_mask = 0; |
563 | u32 str_shift = 0; | 573 | u32 str_shift = 0; |
564 | char chn[8]; | 574 | char chn[8]; |
575 | u32 base = ci->c_inf[0].base; | ||
565 | 576 | ||
566 | if (!(ci->c_inf[0].caps & CC_CAP_PMU)) | 577 | if (!(ci->c_inf[0].caps & CC_CAP_PMU)) |
567 | return; | 578 | return; |
@@ -591,17 +602,17 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, | |||
591 | } | 602 | } |
592 | } | 603 | } |
593 | 604 | ||
594 | brcmf_sdcard_reg_write(sdiodev, | 605 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(base, chipcontrol_addr), |
595 | CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr), | 606 | 1, NULL); |
596 | 4, 1); | 607 | cc_data_temp = |
597 | cc_data_temp = brcmf_sdcard_reg_read(sdiodev, | 608 | brcmf_sdio_regrl(sdiodev, |
598 | CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr), 4); | 609 | CORE_CC_REG(base, chipcontrol_addr), |
610 | NULL); | ||
599 | cc_data_temp &= ~str_mask; | 611 | cc_data_temp &= ~str_mask; |
600 | drivestrength_sel <<= str_shift; | 612 | drivestrength_sel <<= str_shift; |
601 | cc_data_temp |= drivestrength_sel; | 613 | cc_data_temp |= drivestrength_sel; |
602 | brcmf_sdcard_reg_write(sdiodev, | 614 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(base, chipcontrol_addr), |
603 | CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr), | 615 | cc_data_temp, NULL); |
604 | 4, cc_data_temp); | ||
605 | 616 | ||
606 | brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n", | 617 | brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n", |
607 | drivestrength, cc_data_temp); | 618 | drivestrength, cc_data_temp); |