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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-02 16:38:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-02 16:38:27 -0400
commitaecdc33e111b2c447b622e287c6003726daa1426 (patch)
tree3e7657eae4b785e1a1fb5dfb225dbae0b2f0cfc6 /drivers/net/wireless/b43
parenta20acf99f75e49271381d65db097c9763060a1e8 (diff)
parenta3a6cab5ea10cca64d036851fe0d932448f2fe4f (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking changes from David Miller: 1) GRE now works over ipv6, from Dmitry Kozlov. 2) Make SCTP more network namespace aware, from Eric Biederman. 3) TEAM driver now works with non-ethernet devices, from Jiri Pirko. 4) Make openvswitch network namespace aware, from Pravin B Shelar. 5) IPV6 NAT implementation, from Patrick McHardy. 6) Server side support for TCP Fast Open, from Jerry Chu and others. 7) Packet BPF filter supports MOD and XOR, from Eric Dumazet and Daniel Borkmann. 8) Increate the loopback default MTU to 64K, from Eric Dumazet. 9) Use a per-task rather than per-socket page fragment allocator for outgoing networking traffic. This benefits processes that have very many mostly idle sockets, which is quite common. From Eric Dumazet. 10) Use up to 32K for page fragment allocations, with fallbacks to smaller sizes when higher order page allocations fail. Benefits are a) less segments for driver to process b) less calls to page allocator c) less waste of space. From Eric Dumazet. 11) Allow GRO to be used on GRE tunnels, from Eric Dumazet. 12) VXLAN device driver, one way to handle VLAN issues such as the limitation of 4096 VLAN IDs yet still have some level of isolation. From Stephen Hemminger. 13) As usual there is a large boatload of driver changes, with the scale perhaps tilted towards the wireless side this time around. Fix up various fairly trivial conflicts, mostly caused by the user namespace changes. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1012 commits) hyperv: Add buffer for extended info after the RNDIS response message. hyperv: Report actual status in receive completion packet hyperv: Remove extra allocated space for recv_pkt_list elements hyperv: Fix page buffer handling in rndis_filter_send_request() hyperv: Fix the missing return value in rndis_filter_set_packet_filter() hyperv: Fix the max_xfer_size in RNDIS initialization vxlan: put UDP socket in correct namespace vxlan: Depend on CONFIG_INET sfc: Fix the reported priorities of different filter types sfc: Remove EFX_FILTER_FLAG_RX_OVERRIDE_IP sfc: Fix loopback self-test with separate_tx_channels=1 sfc: Fix MCDI structure field lookup sfc: Add parentheses around use of bitfield macro arguments sfc: Fix null function pointer in efx_sriov_channel_type vxlan: virtual extensible lan igmp: export symbol ip_mc_leave_group netlink: add attributes to fdb interface tg3: unconditionally select HWMON support when tg3 is enabled. Revert "net: ti cpsw ethernet: allow reading phy interface mode from DT" gre: fix sparse warning ...
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r--drivers/net/wireless/b43/Makefile1
-rw-r--r--drivers/net/wireless/b43/b43.h10
-rw-r--r--drivers/net/wireless/b43/main.c54
-rw-r--r--drivers/net/wireless/b43/phy_common.c17
-rw-r--r--drivers/net/wireless/b43/phy_common.h6
-rw-r--r--drivers/net/wireless/b43/phy_n.c668
-rw-r--r--drivers/net/wireless/b43/phy_n.h1
-rw-r--r--drivers/net/wireless/b43/radio_2057.c141
-rw-r--r--drivers/net/wireless/b43/radio_2057.h430
-rw-r--r--drivers/net/wireless/b43/tables_nphy.c75
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h10
11 files changed, 1358 insertions, 55 deletions
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 4648bbf76abc..098fe9ee7096 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -4,6 +4,7 @@ b43-y += tables.o
4b43-$(CONFIG_B43_PHY_N) += tables_nphy.o 4b43-$(CONFIG_B43_PHY_N) += tables_nphy.o
5b43-$(CONFIG_B43_PHY_N) += radio_2055.o 5b43-$(CONFIG_B43_PHY_N) += radio_2055.o
6b43-$(CONFIG_B43_PHY_N) += radio_2056.o 6b43-$(CONFIG_B43_PHY_N) += radio_2056.o
7b43-$(CONFIG_B43_PHY_N) += radio_2057.o
7b43-y += phy_common.o 8b43-y += phy_common.o
8b43-y += phy_g.o 9b43-y += phy_g.o
9b43-y += phy_a.o 10b43-y += phy_a.o
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 7c899fc7ddd0..b298e5d68be2 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -241,16 +241,18 @@ enum {
241#define B43_SHM_SH_PHYVER 0x0050 /* PHY version */ 241#define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
242#define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */ 242#define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
243#define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */ 243#define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
244#define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */ 244#define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */
245#define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */ 245#define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */
246#define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */ 246#define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */
247#define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */ 247#define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
248#define B43_SHM_SH_RADAR 0x0066 /* Radar register */ 248#define B43_SHM_SH_RADAR 0x0066 /* Radar register */
249#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */ 249#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
250#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */ 250#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
251#define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */
251#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ 252#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
252#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */ 253#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
253#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */ 254#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
255#define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */
254#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ 256#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
255/* TSSI information */ 257/* TSSI information */
256#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */ 258#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
@@ -415,6 +417,8 @@ enum {
415#define B43_PHYTYPE_HT 0x07 417#define B43_PHYTYPE_HT 0x07
416#define B43_PHYTYPE_LCN 0x08 418#define B43_PHYTYPE_LCN 0x08
417#define B43_PHYTYPE_LCNXN 0x09 419#define B43_PHYTYPE_LCNXN 0x09
420#define B43_PHYTYPE_LCN40 0x0a
421#define B43_PHYTYPE_AC 0x0b
418 422
419/* PHYRegisters */ 423/* PHYRegisters */
420#define B43_PHY_ILT_A_CTRL 0x0072 424#define B43_PHY_ILT_A_CTRL 0x0072
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index a140165dfee0..73730e94e0ac 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -533,11 +533,11 @@ u64 b43_hf_read(struct b43_wldev *dev)
533{ 533{
534 u64 ret; 534 u64 ret;
535 535
536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
537 ret <<= 16; 537 ret <<= 16;
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
539 ret <<= 16; 539 ret <<= 16;
540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
541 541
542 return ret; 542 return ret;
543} 543}
@@ -550,9 +550,9 @@ void b43_hf_write(struct b43_wldev *dev, u64 value)
550 lo = (value & 0x00000000FFFFULL); 550 lo = (value & 0x00000000FFFFULL);
551 mi = (value & 0x0000FFFF0000ULL) >> 16; 551 mi = (value & 0x0000FFFF0000ULL) >> 16;
552 hi = (value & 0xFFFF00000000ULL) >> 32; 552 hi = (value & 0xFFFF00000000ULL) >> 32;
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
556} 556}
557 557
558/* Read the firmware capabilities bitmask (Opensource firmware only) */ 558/* Read the firmware capabilities bitmask (Opensource firmware only) */
@@ -3412,7 +3412,8 @@ static void b43_tx_work(struct work_struct *work)
3412} 3412}
3413 3413
3414static void b43_op_tx(struct ieee80211_hw *hw, 3414static void b43_op_tx(struct ieee80211_hw *hw,
3415 struct sk_buff *skb) 3415 struct ieee80211_tx_control *control,
3416 struct sk_buff *skb)
3416{ 3417{
3417 struct b43_wl *wl = hw_to_b43_wl(hw); 3418 struct b43_wl *wl = hw_to_b43_wl(hw);
3418 3419
@@ -4282,6 +4283,35 @@ out:
4282 return err; 4283 return err;
4283} 4284}
4284 4285
4286static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4287{
4288 switch (phy_type) {
4289 case B43_PHYTYPE_A:
4290 return "A";
4291 case B43_PHYTYPE_B:
4292 return "B";
4293 case B43_PHYTYPE_G:
4294 return "G";
4295 case B43_PHYTYPE_N:
4296 return "N";
4297 case B43_PHYTYPE_LP:
4298 return "LP";
4299 case B43_PHYTYPE_SSLPN:
4300 return "SSLPN";
4301 case B43_PHYTYPE_HT:
4302 return "HT";
4303 case B43_PHYTYPE_LCN:
4304 return "LCN";
4305 case B43_PHYTYPE_LCNXN:
4306 return "LCNXN";
4307 case B43_PHYTYPE_LCN40:
4308 return "LCN40";
4309 case B43_PHYTYPE_AC:
4310 return "AC";
4311 }
4312 return "UNKNOWN";
4313}
4314
4285/* Get PHY and RADIO versioning numbers */ 4315/* Get PHY and RADIO versioning numbers */
4286static int b43_phy_versioning(struct b43_wldev *dev) 4316static int b43_phy_versioning(struct b43_wldev *dev)
4287{ 4317{
@@ -4342,13 +4372,13 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4342 unsupported = 1; 4372 unsupported = 1;
4343 } 4373 }
4344 if (unsupported) { 4374 if (unsupported) {
4345 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4375 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4346 "(Analog %u, Type %u, Revision %u)\n", 4376 analog_type, phy_type, b43_phy_name(dev, phy_type),
4347 analog_type, phy_type, phy_rev); 4377 phy_rev);
4348 return -EOPNOTSUPP; 4378 return -EOPNOTSUPP;
4349 } 4379 }
4350 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4380 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4351 analog_type, phy_type, phy_rev); 4381 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4352 4382
4353 /* Get RADIO versioning */ 4383 /* Get RADIO versioning */
4354 if (dev->dev->core_rev >= 24) { 4384 if (dev->dev->core_rev >= 24) {
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
index 3f8883b14d9c..f01676ac481b 100644
--- a/drivers/net/wireless/b43/phy_common.c
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -240,6 +240,21 @@ void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
240 (b43_radio_read16(dev, offset) & mask) | set); 240 (b43_radio_read16(dev, offset) & mask) | set);
241} 241}
242 242
243bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
244 u16 value, int delay, int timeout)
245{
246 u16 val;
247 int i;
248
249 for (i = 0; i < timeout; i += delay) {
250 val = b43_radio_read(dev, offset);
251 if ((val & mask) == value)
252 return true;
253 udelay(delay);
254 }
255 return false;
256}
257
243u16 b43_phy_read(struct b43_wldev *dev, u16 reg) 258u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
244{ 259{
245 assert_mac_suspended(dev); 260 assert_mac_suspended(dev);
@@ -428,7 +443,7 @@ int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
428 average = (a + b + c + d + 2) / 4; 443 average = (a + b + c + d + 2) / 4;
429 if (is_ofdm) { 444 if (is_ofdm) {
430 /* Adjust for CCK-boost */ 445 /* Adjust for CCK-boost */
431 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO) 446 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
432 & B43_HF_CCKBOOST) 447 & B43_HF_CCKBOOST)
433 average = (average >= 13) ? (average - 13) : 0; 448 average = (average >= 13) ? (average - 13) : 0;
434 } 449 }
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
index 9233b13fc16d..f1b999349876 100644
--- a/drivers/net/wireless/b43/phy_common.h
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -365,6 +365,12 @@ void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
365void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); 365void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
366 366
367/** 367/**
368 * b43_radio_wait_value - Waits for a given value in masked register read
369 */
370bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
371 u16 value, int delay, int timeout);
372
373/**
368 * b43_radio_lock - Lock firmware radio register access 374 * b43_radio_lock - Lock firmware radio register access
369 */ 375 */
370void b43_radio_lock(struct b43_wldev *dev); 376void b43_radio_lock(struct b43_wldev *dev);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index b92bb9c92ad1..3c35382ee6c2 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -32,6 +32,7 @@
32#include "tables_nphy.h" 32#include "tables_nphy.h"
33#include "radio_2055.h" 33#include "radio_2055.h"
34#include "radio_2056.h" 34#include "radio_2056.h"
35#include "radio_2057.h"
35#include "main.h" 36#include "main.h"
36 37
37struct nphy_txgains { 38struct nphy_txgains {
@@ -126,6 +127,46 @@ ok:
126 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 127 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
127} 128}
128 129
130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
131static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
132 u16 value, u8 core, bool off,
133 u8 override)
134{
135 const struct nphy_rf_control_override_rev7 *e;
136 u16 en_addrs[3][2] = {
137 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
138 };
139 u16 en_addr;
140 u16 en_mask = field;
141 u16 val_addr;
142 u8 i;
143
144 /* Remember: we can get NULL! */
145 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
146
147 for (i = 0; i < 2; i++) {
148 if (override >= ARRAY_SIZE(en_addrs)) {
149 b43err(dev->wl, "Invalid override value %d\n", override);
150 return;
151 }
152 en_addr = en_addrs[override][i];
153
154 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
155
156 if (off) {
157 b43_phy_mask(dev, en_addr, ~en_mask);
158 if (e) /* Do it safer, better than wl */
159 b43_phy_mask(dev, val_addr, ~e->val_mask);
160 } else {
161 if (!core || (core & (1 << i))) {
162 b43_phy_set(dev, en_addr, en_mask);
163 if (e)
164 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
165 }
166 }
167 }
168}
169
129/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 170/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
130static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 171static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
131 u16 value, u8 core, bool off) 172 u16 value, u8 core, bool off)
@@ -459,6 +500,137 @@ static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
459} 500}
460 501
461/************************************************** 502/**************************************************
503 * Radio 0x2057
504 **************************************************/
505
506/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
507static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
508{
509 struct b43_phy *phy = &dev->phy;
510 u16 tmp;
511
512 if (phy->radio_rev == 5) {
513 b43_phy_mask(dev, 0x342, ~0x2);
514 udelay(10);
515 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
516 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
517 }
518
519 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
520 udelay(10);
521 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
522 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
523 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
524 return 0;
525 }
526 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
527 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
528 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
529
530 if (phy->radio_rev == 5) {
531 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
532 b43_radio_mask(dev, 0x1ca, ~0x2);
533 }
534 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
535 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
536 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
537 tmp << 2);
538 }
539
540 return tmp & 0x3e;
541}
542
543/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
544static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
545{
546 struct b43_phy *phy = &dev->phy;
547 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
548 phy->radio_rev == 6);
549 u16 tmp;
550
551 if (special) {
552 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
553 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
554 } else {
555 b43_radio_write(dev, 0x1AE, 0x61);
556 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
557 }
558 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
559 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
560 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
561 5000000))
562 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
563 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
564 if (special) {
565 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
566 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
567 } else {
568 b43_radio_write(dev, 0x1AE, 0x69);
569 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
570 }
571 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
572 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
573 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
574 5000000))
575 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
576 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
577 if (special) {
578 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
579 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
580 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
581 } else {
582 b43_radio_write(dev, 0x1AE, 0x73);
583 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
584 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
585 }
586 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
587 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
588 5000000)) {
589 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
590 return 0;
591 }
592 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
593 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
594 return tmp;
595}
596
597static void b43_radio_2057_init_pre(struct b43_wldev *dev)
598{
599 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
600 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
601 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
602 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
603 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
604}
605
606static void b43_radio_2057_init_post(struct b43_wldev *dev)
607{
608 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
609
610 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
611 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
612 mdelay(2);
613 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
614 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
615
616 if (dev->phy.n->init_por) {
617 b43_radio_2057_rcal(dev);
618 b43_radio_2057_rccal(dev);
619 }
620 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
621
622 dev->phy.n->init_por = false;
623}
624
625/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
626static void b43_radio_2057_init(struct b43_wldev *dev)
627{
628 b43_radio_2057_init_pre(dev);
629 r2057_upload_inittabs(dev);
630 b43_radio_2057_init_post(dev);
631}
632
633/**************************************************
462 * Radio 0x2056 634 * Radio 0x2056
463 **************************************************/ 635 **************************************************/
464 636
@@ -545,7 +717,9 @@ static void b43_radio_2056_setup(struct b43_wldev *dev,
545 enum ieee80211_band band = b43_current_band(dev->wl); 717 enum ieee80211_band band = b43_current_band(dev->wl);
546 u16 offset; 718 u16 offset;
547 u8 i; 719 u8 i;
548 u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost; 720 u16 bias, cbias;
721 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
722 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
549 723
550 B43_WARN_ON(dev->phy.rev < 3); 724 B43_WARN_ON(dev->phy.rev < 3);
551 725
@@ -630,7 +804,56 @@ static void b43_radio_2056_setup(struct b43_wldev *dev,
630 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); 804 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
631 } 805 }
632 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) { 806 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
633 /* TODO */ 807 u16 freq = dev->phy.channel_freq;
808 if (freq < 5100) {
809 paa_boost = 0xA;
810 pada_boost = 0x77;
811 pgaa_boost = 0xF;
812 mixa_boost = 0xF;
813 } else if (freq < 5340) {
814 paa_boost = 0x8;
815 pada_boost = 0x77;
816 pgaa_boost = 0xFB;
817 mixa_boost = 0xF;
818 } else if (freq < 5650) {
819 paa_boost = 0x0;
820 pada_boost = 0x77;
821 pgaa_boost = 0xB;
822 mixa_boost = 0xF;
823 } else {
824 paa_boost = 0x0;
825 pada_boost = 0x77;
826 if (freq != 5825)
827 pgaa_boost = -(freq - 18) / 36 + 168;
828 else
829 pgaa_boost = 6;
830 mixa_boost = 0xF;
831 }
832
833 for (i = 0; i < 2; i++) {
834 offset = i ? B2056_TX1 : B2056_TX0;
835
836 b43_radio_write(dev,
837 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
838 b43_radio_write(dev,
839 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
840 b43_radio_write(dev,
841 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
842 b43_radio_write(dev,
843 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
844 b43_radio_write(dev,
845 offset | B2056_TX_TXSPARE1, 0x30);
846 b43_radio_write(dev,
847 offset | B2056_TX_PA_SPARE2, 0xee);
848 b43_radio_write(dev,
849 offset | B2056_TX_PADA_CASCBIAS, 0x03);
850 b43_radio_write(dev,
851 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
852 b43_radio_write(dev,
853 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
854 b43_radio_write(dev,
855 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
856 }
634 } 857 }
635 858
636 udelay(50); 859 udelay(50);
@@ -643,6 +866,37 @@ static void b43_radio_2056_setup(struct b43_wldev *dev,
643 udelay(300); 866 udelay(300);
644} 867}
645 868
869static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
870{
871 struct b43_phy *phy = &dev->phy;
872 u16 mast2, tmp;
873
874 if (phy->rev != 3)
875 return 0;
876
877 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
878 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
879
880 udelay(10);
881 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
882 udelay(10);
883 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
884
885 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
886 1000000)) {
887 b43err(dev->wl, "Radio recalibration timeout\n");
888 return 0;
889 }
890
891 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
892 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
893 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
894
895 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
896
897 return tmp & 0x1f;
898}
899
646static void b43_radio_init2056_pre(struct b43_wldev *dev) 900static void b43_radio_init2056_pre(struct b43_wldev *dev)
647{ 901{
648 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 902 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
@@ -665,10 +919,8 @@ static void b43_radio_init2056_post(struct b43_wldev *dev)
665 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); 919 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
666 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); 920 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
667 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); 921 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
668 /* 922 if (dev->phy.n->init_por)
669 if (nphy->init_por) 923 b43_radio_2056_rcal(dev);
670 Call Radio 2056 Recalibrate
671 */
672} 924}
673 925
674/* 926/*
@@ -680,6 +932,8 @@ static void b43_radio_init2056(struct b43_wldev *dev)
680 b43_radio_init2056_pre(dev); 932 b43_radio_init2056_pre(dev);
681 b2056_upload_inittabs(dev, 0, 0); 933 b2056_upload_inittabs(dev, 0, 0);
682 b43_radio_init2056_post(dev); 934 b43_radio_init2056_post(dev);
935
936 dev->phy.n->init_por = false;
683} 937}
684 938
685/************************************************** 939/**************************************************
@@ -753,8 +1007,6 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
753{ 1007{
754 struct b43_phy_n *nphy = dev->phy.n; 1008 struct b43_phy_n *nphy = dev->phy.n;
755 struct ssb_sprom *sprom = dev->dev->bus_sprom; 1009 struct ssb_sprom *sprom = dev->dev->bus_sprom;
756 int i;
757 u16 val;
758 bool workaround = false; 1010 bool workaround = false;
759 1011
760 if (sprom->revision < 4) 1012 if (sprom->revision < 4)
@@ -777,15 +1029,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
777 b43_radio_set(dev, B2055_CAL_MISC, 0x1); 1029 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
778 msleep(1); 1030 msleep(1);
779 b43_radio_set(dev, B2055_CAL_MISC, 0x40); 1031 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
780 for (i = 0; i < 200; i++) { 1032 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
781 val = b43_radio_read(dev, B2055_CAL_COUT2);
782 if (val & 0x80) {
783 i = 0;
784 break;
785 }
786 udelay(10);
787 }
788 if (i)
789 b43err(dev->wl, "radio post init timeout\n"); 1033 b43err(dev->wl, "radio post init timeout\n");
790 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 1034 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
791 b43_switch_channel(dev, dev->phy.channel); 1035 b43_switch_channel(dev, dev->phy.channel);
@@ -1860,12 +2104,334 @@ static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1860/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ 2104/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1861static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) 2105static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
1862{ 2106{
1863 if (dev->phy.rev >= 3) 2107 if (dev->phy.rev >= 7)
2108 ; /* TODO */
2109 else if (dev->phy.rev >= 3)
1864 b43_nphy_gain_ctl_workarounds_rev3plus(dev); 2110 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
1865 else 2111 else
1866 b43_nphy_gain_ctl_workarounds_rev1_2(dev); 2112 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
1867} 2113}
1868 2114
2115/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2116static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2117{
2118 if (!offset)
2119 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2120 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2121}
2122
2123static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2124{
2125 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2126 struct b43_phy *phy = &dev->phy;
2127
2128 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2129 0x1F };
2130 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2131
2132 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2133 u8 ntab7_138_146[] = { 0x11, 0x11 };
2134 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2135
2136 u16 lpf_20, lpf_40, lpf_11b;
2137 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2138 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2139 bool rccal_ovrd = false;
2140
2141 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2142 u16 bias, conv, filt;
2143
2144 u32 tmp32;
2145 u8 core;
2146
2147 if (phy->rev == 7) {
2148 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2149 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2150 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2151 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2152 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2153 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2154 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2155 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2156 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2157 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2158 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2159 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2160 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2161 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2162 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2163 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2164 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2165 }
2166 if (phy->rev <= 8) {
2167 b43_phy_write(dev, 0x23F, 0x1B0);
2168 b43_phy_write(dev, 0x240, 0x1B0);
2169 }
2170 if (phy->rev >= 8)
2171 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2172
2173 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2174 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2175 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2176 tmp32 &= 0xffffff;
2177 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2178 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2179 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2180
2181 if (b43_nphy_ipa(dev))
2182 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2183 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2184
2185 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2186 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2187
2188 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2189 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2190 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2191 if (b43_nphy_ipa(dev)) {
2192 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2193 phy->radio_rev == 7 || phy->radio_rev == 8) {
2194 bcap_val = b43_radio_read(dev, 0x16b);
2195 scap_val = b43_radio_read(dev, 0x16a);
2196 scap_val_11b = scap_val;
2197 bcap_val_11b = bcap_val;
2198 if (phy->radio_rev == 5 && phy->is_40mhz) {
2199 scap_val_11n_20 = scap_val;
2200 bcap_val_11n_20 = bcap_val;
2201 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2202 rccal_ovrd = true;
2203 } else { /* Rev 7/8 */
2204 lpf_20 = 4;
2205 lpf_11b = 1;
2206 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2207 scap_val_11n_20 = 0xc;
2208 bcap_val_11n_20 = 0xc;
2209 scap_val_11n_40 = 0xa;
2210 bcap_val_11n_40 = 0xa;
2211 } else {
2212 scap_val_11n_20 = 0x14;
2213 bcap_val_11n_20 = 0x14;
2214 scap_val_11n_40 = 0xf;
2215 bcap_val_11n_40 = 0xf;
2216 }
2217 rccal_ovrd = true;
2218 }
2219 }
2220 } else {
2221 if (phy->radio_rev == 5) {
2222 lpf_20 = 1;
2223 lpf_40 = 3;
2224 bcap_val = b43_radio_read(dev, 0x16b);
2225 scap_val = b43_radio_read(dev, 0x16a);
2226 scap_val_11b = scap_val;
2227 bcap_val_11b = bcap_val;
2228 scap_val_11n_20 = 0x11;
2229 scap_val_11n_40 = 0x11;
2230 bcap_val_11n_20 = 0x13;
2231 bcap_val_11n_40 = 0x13;
2232 rccal_ovrd = true;
2233 }
2234 }
2235 if (rccal_ovrd) {
2236 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2237 (scap_val_11b << 3) |
2238 lpf_11b;
2239 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2240 (scap_val_11n_20 << 3) |
2241 lpf_20;
2242 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2243 (scap_val_11n_40 << 3) |
2244 lpf_40;
2245 for (core = 0; core < 2; core++) {
2246 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2247 rx2tx_lut_20_11b);
2248 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2249 rx2tx_lut_20_11n);
2250 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2251 rx2tx_lut_20_11n);
2252 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2253 rx2tx_lut_40_11n);
2254 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2255 rx2tx_lut_40_11n);
2256 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2257 rx2tx_lut_40_11n);
2258 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2259 rx2tx_lut_40_11n);
2260 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2261 rx2tx_lut_40_11n);
2262 }
2263 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
2264 }
2265 b43_phy_write(dev, 0x32F, 0x3);
2266 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2267 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
2268
2269 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2270 if (sprom->revision &&
2271 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2272 b43_radio_write(dev, 0x5, 0x05);
2273 b43_radio_write(dev, 0x6, 0x30);
2274 b43_radio_write(dev, 0x7, 0x00);
2275 b43_radio_set(dev, 0x4f, 0x1);
2276 b43_radio_set(dev, 0xd4, 0x1);
2277 bias = 0x1f;
2278 conv = 0x6f;
2279 filt = 0xaa;
2280 } else {
2281 bias = 0x2b;
2282 conv = 0x7f;
2283 filt = 0xee;
2284 }
2285 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2286 for (core = 0; core < 2; core++) {
2287 if (core == 0) {
2288 b43_radio_write(dev, 0x5F, bias);
2289 b43_radio_write(dev, 0x64, conv);
2290 b43_radio_write(dev, 0x66, filt);
2291 } else {
2292 b43_radio_write(dev, 0xE8, bias);
2293 b43_radio_write(dev, 0xE9, conv);
2294 b43_radio_write(dev, 0xEB, filt);
2295 }
2296 }
2297 }
2298 }
2299
2300 if (b43_nphy_ipa(dev)) {
2301 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2302 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2303 phy->radio_rev == 6) {
2304 for (core = 0; core < 2; core++) {
2305 if (core == 0)
2306 b43_radio_write(dev, 0x51,
2307 0x7f);
2308 else
2309 b43_radio_write(dev, 0xd6,
2310 0x7f);
2311 }
2312 }
2313 if (phy->radio_rev == 3) {
2314 for (core = 0; core < 2; core++) {
2315 if (core == 0) {
2316 b43_radio_write(dev, 0x64,
2317 0x13);
2318 b43_radio_write(dev, 0x5F,
2319 0x1F);
2320 b43_radio_write(dev, 0x66,
2321 0xEE);
2322 b43_radio_write(dev, 0x59,
2323 0x8A);
2324 b43_radio_write(dev, 0x80,
2325 0x3E);
2326 } else {
2327 b43_radio_write(dev, 0x69,
2328 0x13);
2329 b43_radio_write(dev, 0xE8,
2330 0x1F);
2331 b43_radio_write(dev, 0xEB,
2332 0xEE);
2333 b43_radio_write(dev, 0xDE,
2334 0x8A);
2335 b43_radio_write(dev, 0x105,
2336 0x3E);
2337 }
2338 }
2339 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2340 if (!phy->is_40mhz) {
2341 b43_radio_write(dev, 0x5F, 0x14);
2342 b43_radio_write(dev, 0xE8, 0x12);
2343 } else {
2344 b43_radio_write(dev, 0x5F, 0x16);
2345 b43_radio_write(dev, 0xE8, 0x16);
2346 }
2347 }
2348 } else {
2349 u16 freq = phy->channel_freq;
2350 if ((freq >= 5180 && freq <= 5230) ||
2351 (freq >= 5745 && freq <= 5805)) {
2352 b43_radio_write(dev, 0x7D, 0xFF);
2353 b43_radio_write(dev, 0xFE, 0xFF);
2354 }
2355 }
2356 } else {
2357 if (phy->radio_rev != 5) {
2358 for (core = 0; core < 2; core++) {
2359 if (core == 0) {
2360 b43_radio_write(dev, 0x5c, 0x61);
2361 b43_radio_write(dev, 0x51, 0x70);
2362 } else {
2363 b43_radio_write(dev, 0xe1, 0x61);
2364 b43_radio_write(dev, 0xd6, 0x70);
2365 }
2366 }
2367 }
2368 }
2369
2370 if (phy->radio_rev == 4) {
2371 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2372 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2373 for (core = 0; core < 2; core++) {
2374 if (core == 0) {
2375 b43_radio_write(dev, 0x1a1, 0x00);
2376 b43_radio_write(dev, 0x1a2, 0x3f);
2377 b43_radio_write(dev, 0x1a6, 0x3f);
2378 } else {
2379 b43_radio_write(dev, 0x1a7, 0x00);
2380 b43_radio_write(dev, 0x1ab, 0x3f);
2381 b43_radio_write(dev, 0x1ac, 0x3f);
2382 }
2383 }
2384 } else {
2385 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2386 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2387 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2388 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2389
2390 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2391 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2392 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2393 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2394 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2395 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2396
2397 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2398 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2399 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2400 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2401 }
2402
2403 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2404
2405 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2406 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2407 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2408 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2409 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2410 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2411 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2412
2413 if (!phy->is_40mhz) {
2414 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2415 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2416 } else {
2417 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2418 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2419 }
2420
2421 b43_nphy_gain_ctl_workarounds(dev);
2422
2423 /* TODO
2424 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2425 aux_adc_vmid_rev7_core0);
2426 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2427 aux_adc_vmid_rev7_core1);
2428 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2429 aux_adc_gain_rev7);
2430 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2431 aux_adc_gain_rev7);
2432 */
2433}
2434
1869static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) 2435static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1870{ 2436{
1871 struct b43_phy_n *nphy = dev->phy.n; 2437 struct b43_phy_n *nphy = dev->phy.n;
@@ -1916,7 +2482,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1916 rx2tx_delays[6] = 1; 2482 rx2tx_delays[6] = 1;
1917 rx2tx_events[7] = 0x1F; 2483 rx2tx_events[7] = 0x1F;
1918 } 2484 }
1919 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays, 2485 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
1920 ARRAY_SIZE(rx2tx_events)); 2486 ARRAY_SIZE(rx2tx_events));
1921 } 2487 }
1922 2488
@@ -1926,8 +2492,13 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1926 2492
1927 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); 2493 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1928 2494
1929 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 2495 if (!dev->phy.is_40mhz) {
1930 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); 2496 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2497 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2498 } else {
2499 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2500 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2501 }
1931 2502
1932 b43_nphy_gain_ctl_workarounds(dev); 2503 b43_nphy_gain_ctl_workarounds(dev);
1933 2504
@@ -1963,13 +2534,14 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1963 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); 2534 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1964 2535
1965 if (dev->phy.rev == 4 && 2536 if (dev->phy.rev == 4 &&
1966 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2537 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1967 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, 2538 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1968 0x70); 2539 0x70);
1969 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, 2540 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1970 0x70); 2541 0x70);
1971 } 2542 }
1972 2543
2544 /* Dropped probably-always-true condition */
1973 b43_phy_write(dev, 0x224, 0x03eb); 2545 b43_phy_write(dev, 0x224, 0x03eb);
1974 b43_phy_write(dev, 0x225, 0x03eb); 2546 b43_phy_write(dev, 0x225, 0x03eb);
1975 b43_phy_write(dev, 0x226, 0x0341); 2547 b43_phy_write(dev, 0x226, 0x0341);
@@ -1982,6 +2554,9 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1982 b43_phy_write(dev, 0x22d, 0x042b); 2554 b43_phy_write(dev, 0x22d, 0x042b);
1983 b43_phy_write(dev, 0x22e, 0x0381); 2555 b43_phy_write(dev, 0x22e, 0x0381);
1984 b43_phy_write(dev, 0x22f, 0x0381); 2556 b43_phy_write(dev, 0x22f, 0x0381);
2557
2558 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2559 ; /* TODO: 0x0080000000000000 HF */
1985} 2560}
1986 2561
1987static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) 2562static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
@@ -1996,6 +2571,12 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1996 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; 2571 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1997 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 2572 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1998 2573
2574 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2575 dev->dev->board_type == 0x8B) {
2576 delays1[0] = 0x1;
2577 delays1[5] = 0x14;
2578 }
2579
1999 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && 2580 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2000 nphy->band5g_pwrgain) { 2581 nphy->band5g_pwrgain) {
2001 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); 2582 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
@@ -2007,8 +2588,10 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2007 2588
2008 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); 2589 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2009 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); 2590 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2010 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); 2591 if (dev->phy.rev < 3) {
2011 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); 2592 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2593 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2594 }
2012 2595
2013 if (dev->phy.rev < 2) { 2596 if (dev->phy.rev < 2) {
2014 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); 2597 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
@@ -2024,11 +2607,6 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2024 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 2607 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2025 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 2608 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2026 2609
2027 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
2028 dev->dev->board_type == 0x8B) {
2029 delays1[0] = 0x1;
2030 delays1[5] = 0x14;
2031 }
2032 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); 2610 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2033 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); 2611 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2034 2612
@@ -2055,11 +2633,13 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2055 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); 2633 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2056 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); 2634 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2057 2635
2058 b43_phy_mask(dev, B43_NPHY_PIL_DW1, 2636 if (dev->phy.rev < 3) {
2059 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); 2637 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2060 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); 2638 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2061 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); 2639 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2062 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); 2640 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2641 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2642 }
2063 2643
2064 if (dev->phy.rev == 2) 2644 if (dev->phy.rev == 2)
2065 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 2645 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
@@ -2083,7 +2663,9 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
2083 b43_phy_set(dev, B43_NPHY_IQFLIP, 2663 b43_phy_set(dev, B43_NPHY_IQFLIP,
2084 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); 2664 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2085 2665
2086 if (dev->phy.rev >= 3) 2666 if (dev->phy.rev >= 7)
2667 b43_nphy_workarounds_rev7plus(dev);
2668 else if (dev->phy.rev >= 3)
2087 b43_nphy_workarounds_rev3plus(dev); 2669 b43_nphy_workarounds_rev3plus(dev);
2088 else 2670 else
2089 b43_nphy_workarounds_rev1_2(dev); 2671 b43_nphy_workarounds_rev1_2(dev);
@@ -2542,7 +3124,7 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
2542 b43_nphy_ipa_internal_tssi_setup(dev); 3124 b43_nphy_ipa_internal_tssi_setup(dev);
2543 3125
2544 if (phy->rev >= 7) 3126 if (phy->rev >= 7)
2545 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 0, 0 as arguments */ 3127 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
2546 else if (phy->rev >= 3) 3128 else if (phy->rev >= 3)
2547 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false); 3129 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
2548 3130
@@ -2554,7 +3136,7 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
2554 b43_nphy_rssi_select(dev, 0, 0); 3136 b43_nphy_rssi_select(dev, 0, 0);
2555 3137
2556 if (phy->rev >= 7) 3138 if (phy->rev >= 7)
2557 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 1, 0 as arguments */ 3139 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
2558 else if (phy->rev >= 3) 3140 else if (phy->rev >= 3)
2559 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true); 3141 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
2560 3142
@@ -4761,6 +5343,7 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4761 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4); 5343 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4762 nphy->spur_avoid = (phy->rev >= 3) ? 5344 nphy->spur_avoid = (phy->rev >= 3) ?
4763 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE; 5345 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5346 nphy->init_por = true;
4764 nphy->gain_boost = true; /* this way we follow wl, assume it is true */ 5347 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4765 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ 5348 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4766 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ 5349 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
@@ -4801,6 +5384,8 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4801 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2; 5384 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4802 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2; 5385 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4803 } 5386 }
5387
5388 nphy->init_por = true;
4804} 5389}
4805 5390
4806static void b43_nphy_op_free(struct b43_wldev *dev) 5391static void b43_nphy_op_free(struct b43_wldev *dev)
@@ -4887,7 +5472,9 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4887 if (blocked) { 5472 if (blocked) {
4888 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 5473 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4889 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 5474 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4890 if (dev->phy.rev >= 3) { 5475 if (dev->phy.rev >= 7) {
5476 /* TODO */
5477 } else if (dev->phy.rev >= 3) {
4891 b43_radio_mask(dev, 0x09, ~0x2); 5478 b43_radio_mask(dev, 0x09, ~0x2);
4892 5479
4893 b43_radio_write(dev, 0x204D, 0); 5480 b43_radio_write(dev, 0x204D, 0);
@@ -4905,7 +5492,10 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4905 b43_radio_write(dev, 0x3064, 0); 5492 b43_radio_write(dev, 0x3064, 0);
4906 } 5493 }
4907 } else { 5494 } else {
4908 if (dev->phy.rev >= 3) { 5495 if (dev->phy.rev >= 7) {
5496 b43_radio_2057_init(dev);
5497 b43_switch_channel(dev, dev->phy.channel);
5498 } else if (dev->phy.rev >= 3) {
4909 b43_radio_init2056(dev); 5499 b43_radio_init2056(dev);
4910 b43_switch_channel(dev, dev->phy.channel); 5500 b43_switch_channel(dev, dev->phy.channel);
4911 } else { 5501 } else {
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h
index fd12b386fea1..092c0140c249 100644
--- a/drivers/net/wireless/b43/phy_n.h
+++ b/drivers/net/wireless/b43/phy_n.h
@@ -785,6 +785,7 @@ struct b43_phy_n {
785 u16 papd_epsilon_offset[2]; 785 u16 papd_epsilon_offset[2];
786 s32 preamble_override; 786 s32 preamble_override;
787 u32 bb_mult_save; 787 u32 bb_mult_save;
788 bool init_por;
788 789
789 bool gain_boost; 790 bool gain_boost;
790 bool elna_gain_config; 791 bool elna_gain_config;
diff --git a/drivers/net/wireless/b43/radio_2057.c b/drivers/net/wireless/b43/radio_2057.c
new file mode 100644
index 000000000000..d61d6830c5c7
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2057.c
@@ -0,0 +1,141 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n 2057 radio device data tables
5
6 Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
26#include "radio_2057.h"
27#include "phy_common.h"
28
29static u16 r2057_rev4_init[42][2] = {
30 { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 },
31 { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff },
32 { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 },
33 { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c },
34 { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 },
35 { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c },
36 { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
37 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
38 { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
39 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
40 { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
41};
42
43static u16 r2057_rev5_init[44][2] = {
44 { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 },
45 { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 },
46 { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f },
47 { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
48 { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 },
49 { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f },
50 { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
51 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
52 { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 },
53 { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 },
54 { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, { 0x1C2, 0x80 },
55};
56
57static u16 r2057_rev5a_init[45][2] = {
58 { 0x00, 0x15 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 },
59 { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 },
60 { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f },
61 { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
62 { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 },
63 { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f },
64 { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x14E, 0x01 }, { 0x15E, 0x00 },
65 { 0x15F, 0x00 }, { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 },
66 { 0x163, 0x00 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
67 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
68 { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 },
69 { 0x1C2, 0x80 },
70};
71
72static u16 r2057_rev7_init[54][2] = {
73 { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 },
74 { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 },
75 { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x13 },
76 { 0x66, 0xee }, { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 },
77 { 0x7C, 0x14 }, { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f },
78 { 0x92, 0x36 }, { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 },
79 { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x13 }, { 0xEB, 0xee },
80 { 0xF3, 0x58 }, { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x14 },
81 { 0x102, 0xee }, { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 },
82 { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 },
83 { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 },
84 { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 },
85 { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
86 { 0x1B7, 0x05 }, { 0x1C2, 0xa0 },
87};
88
89static u16 r2057_rev8_init[54][2] = {
90 { 0x00, 0x08 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 },
91 { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 },
92 { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x0f },
93 { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, { 0x7C, 0x0f },
94 { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
95 { 0xA1, 0x20 }, { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 },
96 { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0xF3, 0x58 },
97 { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x0f }, { 0x102, 0xee },
98 { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x126, 0x20 },
99 { 0x14E, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 },
100 { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 },
101 { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 },
102 { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
103 { 0x1B7, 0x05 }, { 0x1C2, 0xa0 },
104};
105
106void r2057_upload_inittabs(struct b43_wldev *dev)
107{
108 struct b43_phy *phy = &dev->phy;
109 u16 *table = NULL;
110 u16 size, i;
111
112 if (phy->rev == 7) {
113 table = r2057_rev4_init[0];
114 size = ARRAY_SIZE(r2057_rev4_init);
115 } else if (phy->rev == 8 || phy->rev == 9) {
116 if (phy->radio_rev == 5) {
117 if (phy->radio_rev == 8) {
118 table = r2057_rev5_init[0];
119 size = ARRAY_SIZE(r2057_rev5_init);
120 } else {
121 table = r2057_rev5a_init[0];
122 size = ARRAY_SIZE(r2057_rev5a_init);
123 }
124 } else if (phy->radio_rev == 7) {
125 table = r2057_rev7_init[0];
126 size = ARRAY_SIZE(r2057_rev7_init);
127 } else if (phy->radio_rev == 9) {
128 table = r2057_rev8_init[0];
129 size = ARRAY_SIZE(r2057_rev8_init);
130 }
131 }
132
133 if (table) {
134 for (i = 0; i < 10; i++) {
135 pr_info("radio_write 0x%X ", *table);
136 table++;
137 pr_info("0x%X\n", *table);
138 table++;
139 }
140 }
141}
diff --git a/drivers/net/wireless/b43/radio_2057.h b/drivers/net/wireless/b43/radio_2057.h
new file mode 100644
index 000000000000..eeebd8fbeb0d
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2057.h
@@ -0,0 +1,430 @@
1#ifndef B43_RADIO_2057_H_
2#define B43_RADIO_2057_H_
3
4#include <linux/types.h>
5
6#include "tables_nphy.h"
7
8#define R2057_DACBUF_VINCM_CORE0 0x000
9#define R2057_IDCODE 0x001
10#define R2057_RCCAL_MASTER 0x002
11#define R2057_RCCAL_CAP_SIZE 0x003
12#define R2057_RCAL_CONFIG 0x004
13#define R2057_GPAIO_CONFIG 0x005
14#define R2057_GPAIO_SEL1 0x006
15#define R2057_GPAIO_SEL0 0x007
16#define R2057_CLPO_CONFIG 0x008
17#define R2057_BANDGAP_CONFIG 0x009
18#define R2057_BANDGAP_RCAL_TRIM 0x00a
19#define R2057_AFEREG_CONFIG 0x00b
20#define R2057_TEMPSENSE_CONFIG 0x00c
21#define R2057_XTAL_CONFIG1 0x00d
22#define R2057_XTAL_ICORE_SIZE 0x00e
23#define R2057_XTAL_BUF_SIZE 0x00f
24#define R2057_XTAL_PULLCAP_SIZE 0x010
25#define R2057_RFPLL_MASTER 0x011
26#define R2057_VCOMONITOR_VTH_L 0x012
27#define R2057_VCOMONITOR_VTH_H 0x013
28#define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014
29#define R2057_VCO_VARCSIZE_IDAC 0x015
30#define R2057_VCOCAL_COUNTVAL0 0x016
31#define R2057_VCOCAL_COUNTVAL1 0x017
32#define R2057_VCOCAL_INTCLK_COUNT 0x018
33#define R2057_VCOCAL_MASTER 0x019
34#define R2057_VCOCAL_NUMCAPCHANGE 0x01a
35#define R2057_VCOCAL_WINSIZE 0x01b
36#define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c
37#define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d
38#define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e
39#define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f
40#define R2057_VCO_FORCECAPEN_FORCECAP1 0x020
41#define R2057_VCO_FORCECAP0 0x021
42#define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022
43#define R2057_RFPLL_PFD_RESET_PW 0x023
44#define R2057_RFPLL_LOOPFILTER_R2 0x024
45#define R2057_RFPLL_LOOPFILTER_R1 0x025
46#define R2057_RFPLL_LOOPFILTER_C3 0x026
47#define R2057_RFPLL_LOOPFILTER_C2 0x027
48#define R2057_RFPLL_LOOPFILTER_C1 0x028
49#define R2057_CP_KPD_IDAC 0x029
50#define R2057_RFPLL_IDACS 0x02a
51#define R2057_RFPLL_MISC_EN 0x02b
52#define R2057_RFPLL_MMD0 0x02c
53#define R2057_RFPLL_MMD1 0x02d
54#define R2057_RFPLL_MISC_CAL_RESETN 0x02e
55#define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f
56#define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030
57#define R2057_VCOCAL_READCAP0 0x031
58#define R2057_VCOCAL_READCAP1 0x032
59#define R2057_VCOCAL_STATUS 0x033
60#define R2057_LOGEN_PUS 0x034
61#define R2057_LOGEN_PTAT_RESETS 0x035
62#define R2057_VCOBUF_IDACS 0x036
63#define R2057_VCOBUF_TUNE 0x037
64#define R2057_CMOSBUF_TX2GQ_IDACS 0x038
65#define R2057_CMOSBUF_TX2GI_IDACS 0x039
66#define R2057_CMOSBUF_TX5GQ_IDACS 0x03a
67#define R2057_CMOSBUF_TX5GI_IDACS 0x03b
68#define R2057_CMOSBUF_RX2GQ_IDACS 0x03c
69#define R2057_CMOSBUF_RX2GI_IDACS 0x03d
70#define R2057_CMOSBUF_RX5GQ_IDACS 0x03e
71#define R2057_CMOSBUF_RX5GI_IDACS 0x03f
72#define R2057_LOGEN_MX2G_IDACS 0x040
73#define R2057_LOGEN_MX2G_TUNE 0x041
74#define R2057_LOGEN_MX5G_IDACS 0x042
75#define R2057_LOGEN_MX5G_TUNE 0x043
76#define R2057_LOGEN_MX5G_RCCR 0x044
77#define R2057_LOGEN_INDBUF2G_IDAC 0x045
78#define R2057_LOGEN_INDBUF2G_IBOOST 0x046
79#define R2057_LOGEN_INDBUF2G_TUNE 0x047
80#define R2057_LOGEN_INDBUF5G_IDAC 0x048
81#define R2057_LOGEN_INDBUF5G_IBOOST 0x049
82#define R2057_LOGEN_INDBUF5G_TUNE 0x04a
83#define R2057_CMOSBUF_TX_RCCR 0x04b
84#define R2057_CMOSBUF_RX_RCCR 0x04c
85#define R2057_LOGEN_SEL_PKDET 0x04d
86#define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e
87#define R2057_RXTXBIAS_CONFIG_CORE0 0x04f
88#define R2057_TXGM_TXRF_PUS_CORE0 0x050
89#define R2057_TXGM_IDAC_BLEED_CORE0 0x051
90#define R2057_TXGM_GAIN_CORE0 0x056
91#define R2057_TXGM2G_PKDET_PUS_CORE0 0x057
92#define R2057_PAD2G_PTATS_CORE0 0x058
93#define R2057_PAD2G_IDACS_CORE0 0x059
94#define R2057_PAD2G_BOOST_PU_CORE0 0x05a
95#define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b
96#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c
97#define R2057_TXMIX2G_LODC_CORE0 0x05d
98#define R2057_PAD2G_TUNE_PUS_CORE0 0x05e
99#define R2057_IPA2G_GAIN_CORE0 0x05f
100#define R2057_TSSI2G_SPARE1_CORE0 0x060
101#define R2057_TSSI2G_SPARE2_CORE0 0x061
102#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062
103#define R2057_IPA2G_IMAIN_CORE0 0x063
104#define R2057_IPA2G_CASCONV_CORE0 0x064
105#define R2057_IPA2G_CASCOFFV_CORE0 0x065
106#define R2057_IPA2G_BIAS_FILTER_CORE0 0x066
107#define R2057_TX5G_PKDET_CORE0 0x069
108#define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a
109#define R2057_PAD5G_PTATS1_CORE0 0x06b
110#define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c
111#define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d
112#define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e
113#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f
114#define R2057_PGA_BOOST_TUNE_CORE0 0x070
115#define R2057_PGA_GAIN_CORE0 0x071
116#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072
117#define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073
118#define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074
119#define R2057_IPA5G_IAUX_CORE0 0x075
120#define R2057_IPA5G_GAIN_CORE0 0x076
121#define R2057_TSSI5G_SPARE1_CORE0 0x077
122#define R2057_TSSI5G_SPARE2_CORE0 0x078
123#define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079
124#define R2057_IPA5G_PTAT_CORE0 0x07a
125#define R2057_IPA5G_IMAIN_CORE0 0x07b
126#define R2057_IPA5G_CASCONV_CORE0 0x07c
127#define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d
128#define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080
129#define R2057_TR2G_CONFIG1_CORE0_NU 0x081
130#define R2057_TR2G_CONFIG2_CORE0_NU 0x082
131#define R2057_LNA5G_RFEN_CORE0 0x083
132#define R2057_TR5G_CONFIG2_CORE0_NU 0x084
133#define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085
134#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086
135#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087
136#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088
137#define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089
138#define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a
139#define R2057_LNA2_IAUX_PTAT_CORE0 0x08b
140#define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c
141#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d
142#define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e
143#define R2057_TIA_CONFIG_CORE0 0x08f
144#define R2057_TIA_IQGAIN_CORE0 0x090
145#define R2057_TIA_IBIAS2_CORE0 0x091
146#define R2057_TIA_IBIAS1_CORE0 0x092
147#define R2057_TIA_SPARE_Q_CORE0 0x093
148#define R2057_TIA_SPARE_I_CORE0 0x094
149#define R2057_RXMIX2G_PUS_CORE0 0x095
150#define R2057_RXMIX2G_VCMREFS_CORE0 0x096
151#define R2057_RXMIX2G_LODC_QI_CORE0 0x097
152#define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098
153#define R2057_LNA2G_GAIN_CORE0 0x099
154#define R2057_LNA2G_TUNE_CORE0 0x09a
155#define R2057_RXMIX5G_PUS_CORE0 0x09b
156#define R2057_RXMIX5G_VCMREFS_CORE0 0x09c
157#define R2057_RXMIX5G_LODC_QI_CORE0 0x09d
158#define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e
159#define R2057_LNA5G_GAIN_CORE0 0x09f
160#define R2057_LNA5G_TUNE_CORE0 0x0a0
161#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1
162#define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2
163#define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3
164#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4
165#define R2057_TXBUF_VINCM_CORE0 0x0a5
166#define R2057_TXBUF_IDACS_CORE0 0x0a6
167#define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7
168#define R2057_RXBB_CC_CORE0 0x0a8
169#define R2057_RXBB_SPARE3_CORE0 0x0a9
170#define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa
171#define R2057_LPF_IDACS_CORE0 0x0ab
172#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac
173#define R2057_TXBUF_GAIN_CORE0 0x0ad
174#define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae
175#define R2057_RXBUF_DEGEN_CORE0 0x0af
176#define R2057_RXBB_SPARE2_CORE0 0x0b0
177#define R2057_RXBB_SPARE1_CORE0 0x0b1
178#define R2057_RSSI_MASTER_CORE0 0x0b2
179#define R2057_W2_MASTER_CORE0 0x0b3
180#define R2057_NB_MASTER_CORE0 0x0b4
181#define R2057_W2_IDACS0_Q_CORE0 0x0b5
182#define R2057_W2_IDACS1_Q_CORE0 0x0b6
183#define R2057_W2_IDACS0_I_CORE0 0x0b7
184#define R2057_W2_IDACS1_I_CORE0 0x0b8
185#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0x0b9
186#define R2057_NB_IDACS_Q_CORE0 0x0ba
187#define R2057_NB_IDACS_I_CORE0 0x0bb
188#define R2057_BACKUP4_CORE0 0x0c1
189#define R2057_BACKUP3_CORE0 0x0c2
190#define R2057_BACKUP2_CORE0 0x0c3
191#define R2057_BACKUP1_CORE0 0x0c4
192#define R2057_SPARE16_CORE0 0x0c5
193#define R2057_SPARE15_CORE0 0x0c6
194#define R2057_SPARE14_CORE0 0x0c7
195#define R2057_SPARE13_CORE0 0x0c8
196#define R2057_SPARE12_CORE0 0x0c9
197#define R2057_SPARE11_CORE0 0x0ca
198#define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb
199#define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc
200#define R2057_IQTEST_SEL_PU 0x0cd
201#define R2057_XTAL_CONFIG2 0x0ce
202#define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf
203#define R2057_TXLPF_RCCAL_CORE0 0x0d0
204#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1
205#define R2057_LPF_GAIN_CORE0 0x0d2
206#define R2057_DACBUF_IDACS_BW_CORE0 0x0d3
207#define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4
208#define R2057_TXGM_TXRF_PUS_CORE1 0x0d5
209#define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6
210#define R2057_TXGM_GAIN_CORE1 0x0db
211#define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc
212#define R2057_PAD2G_PTATS_CORE1 0x0dd
213#define R2057_PAD2G_IDACS_CORE1 0x0de
214#define R2057_PAD2G_BOOST_PU_CORE1 0x0df
215#define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0
216#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1
217#define R2057_TXMIX2G_LODC_CORE1 0x0e2
218#define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3
219#define R2057_IPA2G_GAIN_CORE1 0x0e4
220#define R2057_TSSI2G_SPARE1_CORE1 0x0e5
221#define R2057_TSSI2G_SPARE2_CORE1 0x0e6
222#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7
223#define R2057_IPA2G_IMAIN_CORE1 0x0e8
224#define R2057_IPA2G_CASCONV_CORE1 0x0e9
225#define R2057_IPA2G_CASCOFFV_CORE1 0x0ea
226#define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb
227#define R2057_TX5G_PKDET_CORE1 0x0ee
228#define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef
229#define R2057_PAD5G_PTATS1_CORE1 0x0f0
230#define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1
231#define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2
232#define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3
233#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4
234#define R2057_PGA_BOOST_TUNE_CORE1 0x0f5
235#define R2057_PGA_GAIN_CORE1 0x0f6
236#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7
237#define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8
238#define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9
239#define R2057_IPA5G_IAUX_CORE1 0x0fa
240#define R2057_IPA5G_GAIN_CORE1 0x0fb
241#define R2057_TSSI5G_SPARE1_CORE1 0x0fc
242#define R2057_TSSI5G_SPARE2_CORE1 0x0fd
243#define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe
244#define R2057_IPA5G_PTAT_CORE1 0x0ff
245#define R2057_IPA5G_IMAIN_CORE1 0x100
246#define R2057_IPA5G_CASCONV_CORE1 0x101
247#define R2057_IPA5G_BIAS_FILTER_CORE1 0x102
248#define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105
249#define R2057_TR2G_CONFIG1_CORE1_NU 0x106
250#define R2057_TR2G_CONFIG2_CORE1_NU 0x107
251#define R2057_LNA5G_RFEN_CORE1 0x108
252#define R2057_TR5G_CONFIG2_CORE1_NU 0x109
253#define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a
254#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b
255#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c
256#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d
257#define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e
258#define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f
259#define R2057_LNA2_IAUX_PTAT_CORE1 0x110
260#define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111
261#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112
262#define R2057_RXRFBIAS_BANDSEL_CORE1 0x113
263#define R2057_TIA_CONFIG_CORE1 0x114
264#define R2057_TIA_IQGAIN_CORE1 0x115
265#define R2057_TIA_IBIAS2_CORE1 0x116
266#define R2057_TIA_IBIAS1_CORE1 0x117
267#define R2057_TIA_SPARE_Q_CORE1 0x118
268#define R2057_TIA_SPARE_I_CORE1 0x119
269#define R2057_RXMIX2G_PUS_CORE1 0x11a
270#define R2057_RXMIX2G_VCMREFS_CORE1 0x11b
271#define R2057_RXMIX2G_LODC_QI_CORE1 0x11c
272#define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d
273#define R2057_LNA2G_GAIN_CORE1 0x11e
274#define R2057_LNA2G_TUNE_CORE1 0x11f
275#define R2057_RXMIX5G_PUS_CORE1 0x120
276#define R2057_RXMIX5G_VCMREFS_CORE1 0x121
277#define R2057_RXMIX5G_LODC_QI_CORE1 0x122
278#define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123
279#define R2057_LNA5G_GAIN_CORE1 0x124
280#define R2057_LNA5G_TUNE_CORE1 0x125
281#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126
282#define R2057_RXBB_BIAS_MASTER_CORE1 0x127
283#define R2057_RXBB_VGABUF_IDACS_CORE1 0x128
284#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129
285#define R2057_TXBUF_VINCM_CORE1 0x12a
286#define R2057_TXBUF_IDACS_CORE1 0x12b
287#define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c
288#define R2057_RXBB_CC_CORE1 0x12d
289#define R2057_RXBB_SPARE3_CORE1 0x12e
290#define R2057_RXBB_RCCAL_HPC_CORE1 0x12f
291#define R2057_LPF_IDACS_CORE1 0x130
292#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131
293#define R2057_TXBUF_GAIN_CORE1 0x132
294#define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133
295#define R2057_RXBUF_DEGEN_CORE1 0x134
296#define R2057_RXBB_SPARE2_CORE1 0x135
297#define R2057_RXBB_SPARE1_CORE1 0x136
298#define R2057_RSSI_MASTER_CORE1 0x137
299#define R2057_W2_MASTER_CORE1 0x138
300#define R2057_NB_MASTER_CORE1 0x139
301#define R2057_W2_IDACS0_Q_CORE1 0x13a
302#define R2057_W2_IDACS1_Q_CORE1 0x13b
303#define R2057_W2_IDACS0_I_CORE1 0x13c
304#define R2057_W2_IDACS1_I_CORE1 0x13d
305#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e
306#define R2057_NB_IDACS_Q_CORE1 0x13f
307#define R2057_NB_IDACS_I_CORE1 0x140
308#define R2057_BACKUP4_CORE1 0x146
309#define R2057_BACKUP3_CORE1 0x147
310#define R2057_BACKUP2_CORE1 0x148
311#define R2057_BACKUP1_CORE1 0x149
312#define R2057_SPARE16_CORE1 0x14a
313#define R2057_SPARE15_CORE1 0x14b
314#define R2057_SPARE14_CORE1 0x14c
315#define R2057_SPARE13_CORE1 0x14d
316#define R2057_SPARE12_CORE1 0x14e
317#define R2057_SPARE11_CORE1 0x14f
318#define R2057_TX2G_BIAS_RESETS_CORE1 0x150
319#define R2057_TX5G_BIAS_RESETS_CORE1 0x151
320#define R2057_SPARE8_CORE1 0x152
321#define R2057_SPARE7_CORE1 0x153
322#define R2057_BUFS_MISC_LPFBW_CORE1 0x154
323#define R2057_TXLPF_RCCAL_CORE1 0x155
324#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
325#define R2057_LPF_GAIN_CORE1 0x157
326#define R2057_DACBUF_IDACS_BW_CORE1 0x158
327#define R2057_DACBUF_VINCM_CORE1 0x159
328#define R2057_RCCAL_START_R1_Q1_P1 0x15a
329#define R2057_RCCAL_X1 0x15b
330#define R2057_RCCAL_TRC0 0x15c
331#define R2057_RCCAL_TRC1 0x15d
332#define R2057_RCCAL_DONE_OSCCAP 0x15e
333#define R2057_RCCAL_N0_0 0x15f
334#define R2057_RCCAL_N0_1 0x160
335#define R2057_RCCAL_N1_0 0x161
336#define R2057_RCCAL_N1_1 0x162
337#define R2057_RCAL_STATUS 0x163
338#define R2057_XTALPUOVR_PINCTRL 0x164
339#define R2057_OVR_REG0 0x165
340#define R2057_OVR_REG1 0x166
341#define R2057_OVR_REG2 0x167
342#define R2057_OVR_REG3 0x168
343#define R2057_OVR_REG4 0x169
344#define R2057_RCCAL_SCAP_VAL 0x16a
345#define R2057_RCCAL_BCAP_VAL 0x16b
346#define R2057_RCCAL_HPC_VAL 0x16c
347#define R2057_RCCAL_OVERRIDES 0x16d
348#define R2057_TX0_IQCAL_GAIN_BW 0x170
349#define R2057_TX0_LOFT_FINE_I 0x171
350#define R2057_TX0_LOFT_FINE_Q 0x172
351#define R2057_TX0_LOFT_COARSE_I 0x173
352#define R2057_TX0_LOFT_COARSE_Q 0x174
353#define R2057_TX0_TX_SSI_MASTER 0x175
354#define R2057_TX0_IQCAL_VCM_HG 0x176
355#define R2057_TX0_IQCAL_IDAC 0x177
356#define R2057_TX0_TSSI_VCM 0x178
357#define R2057_TX0_TX_SSI_MUX 0x179
358#define R2057_TX0_TSSIA 0x17a
359#define R2057_TX0_TSSIG 0x17b
360#define R2057_TX0_TSSI_MISC1 0x17c
361#define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d
362#define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
363#define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
364#define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
365#define R2057_TX1_IQCAL_GAIN_BW 0x190
366#define R2057_TX1_LOFT_FINE_I 0x191
367#define R2057_TX1_LOFT_FINE_Q 0x192
368#define R2057_TX1_LOFT_COARSE_I 0x193
369#define R2057_TX1_LOFT_COARSE_Q 0x194
370#define R2057_TX1_TX_SSI_MASTER 0x195
371#define R2057_TX1_IQCAL_VCM_HG 0x196
372#define R2057_TX1_IQCAL_IDAC 0x197
373#define R2057_TX1_TSSI_VCM 0x198
374#define R2057_TX1_TX_SSI_MUX 0x199
375#define R2057_TX1_TSSIA 0x19a
376#define R2057_TX1_TSSIG 0x19b
377#define R2057_TX1_TSSI_MISC1 0x19c
378#define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d
379#define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
380#define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
381#define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
382#define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
383#define R2057_AFE_SET_VCM_I_CORE0 0x1a2
384#define R2057_AFE_SET_VCM_Q_CORE0 0x1a3
385#define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4
386#define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5
387#define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6
388#define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7
389#define R2057_AFE_SET_VCM_I_CORE1 0x1a8
390#define R2057_AFE_SET_VCM_Q_CORE1 0x1a9
391#define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa
392#define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab
393#define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac
394
395#define R2057v7_DACBUF_VINCM_CORE0 0x1ad
396#define R2057v7_RCCAL_MASTER 0x1ae
397#define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af
398#define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0
399#define R2057v7_LOGEN_PUS1 0x1b1
400#define R2057v7_OVR_REG5 0x1b2
401#define R2057v7_OVR_REG6 0x1b3
402#define R2057v7_OVR_REG7 0x1b4
403#define R2057v7_OVR_REG8 0x1b5
404#define R2057v7_OVR_REG9 0x1b6
405#define R2057v7_OVR_REG10 0x1b7
406#define R2057v7_OVR_REG11 0x1b8
407#define R2057v7_OVR_REG12 0x1b9
408#define R2057v7_OVR_REG13 0x1ba
409#define R2057v7_OVR_REG14 0x1bb
410#define R2057v7_OVR_REG15 0x1bc
411#define R2057v7_OVR_REG16 0x1bd
412#define R2057v7_OVR_REG1 0x1be
413#define R2057v7_OVR_REG18 0x1bf
414#define R2057v7_OVR_REG19 0x1c0
415#define R2057v7_OVR_REG20 0x1c1
416#define R2057v7_OVR_REG21 0x1c2
417#define R2057v7_OVR_REG2 0x1c3
418#define R2057v7_OVR_REG23 0x1c4
419#define R2057v7_OVR_REG24 0x1c5
420#define R2057v7_OVR_REG25 0x1c6
421#define R2057v7_OVR_REG26 0x1c7
422#define R2057v7_OVR_REG27 0x1c8
423#define R2057v7_OVR_REG28 0x1c9
424#define R2057v7_IQTEST_SEL_PU2 0x1ca
425
426#define R2057_VCM_MASK 0x7
427
428void r2057_upload_inittabs(struct b43_wldev *dev);
429
430#endif /* B43_RADIO_2057_H_ */
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c
index f0d8377429c6..97d4e27bf36f 100644
--- a/drivers/net/wireless/b43/tables_nphy.c
+++ b/drivers/net/wireless/b43/tables_nphy.c
@@ -2757,6 +2757,49 @@ const struct nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = {
2757 { 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */ 2757 { 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */
2758}; 2758};
2759 2759
2760/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */
2761static const struct nphy_rf_control_override_rev7
2762 tbl_rf_control_override_rev7_over0[] = {
2763 { 0x0004, 0x07A, 0x07D, 0x0002, 1 },
2764 { 0x0008, 0x07A, 0x07D, 0x0004, 2 },
2765 { 0x0010, 0x07A, 0x07D, 0x0010, 4 },
2766 { 0x0020, 0x07A, 0x07D, 0x0020, 5 },
2767 { 0x0040, 0x07A, 0x07D, 0x0040, 6 },
2768 { 0x0080, 0x0F8, 0x0FA, 0x0080, 7 },
2769 { 0x0400, 0x0F8, 0x0FA, 0x0070, 4 },
2770 { 0x0800, 0x07B, 0x07E, 0xFFFF, 0 },
2771 { 0x1000, 0x07C, 0x07F, 0xFFFF, 0 },
2772 { 0x6000, 0x348, 0x349, 0xFFFF, 0 },
2773 { 0x2000, 0x348, 0x349, 0x000F, 0 },
2774};
2775
2776/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */
2777static const struct nphy_rf_control_override_rev7
2778 tbl_rf_control_override_rev7_over1[] = {
2779 { 0x0002, 0x340, 0x341, 0x0002, 1 },
2780 { 0x0008, 0x340, 0x341, 0x0008, 3 },
2781 { 0x0020, 0x340, 0x341, 0x0020, 5 },
2782 { 0x0010, 0x340, 0x341, 0x0010, 4 },
2783 { 0x0004, 0x340, 0x341, 0x0004, 2 },
2784 { 0x0080, 0x340, 0x341, 0x0700, 8 },
2785 { 0x0800, 0x340, 0x341, 0x4000, 14 },
2786 { 0x0400, 0x340, 0x341, 0x2000, 13 },
2787 { 0x0200, 0x340, 0x341, 0x0800, 12 },
2788 { 0x0100, 0x340, 0x341, 0x0100, 11 },
2789 { 0x0040, 0x340, 0x341, 0x0040, 6 },
2790 { 0x0001, 0x340, 0x341, 0x0001, 0 },
2791};
2792
2793/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */
2794static const struct nphy_rf_control_override_rev7
2795 tbl_rf_control_override_rev7_over2[] = {
2796 { 0x0008, 0x344, 0x345, 0x0008, 3 },
2797 { 0x0002, 0x344, 0x345, 0x0002, 1 },
2798 { 0x0001, 0x344, 0x345, 0x0001, 0 },
2799 { 0x0004, 0x344, 0x345, 0x0004, 2 },
2800 { 0x0010, 0x344, 0x345, 0x0010, 4 },
2801};
2802
2760struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = { 2803struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = {
2761 { 10, 14, 19, 27 }, 2804 { 10, 14, 19, 27 },
2762 { -5, 6, 10, 15 }, 2805 { -5, 6, 10, 15 },
@@ -3248,3 +3291,35 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
3248 3291
3249 return e; 3292 return e;
3250} 3293}
3294
3295const struct nphy_rf_control_override_rev7 *b43_nphy_get_rf_ctl_over_rev7(
3296 struct b43_wldev *dev, u16 field, u8 override)
3297{
3298 const struct nphy_rf_control_override_rev7 *e;
3299 u8 size, i;
3300
3301 switch (override) {
3302 case 0:
3303 e = tbl_rf_control_override_rev7_over0;
3304 size = ARRAY_SIZE(tbl_rf_control_override_rev7_over0);
3305 break;
3306 case 1:
3307 e = tbl_rf_control_override_rev7_over1;
3308 size = ARRAY_SIZE(tbl_rf_control_override_rev7_over1);
3309 break;
3310 case 2:
3311 e = tbl_rf_control_override_rev7_over2;
3312 size = ARRAY_SIZE(tbl_rf_control_override_rev7_over2);
3313 break;
3314 default:
3315 b43err(dev->wl, "Invalid override value %d\n", override);
3316 return NULL;
3317 }
3318
3319 for (i = 0; i < size; i++) {
3320 if (e[i].field == field)
3321 return &e[i];
3322 }
3323
3324 return NULL;
3325}
diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h
index f348953c0230..c600700ceedc 100644
--- a/drivers/net/wireless/b43/tables_nphy.h
+++ b/drivers/net/wireless/b43/tables_nphy.h
@@ -35,6 +35,14 @@ struct nphy_rf_control_override_rev3 {
35 u8 val_addr1; 35 u8 val_addr1;
36}; 36};
37 37
38struct nphy_rf_control_override_rev7 {
39 u16 field;
40 u16 val_addr_core0;
41 u16 val_addr_core1;
42 u16 val_mask;
43 u8 val_shift;
44};
45
38struct nphy_gain_ctl_workaround_entry { 46struct nphy_gain_ctl_workaround_entry {
39 s8 lna1_gain[4]; 47 s8 lna1_gain[4];
40 s8 lna2_gain[4]; 48 s8 lna2_gain[4];
@@ -202,5 +210,7 @@ extern const struct nphy_rf_control_override_rev2
202 tbl_rf_control_override_rev2[]; 210 tbl_rf_control_override_rev2[];
203extern const struct nphy_rf_control_override_rev3 211extern const struct nphy_rf_control_override_rev3
204 tbl_rf_control_override_rev3[]; 212 tbl_rf_control_override_rev3[];
213const struct nphy_rf_control_override_rev7 *b43_nphy_get_rf_ctl_over_rev7(
214 struct b43_wldev *dev, u16 field, u8 override);
205 215
206#endif /* B43_TABLES_NPHY_H_ */ 216#endif /* B43_TABLES_NPHY_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 11:34:20 -0500