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authorMichael Buesch <mb@bu3sch.de>2008-01-13 15:23:44 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:09:53 -0500
commit53a6e2342d73d509318836e320f70cd286acd69c (patch)
tree835a25c8d48465840a8cdea8c363c58f567d921c /drivers/net/wireless/b43
parentaf4b7450788426a113057ce2d85c25b4f4e440d1 (diff)
b43: Add NPHY radio init code
This adds some code to init the 2055 radio. This patch adds two files "tables_nphy.h" and "tables_nphy.c" Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r--drivers/net/wireless/b43/Makefile1
-rw-r--r--drivers/net/wireless/b43/main.c3
-rw-r--r--drivers/net/wireless/b43/nphy.c98
-rw-r--r--drivers/net/wireless/b43/nphy.h9
-rw-r--r--drivers/net/wireless/b43/phy.c81
-rw-r--r--drivers/net/wireless/b43/phy.h20
-rw-r--r--drivers/net/wireless/b43/tables_nphy.c292
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h17
8 files changed, 512 insertions, 9 deletions
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 2002b8e7feb0..ac1329dba045 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -1,5 +1,6 @@
1b43-y += main.o 1b43-y += main.o
2b43-y += tables.o 2b43-y += tables.o
3b43-y += tables_nphy.o
3b43-y += phy.o 4b43-y += phy.o
4b43-y += nphy.o 5b43-y += nphy.o
5b43-y += sysfs.o 6b43-y += sysfs.o
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 560d1421e679..0d9824c7e28f 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -2132,6 +2132,7 @@ static void b43_rate_memory_init(struct b43_wldev *dev)
2132 switch (dev->phy.type) { 2132 switch (dev->phy.type) {
2133 case B43_PHYTYPE_A: 2133 case B43_PHYTYPE_A:
2134 case B43_PHYTYPE_G: 2134 case B43_PHYTYPE_G:
2135 case B43_PHYTYPE_N:
2135 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2136 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2136 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2137 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2137 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2138 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
@@ -2320,6 +2321,8 @@ static void b43_periodic_every60sec(struct b43_wldev *dev)
2320{ 2321{
2321 struct b43_phy *phy = &dev->phy; 2322 struct b43_phy *phy = &dev->phy;
2322 2323
2324 if (phy->type != B43_PHYTYPE_G)
2325 return;
2323 if (!b43_has_hardware_pctl(phy)) 2326 if (!b43_has_hardware_pctl(phy))
2324 b43_lo_g_ctl_mark_all_unused(dev); 2327 b43_lo_g_ctl_mark_all_unused(dev);
2325 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { 2328 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
diff --git a/drivers/net/wireless/b43/nphy.c b/drivers/net/wireless/b43/nphy.c
index 6d92545b1fae..b427aeeaa1f2 100644
--- a/drivers/net/wireless/b43/nphy.c
+++ b/drivers/net/wireless/b43/nphy.c
@@ -24,11 +24,107 @@
24 24
25#include "b43.h" 25#include "b43.h"
26#include "nphy.h" 26#include "nphy.h"
27#include "tables_nphy.h"
27 28
28 29
30void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
31{//TODO
32}
33
34void b43_nphy_xmitpower(struct b43_wldev *dev)
35{//TODO
36}
37
38/* Tune the hardware to a new channel. Don't call this directly.
39 * Use b43_radio_selectchannel() */
40void b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
41{
42
43//TODO
44}
45
46static void b43_radio_init2055_pre(struct b43_wldev *dev)
47{
48 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
49 ~B43_NPHY_RFCTL_CMD_PORFORCE);
50 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
51 B43_NPHY_RFCTL_CMD_CHIP0PU |
52 B43_NPHY_RFCTL_CMD_OEPORFORCE);
53 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
54 B43_NPHY_RFCTL_CMD_PORFORCE);
55}
56
57static void b43_radio_init2055_post(struct b43_wldev *dev)
58{
59 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
60 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
61 int i;
62 u16 val;
63
64 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
65 msleep(1);
66 if ((sprom->revision != 4) || !(sprom->boardflags_hi & 0x0002)) {
67 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
68 (binfo->type != 0x46D) ||
69 (binfo->rev < 0x41)) {
70 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
71 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
72 msleep(1);
73 }
74 }
75 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
76 msleep(1);
77 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
78 msleep(1);
79 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
80 msleep(1);
81 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
82 msleep(1);
83 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
84 msleep(1);
85 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
86 msleep(1);
87 for (i = 0; i < 100; i++) {
88 val = b43_radio_read16(dev, B2055_CAL_COUT2);
89 if (val & 0x80)
90 break;
91 udelay(10);
92 }
93 msleep(1);
94 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
95 msleep(1);
96 b43_radio_selectchannel(dev, dev->phy.channel, 0);
97 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
98 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
99 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
100 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
101}
102
103/* Initialize a Broadcom 2055 N-radio */
104static void b43_radio_init2055(struct b43_wldev *dev)
105{
106 b43_radio_init2055_pre(dev);
107 if (b43_status(dev) < B43_STAT_INITIALIZED)
108 b2055_upload_inittab(dev, 0, 1);
109 else
110 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
111 b43_radio_init2055_post(dev);
112}
113
114void b43_nphy_radio_turn_on(struct b43_wldev *dev)
115{
116 b43_radio_init2055(dev);
117}
118
119void b43_nphy_radio_turn_off(struct b43_wldev *dev)
120{
121 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
122 ~B43_NPHY_RFCTL_CMD_EN);
123}
124
29int b43_phy_initn(struct b43_wldev *dev) 125int b43_phy_initn(struct b43_wldev *dev)
30{ 126{
31 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); 127 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
32 128
33 return -EOPNOTSUPP; 129 return 0;
34} 130}
diff --git a/drivers/net/wireless/b43/nphy.h b/drivers/net/wireless/b43/nphy.h
index 71446dc7420d..812761d8e1e9 100644
--- a/drivers/net/wireless/b43/nphy.h
+++ b/drivers/net/wireless/b43/nphy.h
@@ -177,6 +177,7 @@
177#define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */ 177#define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */
178#define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */ 178#define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */
179#define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */ 179#define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */
180#define B43_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */
180#define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */ 181#define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */
181#define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12 182#define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12
182#define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */ 183#define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */
@@ -913,4 +914,12 @@ struct b43_wldev;
913 914
914int b43_phy_initn(struct b43_wldev *dev); 915int b43_phy_initn(struct b43_wldev *dev);
915 916
917void b43_nphy_radio_turn_on(struct b43_wldev *dev);
918void b43_nphy_radio_turn_off(struct b43_wldev *dev);
919
920void b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel);
921
922void b43_nphy_xmitpower(struct b43_wldev *dev);
923void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna);
924
916#endif /* B43_NPHY_H_ */ 925#endif /* B43_NPHY_H_ */
diff --git a/drivers/net/wireless/b43/phy.c b/drivers/net/wireless/b43/phy.c
index 2abf125aa2cf..03cca61fdf84 100644
--- a/drivers/net/wireless/b43/phy.c
+++ b/drivers/net/wireless/b43/phy.c
@@ -308,6 +308,24 @@ void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
308 b43_write16(dev, B43_MMIO_PHY_DATA, val); 308 b43_write16(dev, B43_MMIO_PHY_DATA, val);
309} 309}
310 310
311void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
312{
313 b43_phy_write(dev, offset,
314 b43_phy_read(dev, offset) & mask);
315}
316
317void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
318{
319 b43_phy_write(dev, offset,
320 b43_phy_read(dev, offset) | set);
321}
322
323void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
324{
325 b43_phy_write(dev, offset,
326 (b43_phy_read(dev, offset) & mask) | set);
327}
328
311/* Adjust the transmission power output (G-PHY) */ 329/* Adjust the transmission power output (G-PHY) */
312void b43_set_txpower_g(struct b43_wldev *dev, 330void b43_set_txpower_g(struct b43_wldev *dev,
313 const struct b43_bbatt *bbatt, 331 const struct b43_bbatt *bbatt,
@@ -1857,6 +1875,9 @@ void b43_phy_xmitpower(struct b43_wldev *dev)
1857 b43_phy_unlock(dev); 1875 b43_phy_unlock(dev);
1858 break; 1876 break;
1859 } 1877 }
1878 case B43_PHYTYPE_N:
1879 b43_nphy_xmitpower(dev);
1880 break;
1860 default: 1881 default:
1861 B43_WARN_ON(1); 1882 B43_WARN_ON(1);
1862 } 1883 }
@@ -2116,6 +2137,9 @@ void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2116 << B43_PHY_BBANDCFG_RXANT_SHIFT; 2137 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2117 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp); 2138 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2118 break; 2139 break;
2140 case B43_PHYTYPE_N:
2141 b43_nphy_set_rxantenna(dev, antenna);
2142 break;
2119 default: 2143 default:
2120 B43_WARN_ON(1); 2144 B43_WARN_ON(1);
2121 } 2145 }
@@ -2215,6 +2239,24 @@ void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2215 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val); 2239 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2216} 2240}
2217 2241
2242void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
2243{
2244 b43_radio_write16(dev, offset,
2245 b43_radio_read16(dev, offset) & mask);
2246}
2247
2248void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
2249{
2250 b43_radio_write16(dev, offset,
2251 b43_radio_read16(dev, offset) | set);
2252}
2253
2254void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
2255{
2256 b43_radio_write16(dev, offset,
2257 (b43_radio_read16(dev, offset) & mask) | set);
2258}
2259
2218static void b43_set_all_gains(struct b43_wldev *dev, 2260static void b43_set_all_gains(struct b43_wldev *dev,
2219 s16 first, s16 second, s16 third) 2261 s16 first, s16 second, s16 third)
2220{ 2262{
@@ -3852,6 +3894,10 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
3852 case B43_PHYTYPE_G: 3894 case B43_PHYTYPE_G:
3853 channel = B43_DEFAULT_CHANNEL_BG; 3895 channel = B43_DEFAULT_CHANNEL_BG;
3854 break; 3896 break;
3897 case B43_PHYTYPE_N:
3898 //FIXME check if we are on 2.4GHz or 5GHz and set a default channel.
3899 channel = 1;
3900 break;
3855 default: 3901 default:
3856 B43_WARN_ON(1); 3902 B43_WARN_ON(1);
3857 } 3903 }
@@ -3861,11 +3907,13 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
3861 * firmware from sending ghost packets. 3907 * firmware from sending ghost packets.
3862 */ 3908 */
3863 channelcookie = channel; 3909 channelcookie = channel;
3864 if (phy->type == B43_PHYTYPE_A) 3910 if (0 /*FIXME on 5Ghz */)
3865 channelcookie |= 0x100; 3911 channelcookie |= 0x100;
3912 //FIXME set 40Mhz flag if required
3866 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie); 3913 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
3867 3914
3868 if (phy->type == B43_PHYTYPE_A) { 3915 switch (phy->type) {
3916 case B43_PHYTYPE_A:
3869 if (channel > 200) 3917 if (channel > 200)
3870 return -EINVAL; 3918 return -EINVAL;
3871 freq = channel2freq_a(channel); 3919 freq = channel2freq_a(channel);
@@ -3914,7 +3962,8 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
3914 b43_radio_set_tx_iq(dev); 3962 b43_radio_set_tx_iq(dev);
3915 //TODO: TSSI2dbm workaround 3963 //TODO: TSSI2dbm workaround
3916 b43_phy_xmitpower(dev); //FIXME correct? 3964 b43_phy_xmitpower(dev); //FIXME correct?
3917 } else { 3965 break;
3966 case B43_PHYTYPE_G:
3918 if ((channel < 1) || (channel > 14)) 3967 if ((channel < 1) || (channel > 14))
3919 return -EINVAL; 3968 return -EINVAL;
3920 3969
@@ -3939,6 +3988,12 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
3939 b43_read16(dev, B43_MMIO_CHANNEL_EXT) 3988 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3940 & 0xF7BF); 3989 & 0xF7BF);
3941 } 3990 }
3991 break;
3992 case B43_PHYTYPE_N:
3993 b43_nphy_selectchannel(dev, channel);
3994 break;
3995 default:
3996 B43_WARN_ON(1);
3942 } 3997 }
3943 3998
3944 phy->channel = channel; 3999 phy->channel = channel;
@@ -3985,6 +4040,9 @@ void b43_radio_turn_on(struct b43_wldev *dev)
3985 err |= b43_radio_selectchannel(dev, channel, 0); 4040 err |= b43_radio_selectchannel(dev, channel, 0);
3986 B43_WARN_ON(err); 4041 B43_WARN_ON(err);
3987 break; 4042 break;
4043 case B43_PHYTYPE_N:
4044 b43_nphy_radio_turn_on(dev);
4045 break;
3988 default: 4046 default:
3989 B43_WARN_ON(1); 4047 B43_WARN_ON(1);
3990 } 4048 }
@@ -3998,13 +4056,17 @@ void b43_radio_turn_off(struct b43_wldev *dev, bool force)
3998 if (!phy->radio_on && !force) 4056 if (!phy->radio_on && !force)
3999 return; 4057 return;
4000 4058
4001 if (phy->type == B43_PHYTYPE_A) { 4059 switch (phy->type) {
4060 case B43_PHYTYPE_N:
4061 b43_nphy_radio_turn_off(dev);
4062 break;
4063 case B43_PHYTYPE_A:
4002 b43_radio_write16(dev, 0x0004, 0x00FF); 4064 b43_radio_write16(dev, 0x0004, 0x00FF);
4003 b43_radio_write16(dev, 0x0005, 0x00FB); 4065 b43_radio_write16(dev, 0x0005, 0x00FB);
4004 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008); 4066 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
4005 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008); 4067 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
4006 } 4068 break;
4007 if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) { 4069 case B43_PHYTYPE_G: {
4008 u16 rfover, rfoverval; 4070 u16 rfover, rfoverval;
4009 4071
4010 rfover = b43_phy_read(dev, B43_PHY_RFOVER); 4072 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
@@ -4016,7 +4078,10 @@ void b43_radio_turn_off(struct b43_wldev *dev, bool force)
4016 } 4078 }
4017 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C); 4079 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
4018 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73); 4080 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
4019 } else 4081 break;
4020 b43_phy_write(dev, 0x0015, 0xAA00); 4082 }
4083 default:
4084 B43_WARN_ON(1);
4085 }
4021 phy->radio_on = 0; 4086 phy->radio_on = 0;
4022} 4087}
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h
index ab1e7f097022..6d165d822175 100644
--- a/drivers/net/wireless/b43/phy.h
+++ b/drivers/net/wireless/b43/phy.h
@@ -204,8 +204,18 @@ enum {
204void b43_phy_lock(struct b43_wldev *dev); 204void b43_phy_lock(struct b43_wldev *dev);
205void b43_phy_unlock(struct b43_wldev *dev); 205void b43_phy_unlock(struct b43_wldev *dev);
206 206
207
208/* Read a value from a PHY register */
207u16 b43_phy_read(struct b43_wldev *dev, u16 offset); 209u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
210/* Write a value to a PHY register */
208void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val); 211void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
212/* Mask a PHY register with a mask */
213void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
214/* OR a PHY register with a bitmap */
215void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
216/* Mask and OR a PHY register with a mask and bitmap */
217void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
218
209 219
210int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev); 220int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
211 221
@@ -269,8 +279,18 @@ extern const u8 b43_radio_channel_codes_bg[];
269void b43_radio_lock(struct b43_wldev *dev); 279void b43_radio_lock(struct b43_wldev *dev);
270void b43_radio_unlock(struct b43_wldev *dev); 280void b43_radio_unlock(struct b43_wldev *dev);
271 281
282
283/* Read a value from a 16bit radio register */
272u16 b43_radio_read16(struct b43_wldev *dev, u16 offset); 284u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
285/* Write a value to a 16bit radio register */
273void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val); 286void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
287/* Mask a 16bit radio register with a mask */
288void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
289/* OR a 16bit radio register with a bitmap */
290void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
291/* Mask and OR a PHY register with a mask and bitmap */
292void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
293
274 294
275u16 b43_radio_init2050(struct b43_wldev *dev); 295u16 b43_radio_init2050(struct b43_wldev *dev);
276void b43_radio_init2060(struct b43_wldev *dev); 296void b43_radio_init2060(struct b43_wldev *dev);
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c
new file mode 100644
index 000000000000..ba93cf3713a2
--- /dev/null
+++ b/drivers/net/wireless/b43/tables_nphy.c
@@ -0,0 +1,292 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY and radio device data tables
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
26#include "tables_nphy.h"
27#include "phy.h"
28#include "nphy.h"
29
30
31struct b2055_inittab_entry {
32 /* Value to write if we use the 5GHz band. */
33 u16 ghz5;
34 /* Value to write if we use the 2.4GHz band. */
35 u16 ghz2;
36 /* Flags */
37 u8 flags;
38#define B2055_INITTAB_ENTRY_OK 0x01
39#define B2055_INITTAB_UPLOAD 0x02
40};
41#define UPLOAD .flags = B2055_INITTAB_ENTRY_OK | B2055_INITTAB_UPLOAD
42#define NOUPLOAD .flags = B2055_INITTAB_ENTRY_OK
43
44static struct b2055_inittab_entry b2055_inittab [] = {
45 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
46 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
47 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
48 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
49 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
50 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
51 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
52 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
53 [B2055_C2_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
54 [B2055_C1_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
55 [B2055_C2_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
56 [B2055_C1_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, },
57 [B2055_C1_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, },
58 [B2055_C2_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, },
59 [B2055_C2_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, },
60 [B2055_MASTER1] = { .ghz5 = 0x00D0, .ghz2 = 0x00D0, NOUPLOAD, },
61 [B2055_MASTER2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
62 [B2055_PD_LGEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
63 [B2055_PD_PLLTS] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
64 [B2055_C1_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
65 [B2055_C1_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
66 [B2055_C1_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
67 [B2055_C1_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
68 [B2055_C2_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
69 [B2055_C2_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
70 [B2055_C2_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
71 [B2055_C2_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
72 [B2055_PWRDET_LGEN] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, },
73 [B2055_C1_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
74 [B2055_C1_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, },
75 [B2055_C2_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
76 [B2055_C2_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, },
77 [B2055_RRCCAL_CS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
78 [B2055_RRCCAL_NOPTSEL] = { .ghz5 = 0x002C, .ghz2 = 0x002C, NOUPLOAD, },
79 [B2055_CAL_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
80 [B2055_CAL_COUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
81 [B2055_CAL_COUT2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
82 [B2055_CAL_CVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
83 [B2055_CAL_RVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
84 [B2055_CAL_LPOCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
85 [B2055_CAL_TS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
86 [B2055_CAL_RCCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
87 [B2055_CAL_RCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
88 [B2055_PADDRV] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, },
89 [B2055_XOCTL1] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
90 [B2055_XOCTL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
91 [B2055_XOREGUL] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
92 [B2055_XOMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
93 [B2055_PLL_LFC1] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
94 [B2055_PLL_CALVTH] = { .ghz5 = 0x0087, .ghz2 = 0x0087, NOUPLOAD, },
95 [B2055_PLL_LFC2] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, },
96 [B2055_PLL_REF] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
97 [B2055_PLL_LFR1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
98 [B2055_PLL_PFDCP] = { .ghz5 = 0x0018, .ghz2 = 0x0018, UPLOAD, },
99 [B2055_PLL_IDAC_CPOPAMP] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
100 [B2055_PLL_CPREG] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
101 [B2055_PLL_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
102 [B2055_RF_PLLMOD0] = { .ghz5 = 0x009E, .ghz2 = 0x009E, NOUPLOAD, },
103 [B2055_RF_PLLMOD1] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, },
104 [B2055_RF_MMDIDAC1] = { .ghz5 = 0x00C8, .ghz2 = 0x00C8, UPLOAD, },
105 [B2055_RF_MMDIDAC0] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
106 [B2055_RF_MMDSP] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
107 [B2055_VCO_CAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
108 [B2055_VCO_CAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
109 [B2055_VCO_CAL3] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
110 [B2055_VCO_CAL4] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
111 [B2055_VCO_CAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
112 [B2055_VCO_CAL6] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, },
113 [B2055_VCO_CAL7] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, },
114 [B2055_VCO_CAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
115 [B2055_VCO_CAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
116 [B2055_VCO_CAL10] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
117 [B2055_VCO_CAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
118 [B2055_VCO_CAL12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
119 [B2055_VCO_CAL13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
120 [B2055_VCO_CAL14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
121 [B2055_VCO_CAL15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
122 [B2055_VCO_CAL16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
123 [B2055_VCO_KVCO] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
124 [B2055_VCO_CAPTAIL] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
125 [B2055_VCO_IDACVCO] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
126 [B2055_VCO_REG] = { .ghz5 = 0x0084, .ghz2 = 0x0084, UPLOAD, },
127 [B2055_PLL_RFVTH] = { .ghz5 = 0x00C3, .ghz2 = 0x00C3, NOUPLOAD, },
128 [B2055_LGBUF_CENBUF] = { .ghz5 = 0x008F, .ghz2 = 0x008F, NOUPLOAD, },
129 [B2055_LGEN_TUNE1] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
130 [B2055_LGEN_TUNE2] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
131 [B2055_LGEN_IDAC1] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
132 [B2055_LGEN_IDAC2] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
133 [B2055_LGEN_BIASC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
134 [B2055_LGEN_BIASIDAC] = { .ghz5 = 0x00CC, .ghz2 = 0x00CC, NOUPLOAD, },
135 [B2055_LGEN_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
136 [B2055_LGEN_DIV] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
137 [B2055_LGEN_SPARE2] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
138 [B2055_C1_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, },
139 [B2055_C1_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
140 [B2055_C1_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
141 [B2055_C1_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, },
142 [B2055_C1_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
143 [B2055_C1_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
144 [B2055_C1_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, },
145 [B2055_C1_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, },
146 [B2055_C1_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
147 [B2055_C1_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
148 [B2055_C1_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
149 [B2055_C1_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, },
150 [B2055_C1_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
151 [B2055_C1_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
152 [B2055_C1_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
153 [B2055_C1_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
154 [B2055_C1_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
155 [B2055_C1_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
156 [B2055_C1_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
157 [B2055_C1_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, },
158 [B2055_C1_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, },
159 [B2055_C1_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, },
160 [B2055_C1_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, },
161 [B2055_C1_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, },
162 [B2055_C1_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
163 [B2055_C1_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
164 [B2055_C1_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
165 [B2055_C1_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
166 [B2055_C1_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
167 [B2055_C1_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
168 [B2055_C1_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
169 [B2055_C1_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, },
170 [B2055_C1_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
171 [B2055_C1_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, },
172 [B2055_C1_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, },
173 [B2055_C1_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
174 [B2055_C1_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
175 [B2055_C1_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
176 [B2055_C1_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
177 [B2055_C1_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
178 [B2055_C1_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
179 [B2055_C1_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, },
180 [B2055_C1_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
181 [B2055_C1_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, },
182 [B2055_C1_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
183 [B2055_C1_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, },
184 [B2055_C1_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
185 [B2055_C2_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, },
186 [B2055_C2_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
187 [B2055_C2_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
188 [B2055_C2_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, },
189 [B2055_C2_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
190 [B2055_C2_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
191 [B2055_C2_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, },
192 [B2055_C2_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, },
193 [B2055_C2_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
194 [B2055_C2_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
195 [B2055_C2_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
196 [B2055_C2_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, },
197 [B2055_C2_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
198 [B2055_C2_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
199 [B2055_C2_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
200 [B2055_C2_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
201 [B2055_C2_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
202 [B2055_C2_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
203 [B2055_C2_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
204 [B2055_C2_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, },
205 [B2055_C2_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, },
206 [B2055_C2_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, },
207 [B2055_C2_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, },
208 [B2055_C2_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, },
209 [B2055_C2_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
210 [B2055_C2_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
211 [B2055_C2_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
212 [B2055_C2_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
213 [B2055_C2_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
214 [B2055_C2_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
215 [B2055_C2_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
216 [B2055_C2_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, },
217 [B2055_C2_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
218 [B2055_C2_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, },
219 [B2055_C2_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, },
220 [B2055_C2_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
221 [B2055_C2_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
222 [B2055_C2_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
223 [B2055_C2_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
224 [B2055_C2_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
225 [B2055_C2_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
226 [B2055_C2_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, },
227 [B2055_C2_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
228 [B2055_C2_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, },
229 [B2055_C2_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
230 [B2055_C2_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, },
231 [B2055_C2_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
232 [B2055_PRG_GCHP21] = { .ghz5 = 0x0071, .ghz2 = 0x0071, NOUPLOAD, },
233 [B2055_PRG_GCHP22] = { .ghz5 = 0x0072, .ghz2 = 0x0072, NOUPLOAD, },
234 [B2055_PRG_GCHP23] = { .ghz5 = 0x0073, .ghz2 = 0x0073, NOUPLOAD, },
235 [B2055_PRG_GCHP24] = { .ghz5 = 0x0074, .ghz2 = 0x0074, NOUPLOAD, },
236 [B2055_PRG_GCHP25] = { .ghz5 = 0x0075, .ghz2 = 0x0075, NOUPLOAD, },
237 [B2055_PRG_GCHP26] = { .ghz5 = 0x0076, .ghz2 = 0x0076, NOUPLOAD, },
238 [B2055_PRG_GCHP27] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
239 [B2055_PRG_GCHP28] = { .ghz5 = 0x0078, .ghz2 = 0x0078, NOUPLOAD, },
240 [B2055_PRG_GCHP29] = { .ghz5 = 0x0079, .ghz2 = 0x0079, NOUPLOAD, },
241 [B2055_PRG_GCHP30] = { .ghz5 = 0x007A, .ghz2 = 0x007A, NOUPLOAD, },
242 [0xC7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
243 [0xC8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
244 [0xC9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
245 [0xCA] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
246 [0xCB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
247 [0xCC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
248 [B2055_C1_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
249 [0xCE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
250 [0xCF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
251 [0xD0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
252 [0xD1] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
253 [B2055_C1_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
254 [0xD3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
255 [0xD4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
256 [0xD5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
257 [B2055_C1_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
258 [0xD7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
259 [0xD8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
260 [B2055_C2_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
261 [0xDA] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
262 [0xDB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
263 [0xDC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
264 [0xDD] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
265 [B2055_C2_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
266 [0xDF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
267 [0xE0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
268 [0xE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
269 [B2055_C2_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
270};
271
272
273void b2055_upload_inittab(struct b43_wldev *dev,
274 bool ghz5, bool ignore_uploadflag)
275{
276 struct b2055_inittab_entry *e;
277 unsigned int i;
278 u16 value;
279
280 for (i = 0; i < ARRAY_SIZE(b2055_inittab); i++) {
281 e = &(b2055_inittab[i]);
282 if (!(e->flags & B2055_INITTAB_ENTRY_OK))
283 continue;
284 if ((e->flags & B2055_INITTAB_UPLOAD) || ignore_uploadflag) {
285 if (ghz5)
286 value = e->ghz5;
287 else
288 value = e->ghz2;
289 b43_radio_write16(dev, i, value);
290 }
291 }
292}
diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h
new file mode 100644
index 000000000000..1a96cf910003
--- /dev/null
+++ b/drivers/net/wireless/b43/tables_nphy.h
@@ -0,0 +1,17 @@
1#ifndef B43_TABLES_NPHY_H_
2#define B43_TABLES_NPHY_H_
3
4#include <linux/types.h>
5
6
7struct b43_wldev;
8
9/* Upload the default register value table.
10 * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
11 * table is uploaded. If "ignore_uploadflag" is true, we upload any value
12 * and ignore the "UPLOAD" flag. */
13void b2055_upload_inittab(struct b43_wldev *dev,
14 bool ghz5, bool ignore_uploadflag);
15
16
17#endif /* B43_TABLES_NPHY_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 04:51:02 -0400