diff options
author | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
---|---|---|
committer | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
commit | ada47b5fe13d89735805b566185f4885f5a3f750 (patch) | |
tree | 644b88f8a71896307d71438e9b3af49126ffb22b /drivers/net/wireless/b43/phy_n.h | |
parent | 43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff) | |
parent | 3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff) |
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/net/wireless/b43/phy_n.h')
-rw-r--r-- | drivers/net/wireless/b43/phy_n.h | 98 |
1 files changed, 97 insertions, 1 deletions
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h index 1749aef4147d..403aad3f894f 100644 --- a/drivers/net/wireless/b43/phy_n.h +++ b/drivers/net/wireless/b43/phy_n.h | |||
@@ -231,6 +231,7 @@ | |||
231 | #define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */ | 231 | #define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */ |
232 | #define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */ | 232 | #define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */ |
233 | #define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */ | 233 | #define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */ |
234 | #define B43_NPHY_AFECTL_OVER1 B43_PHY_N(0x08F) /* AFE control override 1 */ | ||
234 | #define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */ | 235 | #define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */ |
235 | #define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */ | 236 | #define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */ |
236 | #define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0 | 237 | #define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0 |
@@ -705,6 +706,10 @@ | |||
705 | #define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power controll init */ | 706 | #define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power controll init */ |
706 | #define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ | 707 | #define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ |
707 | #define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 | 708 | #define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 |
709 | #define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ | ||
710 | #define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ | ||
711 | #define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ | ||
712 | #define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ | ||
708 | 713 | ||
709 | 714 | ||
710 | 715 | ||
@@ -919,8 +924,99 @@ | |||
919 | 924 | ||
920 | struct b43_wldev; | 925 | struct b43_wldev; |
921 | 926 | ||
927 | struct b43_phy_n_iq_comp { | ||
928 | s16 a0; | ||
929 | s16 b0; | ||
930 | s16 a1; | ||
931 | s16 b1; | ||
932 | }; | ||
933 | |||
934 | struct b43_phy_n_rssical_cache { | ||
935 | u16 rssical_radio_regs_2G[2]; | ||
936 | u16 rssical_phy_regs_2G[12]; | ||
937 | |||
938 | u16 rssical_radio_regs_5G[2]; | ||
939 | u16 rssical_phy_regs_5G[12]; | ||
940 | }; | ||
941 | |||
942 | struct b43_phy_n_cal_cache { | ||
943 | u16 txcal_radio_regs_2G[8]; | ||
944 | u16 txcal_coeffs_2G[8]; | ||
945 | struct b43_phy_n_iq_comp rxcal_coeffs_2G; | ||
946 | |||
947 | u16 txcal_radio_regs_5G[8]; | ||
948 | u16 txcal_coeffs_5G[8]; | ||
949 | struct b43_phy_n_iq_comp rxcal_coeffs_5G; | ||
950 | }; | ||
951 | |||
952 | struct b43_phy_n_txpwrindex { | ||
953 | s8 index; | ||
954 | s8 index_internal; | ||
955 | s8 index_internal_save; | ||
956 | u16 AfectrlOverride; | ||
957 | u16 AfeCtrlDacGain; | ||
958 | u16 rad_gain; | ||
959 | u8 bbmult; | ||
960 | u16 iqcomp_a; | ||
961 | u16 iqcomp_b; | ||
962 | u16 locomp; | ||
963 | }; | ||
964 | |||
922 | struct b43_phy_n { | 965 | struct b43_phy_n { |
923 | //TODO lots of missing stuff | 966 | u8 antsel_type; |
967 | u8 cal_orig_pwr_idx[2]; | ||
968 | u8 measure_hold; | ||
969 | u8 phyrxchain; | ||
970 | u8 perical; | ||
971 | u32 deaf_count; | ||
972 | u32 rxcalparams; | ||
973 | bool hang_avoid; | ||
974 | bool mute; | ||
975 | u16 papd_epsilon_offset[2]; | ||
976 | s32 preamble_override; | ||
977 | u32 bb_mult_save; | ||
978 | u16 radio_chanspec; | ||
979 | |||
980 | bool gain_boost; | ||
981 | bool elna_gain_config; | ||
982 | bool band5g_pwrgain; | ||
983 | |||
984 | u8 mphase_cal_phase_id; | ||
985 | u16 mphase_txcal_cmdidx; | ||
986 | u16 mphase_txcal_numcmds; | ||
987 | u16 mphase_txcal_bestcoeffs[11]; | ||
988 | |||
989 | u8 txpwrctrl; | ||
990 | u16 txcal_bbmult; | ||
991 | u16 txiqlocal_bestc[11]; | ||
992 | bool txiqlocal_coeffsvalid; | ||
993 | struct b43_phy_n_txpwrindex txpwrindex[2]; | ||
994 | |||
995 | u8 txrx_chain; | ||
996 | u16 tx_rx_cal_phy_saveregs[11]; | ||
997 | u16 tx_rx_cal_radio_saveregs[22]; | ||
998 | |||
999 | u16 rfctrl_intc1_save; | ||
1000 | u16 rfctrl_intc2_save; | ||
1001 | |||
1002 | u16 classifier_state; | ||
1003 | u16 clip_state[2]; | ||
1004 | |||
1005 | bool aband_spurwar_en; | ||
1006 | bool gband_spurwar_en; | ||
1007 | |||
1008 | bool ipa2g_on; | ||
1009 | u8 iqcal_chanspec_2G; | ||
1010 | u8 rssical_chanspec_2G; | ||
1011 | |||
1012 | bool ipa5g_on; | ||
1013 | u8 iqcal_chanspec_5G; | ||
1014 | u8 rssical_chanspec_5G; | ||
1015 | |||
1016 | struct b43_phy_n_rssical_cache rssical_cache; | ||
1017 | struct b43_phy_n_cal_cache cal_cache; | ||
1018 | bool crsminpwr_adjusted; | ||
1019 | bool noisevars_adjusted; | ||
924 | }; | 1020 | }; |
925 | 1021 | ||
926 | 1022 | ||