b43: Add LP-PHY baseband init for >=rev2

This adds code for the baseband init of LP-PHY >=2.

Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 76 insertions, 2 deletions

diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index ec83b8cd2f2e..3c7be8308587 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -3,7 +3,7 @@
   Broadcom B43 wireless driver
   IEEE 802.11g LP-PHY driver
 
-  Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
@@ -25,6 +25,7 @@
 #include "b43.h"
 #include "phy_lp.h"
 #include "phy_common.h"
+#include "tables_lpphy.h"
 
 
 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
@@ -69,7 +70,80 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
 
 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
 {
-        //TODO
+        struct b43_phy_lp *lpphy = dev->phy.lp;
+
+        b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
+        b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
+        b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
+        b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
+        b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
+        b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
+        b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
+        b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
+        b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
+        b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x78);
+        b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
+        b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
+        b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
+        b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
+        b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
+        b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
+        b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
+        b43_phy_maskset(dev, B43_LPPHY_CCKLMSSTEPSIZE, 0xFF01, 0x10);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);//FIXME specs are different
+        b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
+        b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
+        b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
+        b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
+        b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
+        b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
+        b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
+        b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
+        b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
+        b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
+        b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
+        b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
+        b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
+        b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
+
+        if (dev->phy.rev < 2) {
+                //FIXME this will never execute.
+
+                //FIXME 32bit?
+                b43_lptab_write(dev, B43_LPTAB32(0x11, 0x14), 0);
+                b43_lptab_write(dev, B43_LPTAB32(0x08, 0x12), 0x40);
+        } else {
+                //FIXME 32bit?
+                b43_lptab_write(dev, B43_LPTAB32(0x08, 0x14), 0);
+                b43_lptab_write(dev, B43_LPTAB32(0x08, 0x12), 0x40);
+        }
+
+        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+                b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
+                b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
+                b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
+                b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
+                b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
+        } else /* 5GHz */
+                b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
+
+        b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
+        b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
+        b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
+        b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
+        b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
+        b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
+        b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
+                      0x2000 | ((u16)lpphy->rssi_gs << 10) |
+                      ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
 }
 
 static void lpphy_baseband_init(struct b43_wldev *dev)