diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2013-03-09 07:52:12 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2013-03-13 14:27:50 -0400 |
commit | 60e8fb9233e13e98b13a380ecc1cc05515e6e34c (patch) | |
tree | be9d5288e29840d9822744ab10bd89dc619d3745 /drivers/net/wireless/b43/phy_ht.h | |
parent | a51ab25811beef67bdd0ba2c5dd4b03e47948aa1 (diff) |
b43: HT-PHY: implement controlling TX power control
Don't enable it until we have (almost?) whole TX power management
figured out. It's similar to the N-PHY, the difference is that we call a
"fix" *before* disabling power control.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43/phy_ht.h')
-rw-r--r-- | drivers/net/wireless/b43/phy_ht.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h index 684807c2f125..bc7a43f58c61 100644 --- a/drivers/net/wireless/b43/phy_ht.h +++ b/drivers/net/wireless/b43/phy_ht.h | |||
@@ -22,6 +22,13 @@ | |||
22 | #define B43_PHY_HT_BW4 0x1D1 | 22 | #define B43_PHY_HT_BW4 0x1D1 |
23 | #define B43_PHY_HT_BW5 0x1D2 | 23 | #define B43_PHY_HT_BW5 0x1D2 |
24 | #define B43_PHY_HT_BW6 0x1D3 | 24 | #define B43_PHY_HT_BW6 0x1D3 |
25 | #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */ | ||
26 | #define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */ | ||
27 | #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */ | ||
28 | #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */ | ||
29 | #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */ | ||
30 | #define B43_PHY_HT_TXPCTL_CMD_C2 0x222 | ||
31 | #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F | ||
25 | 32 | ||
26 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) | 33 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) |
27 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) | 34 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) |
@@ -51,6 +58,9 @@ | |||
51 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) | 58 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) |
52 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) | 59 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) |
53 | 60 | ||
61 | #define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164) | ||
62 | #define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F | ||
63 | |||
54 | #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) | 64 | #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) |
55 | 65 | ||
56 | 66 | ||
@@ -67,6 +77,9 @@ struct b43_phy_ht_channeltab_e_phy { | |||
67 | 77 | ||
68 | struct b43_phy_ht { | 78 | struct b43_phy_ht { |
69 | u16 rf_ctl_int_save[3]; | 79 | u16 rf_ctl_int_save[3]; |
80 | |||
81 | bool tx_pwr_ctl; | ||
82 | u8 tx_pwr_idx[3]; | ||
70 | }; | 83 | }; |
71 | 84 | ||
72 | 85 | ||