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authorDavid S. Miller <davem@davemloft.net>2009-11-09 14:17:24 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-09 14:17:24 -0500
commitf6d773cd4f3c18c40ab25a5cb92453756237840e (patch)
tree5631a6ea4495ae2eb5058fb63b25dea3b197d61b /drivers/net/wireless/ath
parentd0e1e88d6e7dbd8e1661cb6a058ca30f54ee39e4 (diff)
parentbcb628d579a61d0ab0cac4c6cc8a403de5254920 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Diffstat (limited to 'drivers/net/wireless/ath')
-rw-r--r--drivers/net/wireless/ath/Kconfig1
-rw-r--r--drivers/net/wireless/ath/ar9170/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath5k/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath5k/led.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c669
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h22
-rw-r--r--drivers/net/wireless/ath/ath9k/initvals.h29
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c58
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c1100
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h40
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c3
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c3
18 files changed, 1135 insertions, 827 deletions
diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig
index 6ce86cb37654..4e7a7fd695c8 100644
--- a/drivers/net/wireless/ath/Kconfig
+++ b/drivers/net/wireless/ath/Kconfig
@@ -1,6 +1,5 @@
1menuconfig ATH_COMMON 1menuconfig ATH_COMMON
2 tristate "Atheros Wireless Cards" 2 tristate "Atheros Wireless Cards"
3 depends on WLAN_80211
4 depends on CFG80211 3 depends on CFG80211
5 ---help--- 4 ---help---
6 This will enable the support for the Atheros wireless drivers. 5 This will enable the support for the Atheros wireless drivers.
diff --git a/drivers/net/wireless/ath/ar9170/Kconfig b/drivers/net/wireless/ath/ar9170/Kconfig
index 05918f1e685a..d7a4799d20fb 100644
--- a/drivers/net/wireless/ath/ar9170/Kconfig
+++ b/drivers/net/wireless/ath/ar9170/Kconfig
@@ -1,6 +1,6 @@
1config AR9170_USB 1config AR9170_USB
2 tristate "Atheros AR9170 802.11n USB support" 2 tristate "Atheros AR9170 802.11n USB support"
3 depends on USB && MAC80211 && WLAN_80211 3 depends on USB && MAC80211
4 select FW_LOADER 4 select FW_LOADER
5 help 5 help
6 This is a driver for the Atheros "otus" 802.11n USB devices. 6 This is a driver for the Atheros "otus" 802.11n USB devices.
diff --git a/drivers/net/wireless/ath/ath5k/Kconfig b/drivers/net/wireless/ath/ath5k/Kconfig
index 06d006675d7d..eb83b7b4d0e3 100644
--- a/drivers/net/wireless/ath/ath5k/Kconfig
+++ b/drivers/net/wireless/ath/ath5k/Kconfig
@@ -1,6 +1,6 @@
1config ATH5K 1config ATH5K
2 tristate "Atheros 5xxx wireless cards support" 2 tristate "Atheros 5xxx wireless cards support"
3 depends on PCI && MAC80211 && WLAN_80211 3 depends on PCI && MAC80211
4 select MAC80211_LEDS 4 select MAC80211_LEDS
5 select LEDS_CLASS 5 select LEDS_CLASS
6 select NEW_LEDS 6 select NEW_LEDS
diff --git a/drivers/net/wireless/ath/ath5k/led.c b/drivers/net/wireless/ath/ath5k/led.c
index b767c3b67b24..7ce98bd7c749 100644
--- a/drivers/net/wireless/ath/ath5k/led.c
+++ b/drivers/net/wireless/ath/ath5k/led.c
@@ -59,6 +59,8 @@ static const struct pci_device_id ath5k_led_devices[] = {
59 { ATH_SDEVICE(PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID), ATH_LED(1, 1) }, 59 { ATH_SDEVICE(PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID), ATH_LED(1, 1) },
60 /* Acer Aspire One A150 (maximlevitsky@gmail.com) */ 60 /* Acer Aspire One A150 (maximlevitsky@gmail.com) */
61 { ATH_SDEVICE(PCI_VENDOR_ID_FOXCONN, 0xe008), ATH_LED(3, 0) }, 61 { ATH_SDEVICE(PCI_VENDOR_ID_FOXCONN, 0xe008), ATH_LED(3, 0) },
62 /* Acer Aspire One AO531h AO751h (keng-yu.lin@canonical.com) */
63 { ATH_SDEVICE(PCI_VENDOR_ID_FOXCONN, 0xe00d), ATH_LED(3, 0) },
62 /* Acer Ferrari 5000 (russ.dill@gmail.com) */ 64 /* Acer Ferrari 5000 (russ.dill@gmail.com) */
63 { ATH_SDEVICE(PCI_VENDOR_ID_AMBIT, 0x0422), ATH_LED(1, 1) }, 65 { ATH_SDEVICE(PCI_VENDOR_ID_AMBIT, 0x0422), ATH_LED(1, 1) },
64 /* E-machines E510 (tuliom@gmail.com) */ 66 /* E-machines E510 (tuliom@gmail.com) */
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index 99ce066392a7..b735fb399fb1 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -3,7 +3,7 @@ config ATH9K_HW
3 3
4config ATH9K 4config ATH9K
5 tristate "Atheros 802.11n wireless cards support" 5 tristate "Atheros 802.11n wireless cards support"
6 depends on PCI && MAC80211 && WLAN_80211 6 depends on PCI && MAC80211
7 select ATH9K_HW 7 select ATH9K_HW
8 select MAC80211_LEDS 8 select MAC80211_LEDS
9 select LEDS_CLASS 9 select LEDS_CLASS
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 25531f231b67..329e6bc137ab 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -69,6 +69,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
69 int irq; 69 int irq;
70 int ret = 0; 70 int ret = 0;
71 struct ath_hw *ah; 71 struct ath_hw *ah;
72 char hw_name[64];
72 73
73 if (!pdev->dev.platform_data) { 74 if (!pdev->dev.platform_data) {
74 dev_err(&pdev->dev, "no platform data specified\n"); 75 dev_err(&pdev->dev, "no platform data specified\n");
@@ -133,14 +134,11 @@ static int ath_ahb_probe(struct platform_device *pdev)
133 } 134 }
134 135
135 ah = sc->sc_ah; 136 ah = sc->sc_ah;
137 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
136 printk(KERN_INFO 138 printk(KERN_INFO
137 "%s: Atheros AR%s MAC/BB Rev:%x, " 139 "%s: %s mem=0x%lx, irq=%d\n",
138 "AR%s RF Rev:%x, mem=0x%lx, irq=%d\n",
139 wiphy_name(hw->wiphy), 140 wiphy_name(hw->wiphy),
140 ath_mac_bb_name(ah->hw_version.macVersion), 141 hw_name,
141 ah->hw_version.macRev,
142 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
143 ah->hw_version.phyRev,
144 (unsigned long)mem, irq); 142 (unsigned long)mem, irq);
145 143
146 return 0; 144 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 551f8801459f..238a5744d8e9 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -877,7 +877,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); 877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
878 878
879 /* find off_6_1; */ 879 /* find off_6_1; */
880 for (i = 6; i >= 0; i--) { 880 for (i = 6; i > 0; i--) {
881 regVal = REG_READ(ah, 0x7834); 881 regVal = REG_READ(ah, 0x7834);
882 regVal |= (1 << (20 + i)); 882 regVal |= (1 << (20 + i));
883 REG_WRITE(ah, 0x7834, regVal); 883 REG_WRITE(ah, 0x7834, regVal);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 58167d861dc6..68db16690abf 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -1112,6 +1112,10 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1112 1112
1113 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1113 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1114 pModal->txEndToRxOn); 1114 pModal->txEndToRxOn);
1115
1116 if (AR_SREV_9271_10(ah))
1117 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1118 pModal->txEndToRxOn);
1115 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1119 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1116 pModal->thresh62); 1120 pModal->thresh62);
1117 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1121 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index cab17c6c8a37..111ff049f75d 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -30,8 +30,6 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData, 31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value); 32 u32 reg, u32 value);
33static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
34static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35 33
36MODULE_AUTHOR("Atheros Communications"); 34MODULE_AUTHOR("Atheros Communications");
37MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -454,21 +452,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
454 ah->power_mode = ATH9K_PM_UNDEFINED; 452 ah->power_mode = ATH9K_PM_UNDEFINED;
455} 453}
456 454
457static int ath9k_hw_rfattach(struct ath_hw *ah)
458{
459 bool rfStatus = false;
460 int ecode = 0;
461
462 rfStatus = ath9k_hw_init_rf(ah, &ecode);
463 if (!rfStatus) {
464 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
465 "RF setup failed, status: %u\n", ecode);
466 return ecode;
467 }
468
469 return 0;
470}
471
472static int ath9k_hw_rf_claim(struct ath_hw *ah) 455static int ath9k_hw_rf_claim(struct ath_hw *ah)
473{ 456{
474 u32 val; 457 u32 val;
@@ -585,9 +568,15 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
585 ah->eep_ops->get_eeprom_ver(ah), 568 ah->eep_ops->get_eeprom_ver(ah),
586 ah->eep_ops->get_eeprom_rev(ah)); 569 ah->eep_ops->get_eeprom_rev(ah));
587 570
588 ecode = ath9k_hw_rfattach(ah); 571 if (!AR_SREV_9280_10_OR_LATER(ah)) {
589 if (ecode != 0) 572 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
590 return ecode; 573 if (ecode) {
574 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
575 "Failed allocating banks for "
576 "external radio\n");
577 return ecode;
578 }
579 }
591 580
592 if (!AR_SREV_9100(ah)) { 581 if (!AR_SREV_9100(ah)) {
593 ath9k_hw_ani_setup(ah); 582 ath9k_hw_ani_setup(ah);
@@ -662,10 +651,13 @@ static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
662static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 651static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
663{ 652{
664 if (AR_SREV_9271(ah)) { 653 if (AR_SREV_9271(ah)) {
665 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0, 654 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
666 ARRAY_SIZE(ar9271Modes_9271_1_0), 6); 655 ARRAY_SIZE(ar9271Modes_9271), 6);
667 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0, 656 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
668 ARRAY_SIZE(ar9271Common_9271_1_0), 2); 657 ARRAY_SIZE(ar9271Common_9271), 2);
658 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
659 ar9271Modes_9271_1_0_only,
660 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
669 return; 661 return;
670 } 662 }
671 663
@@ -957,8 +949,14 @@ int ath9k_hw_init(struct ath_hw *ah)
957 ath9k_hw_init_cal_settings(ah); 949 ath9k_hw_init_cal_settings(ah);
958 950
959 ah->ani_function = ATH9K_ANI_ALL; 951 ah->ani_function = ATH9K_ANI_ALL;
960 if (AR_SREV_9280_10_OR_LATER(ah)) 952 if (AR_SREV_9280_10_OR_LATER(ah)) {
961 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 953 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
954 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
955 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
956 } else {
957 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
958 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
959 }
962 960
963 ath9k_hw_init_mode_regs(ah); 961 ath9k_hw_init_mode_regs(ah);
964 962
@@ -1037,6 +1035,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
1037 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 1035 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1038} 1036}
1039 1037
1038static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1039{
1040 u32 lcr;
1041 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1042
1043 lcr = REG_READ(ah , 0x5100c);
1044 lcr |= 0x80;
1045
1046 REG_WRITE(ah, 0x5100c, lcr);
1047 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1048 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1049
1050 lcr &= ~0x80;
1051 REG_WRITE(ah, 0x5100c, lcr);
1052}
1053
1040static void ath9k_hw_init_pll(struct ath_hw *ah, 1054static void ath9k_hw_init_pll(struct ath_hw *ah,
1041 struct ath9k_channel *chan) 1055 struct ath9k_channel *chan)
1042{ 1056{
@@ -1100,6 +1114,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1100 } 1114 }
1101 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1115 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1102 1116
1117 /* Switch the core clock for ar9271 to 117Mhz */
1118 if (AR_SREV_9271(ah)) {
1119 if ((pll == 0x142c) || (pll == 0x2850) ) {
1120 udelay(500);
1121 /* set CLKOBS to output AHB clock */
1122 REG_WRITE(ah, 0x7020, 0xe);
1123 /*
1124 * 0x304: 117Mhz, ahb_ratio: 1x1
1125 * 0x306: 40Mhz, ahb_ratio: 1x1
1126 */
1127 REG_WRITE(ah, 0x50040, 0x304);
1128 /*
1129 * makes adjustments for the baud dividor to keep the
1130 * targetted baud rate based on the used core clock.
1131 */
1132 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1133 AR9271_TARGET_BAUD_RATE);
1134 }
1135 }
1136
1103 udelay(RTC_PLL_SETTLE_DELAY); 1137 udelay(RTC_PLL_SETTLE_DELAY);
1104 1138
1105 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1139 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
@@ -1252,7 +1286,8 @@ void ath9k_hw_detach(struct ath_hw *ah)
1252 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1286 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1253 1287
1254free_hw: 1288free_hw:
1255 ath9k_hw_rf_free(ah); 1289 if (!AR_SREV_9280_10_OR_LATER(ah))
1290 ath9k_hw_rf_free_ext_banks(ah);
1256 kfree(ah); 1291 kfree(ah);
1257 ah = NULL; 1292 ah = NULL;
1258} 1293}
@@ -1274,7 +1309,8 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
1274 * AR9271 1.1 1309 * AR9271 1.1
1275 */ 1310 */
1276 if (AR_SREV_9271_10(ah)) { 1311 if (AR_SREV_9271_10(ah)) {
1277 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE; 1312 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1313 AR_PHY_SPECTRAL_SCAN_ENABLE;
1278 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); 1314 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1279 } 1315 }
1280 else if (AR_SREV_9271_11(ah)) 1316 else if (AR_SREV_9271_11(ah))
@@ -1489,7 +1525,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1489 DO_DELAY(regWrites); 1525 DO_DELAY(regWrites);
1490 } 1526 }
1491 1527
1492 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1528 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1529
1530 if (AR_SREV_9271_10(ah))
1531 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1532 modesIndex, regWrites);
1493 1533
1494 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1534 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1495 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1535 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
@@ -1832,6 +1872,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1832 struct ath_common *common = ath9k_hw_common(ah); 1872 struct ath_common *common = ath9k_hw_common(ah);
1833 struct ieee80211_channel *channel = chan->chan; 1873 struct ieee80211_channel *channel = chan->chan;
1834 u32 synthDelay, qnum; 1874 u32 synthDelay, qnum;
1875 int r;
1835 1876
1836 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1877 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1837 if (ath9k_hw_numtxpending(ah, qnum)) { 1878 if (ath9k_hw_numtxpending(ah, qnum)) {
@@ -1852,14 +1893,11 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1852 1893
1853 ath9k_hw_set_regs(ah, chan); 1894 ath9k_hw_set_regs(ah, chan);
1854 1895
1855 if (AR_SREV_9280_10_OR_LATER(ah)) { 1896 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1856 ath9k_hw_ar9280_set_channel(ah, chan); 1897 if (r) {
1857 } else { 1898 ath_print(common, ATH_DBG_FATAL,
1858 if (!(ath9k_hw_set_channel(ah, chan))) { 1899 "Failed to set channel\n");
1859 ath_print(common, ATH_DBG_FATAL, 1900 return false;
1860 "Failed to set channel\n");
1861 return false;
1862 }
1863 } 1901 }
1864 1902
1865 ah->eep_ops->set_txpower(ah, chan, 1903 ah->eep_ops->set_txpower(ah, chan,
@@ -1882,10 +1920,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1882 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1920 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1883 ath9k_hw_set_delta_slope(ah, chan); 1921 ath9k_hw_set_delta_slope(ah, chan);
1884 1922
1885 if (AR_SREV_9280_10_OR_LATER(ah)) 1923 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1886 ath9k_hw_9280_spur_mitigate(ah, chan);
1887 else
1888 ath9k_hw_spur_mitigate(ah, chan);
1889 1924
1890 if (!chan->oneTimeCalsDone) 1925 if (!chan->oneTimeCalsDone)
1891 chan->oneTimeCalsDone = true; 1926 chan->oneTimeCalsDone = true;
@@ -1893,457 +1928,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1893 return true; 1928 return true;
1894} 1929}
1895 1930
1896static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1897{
1898 int bb_spur = AR_NO_SPUR;
1899 int freq;
1900 int bin, cur_bin;
1901 int bb_spur_off, spur_subchannel_sd;
1902 int spur_freq_sd;
1903 int spur_delta_phase;
1904 int denominator;
1905 int upper, lower, cur_vit_mask;
1906 int tmp, newVal;
1907 int i;
1908 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1909 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1910 };
1911 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1912 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1913 };
1914 int inc[4] = { 0, 100, 0, 0 };
1915 struct chan_centers centers;
1916
1917 int8_t mask_m[123];
1918 int8_t mask_p[123];
1919 int8_t mask_amt;
1920 int tmp_mask;
1921 int cur_bb_spur;
1922 bool is2GHz = IS_CHAN_2GHZ(chan);
1923
1924 memset(&mask_m, 0, sizeof(int8_t) * 123);
1925 memset(&mask_p, 0, sizeof(int8_t) * 123);
1926
1927 ath9k_hw_get_channel_centers(ah, chan, &centers);
1928 freq = centers.synth_center;
1929
1930 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1931 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1932 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1933
1934 if (is2GHz)
1935 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1936 else
1937 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1938
1939 if (AR_NO_SPUR == cur_bb_spur)
1940 break;
1941 cur_bb_spur = cur_bb_spur - freq;
1942
1943 if (IS_CHAN_HT40(chan)) {
1944 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1945 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1946 bb_spur = cur_bb_spur;
1947 break;
1948 }
1949 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1950 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1951 bb_spur = cur_bb_spur;
1952 break;
1953 }
1954 }
1955
1956 if (AR_NO_SPUR == bb_spur) {
1957 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1958 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1959 return;
1960 } else {
1961 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1962 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1963 }
1964
1965 bin = bb_spur * 320;
1966
1967 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1968
1969 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1970 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1971 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1972 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1973 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1974
1975 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1976 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1977 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1978 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1979 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1980 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1981
1982 if (IS_CHAN_HT40(chan)) {
1983 if (bb_spur < 0) {
1984 spur_subchannel_sd = 1;
1985 bb_spur_off = bb_spur + 10;
1986 } else {
1987 spur_subchannel_sd = 0;
1988 bb_spur_off = bb_spur - 10;
1989 }
1990 } else {
1991 spur_subchannel_sd = 0;
1992 bb_spur_off = bb_spur;
1993 }
1994
1995 if (IS_CHAN_HT40(chan))
1996 spur_delta_phase =
1997 ((bb_spur * 262144) /
1998 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1999 else
2000 spur_delta_phase =
2001 ((bb_spur * 524288) /
2002 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2003
2004 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2005 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2006
2007 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2008 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2009 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2010 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2011
2012 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2013 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2014
2015 cur_bin = -6000;
2016 upper = bin + 100;
2017 lower = bin - 100;
2018
2019 for (i = 0; i < 4; i++) {
2020 int pilot_mask = 0;
2021 int chan_mask = 0;
2022 int bp = 0;
2023 for (bp = 0; bp < 30; bp++) {
2024 if ((cur_bin > lower) && (cur_bin < upper)) {
2025 pilot_mask = pilot_mask | 0x1 << bp;
2026 chan_mask = chan_mask | 0x1 << bp;
2027 }
2028 cur_bin += 100;
2029 }
2030 cur_bin += inc[i];
2031 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2032 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2033 }
2034
2035 cur_vit_mask = 6100;
2036 upper = bin + 120;
2037 lower = bin - 120;
2038
2039 for (i = 0; i < 123; i++) {
2040 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2041
2042 /* workaround for gcc bug #37014 */
2043 volatile int tmp_v = abs(cur_vit_mask - bin);
2044
2045 if (tmp_v < 75)
2046 mask_amt = 1;
2047 else
2048 mask_amt = 0;
2049 if (cur_vit_mask < 0)
2050 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2051 else
2052 mask_p[cur_vit_mask / 100] = mask_amt;
2053 }
2054 cur_vit_mask -= 100;
2055 }
2056
2057 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2058 | (mask_m[48] << 26) | (mask_m[49] << 24)
2059 | (mask_m[50] << 22) | (mask_m[51] << 20)
2060 | (mask_m[52] << 18) | (mask_m[53] << 16)
2061 | (mask_m[54] << 14) | (mask_m[55] << 12)
2062 | (mask_m[56] << 10) | (mask_m[57] << 8)
2063 | (mask_m[58] << 6) | (mask_m[59] << 4)
2064 | (mask_m[60] << 2) | (mask_m[61] << 0);
2065 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2066 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2067
2068 tmp_mask = (mask_m[31] << 28)
2069 | (mask_m[32] << 26) | (mask_m[33] << 24)
2070 | (mask_m[34] << 22) | (mask_m[35] << 20)
2071 | (mask_m[36] << 18) | (mask_m[37] << 16)
2072 | (mask_m[48] << 14) | (mask_m[39] << 12)
2073 | (mask_m[40] << 10) | (mask_m[41] << 8)
2074 | (mask_m[42] << 6) | (mask_m[43] << 4)
2075 | (mask_m[44] << 2) | (mask_m[45] << 0);
2076 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2077 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2078
2079 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2080 | (mask_m[18] << 26) | (mask_m[18] << 24)
2081 | (mask_m[20] << 22) | (mask_m[20] << 20)
2082 | (mask_m[22] << 18) | (mask_m[22] << 16)
2083 | (mask_m[24] << 14) | (mask_m[24] << 12)
2084 | (mask_m[25] << 10) | (mask_m[26] << 8)
2085 | (mask_m[27] << 6) | (mask_m[28] << 4)
2086 | (mask_m[29] << 2) | (mask_m[30] << 0);
2087 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2088 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2089
2090 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2091 | (mask_m[2] << 26) | (mask_m[3] << 24)
2092 | (mask_m[4] << 22) | (mask_m[5] << 20)
2093 | (mask_m[6] << 18) | (mask_m[7] << 16)
2094 | (mask_m[8] << 14) | (mask_m[9] << 12)
2095 | (mask_m[10] << 10) | (mask_m[11] << 8)
2096 | (mask_m[12] << 6) | (mask_m[13] << 4)
2097 | (mask_m[14] << 2) | (mask_m[15] << 0);
2098 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2099 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2100
2101 tmp_mask = (mask_p[15] << 28)
2102 | (mask_p[14] << 26) | (mask_p[13] << 24)
2103 | (mask_p[12] << 22) | (mask_p[11] << 20)
2104 | (mask_p[10] << 18) | (mask_p[9] << 16)
2105 | (mask_p[8] << 14) | (mask_p[7] << 12)
2106 | (mask_p[6] << 10) | (mask_p[5] << 8)
2107 | (mask_p[4] << 6) | (mask_p[3] << 4)
2108 | (mask_p[2] << 2) | (mask_p[1] << 0);
2109 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2110 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2111
2112 tmp_mask = (mask_p[30] << 28)
2113 | (mask_p[29] << 26) | (mask_p[28] << 24)
2114 | (mask_p[27] << 22) | (mask_p[26] << 20)
2115 | (mask_p[25] << 18) | (mask_p[24] << 16)
2116 | (mask_p[23] << 14) | (mask_p[22] << 12)
2117 | (mask_p[21] << 10) | (mask_p[20] << 8)
2118 | (mask_p[19] << 6) | (mask_p[18] << 4)
2119 | (mask_p[17] << 2) | (mask_p[16] << 0);
2120 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2121 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2122
2123 tmp_mask = (mask_p[45] << 28)
2124 | (mask_p[44] << 26) | (mask_p[43] << 24)
2125 | (mask_p[42] << 22) | (mask_p[41] << 20)
2126 | (mask_p[40] << 18) | (mask_p[39] << 16)
2127 | (mask_p[38] << 14) | (mask_p[37] << 12)
2128 | (mask_p[36] << 10) | (mask_p[35] << 8)
2129 | (mask_p[34] << 6) | (mask_p[33] << 4)
2130 | (mask_p[32] << 2) | (mask_p[31] << 0);
2131 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2132 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2133
2134 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2135 | (mask_p[59] << 26) | (mask_p[58] << 24)
2136 | (mask_p[57] << 22) | (mask_p[56] << 20)
2137 | (mask_p[55] << 18) | (mask_p[54] << 16)
2138 | (mask_p[53] << 14) | (mask_p[52] << 12)
2139 | (mask_p[51] << 10) | (mask_p[50] << 8)
2140 | (mask_p[49] << 6) | (mask_p[48] << 4)
2141 | (mask_p[47] << 2) | (mask_p[46] << 0);
2142 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2143 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2144}
2145
2146static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2147{
2148 int bb_spur = AR_NO_SPUR;
2149 int bin, cur_bin;
2150 int spur_freq_sd;
2151 int spur_delta_phase;
2152 int denominator;
2153 int upper, lower, cur_vit_mask;
2154 int tmp, new;
2155 int i;
2156 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2157 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2158 };
2159 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2160 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2161 };
2162 int inc[4] = { 0, 100, 0, 0 };
2163
2164 int8_t mask_m[123];
2165 int8_t mask_p[123];
2166 int8_t mask_amt;
2167 int tmp_mask;
2168 int cur_bb_spur;
2169 bool is2GHz = IS_CHAN_2GHZ(chan);
2170
2171 memset(&mask_m, 0, sizeof(int8_t) * 123);
2172 memset(&mask_p, 0, sizeof(int8_t) * 123);
2173
2174 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2175 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2176 if (AR_NO_SPUR == cur_bb_spur)
2177 break;
2178 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2179 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2180 bb_spur = cur_bb_spur;
2181 break;
2182 }
2183 }
2184
2185 if (AR_NO_SPUR == bb_spur)
2186 return;
2187
2188 bin = bb_spur * 32;
2189
2190 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2191 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2192 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2193 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2194 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2195
2196 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2197
2198 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2199 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2200 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2201 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2202 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2203 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2204
2205 spur_delta_phase = ((bb_spur * 524288) / 100) &
2206 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2207
2208 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2209 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2210
2211 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2212 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2213 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2214 REG_WRITE(ah, AR_PHY_TIMING11, new);
2215
2216 cur_bin = -6000;
2217 upper = bin + 100;
2218 lower = bin - 100;
2219
2220 for (i = 0; i < 4; i++) {
2221 int pilot_mask = 0;
2222 int chan_mask = 0;
2223 int bp = 0;
2224 for (bp = 0; bp < 30; bp++) {
2225 if ((cur_bin > lower) && (cur_bin < upper)) {
2226 pilot_mask = pilot_mask | 0x1 << bp;
2227 chan_mask = chan_mask | 0x1 << bp;
2228 }
2229 cur_bin += 100;
2230 }
2231 cur_bin += inc[i];
2232 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2233 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2234 }
2235
2236 cur_vit_mask = 6100;
2237 upper = bin + 120;
2238 lower = bin - 120;
2239
2240 for (i = 0; i < 123; i++) {
2241 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2242
2243 /* workaround for gcc bug #37014 */
2244 volatile int tmp_v = abs(cur_vit_mask - bin);
2245
2246 if (tmp_v < 75)
2247 mask_amt = 1;
2248 else
2249 mask_amt = 0;
2250 if (cur_vit_mask < 0)
2251 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2252 else
2253 mask_p[cur_vit_mask / 100] = mask_amt;
2254 }
2255 cur_vit_mask -= 100;
2256 }
2257
2258 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2259 | (mask_m[48] << 26) | (mask_m[49] << 24)
2260 | (mask_m[50] << 22) | (mask_m[51] << 20)
2261 | (mask_m[52] << 18) | (mask_m[53] << 16)
2262 | (mask_m[54] << 14) | (mask_m[55] << 12)
2263 | (mask_m[56] << 10) | (mask_m[57] << 8)
2264 | (mask_m[58] << 6) | (mask_m[59] << 4)
2265 | (mask_m[60] << 2) | (mask_m[61] << 0);
2266 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2267 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2268
2269 tmp_mask = (mask_m[31] << 28)
2270 | (mask_m[32] << 26) | (mask_m[33] << 24)
2271 | (mask_m[34] << 22) | (mask_m[35] << 20)
2272 | (mask_m[36] << 18) | (mask_m[37] << 16)
2273 | (mask_m[48] << 14) | (mask_m[39] << 12)
2274 | (mask_m[40] << 10) | (mask_m[41] << 8)
2275 | (mask_m[42] << 6) | (mask_m[43] << 4)
2276 | (mask_m[44] << 2) | (mask_m[45] << 0);
2277 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2278 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2279
2280 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2281 | (mask_m[18] << 26) | (mask_m[18] << 24)
2282 | (mask_m[20] << 22) | (mask_m[20] << 20)
2283 | (mask_m[22] << 18) | (mask_m[22] << 16)
2284 | (mask_m[24] << 14) | (mask_m[24] << 12)
2285 | (mask_m[25] << 10) | (mask_m[26] << 8)
2286 | (mask_m[27] << 6) | (mask_m[28] << 4)
2287 | (mask_m[29] << 2) | (mask_m[30] << 0);
2288 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2289 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2290
2291 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2292 | (mask_m[2] << 26) | (mask_m[3] << 24)
2293 | (mask_m[4] << 22) | (mask_m[5] << 20)
2294 | (mask_m[6] << 18) | (mask_m[7] << 16)
2295 | (mask_m[8] << 14) | (mask_m[9] << 12)
2296 | (mask_m[10] << 10) | (mask_m[11] << 8)
2297 | (mask_m[12] << 6) | (mask_m[13] << 4)
2298 | (mask_m[14] << 2) | (mask_m[15] << 0);
2299 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2300 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2301
2302 tmp_mask = (mask_p[15] << 28)
2303 | (mask_p[14] << 26) | (mask_p[13] << 24)
2304 | (mask_p[12] << 22) | (mask_p[11] << 20)
2305 | (mask_p[10] << 18) | (mask_p[9] << 16)
2306 | (mask_p[8] << 14) | (mask_p[7] << 12)
2307 | (mask_p[6] << 10) | (mask_p[5] << 8)
2308 | (mask_p[4] << 6) | (mask_p[3] << 4)
2309 | (mask_p[2] << 2) | (mask_p[1] << 0);
2310 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2311 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2312
2313 tmp_mask = (mask_p[30] << 28)
2314 | (mask_p[29] << 26) | (mask_p[28] << 24)
2315 | (mask_p[27] << 22) | (mask_p[26] << 20)
2316 | (mask_p[25] << 18) | (mask_p[24] << 16)
2317 | (mask_p[23] << 14) | (mask_p[22] << 12)
2318 | (mask_p[21] << 10) | (mask_p[20] << 8)
2319 | (mask_p[19] << 6) | (mask_p[18] << 4)
2320 | (mask_p[17] << 2) | (mask_p[16] << 0);
2321 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2322 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2323
2324 tmp_mask = (mask_p[45] << 28)
2325 | (mask_p[44] << 26) | (mask_p[43] << 24)
2326 | (mask_p[42] << 22) | (mask_p[41] << 20)
2327 | (mask_p[40] << 18) | (mask_p[39] << 16)
2328 | (mask_p[38] << 14) | (mask_p[37] << 12)
2329 | (mask_p[36] << 10) | (mask_p[35] << 8)
2330 | (mask_p[34] << 6) | (mask_p[33] << 4)
2331 | (mask_p[32] << 2) | (mask_p[31] << 0);
2332 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2333 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2334
2335 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2336 | (mask_p[59] << 26) | (mask_p[58] << 24)
2337 | (mask_p[57] << 22) | (mask_p[56] << 20)
2338 | (mask_p[55] << 18) | (mask_p[54] << 16)
2339 | (mask_p[53] << 14) | (mask_p[52] << 12)
2340 | (mask_p[51] << 10) | (mask_p[50] << 8)
2341 | (mask_p[49] << 6) | (mask_p[48] << 4)
2342 | (mask_p[47] << 2) | (mask_p[46] << 0);
2343 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2344 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2345}
2346
2347static void ath9k_enable_rfkill(struct ath_hw *ah) 1931static void ath9k_enable_rfkill(struct ath_hw *ah)
2348{ 1932{
2349 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1933 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -2469,14 +2053,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2469 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2053 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2470 ath9k_hw_set_delta_slope(ah, chan); 2054 ath9k_hw_set_delta_slope(ah, chan);
2471 2055
2472 if (AR_SREV_9280_10_OR_LATER(ah)) 2056 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2473 ath9k_hw_9280_spur_mitigate(ah, chan);
2474 else
2475 ath9k_hw_spur_mitigate(ah, chan);
2476
2477 ah->eep_ops->set_board_values(ah, chan); 2057 ah->eep_ops->set_board_values(ah, chan);
2478 2058
2479 ath9k_hw_decrease_chain_power(ah, chan); 2059 if (AR_SREV_5416(ah))
2060 ath9k_hw_decrease_chain_power(ah, chan);
2480 2061
2481 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 2062 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2482 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 2063 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
@@ -2497,11 +2078,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2497 2078
2498 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2079 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2499 2080
2500 if (AR_SREV_9280_10_OR_LATER(ah)) 2081 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2501 ath9k_hw_ar9280_set_channel(ah, chan); 2082 if (r)
2502 else 2083 return r;
2503 if (!(ath9k_hw_set_channel(ah, chan)))
2504 return -EIO;
2505 2084
2506 for (i = 0; i < AR_NUM_DCU; i++) 2085 for (i = 0; i < AR_NUM_DCU; i++)
2507 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2086 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
@@ -4350,3 +3929,89 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4350 } 3929 }
4351} 3930}
4352EXPORT_SYMBOL(ath_gen_timer_isr); 3931EXPORT_SYMBOL(ath_gen_timer_isr);
3932
3933static struct {
3934 u32 version;
3935 const char * name;
3936} ath_mac_bb_names[] = {
3937 /* Devices with external radios */
3938 { AR_SREV_VERSION_5416_PCI, "5416" },
3939 { AR_SREV_VERSION_5416_PCIE, "5418" },
3940 { AR_SREV_VERSION_9100, "9100" },
3941 { AR_SREV_VERSION_9160, "9160" },
3942 /* Single-chip solutions */
3943 { AR_SREV_VERSION_9280, "9280" },
3944 { AR_SREV_VERSION_9285, "9285" },
3945 { AR_SREV_VERSION_9287, "9287" },
3946 { AR_SREV_VERSION_9271, "9271" },
3947};
3948
3949/* For devices with external radios */
3950static struct {
3951 u16 version;
3952 const char * name;
3953} ath_rf_names[] = {
3954 { 0, "5133" },
3955 { AR_RAD5133_SREV_MAJOR, "5133" },
3956 { AR_RAD5122_SREV_MAJOR, "5122" },
3957 { AR_RAD2133_SREV_MAJOR, "2133" },
3958 { AR_RAD2122_SREV_MAJOR, "2122" }
3959};
3960
3961/*
3962 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3963 */
3964static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3965{
3966 int i;
3967
3968 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3969 if (ath_mac_bb_names[i].version == mac_bb_version) {
3970 return ath_mac_bb_names[i].name;
3971 }
3972 }
3973
3974 return "????";
3975}
3976
3977/*
3978 * Return the RF name. "????" is returned if the RF is unknown.
3979 * Used for devices with external radios.
3980 */
3981static const char *ath9k_hw_rf_name(u16 rf_version)
3982{
3983 int i;
3984
3985 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3986 if (ath_rf_names[i].version == rf_version) {
3987 return ath_rf_names[i].name;
3988 }
3989 }
3990
3991 return "????";
3992}
3993
3994void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3995{
3996 int used;
3997
3998 /* chipsets >= AR9280 are single-chip */
3999 if (AR_SREV_9280_10_OR_LATER(ah)) {
4000 used = snprintf(hw_name, len,
4001 "Atheros AR%s Rev:%x",
4002 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4003 ah->hw_version.macRev);
4004 }
4005 else {
4006 used = snprintf(hw_name, len,
4007 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
4008 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4009 ah->hw_version.macRev,
4010 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
4011 AR_RADIO_SREV_MAJOR)),
4012 ah->hw_version.phyRev);
4013 }
4014
4015 hw_name[used] = '\0';
4016}
4017EXPORT_SYMBOL(ath9k_hw_name);
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index cdaec526db35..c7b0c4d5f75a 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -148,6 +148,15 @@ enum wireless_mode {
148 ATH9K_MODE_MAX, 148 ATH9K_MODE_MAX,
149}; 149};
150 150
151/**
152 * ath9k_ant_setting - transmit antenna settings
153 *
154 * Configures the antenna setting to use for transmit.
155 *
156 * @ATH9K_ANT_VARIABLE: this means transmit on all active antennas
157 * @ATH9K_ANT_FIXED_A: this means transmit on the first antenna only
158 * @ATH9K_ANT_FIXED_B: this means transmit on the second antenna only
159 */
151enum ath9k_ant_setting { 160enum ath9k_ant_setting {
152 ATH9K_ANT_VARIABLE = 0, 161 ATH9K_ANT_VARIABLE = 0,
153 ATH9K_ANT_FIXED_A, 162 ATH9K_ANT_FIXED_A,
@@ -539,7 +548,14 @@ struct ath_hw {
539 DONT_USE_32KHZ, 548 DONT_USE_32KHZ,
540 } enable_32kHz_clock; 549 } enable_32kHz_clock;
541 550
542 /* RF */ 551 /* Callback for radio frequency change */
552 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
553
554 /* Callback for baseband spur frequency */
555 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
556 struct ath9k_channel *chan);
557
558 /* Used to program the radio on non single-chip devices */
543 u32 *analogBank0Data; 559 u32 *analogBank0Data;
544 u32 *analogBank1Data; 560 u32 *analogBank1Data;
545 u32 *analogBank2Data; 561 u32 *analogBank2Data;
@@ -596,6 +612,7 @@ struct ath_hw {
596 struct ar5416IniArray iniModesAdditional; 612 struct ar5416IniArray iniModesAdditional;
597 struct ar5416IniArray iniModesRxGain; 613 struct ar5416IniArray iniModesRxGain;
598 struct ar5416IniArray iniModesTxGain; 614 struct ar5416IniArray iniModesTxGain;
615 struct ar5416IniArray iniModes_9271_1_0_only;
599 struct ar5416IniArray iniCckfirNormal; 616 struct ar5416IniArray iniCckfirNormal;
600 struct ar5416IniArray iniCckfirJapan2484; 617 struct ar5416IniArray iniCckfirJapan2484;
601 618
@@ -618,7 +635,6 @@ static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
618const char *ath9k_hw_probe(u16 vendorid, u16 devid); 635const char *ath9k_hw_probe(u16 vendorid, u16 devid);
619void ath9k_hw_detach(struct ath_hw *ah); 636void ath9k_hw_detach(struct ath_hw *ah);
620int ath9k_hw_init(struct ath_hw *ah); 637int ath9k_hw_init(struct ath_hw *ah);
621void ath9k_hw_rf_free(struct ath_hw *ah);
622int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 638int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
623 bool bChannelChange); 639 bool bChannelChange);
624void ath9k_hw_fill_cap_info(struct ath_hw *ah); 640void ath9k_hw_fill_cap_info(struct ath_hw *ah);
@@ -704,6 +720,8 @@ void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
704void ath_gen_timer_isr(struct ath_hw *hw); 720void ath_gen_timer_isr(struct ath_hw *hw);
705u32 ath9k_hw_gettsf32(struct ath_hw *ah); 721u32 ath9k_hw_gettsf32(struct ath_hw *ah);
706 722
723void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
724
707#define ATH_PCIE_CAP_LINK_CTRL 0x70 725#define ATH_PCIE_CAP_LINK_CTRL 0x70
708#define ATH_PCIE_CAP_LINK_L0S 1 726#define ATH_PCIE_CAP_LINK_L0S 1
709#define ATH_PCIE_CAP_LINK_L1 2 727#define ATH_PCIE_CAP_LINK_L1 2
diff --git a/drivers/net/wireless/ath/ath9k/initvals.h b/drivers/net/wireless/ath/ath9k/initvals.h
index 3ee6658d809b..8a3bf3ab998d 100644
--- a/drivers/net/wireless/ath/ath9k/initvals.h
+++ b/drivers/net/wireless/ath/ath9k/initvals.h
@@ -6379,8 +6379,8 @@ static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
6379}; 6379};
6380 6380
6381 6381
6382/* AR9271 initialization values automaticaly created: 03/23/09 */ 6382/* AR9271 initialization values automaticaly created: 06/04/09 */
6383static const u_int32_t ar9271Modes_9271_1_0[][6] = { 6383static const u_int32_t ar9271Modes_9271[][6] = {
6384 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 6384 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6385 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 6385 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6386 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 6386 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -6390,8 +6390,8 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6390 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, 6390 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
6391 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 6391 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
6392 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 6392 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
6393 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6393 { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
6394 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 6394 { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
6395 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6395 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6396 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 6396 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
6397 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e }, 6397 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
@@ -6405,6 +6405,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6405 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 6405 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
6406 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, 6406 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
6407 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, 6407 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
6408 { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
6408 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 6409 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
6409 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 6410 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
6410 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d }, 6411 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
@@ -6415,7 +6416,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6415 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, 6416 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
6416 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 6417 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
6417 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 6418 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
6418 { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 }, 6419 { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
6419 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 6420 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
6420 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 6421 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
6421 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 6422 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -6704,7 +6705,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6704 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 6705 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6705}; 6706};
6706 6707
6707static const u_int32_t ar9271Common_9271_1_0[][2] = { 6708static const u_int32_t ar9271Common_9271[][2] = {
6708 { 0x0000000c, 0x00000000 }, 6709 { 0x0000000c, 0x00000000 },
6709 { 0x00000030, 0x00020045 }, 6710 { 0x00000030, 0x00020045 },
6710 { 0x00000034, 0x00000005 }, 6711 { 0x00000034, 0x00000005 },
@@ -6800,7 +6801,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6800 { 0x0000803c, 0x00000000 }, 6801 { 0x0000803c, 0x00000000 },
6801 { 0x00008048, 0x00000000 }, 6802 { 0x00008048, 0x00000000 },
6802 { 0x00008054, 0x00000000 }, 6803 { 0x00008054, 0x00000000 },
6803 { 0x00008058, 0x02000000 }, 6804 { 0x00008058, 0x00000000 },
6804 { 0x0000805c, 0x000fc78f }, 6805 { 0x0000805c, 0x000fc78f },
6805 { 0x00008060, 0x0000000f }, 6806 { 0x00008060, 0x0000000f },
6806 { 0x00008064, 0x00000000 }, 6807 { 0x00008064, 0x00000000 },
@@ -6831,7 +6832,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6831 { 0x00008110, 0x00000168 }, 6832 { 0x00008110, 0x00000168 },
6832 { 0x00008118, 0x000100aa }, 6833 { 0x00008118, 0x000100aa },
6833 { 0x0000811c, 0x00003210 }, 6834 { 0x0000811c, 0x00003210 },
6834 { 0x00008120, 0x08f04814 }, 6835 { 0x00008120, 0x08f04810 },
6835 { 0x00008124, 0x00000000 }, 6836 { 0x00008124, 0x00000000 },
6836 { 0x00008128, 0x00000000 }, 6837 { 0x00008128, 0x00000000 },
6837 { 0x0000812c, 0x00000000 }, 6838 { 0x0000812c, 0x00000000 },
@@ -6878,7 +6879,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6878 { 0x00008258, 0x00000000 }, 6879 { 0x00008258, 0x00000000 },
6879 { 0x0000825c, 0x400000ff }, 6880 { 0x0000825c, 0x400000ff },
6880 { 0x00008260, 0x00080922 }, 6881 { 0x00008260, 0x00080922 },
6881 { 0x00008264, 0xa8a00010 }, 6882 { 0x00008264, 0x88a00010 },
6882 { 0x00008270, 0x00000000 }, 6883 { 0x00008270, 0x00000000 },
6883 { 0x00008274, 0x40000000 }, 6884 { 0x00008274, 0x40000000 },
6884 { 0x00008278, 0x003e4180 }, 6885 { 0x00008278, 0x003e4180 },
@@ -6910,7 +6911,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6910 { 0x00007814, 0x924934a8 }, 6911 { 0x00007814, 0x924934a8 },
6911 { 0x0000781c, 0x00000000 }, 6912 { 0x0000781c, 0x00000000 },
6912 { 0x00007820, 0x00000c04 }, 6913 { 0x00007820, 0x00000c04 },
6913 { 0x00007824, 0x00d86bff }, 6914 { 0x00007824, 0x00d8abff },
6914 { 0x00007828, 0x66964300 }, 6915 { 0x00007828, 0x66964300 },
6915 { 0x0000782c, 0x8db6d961 }, 6916 { 0x0000782c, 0x8db6d961 },
6916 { 0x00007830, 0x8db6d96c }, 6917 { 0x00007830, 0x8db6d96c },
@@ -6944,7 +6945,6 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6944 { 0x00009904, 0x00000000 }, 6945 { 0x00009904, 0x00000000 },
6945 { 0x00009908, 0x00000000 }, 6946 { 0x00009908, 0x00000000 },
6946 { 0x0000990c, 0x00000000 }, 6947 { 0x0000990c, 0x00000000 },
6947 { 0x00009910, 0x30002310 },
6948 { 0x0000991c, 0x10000fff }, 6948 { 0x0000991c, 0x10000fff },
6949 { 0x00009920, 0x04900000 }, 6949 { 0x00009920, 0x04900000 },
6950 { 0x00009928, 0x00000001 }, 6950 { 0x00009928, 0x00000001 },
@@ -6958,7 +6958,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6958 { 0x00009954, 0x5f3ca3de }, 6958 { 0x00009954, 0x5f3ca3de },
6959 { 0x00009958, 0x0108ecff }, 6959 { 0x00009958, 0x0108ecff },
6960 { 0x00009968, 0x000003ce }, 6960 { 0x00009968, 0x000003ce },
6961 { 0x00009970, 0x192bb515 }, 6961 { 0x00009970, 0x192bb514 },
6962 { 0x00009974, 0x00000000 }, 6962 { 0x00009974, 0x00000000 },
6963 { 0x00009978, 0x00000001 }, 6963 { 0x00009978, 0x00000001 },
6964 { 0x0000997c, 0x00000000 }, 6964 { 0x0000997c, 0x00000000 },
@@ -7045,3 +7045,8 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
7045 { 0x0000d380, 0x7f3c7bba }, 7045 { 0x0000d380, 0x7f3c7bba },
7046 { 0x0000d384, 0xf3307ff0 }, 7046 { 0x0000d384, 0xf3307ff0 },
7047}; 7047};
7048
7049static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
7050 { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
7051 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7052};
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 69cf702b18c2..9fefc51aec17 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -3191,64 +3191,6 @@ struct ieee80211_ops ath9k_ops = {
3191 .rfkill_poll = ath9k_rfkill_poll_state, 3191 .rfkill_poll = ath9k_rfkill_poll_state,
3192}; 3192};
3193 3193
3194static struct {
3195 u32 version;
3196 const char * name;
3197} ath_mac_bb_names[] = {
3198 { AR_SREV_VERSION_5416_PCI, "5416" },
3199 { AR_SREV_VERSION_5416_PCIE, "5418" },
3200 { AR_SREV_VERSION_9100, "9100" },
3201 { AR_SREV_VERSION_9160, "9160" },
3202 { AR_SREV_VERSION_9280, "9280" },
3203 { AR_SREV_VERSION_9285, "9285" },
3204 { AR_SREV_VERSION_9287, "9287" }
3205};
3206
3207static struct {
3208 u16 version;
3209 const char * name;
3210} ath_rf_names[] = {
3211 { 0, "5133" },
3212 { AR_RAD5133_SREV_MAJOR, "5133" },
3213 { AR_RAD5122_SREV_MAJOR, "5122" },
3214 { AR_RAD2133_SREV_MAJOR, "2133" },
3215 { AR_RAD2122_SREV_MAJOR, "2122" }
3216};
3217
3218/*
3219 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3220 */
3221const char *
3222ath_mac_bb_name(u32 mac_bb_version)
3223{
3224 int i;
3225
3226 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3227 if (ath_mac_bb_names[i].version == mac_bb_version) {
3228 return ath_mac_bb_names[i].name;
3229 }
3230 }
3231
3232 return "????";
3233}
3234
3235/*
3236 * Return the RF name. "????" is returned if the RF is unknown.
3237 */
3238const char *
3239ath_rf_name(u16 rf_version)
3240{
3241 int i;
3242
3243 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3244 if (ath_rf_names[i].version == rf_version) {
3245 return ath_rf_names[i].name;
3246 }
3247 }
3248
3249 return "????";
3250}
3251
3252static int __init ath9k_init(void) 3194static int __init ath9k_init(void)
3253{ 3195{
3254 int error; 3196 int error;
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 63059b6a90da..5321f735e5a0 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -114,6 +114,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
114 u32 val; 114 u32 val;
115 int ret = 0; 115 int ret = 0;
116 struct ath_hw *ah; 116 struct ath_hw *ah;
117 char hw_name[64];
117 118
118 if (pci_enable_device(pdev)) 119 if (pci_enable_device(pdev))
119 return -EIO; 120 return -EIO;
@@ -218,14 +219,11 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
218 sc->irq = pdev->irq; 219 sc->irq = pdev->irq;
219 220
220 ah = sc->sc_ah; 221 ah = sc->sc_ah;
222 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
221 printk(KERN_INFO 223 printk(KERN_INFO
222 "%s: Atheros AR%s MAC/BB Rev:%x " 224 "%s: %s mem=0x%lx, irq=%d\n",
223 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
224 wiphy_name(hw->wiphy), 225 wiphy_name(hw->wiphy),
225 ath_mac_bb_name(ah->hw_version.macVersion), 226 hw_name,
226 ah->hw_version.macRev,
227 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
228 ah->hw_version.phyRev,
229 (unsigned long)mem, pdev->irq); 227 (unsigned long)mem, pdev->irq);
230 228
231 return 0; 229 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index 72a17c43a5a0..13ab4d7eb7aa 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -14,91 +14,70 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
17#include "hw.h" 42#include "hw.h"
18 43
19void 44/**
20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, 45 * ath9k_hw_write_regs - ??
21 int regWrites) 46 *
47 * @ah: atheros hardware structure
48 * @freqIndex:
49 * @regWrites:
50 *
51 * Used for both the chipsets with an external AR2133/AR5133 radios and
52 * single-chip devices.
53 */
54void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
22{ 55{
23 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 56 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
24} 57}
25 58
26bool 59/**
27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 60 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
28{ 61 * @ah: atheros hardware structure
29 struct ath_common *common = ath9k_hw_common(ah); 62 * @chan:
30 u32 channelSel = 0; 63 *
31 u32 bModeSynth = 0; 64 * This is the function to change channel on single-chip devices, that is
32 u32 aModeRefSel = 0; 65 * all devices after ar9280.
33 u32 reg32 = 0; 66 *
34 u16 freq; 67 * This function takes the channel value in MHz and sets
35 struct chan_centers centers; 68 * hardware channel value. Assumes writes have been enabled to analog bus.
36 69 *
37 ath9k_hw_get_channel_centers(ah, chan, &centers); 70 * Actual Expression,
38 freq = centers.synth_center; 71 *
39 72 * For 2GHz channel,
40 if (freq < 4800) { 73 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
41 u32 txctl; 74 * (freq_ref = 40MHz)
42 75 *
43 if (((freq - 2192) % 5) == 0) { 76 * For 5GHz channel,
44 channelSel = ((freq - 672) * 2 - 3040) / 10; 77 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
45 bModeSynth = 0; 78 * (freq_ref = 40MHz/(24>>amodeRefSel))
46 } else if (((freq - 2224) % 5) == 0) { 79 */
47 channelSel = ((freq - 704) * 2 - 3040) / 10; 80int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
48 bModeSynth = 1;
49 } else {
50 ath_print(common, ATH_DBG_FATAL,
51 "Invalid channel %u MHz\n", freq);
52 return false;
53 }
54
55 channelSel = (channelSel << 2) & 0xff;
56 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
57
58 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
59 if (freq == 2484) {
60
61 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
62 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
63 } else {
64 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
65 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
66 }
67
68 } else if ((freq % 20) == 0 && freq >= 5120) {
69 channelSel =
70 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
71 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
72 } else if ((freq % 10) == 0) {
73 channelSel =
74 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
75 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
76 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
77 else
78 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
79 } else if ((freq % 5) == 0) {
80 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
81 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
82 } else {
83 ath_print(common, ATH_DBG_FATAL,
84 "Invalid channel %u MHz\n", freq);
85 return false;
86 }
87
88 reg32 =
89 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
90 (1 << 5) | 0x1;
91
92 REG_WRITE(ah, AR_PHY(0x37), reg32);
93
94 ah->curchan = chan;
95 ah->curchan_rad_index = -1;
96
97 return true;
98}
99
100void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
101 struct ath9k_channel *chan)
102{ 81{
103 u16 bMode, fracMode, aModeRefSel = 0; 82 u16 bMode, fracMode, aModeRefSel = 0;
104 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; 83 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
@@ -111,7 +90,7 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
111 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); 90 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
112 reg32 &= 0xc0000000; 91 reg32 &= 0xc0000000;
113 92
114 if (freq < 4800) { 93 if (freq < 4800) { /* 2 GHz, fractional mode */
115 u32 txctl; 94 u32 txctl;
116 int regWrites = 0; 95 int regWrites = 0;
117 96
@@ -122,6 +101,7 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
122 101
123 if (AR_SREV_9287_11_OR_LATER(ah)) { 102 if (AR_SREV_9287_11_OR_LATER(ah)) {
124 if (freq == 2484) { 103 if (freq == 2484) {
104 /* Enable channel spreading for channel 14 */
125 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, 105 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
126 1, regWrites); 106 1, regWrites);
127 } else { 107 } else {
@@ -155,10 +135,15 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
155 case 1: 135 case 1:
156 default: 136 default:
157 aModeRefSel = 0; 137 aModeRefSel = 0;
138 /*
139 * Enable 2G (fractional) mode for channels
140 * which are 5MHz spaced.
141 */
158 fracMode = 1; 142 fracMode = 1;
159 refDivA = 1; 143 refDivA = 1;
160 channelSel = (freq * 0x8000) / 15; 144 channelSel = (freq * 0x8000) / 15;
161 145
146 /* RefDivA setting */
162 REG_RMW_FIELD(ah, AR_AN_SYNTH9, 147 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
163 AR_AN_SYNTH9_REFDIVA, refDivA); 148 AR_AN_SYNTH9_REFDIVA, refDivA);
164 149
@@ -180,12 +165,284 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
180 165
181 ah->curchan = chan; 166 ah->curchan = chan;
182 ah->curchan_rad_index = -1; 167 ah->curchan_rad_index = -1;
168
169 return 0;
170}
171
172/**
173 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
174 * @ah: atheros hardware structure
175 * @chan:
176 *
177 * For single-chip solutions. Converts to baseband spur frequency given the
178 * input channel frequency and compute register settings below.
179 */
180void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
181{
182 int bb_spur = AR_NO_SPUR;
183 int freq;
184 int bin, cur_bin;
185 int bb_spur_off, spur_subchannel_sd;
186 int spur_freq_sd;
187 int spur_delta_phase;
188 int denominator;
189 int upper, lower, cur_vit_mask;
190 int tmp, newVal;
191 int i;
192 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
193 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
194 };
195 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
196 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
197 };
198 int inc[4] = { 0, 100, 0, 0 };
199 struct chan_centers centers;
200
201 int8_t mask_m[123];
202 int8_t mask_p[123];
203 int8_t mask_amt;
204 int tmp_mask;
205 int cur_bb_spur;
206 bool is2GHz = IS_CHAN_2GHZ(chan);
207
208 memset(&mask_m, 0, sizeof(int8_t) * 123);
209 memset(&mask_p, 0, sizeof(int8_t) * 123);
210
211 ath9k_hw_get_channel_centers(ah, chan, &centers);
212 freq = centers.synth_center;
213
214 ah->config.spurmode = SPUR_ENABLE_EEPROM;
215 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
216 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
217
218 if (is2GHz)
219 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
220 else
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
222
223 if (AR_NO_SPUR == cur_bb_spur)
224 break;
225 cur_bb_spur = cur_bb_spur - freq;
226
227 if (IS_CHAN_HT40(chan)) {
228 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
229 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
230 bb_spur = cur_bb_spur;
231 break;
232 }
233 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
234 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
235 bb_spur = cur_bb_spur;
236 break;
237 }
238 }
239
240 if (AR_NO_SPUR == bb_spur) {
241 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
242 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
243 return;
244 } else {
245 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
246 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
247 }
248
249 bin = bb_spur * 320;
250
251 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
252
253 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
254 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
255 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
256 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
257 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
258
259 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
260 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
261 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
262 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
263 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
264 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
265
266 if (IS_CHAN_HT40(chan)) {
267 if (bb_spur < 0) {
268 spur_subchannel_sd = 1;
269 bb_spur_off = bb_spur + 10;
270 } else {
271 spur_subchannel_sd = 0;
272 bb_spur_off = bb_spur - 10;
273 }
274 } else {
275 spur_subchannel_sd = 0;
276 bb_spur_off = bb_spur;
277 }
278
279 if (IS_CHAN_HT40(chan))
280 spur_delta_phase =
281 ((bb_spur * 262144) /
282 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
283 else
284 spur_delta_phase =
285 ((bb_spur * 524288) /
286 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
287
288 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
289 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
290
291 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
292 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
293 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
294 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
295
296 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
297 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
298
299 cur_bin = -6000;
300 upper = bin + 100;
301 lower = bin - 100;
302
303 for (i = 0; i < 4; i++) {
304 int pilot_mask = 0;
305 int chan_mask = 0;
306 int bp = 0;
307 for (bp = 0; bp < 30; bp++) {
308 if ((cur_bin > lower) && (cur_bin < upper)) {
309 pilot_mask = pilot_mask | 0x1 << bp;
310 chan_mask = chan_mask | 0x1 << bp;
311 }
312 cur_bin += 100;
313 }
314 cur_bin += inc[i];
315 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
316 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
317 }
318
319 cur_vit_mask = 6100;
320 upper = bin + 120;
321 lower = bin - 120;
322
323 for (i = 0; i < 123; i++) {
324 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
325
326 /* workaround for gcc bug #37014 */
327 volatile int tmp_v = abs(cur_vit_mask - bin);
328
329 if (tmp_v < 75)
330 mask_amt = 1;
331 else
332 mask_amt = 0;
333 if (cur_vit_mask < 0)
334 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
335 else
336 mask_p[cur_vit_mask / 100] = mask_amt;
337 }
338 cur_vit_mask -= 100;
339 }
340
341 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
342 | (mask_m[48] << 26) | (mask_m[49] << 24)
343 | (mask_m[50] << 22) | (mask_m[51] << 20)
344 | (mask_m[52] << 18) | (mask_m[53] << 16)
345 | (mask_m[54] << 14) | (mask_m[55] << 12)
346 | (mask_m[56] << 10) | (mask_m[57] << 8)
347 | (mask_m[58] << 6) | (mask_m[59] << 4)
348 | (mask_m[60] << 2) | (mask_m[61] << 0);
349 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
350 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
351
352 tmp_mask = (mask_m[31] << 28)
353 | (mask_m[32] << 26) | (mask_m[33] << 24)
354 | (mask_m[34] << 22) | (mask_m[35] << 20)
355 | (mask_m[36] << 18) | (mask_m[37] << 16)
356 | (mask_m[48] << 14) | (mask_m[39] << 12)
357 | (mask_m[40] << 10) | (mask_m[41] << 8)
358 | (mask_m[42] << 6) | (mask_m[43] << 4)
359 | (mask_m[44] << 2) | (mask_m[45] << 0);
360 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
361 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
362
363 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
364 | (mask_m[18] << 26) | (mask_m[18] << 24)
365 | (mask_m[20] << 22) | (mask_m[20] << 20)
366 | (mask_m[22] << 18) | (mask_m[22] << 16)
367 | (mask_m[24] << 14) | (mask_m[24] << 12)
368 | (mask_m[25] << 10) | (mask_m[26] << 8)
369 | (mask_m[27] << 6) | (mask_m[28] << 4)
370 | (mask_m[29] << 2) | (mask_m[30] << 0);
371 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
372 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
373
374 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
375 | (mask_m[2] << 26) | (mask_m[3] << 24)
376 | (mask_m[4] << 22) | (mask_m[5] << 20)
377 | (mask_m[6] << 18) | (mask_m[7] << 16)
378 | (mask_m[8] << 14) | (mask_m[9] << 12)
379 | (mask_m[10] << 10) | (mask_m[11] << 8)
380 | (mask_m[12] << 6) | (mask_m[13] << 4)
381 | (mask_m[14] << 2) | (mask_m[15] << 0);
382 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
383 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
384
385 tmp_mask = (mask_p[15] << 28)
386 | (mask_p[14] << 26) | (mask_p[13] << 24)
387 | (mask_p[12] << 22) | (mask_p[11] << 20)
388 | (mask_p[10] << 18) | (mask_p[9] << 16)
389 | (mask_p[8] << 14) | (mask_p[7] << 12)
390 | (mask_p[6] << 10) | (mask_p[5] << 8)
391 | (mask_p[4] << 6) | (mask_p[3] << 4)
392 | (mask_p[2] << 2) | (mask_p[1] << 0);
393 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
394 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
395
396 tmp_mask = (mask_p[30] << 28)
397 | (mask_p[29] << 26) | (mask_p[28] << 24)
398 | (mask_p[27] << 22) | (mask_p[26] << 20)
399 | (mask_p[25] << 18) | (mask_p[24] << 16)
400 | (mask_p[23] << 14) | (mask_p[22] << 12)
401 | (mask_p[21] << 10) | (mask_p[20] << 8)
402 | (mask_p[19] << 6) | (mask_p[18] << 4)
403 | (mask_p[17] << 2) | (mask_p[16] << 0);
404 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
405 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
406
407 tmp_mask = (mask_p[45] << 28)
408 | (mask_p[44] << 26) | (mask_p[43] << 24)
409 | (mask_p[42] << 22) | (mask_p[41] << 20)
410 | (mask_p[40] << 18) | (mask_p[39] << 16)
411 | (mask_p[38] << 14) | (mask_p[37] << 12)
412 | (mask_p[36] << 10) | (mask_p[35] << 8)
413 | (mask_p[34] << 6) | (mask_p[33] << 4)
414 | (mask_p[32] << 2) | (mask_p[31] << 0);
415 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
416 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
417
418 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
419 | (mask_p[59] << 26) | (mask_p[58] << 24)
420 | (mask_p[57] << 22) | (mask_p[56] << 20)
421 | (mask_p[55] << 18) | (mask_p[54] << 16)
422 | (mask_p[53] << 14) | (mask_p[52] << 12)
423 | (mask_p[51] << 10) | (mask_p[50] << 8)
424 | (mask_p[49] << 6) | (mask_p[48] << 4)
425 | (mask_p[47] << 2) | (mask_p[46] << 0);
426 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
427 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
183} 428}
184 429
185static void 430/* All code below is for non single-chip solutions */
186ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 431
187 u32 numBits, u32 firstBit, 432/**
188 u32 column) 433 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
434 * @rfbuf:
435 * @reg32:
436 * @numBits:
437 * @firstBit:
438 * @column:
439 *
440 * Performs analog "swizzling" of parameters into their location.
441 * Used on external AR2133/AR5133 radios.
442 */
443static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
444 u32 numBits, u32 firstBit,
445 u32 column)
189{ 446{
190 u32 tmp32, mask, arrayEntry, lastBit; 447 u32 tmp32, mask, arrayEntry, lastBit;
191 int32_t bitPosition, bitsLeft; 448 int32_t bitPosition, bitsLeft;
@@ -209,26 +466,556 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
209 } 466 }
210} 467}
211 468
212bool 469/*
213ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, 470 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
214 u16 modesIndex) 471 * rf_pwd_icsyndiv.
472 *
473 * Theoretical Rules:
474 * if 2 GHz band
475 * if forceBiasAuto
476 * if synth_freq < 2412
477 * bias = 0
478 * else if 2412 <= synth_freq <= 2422
479 * bias = 1
480 * else // synth_freq > 2422
481 * bias = 2
482 * else if forceBias > 0
483 * bias = forceBias & 7
484 * else
485 * no change, use value from ini file
486 * else
487 * no change, invalid band
488 *
489 * 1st Mod:
490 * 2422 also uses value of 2
491 * <approved>
492 *
493 * 2nd Mod:
494 * Less than 2412 uses value of 0, 2412 and above uses value of 2
495 */
496static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
497{
498 struct ath_common *common = ath9k_hw_common(ah);
499 u32 tmp_reg;
500 int reg_writes = 0;
501 u32 new_bias = 0;
502
503 if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
504 return;
505 }
506
507 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
508
509 if (synth_freq < 2412)
510 new_bias = 0;
511 else if (synth_freq < 2422)
512 new_bias = 1;
513 else
514 new_bias = 2;
515
516 /* pre-reverse this field */
517 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
518
519 ath_print(common, ATH_DBG_CONFIG,
520 "Force rf_pwd_icsyndiv to %1d on %4d\n",
521 new_bias, synth_freq);
522
523 /* swizzle rf_pwd_icsyndiv */
524 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
525
526 /* write Bank 6 with new params */
527 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
528}
529
530/**
531 * ath9k_hw_decrease_chain_power()
532 *
533 * @ah: atheros hardware structure
534 * @chan:
535 *
536 * Only used on the AR5416 and AR5418 with the external AR2133/AR5133 radios.
537 *
538 * Sets a chain internal RF path to the lowest output power. Any
539 * further writes to bank6 after this setting will override these
540 * changes. Thus this function must be the last function in the
541 * sequence to modify bank 6.
542 *
543 * This function must be called after ar5416SetRfRegs() which is
544 * called from ath9k_hw_process_ini() due to swizzling of bank 6.
545 * Depends on ah->analogBank6Data being initialized by
546 * ath9k_hw_set_rf_regs()
547 *
548 * Additional additive reduction in power -
549 * change chain's switch table so chain's tx state is actually the rx
550 * state value. May produce different results in 2GHz/5GHz as well as
551 * board to board but in general should be a reduction.
552 *
553 * Activated by #ifdef ALTER_SWITCH. Not tried yet. If so, must be
554 * called after ah->eep_ops->set_board_values() due to RMW of
555 * PHY_SWITCH_CHAIN_0.
556 */
557void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
558 struct ath9k_channel *chan)
559{
560 int i, regWrites = 0;
561 u32 bank6SelMask;
562 u32 *bank6Temp = ah->bank6Temp;
563
564 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
565
566 switch (ah->config.diversity_control) {
567 case ATH9K_ANT_FIXED_A:
568 bank6SelMask =
569 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
570 REDUCE_CHAIN_0 : /* swapped, reduce chain 0 */
571 REDUCE_CHAIN_1; /* normal, select chain 1/2 to reduce */
572 break;
573 case ATH9K_ANT_FIXED_B:
574 bank6SelMask =
575 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
576 REDUCE_CHAIN_1 : /* swapped, reduce chain 1/2 */
577 REDUCE_CHAIN_0; /* normal, select chain 0 to reduce */
578 break;
579 case ATH9K_ANT_VARIABLE:
580 return; /* do not change anything */
581 break;
582 default:
583 return; /* do not change anything */
584 break;
585 }
586
587 for (i = 0; i < ah->iniBank6.ia_rows; i++)
588 bank6Temp[i] = ah->analogBank6Data[i];
589
590 /* Write Bank 5 to switch Bank 6 write to selected chain only */
591 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
592
593 /*
594 * Modify Bank6 selected chain to use lowest amplification.
595 * Modifies the parameters to a value of 1.
596 * Depends on existing bank 6 values to be cached in
597 * ah->analogBank6Data
598 */
599 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
600 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
601 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
602 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
603 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
604 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
605 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
606 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
607 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
608
609 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
610
611 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
612#ifdef ALTER_SWITCH
613 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
614 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
615 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
616#endif
617}
618
619/**
620 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
621 * @ah: atheros hardware stucture
622 * @chan:
623 *
624 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
625 * the channel value. Assumes writes enabled to analog bus and bank6 register
626 * cache in ah->analogBank6Data.
627 */
628int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
629{
630 struct ath_common *common = ath9k_hw_common(ah);
631 u32 channelSel = 0;
632 u32 bModeSynth = 0;
633 u32 aModeRefSel = 0;
634 u32 reg32 = 0;
635 u16 freq;
636 struct chan_centers centers;
637
638 ath9k_hw_get_channel_centers(ah, chan, &centers);
639 freq = centers.synth_center;
640
641 if (freq < 4800) {
642 u32 txctl;
643
644 if (((freq - 2192) % 5) == 0) {
645 channelSel = ((freq - 672) * 2 - 3040) / 10;
646 bModeSynth = 0;
647 } else if (((freq - 2224) % 5) == 0) {
648 channelSel = ((freq - 704) * 2 - 3040) / 10;
649 bModeSynth = 1;
650 } else {
651 ath_print(common, ATH_DBG_FATAL,
652 "Invalid channel %u MHz\n", freq);
653 return -EINVAL;
654 }
655
656 channelSel = (channelSel << 2) & 0xff;
657 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
658
659 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
660 if (freq == 2484) {
661
662 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
663 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
664 } else {
665 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
666 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
667 }
668
669 } else if ((freq % 20) == 0 && freq >= 5120) {
670 channelSel =
671 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
672 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
673 } else if ((freq % 10) == 0) {
674 channelSel =
675 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
676 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
677 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
678 else
679 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
680 } else if ((freq % 5) == 0) {
681 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
682 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
683 } else {
684 ath_print(common, ATH_DBG_FATAL,
685 "Invalid channel %u MHz\n", freq);
686 return -EINVAL;
687 }
688
689 ath9k_hw_force_bias(ah, freq);
690 ath9k_hw_decrease_chain_power(ah, chan);
691
692 reg32 =
693 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
694 (1 << 5) | 0x1;
695
696 REG_WRITE(ah, AR_PHY(0x37), reg32);
697
698 ah->curchan = chan;
699 ah->curchan_rad_index = -1;
700
701 return 0;
702}
703
704/**
705 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
706 * @ah: atheros hardware structure
707 * @chan:
708 *
709 * For non single-chip solutions. Converts to baseband spur frequency given the
710 * input channel frequency and compute register settings below.
711 */
712void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
713{
714 int bb_spur = AR_NO_SPUR;
715 int bin, cur_bin;
716 int spur_freq_sd;
717 int spur_delta_phase;
718 int denominator;
719 int upper, lower, cur_vit_mask;
720 int tmp, new;
721 int i;
722 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
723 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
724 };
725 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
726 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
727 };
728 int inc[4] = { 0, 100, 0, 0 };
729
730 int8_t mask_m[123];
731 int8_t mask_p[123];
732 int8_t mask_amt;
733 int tmp_mask;
734 int cur_bb_spur;
735 bool is2GHz = IS_CHAN_2GHZ(chan);
736
737 memset(&mask_m, 0, sizeof(int8_t) * 123);
738 memset(&mask_p, 0, sizeof(int8_t) * 123);
739
740 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
741 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
742 if (AR_NO_SPUR == cur_bb_spur)
743 break;
744 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
745 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
746 bb_spur = cur_bb_spur;
747 break;
748 }
749 }
750
751 if (AR_NO_SPUR == bb_spur)
752 return;
753
754 bin = bb_spur * 32;
755
756 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
757 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
758 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
759 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
760 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
761
762 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
763
764 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
765 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
766 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
767 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
768 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
769 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
770
771 spur_delta_phase = ((bb_spur * 524288) / 100) &
772 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
773
774 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
775 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
776
777 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
778 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
779 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
780 REG_WRITE(ah, AR_PHY_TIMING11, new);
781
782 cur_bin = -6000;
783 upper = bin + 100;
784 lower = bin - 100;
785
786 for (i = 0; i < 4; i++) {
787 int pilot_mask = 0;
788 int chan_mask = 0;
789 int bp = 0;
790 for (bp = 0; bp < 30; bp++) {
791 if ((cur_bin > lower) && (cur_bin < upper)) {
792 pilot_mask = pilot_mask | 0x1 << bp;
793 chan_mask = chan_mask | 0x1 << bp;
794 }
795 cur_bin += 100;
796 }
797 cur_bin += inc[i];
798 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
799 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
800 }
801
802 cur_vit_mask = 6100;
803 upper = bin + 120;
804 lower = bin - 120;
805
806 for (i = 0; i < 123; i++) {
807 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
808
809 /* workaround for gcc bug #37014 */
810 volatile int tmp_v = abs(cur_vit_mask - bin);
811
812 if (tmp_v < 75)
813 mask_amt = 1;
814 else
815 mask_amt = 0;
816 if (cur_vit_mask < 0)
817 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
818 else
819 mask_p[cur_vit_mask / 100] = mask_amt;
820 }
821 cur_vit_mask -= 100;
822 }
823
824 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
825 | (mask_m[48] << 26) | (mask_m[49] << 24)
826 | (mask_m[50] << 22) | (mask_m[51] << 20)
827 | (mask_m[52] << 18) | (mask_m[53] << 16)
828 | (mask_m[54] << 14) | (mask_m[55] << 12)
829 | (mask_m[56] << 10) | (mask_m[57] << 8)
830 | (mask_m[58] << 6) | (mask_m[59] << 4)
831 | (mask_m[60] << 2) | (mask_m[61] << 0);
832 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
833 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
834
835 tmp_mask = (mask_m[31] << 28)
836 | (mask_m[32] << 26) | (mask_m[33] << 24)
837 | (mask_m[34] << 22) | (mask_m[35] << 20)
838 | (mask_m[36] << 18) | (mask_m[37] << 16)
839 | (mask_m[48] << 14) | (mask_m[39] << 12)
840 | (mask_m[40] << 10) | (mask_m[41] << 8)
841 | (mask_m[42] << 6) | (mask_m[43] << 4)
842 | (mask_m[44] << 2) | (mask_m[45] << 0);
843 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
844 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
845
846 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
847 | (mask_m[18] << 26) | (mask_m[18] << 24)
848 | (mask_m[20] << 22) | (mask_m[20] << 20)
849 | (mask_m[22] << 18) | (mask_m[22] << 16)
850 | (mask_m[24] << 14) | (mask_m[24] << 12)
851 | (mask_m[25] << 10) | (mask_m[26] << 8)
852 | (mask_m[27] << 6) | (mask_m[28] << 4)
853 | (mask_m[29] << 2) | (mask_m[30] << 0);
854 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
855 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
856
857 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
858 | (mask_m[2] << 26) | (mask_m[3] << 24)
859 | (mask_m[4] << 22) | (mask_m[5] << 20)
860 | (mask_m[6] << 18) | (mask_m[7] << 16)
861 | (mask_m[8] << 14) | (mask_m[9] << 12)
862 | (mask_m[10] << 10) | (mask_m[11] << 8)
863 | (mask_m[12] << 6) | (mask_m[13] << 4)
864 | (mask_m[14] << 2) | (mask_m[15] << 0);
865 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
866 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
867
868 tmp_mask = (mask_p[15] << 28)
869 | (mask_p[14] << 26) | (mask_p[13] << 24)
870 | (mask_p[12] << 22) | (mask_p[11] << 20)
871 | (mask_p[10] << 18) | (mask_p[9] << 16)
872 | (mask_p[8] << 14) | (mask_p[7] << 12)
873 | (mask_p[6] << 10) | (mask_p[5] << 8)
874 | (mask_p[4] << 6) | (mask_p[3] << 4)
875 | (mask_p[2] << 2) | (mask_p[1] << 0);
876 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
877 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
878
879 tmp_mask = (mask_p[30] << 28)
880 | (mask_p[29] << 26) | (mask_p[28] << 24)
881 | (mask_p[27] << 22) | (mask_p[26] << 20)
882 | (mask_p[25] << 18) | (mask_p[24] << 16)
883 | (mask_p[23] << 14) | (mask_p[22] << 12)
884 | (mask_p[21] << 10) | (mask_p[20] << 8)
885 | (mask_p[19] << 6) | (mask_p[18] << 4)
886 | (mask_p[17] << 2) | (mask_p[16] << 0);
887 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
888 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
889
890 tmp_mask = (mask_p[45] << 28)
891 | (mask_p[44] << 26) | (mask_p[43] << 24)
892 | (mask_p[42] << 22) | (mask_p[41] << 20)
893 | (mask_p[40] << 18) | (mask_p[39] << 16)
894 | (mask_p[38] << 14) | (mask_p[37] << 12)
895 | (mask_p[36] << 10) | (mask_p[35] << 8)
896 | (mask_p[34] << 6) | (mask_p[33] << 4)
897 | (mask_p[32] << 2) | (mask_p[31] << 0);
898 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
899 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
900
901 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
902 | (mask_p[59] << 26) | (mask_p[58] << 24)
903 | (mask_p[57] << 22) | (mask_p[56] << 20)
904 | (mask_p[55] << 18) | (mask_p[54] << 16)
905 | (mask_p[53] << 14) | (mask_p[52] << 12)
906 | (mask_p[51] << 10) | (mask_p[50] << 8)
907 | (mask_p[49] << 6) | (mask_p[48] << 4)
908 | (mask_p[47] << 2) | (mask_p[46] << 0);
909 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
910 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
911}
912
913/**
914 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
915 * @ah: atheros hardware structure
916 *
917 * Only required for older devices with external AR2133/AR5133 radios.
918 */
919int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
920{
921#define ATH_ALLOC_BANK(bank, size) do { \
922 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
923 if (!bank) { \
924 ath_print(common, ATH_DBG_FATAL, \
925 "Cannot allocate RF banks\n"); \
926 return -ENOMEM; \
927 } \
928 } while (0);
929
930 struct ath_common *common = ath9k_hw_common(ah);
931
932 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
933
934 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
935 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
936 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
937 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
938 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
939 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
940 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
941 ATH_ALLOC_BANK(ah->addac5416_21,
942 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
943 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
944
945 return 0;
946#undef ATH_ALLOC_BANK
947}
948
949
950/**
951 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
952 * @ah: atheros hardware struture
953 * For the external AR2133/AR5133 radios banks.
954 */
955void
956ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
957{
958#define ATH_FREE_BANK(bank) do { \
959 kfree(bank); \
960 bank = NULL; \
961 } while (0);
962
963 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
964
965 ATH_FREE_BANK(ah->analogBank0Data);
966 ATH_FREE_BANK(ah->analogBank1Data);
967 ATH_FREE_BANK(ah->analogBank2Data);
968 ATH_FREE_BANK(ah->analogBank3Data);
969 ATH_FREE_BANK(ah->analogBank6Data);
970 ATH_FREE_BANK(ah->analogBank6TPCData);
971 ATH_FREE_BANK(ah->analogBank7Data);
972 ATH_FREE_BANK(ah->addac5416_21);
973 ATH_FREE_BANK(ah->bank6Temp);
974
975#undef ATH_FREE_BANK
976}
977
978/* *
979 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
980 * @ah: atheros hardware structure
981 * @chan:
982 * @modesIndex:
983 *
984 * Used for the external AR2133/AR5133 radios.
985 *
986 * Reads the EEPROM header info from the device structure and programs
987 * all rf registers. This routine requires access to the analog
988 * rf device. This is not required for single-chip devices.
989 */
990bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
991 u16 modesIndex)
215{ 992{
216 u32 eepMinorRev; 993 u32 eepMinorRev;
217 u32 ob5GHz = 0, db5GHz = 0; 994 u32 ob5GHz = 0, db5GHz = 0;
218 u32 ob2GHz = 0, db2GHz = 0; 995 u32 ob2GHz = 0, db2GHz = 0;
219 int regWrites = 0; 996 int regWrites = 0;
220 997
998 /*
999 * Software does not need to program bank data
1000 * for single chip devices, that is AR9280 or anything
1001 * after that.
1002 */
221 if (AR_SREV_9280_10_OR_LATER(ah)) 1003 if (AR_SREV_9280_10_OR_LATER(ah))
222 return true; 1004 return true;
223 1005
1006 /* Setup rf parameters */
224 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 1007 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
225 1008
1009 /* Setup Bank 0 Write */
226 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); 1010 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
227 1011
1012 /* Setup Bank 1 Write */
228 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); 1013 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
229 1014
1015 /* Setup Bank 2 Write */
230 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); 1016 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
231 1017
1018 /* Setup Bank 6 Write */
232 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, 1019 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
233 modesIndex); 1020 modesIndex);
234 { 1021 {
@@ -239,6 +1026,7 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
239 } 1026 }
240 } 1027 }
241 1028
1029 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
242 if (eepMinorRev >= 2) { 1030 if (eepMinorRev >= 2) {
243 if (IS_CHAN_2GHZ(chan)) { 1031 if (IS_CHAN_2GHZ(chan)) {
244 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 1032 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
@@ -257,8 +1045,10 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
257 } 1045 }
258 } 1046 }
259 1047
1048 /* Setup Bank 7 Setup */
260 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); 1049 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
261 1050
1051 /* Write Analog registers */
262 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 1052 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
263 regWrites); 1053 regWrites);
264 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 1054 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
@@ -274,139 +1064,3 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
274 1064
275 return true; 1065 return true;
276} 1066}
277
278void
279ath9k_hw_rf_free(struct ath_hw *ah)
280{
281#define ATH_FREE_BANK(bank) do { \
282 kfree(bank); \
283 bank = NULL; \
284 } while (0);
285
286 ATH_FREE_BANK(ah->analogBank0Data);
287 ATH_FREE_BANK(ah->analogBank1Data);
288 ATH_FREE_BANK(ah->analogBank2Data);
289 ATH_FREE_BANK(ah->analogBank3Data);
290 ATH_FREE_BANK(ah->analogBank6Data);
291 ATH_FREE_BANK(ah->analogBank6TPCData);
292 ATH_FREE_BANK(ah->analogBank7Data);
293 ATH_FREE_BANK(ah->addac5416_21);
294 ATH_FREE_BANK(ah->bank6Temp);
295#undef ATH_FREE_BANK
296}
297
298bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
299{
300 struct ath_common *common = ath9k_hw_common(ah);
301
302 if (!AR_SREV_9280_10_OR_LATER(ah)) {
303 ah->analogBank0Data =
304 kzalloc((sizeof(u32) *
305 ah->iniBank0.ia_rows), GFP_KERNEL);
306 ah->analogBank1Data =
307 kzalloc((sizeof(u32) *
308 ah->iniBank1.ia_rows), GFP_KERNEL);
309 ah->analogBank2Data =
310 kzalloc((sizeof(u32) *
311 ah->iniBank2.ia_rows), GFP_KERNEL);
312 ah->analogBank3Data =
313 kzalloc((sizeof(u32) *
314 ah->iniBank3.ia_rows), GFP_KERNEL);
315 ah->analogBank6Data =
316 kzalloc((sizeof(u32) *
317 ah->iniBank6.ia_rows), GFP_KERNEL);
318 ah->analogBank6TPCData =
319 kzalloc((sizeof(u32) *
320 ah->iniBank6TPC.ia_rows), GFP_KERNEL);
321 ah->analogBank7Data =
322 kzalloc((sizeof(u32) *
323 ah->iniBank7.ia_rows), GFP_KERNEL);
324
325 if (ah->analogBank0Data == NULL
326 || ah->analogBank1Data == NULL
327 || ah->analogBank2Data == NULL
328 || ah->analogBank3Data == NULL
329 || ah->analogBank6Data == NULL
330 || ah->analogBank6TPCData == NULL
331 || ah->analogBank7Data == NULL) {
332 ath_print(common, ATH_DBG_FATAL,
333 "Cannot allocate RF banks\n");
334 *status = -ENOMEM;
335 return false;
336 }
337
338 ah->addac5416_21 =
339 kzalloc((sizeof(u32) *
340 ah->iniAddac.ia_rows *
341 ah->iniAddac.ia_columns), GFP_KERNEL);
342 if (ah->addac5416_21 == NULL) {
343 ath_print(common, ATH_DBG_FATAL,
344 "Cannot allocate addac5416_21\n");
345 *status = -ENOMEM;
346 return false;
347 }
348
349 ah->bank6Temp =
350 kzalloc((sizeof(u32) *
351 ah->iniBank6.ia_rows), GFP_KERNEL);
352 if (ah->bank6Temp == NULL) {
353 ath_print(common, ATH_DBG_FATAL,
354 "Cannot allocate bank6Temp\n");
355 *status = -ENOMEM;
356 return false;
357 }
358 }
359
360 return true;
361}
362
363void
364ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
365{
366 int i, regWrites = 0;
367 u32 bank6SelMask;
368 u32 *bank6Temp = ah->bank6Temp;
369
370 switch (ah->config.diversity_control) {
371 case ATH9K_ANT_FIXED_A:
372 bank6SelMask =
373 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
374 REDUCE_CHAIN_0 : REDUCE_CHAIN_1;
375 break;
376 case ATH9K_ANT_FIXED_B:
377 bank6SelMask =
378 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
379 REDUCE_CHAIN_1 : REDUCE_CHAIN_0;
380 break;
381 case ATH9K_ANT_VARIABLE:
382 return;
383 break;
384 default:
385 return;
386 break;
387 }
388
389 for (i = 0; i < ah->iniBank6.ia_rows; i++)
390 bank6Temp[i] = ah->analogBank6Data[i];
391
392 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
393
394 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
395 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
396 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
397 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
398 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
399 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
400 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
401 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
402 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
403
404 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
405
406 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
407#ifdef ALTER_SWITCH
408 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
409 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
410 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
411#endif
412}
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 140fef74c666..dc145a135dc7 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,20 +17,26 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 20/* Common between single chip and non single-chip solutions */
21 struct ath9k_channel 21void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
22 *chan); 22
23bool ath9k_hw_set_channel(struct ath_hw *ah, 23/* Single chip radio settings */
24 struct ath9k_channel *chan); 24int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
25void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, 25void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
26 u32 freqIndex, int regWrites); 26
27/* Routines below are for non single-chip solutions */
28int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
29void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
30
31int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33
27bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 34bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
28 struct ath9k_channel *chan, 35 struct ath9k_channel *chan,
29 u16 modesIndex); 36 u16 modesIndex);
37
30void ath9k_hw_decrease_chain_power(struct ath_hw *ah, 38void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
31 struct ath9k_channel *chan); 39 struct ath9k_channel *chan);
32bool ath9k_hw_init_rf(struct ath_hw *ah,
33 int *status);
34 40
35#define AR_PHY_BASE 0x9800 41#define AR_PHY_BASE 0x9800
36#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 42#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
@@ -186,8 +192,20 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
186#define AR_PHY_PLL_CTL_44_2133 0xeb 192#define AR_PHY_PLL_CTL_44_2133 0xeb
187#define AR_PHY_PLL_CTL_40_2133 0xea 193#define AR_PHY_PLL_CTL_40_2133 0xea
188 194
189#define AR_PHY_SPECTRAL_SCAN 0x9912 195#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
190#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 196#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
197#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
198#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
199#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
200#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
201#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
202#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
203#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
204#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
205#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
206#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
207#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
208#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
191 209
192#define AR_PHY_RX_DELAY 0x9914 210#define AR_PHY_RX_DELAY 0x9914
193#define AR_PHY_SEARCH_START_DELAY 0x9918 211#define AR_PHY_SEARCH_START_DELAY 0x9918
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index c880a55939bf..355dd1834e1d 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -202,7 +202,8 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
202 } 202 }
203 203
204 rcu_read_lock(); 204 rcu_read_lock();
205 sta = ieee80211_find_sta(sc->hw, hdr->addr2); 205 /* XXX: use ieee80211_find_sta! */
206 sta = ieee80211_find_sta_by_hw(sc->hw, hdr->addr2);
206 if (sta) { 207 if (sta) {
207 an = (struct ath_node *) sta->drv_priv; 208 an = (struct ath_node *) sta->drv_priv;
208 if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD && 209 if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD &&
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index ceed0095efac..061e12ce0b24 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1704,4 +1704,7 @@ enum {
1704#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1704#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
1705#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1705#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
1706 1706
1707#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1708#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
1709
1707#endif 1710#endif
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 2a4efcbced60..8e052f406c35 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -282,7 +282,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
282 282
283 rcu_read_lock(); 283 rcu_read_lock();
284 284
285 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 285 /* XXX: use ieee80211_find_sta! */
286 sta = ieee80211_find_sta_by_hw(sc->hw, hdr->addr1);
286 if (!sta) { 287 if (!sta) {
287 rcu_read_unlock(); 288 rcu_read_unlock();
288 return; 289 return;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 21:03:57 -0500