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authorJohn W. Linville <linville@tuxdriver.com>2012-07-20 12:30:48 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-07-20 12:30:48 -0400
commit90b90f60c4f8e3a8525dfeb4aec46a9c7a29c857 (patch)
tree9b1d8ca6084012a02b302520bc26e5be65ba7b2a /drivers/net/wireless/ath
parent769162e38b91e1d300752e666260fa6c7b203fbc (diff)
parent36eb22e97a2b621fb707eead58ef915ab0f46e9e (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem
Diffstat (limited to 'drivers/net/wireless/ath')
-rw-r--r--drivers/net/wireless/ath/ath.h2
-rw-r--r--drivers/net/wireless/ath/ath5k/mac80211-ops.c2
-rw-r--r--drivers/net/wireless/ath/ath6kl/cfg80211.c58
-rw-r--r--drivers/net/wireless/ath/ath6kl/cfg80211.h6
-rw-r--r--drivers/net/wireless/ath/ath6kl/core.c8
-rw-r--r--drivers/net/wireless/ath/ath6kl/core.h5
-rw-r--r--drivers/net/wireless/ath/ath6kl/wmi.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/Kconfig2
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c160
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_initvals.h14
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c198
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c546
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h5
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h40
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c523
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.h6
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c13
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h24
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c16
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h84
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c21
-rw-r--r--drivers/net/wireless/ath/ath9k/link.c73
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c691
-rw-r--r--drivers/net/wireless/ath/ath9k/mci.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c3
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h145
-rw-r--r--drivers/net/wireless/ath/ath9k/wow.c532
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c102
34 files changed, 2076 insertions, 1233 deletions
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 420d69b2674c..6169fbd23ed1 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -216,6 +216,7 @@ void ath_printk(const char *level, const struct ath_common *common,
216 * used exclusively for WLAN-BT coexistence starting from 216 * used exclusively for WLAN-BT coexistence starting from
217 * AR9462. 217 * AR9462.
218 * @ATH_DBG_DFS: radar datection 218 * @ATH_DBG_DFS: radar datection
219 * @ATH_DBG_WOW: Wake on Wireless
219 * @ATH_DBG_ANY: enable all debugging 220 * @ATH_DBG_ANY: enable all debugging
220 * 221 *
221 * The debug level is used to control the amount and type of debugging output 222 * The debug level is used to control the amount and type of debugging output
@@ -243,6 +244,7 @@ enum ATH_DEBUG {
243 ATH_DBG_BSTUCK = 0x00008000, 244 ATH_DBG_BSTUCK = 0x00008000,
244 ATH_DBG_MCI = 0x00010000, 245 ATH_DBG_MCI = 0x00010000,
245 ATH_DBG_DFS = 0x00020000, 246 ATH_DBG_DFS = 0x00020000,
247 ATH_DBG_WOW = 0x00040000,
246 ATH_DBG_ANY = 0xffffffff 248 ATH_DBG_ANY = 0xffffffff
247}; 249};
248 250
diff --git a/drivers/net/wireless/ath/ath5k/mac80211-ops.c b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
index 22b80af0f47c..260e7dc7f751 100644
--- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
+++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
@@ -594,7 +594,7 @@ ath5k_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
594 qi.tqi_aifs = params->aifs; 594 qi.tqi_aifs = params->aifs;
595 qi.tqi_cw_min = params->cw_min; 595 qi.tqi_cw_min = params->cw_min;
596 qi.tqi_cw_max = params->cw_max; 596 qi.tqi_cw_max = params->cw_max;
597 qi.tqi_burst_time = params->txop; 597 qi.tqi_burst_time = params->txop * 32;
598 598
599 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, 599 ATH5K_DBG(ah, ATH5K_DEBUG_ANY,
600 "Configure tx [queue %d], " 600 "Configure tx [queue %d], "
diff --git a/drivers/net/wireless/ath/ath6kl/cfg80211.c b/drivers/net/wireless/ath/ath6kl/cfg80211.c
index aca1d2689e90..86aeef4b9d7e 100644
--- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
+++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
@@ -966,11 +966,11 @@ static int ath6kl_set_probed_ssids(struct ath6kl *ar,
966 return 0; 966 return 0;
967} 967}
968 968
969static int ath6kl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, 969static int ath6kl_cfg80211_scan(struct wiphy *wiphy,
970 struct cfg80211_scan_request *request) 970 struct cfg80211_scan_request *request)
971{ 971{
972 struct ath6kl *ar = ath6kl_priv(ndev); 972 struct ath6kl_vif *vif = ath6kl_vif_from_wdev(request->wdev);
973 struct ath6kl_vif *vif = netdev_priv(ndev); 973 struct ath6kl *ar = ath6kl_priv(vif->ndev);
974 s8 n_channels = 0; 974 s8 n_channels = 0;
975 u16 *channels = NULL; 975 u16 *channels = NULL;
976 int ret = 0; 976 int ret = 0;
@@ -1487,14 +1487,14 @@ static int ath6kl_cfg80211_set_power_mgmt(struct wiphy *wiphy,
1487 return 0; 1487 return 0;
1488} 1488}
1489 1489
1490static struct net_device *ath6kl_cfg80211_add_iface(struct wiphy *wiphy, 1490static struct wireless_dev *ath6kl_cfg80211_add_iface(struct wiphy *wiphy,
1491 char *name, 1491 char *name,
1492 enum nl80211_iftype type, 1492 enum nl80211_iftype type,
1493 u32 *flags, 1493 u32 *flags,
1494 struct vif_params *params) 1494 struct vif_params *params)
1495{ 1495{
1496 struct ath6kl *ar = wiphy_priv(wiphy); 1496 struct ath6kl *ar = wiphy_priv(wiphy);
1497 struct net_device *ndev; 1497 struct wireless_dev *wdev;
1498 u8 if_idx, nw_type; 1498 u8 if_idx, nw_type;
1499 1499
1500 if (ar->num_vif == ar->vif_max) { 1500 if (ar->num_vif == ar->vif_max) {
@@ -1507,20 +1507,20 @@ static struct net_device *ath6kl_cfg80211_add_iface(struct wiphy *wiphy,
1507 return ERR_PTR(-EINVAL); 1507 return ERR_PTR(-EINVAL);
1508 } 1508 }
1509 1509
1510 ndev = ath6kl_interface_add(ar, name, type, if_idx, nw_type); 1510 wdev = ath6kl_interface_add(ar, name, type, if_idx, nw_type);
1511 if (!ndev) 1511 if (!wdev)
1512 return ERR_PTR(-ENOMEM); 1512 return ERR_PTR(-ENOMEM);
1513 1513
1514 ar->num_vif++; 1514 ar->num_vif++;
1515 1515
1516 return ndev; 1516 return wdev;
1517} 1517}
1518 1518
1519static int ath6kl_cfg80211_del_iface(struct wiphy *wiphy, 1519static int ath6kl_cfg80211_del_iface(struct wiphy *wiphy,
1520 struct net_device *ndev) 1520 struct wireless_dev *wdev)
1521{ 1521{
1522 struct ath6kl *ar = wiphy_priv(wiphy); 1522 struct ath6kl *ar = wiphy_priv(wiphy);
1523 struct ath6kl_vif *vif = netdev_priv(ndev); 1523 struct ath6kl_vif *vif = netdev_priv(wdev->netdev);
1524 1524
1525 spin_lock_bh(&ar->list_lock); 1525 spin_lock_bh(&ar->list_lock);
1526 list_del(&vif->list); 1526 list_del(&vif->list);
@@ -2975,14 +2975,14 @@ static int ath6kl_change_station(struct wiphy *wiphy, struct net_device *dev,
2975} 2975}
2976 2976
2977static int ath6kl_remain_on_channel(struct wiphy *wiphy, 2977static int ath6kl_remain_on_channel(struct wiphy *wiphy,
2978 struct net_device *dev, 2978 struct wireless_dev *wdev,
2979 struct ieee80211_channel *chan, 2979 struct ieee80211_channel *chan,
2980 enum nl80211_channel_type channel_type, 2980 enum nl80211_channel_type channel_type,
2981 unsigned int duration, 2981 unsigned int duration,
2982 u64 *cookie) 2982 u64 *cookie)
2983{ 2983{
2984 struct ath6kl *ar = ath6kl_priv(dev); 2984 struct ath6kl_vif *vif = ath6kl_vif_from_wdev(wdev);
2985 struct ath6kl_vif *vif = netdev_priv(dev); 2985 struct ath6kl *ar = ath6kl_priv(vif->ndev);
2986 u32 id; 2986 u32 id;
2987 2987
2988 /* TODO: if already pending or ongoing remain-on-channel, 2988 /* TODO: if already pending or ongoing remain-on-channel,
@@ -2999,11 +2999,11 @@ static int ath6kl_remain_on_channel(struct wiphy *wiphy,
2999} 2999}
3000 3000
3001static int ath6kl_cancel_remain_on_channel(struct wiphy *wiphy, 3001static int ath6kl_cancel_remain_on_channel(struct wiphy *wiphy,
3002 struct net_device *dev, 3002 struct wireless_dev *wdev,
3003 u64 cookie) 3003 u64 cookie)
3004{ 3004{
3005 struct ath6kl *ar = ath6kl_priv(dev); 3005 struct ath6kl_vif *vif = ath6kl_vif_from_wdev(wdev);
3006 struct ath6kl_vif *vif = netdev_priv(dev); 3006 struct ath6kl *ar = ath6kl_priv(vif->ndev);
3007 3007
3008 if (cookie != vif->last_roc_id) 3008 if (cookie != vif->last_roc_id)
3009 return -ENOENT; 3009 return -ENOENT;
@@ -3134,15 +3134,15 @@ static bool ath6kl_is_p2p_go_ssid(const u8 *buf, size_t len)
3134 return false; 3134 return false;
3135} 3135}
3136 3136
3137static int ath6kl_mgmt_tx(struct wiphy *wiphy, struct net_device *dev, 3137static int ath6kl_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
3138 struct ieee80211_channel *chan, bool offchan, 3138 struct ieee80211_channel *chan, bool offchan,
3139 enum nl80211_channel_type channel_type, 3139 enum nl80211_channel_type channel_type,
3140 bool channel_type_valid, unsigned int wait, 3140 bool channel_type_valid, unsigned int wait,
3141 const u8 *buf, size_t len, bool no_cck, 3141 const u8 *buf, size_t len, bool no_cck,
3142 bool dont_wait_for_ack, u64 *cookie) 3142 bool dont_wait_for_ack, u64 *cookie)
3143{ 3143{
3144 struct ath6kl *ar = ath6kl_priv(dev); 3144 struct ath6kl_vif *vif = ath6kl_vif_from_wdev(wdev);
3145 struct ath6kl_vif *vif = netdev_priv(dev); 3145 struct ath6kl *ar = ath6kl_priv(vif->ndev);
3146 u32 id; 3146 u32 id;
3147 const struct ieee80211_mgmt *mgmt; 3147 const struct ieee80211_mgmt *mgmt;
3148 bool more_data, queued; 3148 bool more_data, queued;
@@ -3187,10 +3187,10 @@ static int ath6kl_mgmt_tx(struct wiphy *wiphy, struct net_device *dev,
3187} 3187}
3188 3188
3189static void ath6kl_mgmt_frame_register(struct wiphy *wiphy, 3189static void ath6kl_mgmt_frame_register(struct wiphy *wiphy,
3190 struct net_device *dev, 3190 struct wireless_dev *wdev,
3191 u16 frame_type, bool reg) 3191 u16 frame_type, bool reg)
3192{ 3192{
3193 struct ath6kl_vif *vif = netdev_priv(dev); 3193 struct ath6kl_vif *vif = ath6kl_vif_from_wdev(wdev);
3194 3194
3195 ath6kl_dbg(ATH6KL_DBG_WLAN_CFG, "%s: frame_type=0x%x reg=%d\n", 3195 ath6kl_dbg(ATH6KL_DBG_WLAN_CFG, "%s: frame_type=0x%x reg=%d\n",
3196 __func__, frame_type, reg); 3196 __func__, frame_type, reg);
@@ -3477,9 +3477,9 @@ void ath6kl_cfg80211_vif_cleanup(struct ath6kl_vif *vif)
3477 ar->num_vif--; 3477 ar->num_vif--;
3478} 3478}
3479 3479
3480struct net_device *ath6kl_interface_add(struct ath6kl *ar, char *name, 3480struct wireless_dev *ath6kl_interface_add(struct ath6kl *ar, char *name,
3481 enum nl80211_iftype type, u8 fw_vif_idx, 3481 enum nl80211_iftype type,
3482 u8 nw_type) 3482 u8 fw_vif_idx, u8 nw_type)
3483{ 3483{
3484 struct net_device *ndev; 3484 struct net_device *ndev;
3485 struct ath6kl_vif *vif; 3485 struct ath6kl_vif *vif;
@@ -3533,7 +3533,7 @@ struct net_device *ath6kl_interface_add(struct ath6kl *ar, char *name,
3533 list_add_tail(&vif->list, &ar->vif_list); 3533 list_add_tail(&vif->list, &ar->vif_list);
3534 spin_unlock_bh(&ar->list_lock); 3534 spin_unlock_bh(&ar->list_lock);
3535 3535
3536 return ndev; 3536 return &vif->wdev;
3537 3537
3538err: 3538err:
3539 aggr_module_destroy(vif->aggr_cntxt); 3539 aggr_module_destroy(vif->aggr_cntxt);
diff --git a/drivers/net/wireless/ath/ath6kl/cfg80211.h b/drivers/net/wireless/ath/ath6kl/cfg80211.h
index b992046a1b0e..56b1ebe79812 100644
--- a/drivers/net/wireless/ath/ath6kl/cfg80211.h
+++ b/drivers/net/wireless/ath/ath6kl/cfg80211.h
@@ -25,9 +25,9 @@ enum ath6kl_cfg_suspend_mode {
25 ATH6KL_CFG_SUSPEND_SCHED_SCAN, 25 ATH6KL_CFG_SUSPEND_SCHED_SCAN,
26}; 26};
27 27
28struct net_device *ath6kl_interface_add(struct ath6kl *ar, char *name, 28struct wireless_dev *ath6kl_interface_add(struct ath6kl *ar, char *name,
29 enum nl80211_iftype type, 29 enum nl80211_iftype type,
30 u8 fw_vif_idx, u8 nw_type); 30 u8 fw_vif_idx, u8 nw_type);
31void ath6kl_cfg80211_ch_switch_notify(struct ath6kl_vif *vif, int freq, 31void ath6kl_cfg80211_ch_switch_notify(struct ath6kl_vif *vif, int freq,
32 enum wmi_phy_mode mode); 32 enum wmi_phy_mode mode);
33void ath6kl_cfg80211_scan_complete_event(struct ath6kl_vif *vif, bool aborted); 33void ath6kl_cfg80211_scan_complete_event(struct ath6kl_vif *vif, bool aborted);
diff --git a/drivers/net/wireless/ath/ath6kl/core.c b/drivers/net/wireless/ath/ath6kl/core.c
index fdb3b1decc76..82c4dd2a960e 100644
--- a/drivers/net/wireless/ath/ath6kl/core.c
+++ b/drivers/net/wireless/ath/ath6kl/core.c
@@ -56,7 +56,7 @@ EXPORT_SYMBOL(ath6kl_core_rx_complete);
56int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type) 56int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type)
57{ 57{
58 struct ath6kl_bmi_target_info targ_info; 58 struct ath6kl_bmi_target_info targ_info;
59 struct net_device *ndev; 59 struct wireless_dev *wdev;
60 int ret = 0, i; 60 int ret = 0, i;
61 61
62 switch (htc_type) { 62 switch (htc_type) {
@@ -187,12 +187,12 @@ int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type)
187 rtnl_lock(); 187 rtnl_lock();
188 188
189 /* Add an initial station interface */ 189 /* Add an initial station interface */
190 ndev = ath6kl_interface_add(ar, "wlan%d", NL80211_IFTYPE_STATION, 0, 190 wdev = ath6kl_interface_add(ar, "wlan%d", NL80211_IFTYPE_STATION, 0,
191 INFRA_NETWORK); 191 INFRA_NETWORK);
192 192
193 rtnl_unlock(); 193 rtnl_unlock();
194 194
195 if (!ndev) { 195 if (!wdev) {
196 ath6kl_err("Failed to instantiate a network device\n"); 196 ath6kl_err("Failed to instantiate a network device\n");
197 ret = -ENOMEM; 197 ret = -ENOMEM;
198 wiphy_unregister(ar->wiphy); 198 wiphy_unregister(ar->wiphy);
@@ -200,7 +200,7 @@ int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type)
200 } 200 }
201 201
202 ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n", 202 ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n",
203 __func__, ndev->name, ndev, ar); 203 __func__, wdev->netdev->name, wdev->netdev, ar);
204 204
205 return ret; 205 return ret;
206 206
diff --git a/drivers/net/wireless/ath/ath6kl/core.h b/drivers/net/wireless/ath/ath6kl/core.h
index d38a31de344c..cec49a31029a 100644
--- a/drivers/net/wireless/ath/ath6kl/core.h
+++ b/drivers/net/wireless/ath/ath6kl/core.h
@@ -589,6 +589,11 @@ struct ath6kl_vif {
589 struct list_head mc_filter; 589 struct list_head mc_filter;
590}; 590};
591 591
592static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
593{
594 return container_of(wdev, struct ath6kl_vif, wdev);
595}
596
592#define WOW_LIST_ID 0 597#define WOW_LIST_ID 0
593#define WOW_HOST_REQ_DELAY 500 /* ms */ 598#define WOW_HOST_REQ_DELAY 500 /* ms */
594 599
diff --git a/drivers/net/wireless/ath/ath6kl/wmi.c b/drivers/net/wireless/ath/ath6kl/wmi.c
index a6caa673e8ad..c30ab4b11d61 100644
--- a/drivers/net/wireless/ath/ath6kl/wmi.c
+++ b/drivers/net/wireless/ath/ath6kl/wmi.c
@@ -474,7 +474,7 @@ static int ath6kl_wmi_remain_on_chnl_event_rx(struct wmi *wmi, u8 *datap,
474 return -EINVAL; 474 return -EINVAL;
475 } 475 }
476 id = vif->last_roc_id; 476 id = vif->last_roc_id;
477 cfg80211_ready_on_channel(vif->ndev, id, chan, NL80211_CHAN_NO_HT, 477 cfg80211_ready_on_channel(&vif->wdev, id, chan, NL80211_CHAN_NO_HT,
478 dur, GFP_ATOMIC); 478 dur, GFP_ATOMIC);
479 479
480 return 0; 480 return 0;
@@ -513,7 +513,7 @@ static int ath6kl_wmi_cancel_remain_on_chnl_event_rx(struct wmi *wmi,
513 else 513 else
514 id = vif->last_roc_id; /* timeout on uncanceled r-o-c */ 514 id = vif->last_roc_id; /* timeout on uncanceled r-o-c */
515 vif->last_cancel_roc_id = 0; 515 vif->last_cancel_roc_id = 0;
516 cfg80211_remain_on_channel_expired(vif->ndev, id, chan, 516 cfg80211_remain_on_channel_expired(&vif->wdev, id, chan,
517 NL80211_CHAN_NO_HT, GFP_ATOMIC); 517 NL80211_CHAN_NO_HT, GFP_ATOMIC);
518 518
519 return 0; 519 return 0;
@@ -533,7 +533,7 @@ static int ath6kl_wmi_tx_status_event_rx(struct wmi *wmi, u8 *datap, int len,
533 ath6kl_dbg(ATH6KL_DBG_WMI, "tx_status: id=%x ack_status=%u\n", 533 ath6kl_dbg(ATH6KL_DBG_WMI, "tx_status: id=%x ack_status=%u\n",
534 id, ev->ack_status); 534 id, ev->ack_status);
535 if (wmi->last_mgmt_tx_frame) { 535 if (wmi->last_mgmt_tx_frame) {
536 cfg80211_mgmt_tx_status(vif->ndev, id, 536 cfg80211_mgmt_tx_status(&vif->wdev, id,
537 wmi->last_mgmt_tx_frame, 537 wmi->last_mgmt_tx_frame,
538 wmi->last_mgmt_tx_frame_len, 538 wmi->last_mgmt_tx_frame_len,
539 !!ev->ack_status, GFP_ATOMIC); 539 !!ev->ack_status, GFP_ATOMIC);
@@ -568,7 +568,7 @@ static int ath6kl_wmi_rx_probe_req_event_rx(struct wmi *wmi, u8 *datap, int len,
568 dlen, freq, vif->probe_req_report); 568 dlen, freq, vif->probe_req_report);
569 569
570 if (vif->probe_req_report || vif->nw_type == AP_NETWORK) 570 if (vif->probe_req_report || vif->nw_type == AP_NETWORK)
571 cfg80211_rx_mgmt(vif->ndev, freq, 0, 571 cfg80211_rx_mgmt(&vif->wdev, freq, 0,
572 ev->data, dlen, GFP_ATOMIC); 572 ev->data, dlen, GFP_ATOMIC);
573 573
574 return 0; 574 return 0;
@@ -608,7 +608,7 @@ static int ath6kl_wmi_rx_action_event_rx(struct wmi *wmi, u8 *datap, int len,
608 return -EINVAL; 608 return -EINVAL;
609 } 609 }
610 ath6kl_dbg(ATH6KL_DBG_WMI, "rx_action: len=%u freq=%u\n", dlen, freq); 610 ath6kl_dbg(ATH6KL_DBG_WMI, "rx_action: len=%u freq=%u\n", dlen, freq);
611 cfg80211_rx_mgmt(vif->ndev, freq, 0, 611 cfg80211_rx_mgmt(&vif->wdev, freq, 0,
612 ev->data, dlen, GFP_ATOMIC); 612 ev->data, dlen, GFP_ATOMIC);
613 613
614 return 0; 614 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index e507e78398f3..c7aa6646123e 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -64,7 +64,7 @@ config ATH9K_DEBUGFS
64 64
65config ATH9K_DFS_CERTIFIED 65config ATH9K_DFS_CERTIFIED
66 bool "Atheros DFS support for certified platforms" 66 bool "Atheros DFS support for certified platforms"
67 depends on ATH9K && EXPERT 67 depends on ATH9K && CFG80211_CERTIFICATION_ONUS
68 default n 68 default n
69 ---help--- 69 ---help---
70 This option enables DFS support for initiating radiation on 70 This option enables DFS support for initiating radiation on
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 9c41232b0cd0..2ad8f9474ba1 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -17,6 +17,7 @@ ath9k-$(CONFIG_ATH9K_DFS_CERTIFIED) += \
17 dfs.o \ 17 dfs.o \
18 dfs_pattern_detector.o \ 18 dfs_pattern_detector.o \
19 dfs_pri_detector.o 19 dfs_pri_detector.o
20ath9k-$(CONFIG_PM_SLEEP) += wow.o
20 21
21obj-$(CONFIG_ATH9K) += ath9k.o 22obj-$(CONFIG_ATH9K) += ath9k.o
22 23
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index edf21ea4fe93..648da3e885e9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -26,101 +26,74 @@
26static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 26static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
27{ 27{
28 if (AR_SREV_9271(ah)) { 28 if (AR_SREV_9271(ah)) {
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, 29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
30 ARRAY_SIZE(ar9271Modes_9271), 5); 30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
31 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, 31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
32 ARRAY_SIZE(ar9271Common_9271), 2);
33 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
34 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
35 return; 32 return;
36 } 33 }
37 34
38 if (ah->config.pcie_clock_req) 35 if (ah->config.pcie_clock_req)
39 INIT_INI_ARRAY(&ah->iniPcieSerdes, 36 INIT_INI_ARRAY(&ah->iniPcieSerdes,
40 ar9280PciePhy_clkreq_off_L1_9280, 37 ar9280PciePhy_clkreq_off_L1_9280);
41 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
42 else 38 else
43 INIT_INI_ARRAY(&ah->iniPcieSerdes, 39 INIT_INI_ARRAY(&ah->iniPcieSerdes,
44 ar9280PciePhy_clkreq_always_on_L1_9280, 40 ar9280PciePhy_clkreq_always_on_L1_9280);
45 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 41#ifdef CONFIG_PM_SLEEP
42 INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
43 ar9280PciePhy_awow);
44#endif
46 45
47 if (AR_SREV_9287_11_OR_LATER(ah)) { 46 if (AR_SREV_9287_11_OR_LATER(ah)) {
48 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, 47 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
49 ARRAY_SIZE(ar9287Modes_9287_1_1), 5); 48 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
50 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
51 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
52 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 49 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
53 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 50 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
54 ARRAY_SIZE(ar9285Modes_9285_1_2), 5); 51 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
55 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
56 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
57 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 52 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
58 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 53 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
59 ARRAY_SIZE(ar9280Modes_9280_2), 5); 54 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
60 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
61 ARRAY_SIZE(ar9280Common_9280_2), 2);
62 55
63 INIT_INI_ARRAY(&ah->iniModesFastClock, 56 INIT_INI_ARRAY(&ah->iniModesFastClock,
64 ar9280Modes_fast_clock_9280_2, 57 ar9280Modes_fast_clock_9280_2);
65 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
66 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 58 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
67 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 59 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
68 ARRAY_SIZE(ar5416Modes_9160), 5); 60 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
69 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
70 ARRAY_SIZE(ar5416Common_9160), 2);
71 if (AR_SREV_9160_11(ah)) { 61 if (AR_SREV_9160_11(ah)) {
72 INIT_INI_ARRAY(&ah->iniAddac, 62 INIT_INI_ARRAY(&ah->iniAddac,
73 ar5416Addac_9160_1_1, 63 ar5416Addac_9160_1_1);
74 ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
75 } else { 64 } else {
76 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, 65 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
77 ARRAY_SIZE(ar5416Addac_9160), 2);
78 } 66 }
79 } else if (AR_SREV_9100_OR_LATER(ah)) { 67 } else if (AR_SREV_9100_OR_LATER(ah)) {
80 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, 68 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
81 ARRAY_SIZE(ar5416Modes_9100), 5); 69 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
82 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, 70 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
83 ARRAY_SIZE(ar5416Common_9100), 2); 71 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
84 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
85 ARRAY_SIZE(ar5416Bank6_9100), 3);
86 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
87 ARRAY_SIZE(ar5416Addac_9100), 2);
88 } else { 72 } else {
89 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, 73 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
90 ARRAY_SIZE(ar5416Modes), 5); 74 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
91 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, 75 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
92 ARRAY_SIZE(ar5416Common), 2); 76 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
93 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
94 ARRAY_SIZE(ar5416Bank6TPC), 3);
95 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
96 ARRAY_SIZE(ar5416Addac), 2);
97 } 77 }
98 78
99 if (!AR_SREV_9280_20_OR_LATER(ah)) { 79 if (!AR_SREV_9280_20_OR_LATER(ah)) {
100 /* Common for AR5416, AR913x, AR9160 */ 80 /* Common for AR5416, AR913x, AR9160 */
101 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, 81 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
102 ARRAY_SIZE(ar5416BB_RfGain), 3); 82
103 83 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
104 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, 84 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
105 ARRAY_SIZE(ar5416Bank0), 2); 85 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
106 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, 86 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
107 ARRAY_SIZE(ar5416Bank1), 2); 87 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
108 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
109 ARRAY_SIZE(ar5416Bank2), 2);
110 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
111 ARRAY_SIZE(ar5416Bank3), 3);
112 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
113 ARRAY_SIZE(ar5416Bank7), 2);
114 88
115 /* Common for AR5416, AR9160 */ 89 /* Common for AR5416, AR9160 */
116 if (!AR_SREV_9100(ah)) 90 if (!AR_SREV_9100(ah))
117 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, 91 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
118 ARRAY_SIZE(ar5416Bank6), 3);
119 92
120 /* Common for AR913x, AR9160 */ 93 /* Common for AR913x, AR9160 */
121 if (!AR_SREV_5416(ah)) 94 if (!AR_SREV_5416(ah))
122 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, 95 INIT_INI_ARRAY(&ah->iniBank6TPC,
123 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 96 ar5416Bank6TPC_9100);
124 } 97 }
125 98
126 /* iniAddac needs to be modified for these chips */ 99 /* iniAddac needs to be modified for these chips */
@@ -143,13 +116,9 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
143 } 116 }
144 if (AR_SREV_9287_11_OR_LATER(ah)) { 117 if (AR_SREV_9287_11_OR_LATER(ah)) {
145 INIT_INI_ARRAY(&ah->iniCckfirNormal, 118 INIT_INI_ARRAY(&ah->iniCckfirNormal,
146 ar9287Common_normal_cck_fir_coeff_9287_1_1, 119 ar9287Common_normal_cck_fir_coeff_9287_1_1);
147 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
148 2);
149 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 120 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
150 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 121 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
151 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
152 2);
153 } 122 }
154} 123}
155 124
@@ -163,20 +132,16 @@ static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
163 132
164 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 133 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
165 INIT_INI_ARRAY(&ah->iniModesRxGain, 134 INIT_INI_ARRAY(&ah->iniModesRxGain,
166 ar9280Modes_backoff_13db_rxgain_9280_2, 135 ar9280Modes_backoff_13db_rxgain_9280_2);
167 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
168 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 136 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
169 INIT_INI_ARRAY(&ah->iniModesRxGain, 137 INIT_INI_ARRAY(&ah->iniModesRxGain,
170 ar9280Modes_backoff_23db_rxgain_9280_2, 138 ar9280Modes_backoff_23db_rxgain_9280_2);
171 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
172 else 139 else
173 INIT_INI_ARRAY(&ah->iniModesRxGain, 140 INIT_INI_ARRAY(&ah->iniModesRxGain,
174 ar9280Modes_original_rxgain_9280_2, 141 ar9280Modes_original_rxgain_9280_2);
175 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
176 } else { 142 } else {
177 INIT_INI_ARRAY(&ah->iniModesRxGain, 143 INIT_INI_ARRAY(&ah->iniModesRxGain,
178 ar9280Modes_original_rxgain_9280_2, 144 ar9280Modes_original_rxgain_9280_2);
179 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
180 } 145 }
181} 146}
182 147
@@ -186,16 +151,13 @@ static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
186 AR5416_EEP_MINOR_VER_19) { 151 AR5416_EEP_MINOR_VER_19) {
187 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 152 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
188 INIT_INI_ARRAY(&ah->iniModesTxGain, 153 INIT_INI_ARRAY(&ah->iniModesTxGain,
189 ar9280Modes_high_power_tx_gain_9280_2, 154 ar9280Modes_high_power_tx_gain_9280_2);
190 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
191 else 155 else
192 INIT_INI_ARRAY(&ah->iniModesTxGain, 156 INIT_INI_ARRAY(&ah->iniModesTxGain,
193 ar9280Modes_original_tx_gain_9280_2, 157 ar9280Modes_original_tx_gain_9280_2);
194 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
195 } else { 158 } else {
196 INIT_INI_ARRAY(&ah->iniModesTxGain, 159 INIT_INI_ARRAY(&ah->iniModesTxGain,
197 ar9280Modes_original_tx_gain_9280_2, 160 ar9280Modes_original_tx_gain_9280_2);
198 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
199 } 161 }
200} 162}
201 163
@@ -203,12 +165,10 @@ static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
203{ 165{
204 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 166 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
205 INIT_INI_ARRAY(&ah->iniModesTxGain, 167 INIT_INI_ARRAY(&ah->iniModesTxGain,
206 ar9271Modes_high_power_tx_gain_9271, 168 ar9271Modes_high_power_tx_gain_9271);
207 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
208 else 169 else
209 INIT_INI_ARRAY(&ah->iniModesTxGain, 170 INIT_INI_ARRAY(&ah->iniModesTxGain,
210 ar9271Modes_normal_power_tx_gain_9271, 171 ar9271Modes_normal_power_tx_gain_9271);
211 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
212} 172}
213 173
214static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) 174static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
@@ -217,8 +177,7 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
217 177
218 if (AR_SREV_9287_11_OR_LATER(ah)) 178 if (AR_SREV_9287_11_OR_LATER(ah))
219 INIT_INI_ARRAY(&ah->iniModesRxGain, 179 INIT_INI_ARRAY(&ah->iniModesRxGain,
220 ar9287Modes_rx_gain_9287_1_1, 180 ar9287Modes_rx_gain_9287_1_1);
221 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
222 else if (AR_SREV_9280_20(ah)) 181 else if (AR_SREV_9280_20(ah))
223 ar9280_20_hw_init_rxgain_ini(ah); 182 ar9280_20_hw_init_rxgain_ini(ah);
224 183
@@ -226,8 +185,7 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
226 ar9271_hw_init_txgain_ini(ah, txgain_type); 185 ar9271_hw_init_txgain_ini(ah, txgain_type);
227 } else if (AR_SREV_9287_11_OR_LATER(ah)) { 186 } else if (AR_SREV_9287_11_OR_LATER(ah)) {
228 INIT_INI_ARRAY(&ah->iniModesTxGain, 187 INIT_INI_ARRAY(&ah->iniModesTxGain,
229 ar9287Modes_tx_gain_9287_1_1, 188 ar9287Modes_tx_gain_9287_1_1);
230 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
231 } else if (AR_SREV_9280_20(ah)) { 189 } else if (AR_SREV_9280_20(ah)) {
232 ar9280_20_hw_init_txgain_ini(ah, txgain_type); 190 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
233 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 191 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
@@ -235,26 +193,18 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
235 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 193 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
236 if (AR_SREV_9285E_20(ah)) { 194 if (AR_SREV_9285E_20(ah)) {
237 INIT_INI_ARRAY(&ah->iniModesTxGain, 195 INIT_INI_ARRAY(&ah->iniModesTxGain,
238 ar9285Modes_XE2_0_high_power, 196 ar9285Modes_XE2_0_high_power);
239 ARRAY_SIZE(
240 ar9285Modes_XE2_0_high_power), 5);
241 } else { 197 } else {
242 INIT_INI_ARRAY(&ah->iniModesTxGain, 198 INIT_INI_ARRAY(&ah->iniModesTxGain,
243 ar9285Modes_high_power_tx_gain_9285_1_2, 199 ar9285Modes_high_power_tx_gain_9285_1_2);
244 ARRAY_SIZE(
245 ar9285Modes_high_power_tx_gain_9285_1_2), 5);
246 } 200 }
247 } else { 201 } else {
248 if (AR_SREV_9285E_20(ah)) { 202 if (AR_SREV_9285E_20(ah)) {
249 INIT_INI_ARRAY(&ah->iniModesTxGain, 203 INIT_INI_ARRAY(&ah->iniModesTxGain,
250 ar9285Modes_XE2_0_normal_power, 204 ar9285Modes_XE2_0_normal_power);
251 ARRAY_SIZE(
252 ar9285Modes_XE2_0_normal_power), 5);
253 } else { 205 } else {
254 INIT_INI_ARRAY(&ah->iniModesTxGain, 206 INIT_INI_ARRAY(&ah->iniModesTxGain,
255 ar9285Modes_original_tx_gain_9285_1_2, 207 ar9285Modes_original_tx_gain_9285_1_2);
256 ARRAY_SIZE(
257 ar9285Modes_original_tx_gain_9285_1_2), 5);
258 } 208 }
259 } 209 }
260 } 210 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
index 4d18c66a6790..beb6162cf97c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
@@ -925,6 +925,20 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
925 {0x00004044, 0x00000000}, 925 {0x00004044, 0x00000000},
926}; 926};
927 927
928static const u32 ar9280PciePhy_awow[][2] = {
929 /* Addr allmodes */
930 {0x00004040, 0x9248fd00},
931 {0x00004040, 0x24924924},
932 {0x00004040, 0xa8000019},
933 {0x00004040, 0x13160820},
934 {0x00004040, 0xe5980560},
935 {0x00004040, 0xc01dcffd},
936 {0x00004040, 0x1aaabe41},
937 {0x00004040, 0xbe105554},
938 {0x00004040, 0x00043007},
939 {0x00004044, 0x00000000},
940};
941
928static const u32 ar9285Modes_9285_1_2[][5] = { 942static const u32 ar9285Modes_9285_1_2[][5] = {
929 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 943 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
930 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 944 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index ab2bfcb3bed2..2588848f4a82 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300_default = {
131 .thresh62 = 28, 131 .thresh62 = 28,
132 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
134 .xlna_bias_strength = 0,
134 .futureModal = { 135 .futureModal = {
135 0, 0, 0, 0, 0, 0, 0, 0, 136 0, 0, 0, 0, 0, 0, 0,
136 }, 137 },
137 }, 138 },
138 .base_ext1 = { 139 .base_ext1 = {
@@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300_default = {
331 .thresh62 = 28, 332 .thresh62 = 28,
332 .papdRateMaskHt20 = LE32(0x0c80c080), 333 .papdRateMaskHt20 = LE32(0x0c80c080),
333 .papdRateMaskHt40 = LE32(0x0080c080), 334 .papdRateMaskHt40 = LE32(0x0080c080),
335 .xlna_bias_strength = 0,
334 .futureModal = { 336 .futureModal = {
335 0, 0, 0, 0, 0, 0, 0, 0, 337 0, 0, 0, 0, 0, 0, 0,
336 }, 338 },
337 }, 339 },
338 .base_ext2 = { 340 .base_ext2 = {
@@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300_x113 = {
704 .thresh62 = 28, 706 .thresh62 = 28,
705 .papdRateMaskHt20 = LE32(0x0c80c080), 707 .papdRateMaskHt20 = LE32(0x0c80c080),
706 .papdRateMaskHt40 = LE32(0x0080c080), 708 .papdRateMaskHt40 = LE32(0x0080c080),
709 .xlna_bias_strength = 0,
707 .futureModal = { 710 .futureModal = {
708 0, 0, 0, 0, 0, 0, 0, 0, 711 0, 0, 0, 0, 0, 0, 0,
709 }, 712 },
710 }, 713 },
711 .base_ext1 = { 714 .base_ext1 = {
@@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300_x113 = {
904 .thresh62 = 28, 907 .thresh62 = 28,
905 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 908 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
906 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 909 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
910 .xlna_bias_strength = 0,
907 .futureModal = { 911 .futureModal = {
908 0, 0, 0, 0, 0, 0, 0, 0, 912 0, 0, 0, 0, 0, 0, 0,
909 }, 913 },
910 }, 914 },
911 .base_ext2 = { 915 .base_ext2 = {
@@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300_h112 = {
1278 .thresh62 = 28, 1282 .thresh62 = 28,
1279 .papdRateMaskHt20 = LE32(0x0c80c080), 1283 .papdRateMaskHt20 = LE32(0x0c80c080),
1280 .papdRateMaskHt40 = LE32(0x0080c080), 1284 .papdRateMaskHt40 = LE32(0x0080c080),
1285 .xlna_bias_strength = 0,
1281 .futureModal = { 1286 .futureModal = {
1282 0, 0, 0, 0, 0, 0, 0, 0, 1287 0, 0, 0, 0, 0, 0, 0,
1283 }, 1288 },
1284 }, 1289 },
1285 .base_ext1 = { 1290 .base_ext1 = {
@@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300_h112 = {
1478 .thresh62 = 28, 1483 .thresh62 = 28,
1479 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 1484 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 1485 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1486 .xlna_bias_strength = 0,
1481 .futureModal = { 1487 .futureModal = {
1482 0, 0, 0, 0, 0, 0, 0, 0, 1488 0, 0, 0, 0, 0, 0, 0,
1483 }, 1489 },
1484 }, 1490 },
1485 .base_ext2 = { 1491 .base_ext2 = {
@@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300_x112 = {
1852 .thresh62 = 28, 1858 .thresh62 = 28,
1853 .papdRateMaskHt20 = LE32(0x0c80c080), 1859 .papdRateMaskHt20 = LE32(0x0c80c080),
1854 .papdRateMaskHt40 = LE32(0x0080c080), 1860 .papdRateMaskHt40 = LE32(0x0080c080),
1861 .xlna_bias_strength = 0,
1855 .futureModal = { 1862 .futureModal = {
1856 0, 0, 0, 0, 0, 0, 0, 0, 1863 0, 0, 0, 0, 0, 0, 0,
1857 }, 1864 },
1858 }, 1865 },
1859 .base_ext1 = { 1866 .base_ext1 = {
@@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300_x112 = {
2052 .thresh62 = 28, 2059 .thresh62 = 28,
2053 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2060 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2061 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2062 .xlna_bias_strength = 0,
2055 .futureModal = { 2063 .futureModal = {
2056 0, 0, 0, 0, 0, 0, 0, 0, 2064 0, 0, 0, 0, 0, 0, 0,
2057 }, 2065 },
2058 }, 2066 },
2059 .base_ext2 = { 2067 .base_ext2 = {
@@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300_h116 = {
2425 .thresh62 = 28, 2433 .thresh62 = 28,
2426 .papdRateMaskHt20 = LE32(0x0c80C080), 2434 .papdRateMaskHt20 = LE32(0x0c80C080),
2427 .papdRateMaskHt40 = LE32(0x0080C080), 2435 .papdRateMaskHt40 = LE32(0x0080C080),
2436 .xlna_bias_strength = 0,
2428 .futureModal = { 2437 .futureModal = {
2429 0, 0, 0, 0, 0, 0, 0, 0, 2438 0, 0, 0, 0, 0, 0, 0,
2430 }, 2439 },
2431 }, 2440 },
2432 .base_ext1 = { 2441 .base_ext1 = {
@@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300_h116 = {
2625 .thresh62 = 28, 2634 .thresh62 = 28,
2626 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2635 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2636 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2637 .xlna_bias_strength = 0,
2628 .futureModal = { 2638 .futureModal = {
2629 0, 0, 0, 0, 0, 0, 0, 0, 2639 0, 0, 0, 0, 0, 0, 0,
2630 }, 2640 },
2631 }, 2641 },
2632 .base_ext2 = { 2642 .base_ext2 = {
@@ -2971,14 +2981,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2971 return (pBase->txrxMask >> 4) & 0xf; 2981 return (pBase->txrxMask >> 4) & 0xf;
2972 case EEP_RX_MASK: 2982 case EEP_RX_MASK:
2973 return pBase->txrxMask & 0xf; 2983 return pBase->txrxMask & 0xf;
2974 case EEP_DRIVE_STRENGTH:
2975#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
2976 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2977 case EEP_INTERNAL_REGULATOR:
2978 /* Bit 4 is internal regulator flag */
2979 return (pBase->featureEnable & 0x10) >> 4;
2980 case EEP_SWREG:
2981 return le32_to_cpu(pBase->swreg);
2982 case EEP_PAPRD: 2984 case EEP_PAPRD:
2983 return !!(pBase->featureEnable & BIT(5)); 2985 return !!(pBase->featureEnable & BIT(5));
2984 case EEP_CHAIN_MASK_REDUCE: 2986 case EEP_CHAIN_MASK_REDUCE:
@@ -2989,8 +2991,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2989 return eep->modalHeader5G.antennaGain; 2991 return eep->modalHeader5G.antennaGain;
2990 case EEP_ANTENNA_GAIN_2G: 2992 case EEP_ANTENNA_GAIN_2G:
2991 return eep->modalHeader2G.antennaGain; 2993 return eep->modalHeader2G.antennaGain;
2992 case EEP_QUICK_DROP:
2993 return pBase->miscConfiguration & BIT(1);
2994 default: 2994 default:
2995 return 0; 2995 return 0;
2996 } 2996 }
@@ -3260,10 +3260,20 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3260 int it; 3260 int it;
3261 u16 checksum, mchecksum; 3261 u16 checksum, mchecksum;
3262 struct ath_common *common = ath9k_hw_common(ah); 3262 struct ath_common *common = ath9k_hw_common(ah);
3263 struct ar9300_eeprom *eep;
3263 eeprom_read_op read; 3264 eeprom_read_op read;
3264 3265
3265 if (ath9k_hw_use_flash(ah)) 3266 if (ath9k_hw_use_flash(ah)) {
3266 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size); 3267 u8 txrx;
3268
3269 ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3270
3271 /* check if eeprom contains valid data */
3272 eep = (struct ar9300_eeprom *) mptr;
3273 txrx = eep->baseEepHeader.txrxMask;
3274 if (txrx != 0 && txrx != 0xff)
3275 return 0;
3276 }
3267 3277
3268 word = kzalloc(2048, GFP_KERNEL); 3278 word = kzalloc(2048, GFP_KERNEL);
3269 if (!word) 3279 if (!word)
@@ -3493,19 +3503,20 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3493 return 0; 3503 return 0;
3494} 3504}
3495 3505
3496static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz) 3506static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3507 bool is2ghz)
3497{ 3508{
3498 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3509 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3499 3510
3500 if (is2ghz) 3511 if (is2ghz)
3501 return eep->modalHeader2G.xpaBiasLvl; 3512 return &eep->modalHeader2G;
3502 else 3513 else
3503 return eep->modalHeader5G.xpaBiasLvl; 3514 return &eep->modalHeader5G;
3504} 3515}
3505 3516
3506static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 3517static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3507{ 3518{
3508 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); 3519 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
3509 3520
3510 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3521 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3511 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3522 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
@@ -3521,57 +3532,26 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3521 } 3532 }
3522} 3533}
3523 3534
3524static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz) 3535static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
3525{ 3536{
3526 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3537 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
3527 __le16 val;
3528
3529 if (is_2ghz)
3530 val = eep->modalHeader2G.switchcomspdt;
3531 else
3532 val = eep->modalHeader5G.switchcomspdt;
3533 return le16_to_cpu(val);
3534} 3538}
3535 3539
3536 3540
3537static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) 3541static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3538{ 3542{
3539 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3543 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
3540 __le32 val;
3541
3542 if (is2ghz)
3543 val = eep->modalHeader2G.antCtrlCommon;
3544 else
3545 val = eep->modalHeader5G.antCtrlCommon;
3546 return le32_to_cpu(val);
3547} 3544}
3548 3545
3549static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) 3546static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3550{ 3547{
3551 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3548 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
3552 __le32 val;
3553
3554 if (is2ghz)
3555 val = eep->modalHeader2G.antCtrlCommon2;
3556 else
3557 val = eep->modalHeader5G.antCtrlCommon2;
3558 return le32_to_cpu(val);
3559} 3549}
3560 3550
3561static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, 3551static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3562 int chain,
3563 bool is2ghz) 3552 bool is2ghz)
3564{ 3553{
3565 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3554 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
3566 __le16 val = 0;
3567
3568 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3569 if (is2ghz)
3570 val = eep->modalHeader2G.antCtrlChain[chain];
3571 else
3572 val = eep->modalHeader5G.antCtrlChain[chain];
3573 }
3574
3575 return le16_to_cpu(val); 3555 return le16_to_cpu(val);
3576} 3556}
3577 3557
@@ -3681,11 +3661,12 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3681 3661
3682static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) 3662static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3683{ 3663{
3664 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3665 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3684 int drive_strength; 3666 int drive_strength;
3685 unsigned long reg; 3667 unsigned long reg;
3686 3668
3687 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH); 3669 drive_strength = pBase->miscConfiguration & BIT(0);
3688
3689 if (!drive_strength) 3670 if (!drive_strength)
3690 return; 3671 return;
3691 3672
@@ -3815,11 +3796,11 @@ static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3815 3796
3816void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 3797void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3817{ 3798{
3818 int internal_regulator = 3799 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3819 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); 3800 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3820 u32 reg_val; 3801 u32 reg_val;
3821 3802
3822 if (internal_regulator) { 3803 if (pBase->featureEnable & BIT(4)) {
3823 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3804 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3824 int reg_pmu_set; 3805 int reg_pmu_set;
3825 3806
@@ -3863,11 +3844,11 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3863 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3844 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3864 return; 3845 return;
3865 } else if (AR_SREV_9462(ah)) { 3846 } else if (AR_SREV_9462(ah)) {
3866 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3847 reg_val = le32_to_cpu(pBase->swreg);
3867 REG_WRITE(ah, AR_PHY_PMU1, reg_val); 3848 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3868 } else { 3849 } else {
3869 /* Internal regulator is ON. Write swreg register. */ 3850 /* Internal regulator is ON. Write swreg register. */
3870 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3851 reg_val = le32_to_cpu(pBase->swreg);
3871 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3852 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3872 REG_READ(ah, AR_RTC_REG_CONTROL1) & 3853 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3873 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); 3854 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
@@ -3909,6 +3890,9 @@ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3909 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3890 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3910 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; 3891 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3911 3892
3893 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3894 return;
3895
3912 if (eep->baseEepHeader.featureEnable & 0x40) { 3896 if (eep->baseEepHeader.featureEnable & 0x40) {
3913 tuning_caps_param &= 0x7f; 3897 tuning_caps_param &= 0x7f;
3914 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, 3898 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
@@ -3921,10 +3905,11 @@ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3921static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq) 3905static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3922{ 3906{
3923 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3907 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3924 int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP); 3908 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3909 int quick_drop;
3925 s32 t[3], f[3] = {5180, 5500, 5785}; 3910 s32 t[3], f[3] = {5180, 5500, 5785};
3926 3911
3927 if (!quick_drop) 3912 if (!(pBase->miscConfiguration & BIT(1)))
3928 return; 3913 return;
3929 3914
3930 if (freq < 4000) 3915 if (freq < 4000)
@@ -3938,13 +3923,11 @@ static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3938 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop); 3923 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3939} 3924}
3940 3925
3941static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq) 3926static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
3942{ 3927{
3943 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3944 u32 value; 3928 u32 value;
3945 3929
3946 value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff : 3930 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
3947 eep->modalHeader5G.txEndToXpaOff;
3948 3931
3949 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, 3932 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3950 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value); 3933 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
@@ -3952,19 +3935,63 @@ static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3952 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value); 3935 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3953} 3936}
3954 3937
3938static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
3939{
3940 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3941 u8 xpa_ctl;
3942
3943 if (!(eep->baseEepHeader.featureEnable & 0x80))
3944 return;
3945
3946 if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
3947 return;
3948
3949 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
3950 if (is2ghz)
3951 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3952 AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
3953 else
3954 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3955 AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
3956}
3957
3958static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
3959{
3960 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3961 u8 bias;
3962
3963 if (!(eep->baseEepHeader.featureEnable & 0x40))
3964 return;
3965
3966 if (!AR_SREV_9300(ah))
3967 return;
3968
3969 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
3970 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3971 bias & 0x3);
3972 bias >>= 2;
3973 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3974 bias & 0x3);
3975 bias >>= 2;
3976 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3977 bias & 0x3);
3978}
3979
3955static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, 3980static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3956 struct ath9k_channel *chan) 3981 struct ath9k_channel *chan)
3957{ 3982{
3958 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan)); 3983 bool is2ghz = IS_CHAN_2GHZ(chan);
3959 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); 3984 ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
3985 ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
3986 ar9003_hw_ant_ctrl_apply(ah, is2ghz);
3960 ar9003_hw_drive_strength_apply(ah); 3987 ar9003_hw_drive_strength_apply(ah);
3988 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
3961 ar9003_hw_atten_apply(ah, chan); 3989 ar9003_hw_atten_apply(ah, chan);
3962 ar9003_hw_quick_drop_apply(ah, chan->channel); 3990 ar9003_hw_quick_drop_apply(ah, chan->channel);
3963 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah)) 3991 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
3964 ar9003_hw_internal_regulator_apply(ah); 3992 ar9003_hw_internal_regulator_apply(ah);
3965 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3993 ar9003_hw_apply_tuning_caps(ah);
3966 ar9003_hw_apply_tuning_caps(ah); 3994 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
3967 ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
3968} 3995}
3969 3996
3970static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, 3997static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -5100,14 +5127,9 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5100 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ 5127 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5101} 5128}
5102 5129
5103u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz) 5130u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
5104{ 5131{
5105 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5132 return ar9003_modal_header(ah, is2ghz)->spurChans;
5106
5107 if (is_2ghz)
5108 return eep->modalHeader2G.spurChans;
5109 else
5110 return eep->modalHeader5G.spurChans;
5111} 5133}
5112 5134
5113unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, 5135unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 8396d150ce01..3a1ff55bceb9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
231 __le32 papdRateMaskHt20; 231 __le32 papdRateMaskHt20;
232 __le32 papdRateMaskHt40; 232 __le32 papdRateMaskHt40;
233 __le16 switchcomspdt; 233 __le16 switchcomspdt;
234 u8 futureModal[8]; 234 u8 xlna_bias_strength;
235 u8 futureModal[7];
235} __packed; 236} __packed;
236 237
237struct ar9300_cal_data_per_freq_op_loop { 238struct ar9300_cal_data_per_freq_op_loop {
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 41e88c660e48..1e8a4da5952f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
45 if (AR_SREV_9330_11(ah)) { 45 if (AR_SREV_9330_11(ah)) {
46 /* mac */ 46 /* mac */
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
48 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
49 ar9331_1p1_mac_core, 48 ar9331_1p1_mac_core);
50 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
51 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 49 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
52 ar9331_1p1_mac_postamble, 50 ar9331_1p1_mac_postamble);
53 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
54 51
55 /* bb */ 52 /* bb */
56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
57 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
58 ar9331_1p1_baseband_core, 54 ar9331_1p1_baseband_core);
59 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
60 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
61 ar9331_1p1_baseband_postamble, 56 ar9331_1p1_baseband_postamble);
62 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
63 57
64 /* radio */ 58 /* radio */
65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
66 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 59 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
67 ar9331_1p1_radio_core, 60 ar9331_1p1_radio_core);
68 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
69 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
70 61
71 /* soc */ 62 /* soc */
72 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
73 ar9331_1p1_soc_preamble, 64 ar9331_1p1_soc_preamble);
74 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
75 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
76 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
77 ar9331_1p1_soc_postamble, 66 ar9331_1p1_soc_postamble);
78 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
79 67
80 /* rx/tx gain */ 68 /* rx/tx gain */
81 INIT_INI_ARRAY(&ah->iniModesRxGain, 69 INIT_INI_ARRAY(&ah->iniModesRxGain,
82 ar9331_common_rx_gain_1p1, 70 ar9331_common_rx_gain_1p1);
83 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
84 INIT_INI_ARRAY(&ah->iniModesTxGain, 71 INIT_INI_ARRAY(&ah->iniModesTxGain,
85 ar9331_modes_lowest_ob_db_tx_gain_1p1, 72 ar9331_modes_lowest_ob_db_tx_gain_1p1);
86 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
87 5);
88 73
89 /* additional clock settings */ 74 /* additional clock settings */
90 if (ah->is_clk_25mhz) 75 if (ah->is_clk_25mhz)
91 INIT_INI_ARRAY(&ah->iniAdditional, 76 INIT_INI_ARRAY(&ah->iniAdditional,
92 ar9331_1p1_xtal_25M, 77 ar9331_1p1_xtal_25M);
93 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
94 else 78 else
95 INIT_INI_ARRAY(&ah->iniAdditional, 79 INIT_INI_ARRAY(&ah->iniAdditional,
96 ar9331_1p1_xtal_40M, 80 ar9331_1p1_xtal_40M);
97 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
98 } else if (AR_SREV_9330_12(ah)) { 81 } else if (AR_SREV_9330_12(ah)) {
99 /* mac */ 82 /* mac */
100 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
101 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 83 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
102 ar9331_1p2_mac_core, 84 ar9331_1p2_mac_core);
103 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
104 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
105 ar9331_1p2_mac_postamble, 86 ar9331_1p2_mac_postamble);
106 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
107 87
108 /* bb */ 88 /* bb */
109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
110 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 89 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
111 ar9331_1p2_baseband_core, 90 ar9331_1p2_baseband_core);
112 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
113 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
114 ar9331_1p2_baseband_postamble, 92 ar9331_1p2_baseband_postamble);
115 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
116 93
117 /* radio */ 94 /* radio */
118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
119 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 95 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
120 ar9331_1p2_radio_core, 96 ar9331_1p2_radio_core);
121 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
122 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
123 97
124 /* soc */ 98 /* soc */
125 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 99 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
126 ar9331_1p2_soc_preamble, 100 ar9331_1p2_soc_preamble);
127 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
128 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
129 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
130 ar9331_1p2_soc_postamble, 102 ar9331_1p2_soc_postamble);
131 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
132 103
133 /* rx/tx gain */ 104 /* rx/tx gain */
134 INIT_INI_ARRAY(&ah->iniModesRxGain, 105 INIT_INI_ARRAY(&ah->iniModesRxGain,
135 ar9331_common_rx_gain_1p2, 106 ar9331_common_rx_gain_1p2);
136 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
137 INIT_INI_ARRAY(&ah->iniModesTxGain, 107 INIT_INI_ARRAY(&ah->iniModesTxGain,
138 ar9331_modes_lowest_ob_db_tx_gain_1p2, 108 ar9331_modes_lowest_ob_db_tx_gain_1p2);
139 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
140 5);
141 109
142 /* additional clock settings */ 110 /* additional clock settings */
143 if (ah->is_clk_25mhz) 111 if (ah->is_clk_25mhz)
144 INIT_INI_ARRAY(&ah->iniAdditional, 112 INIT_INI_ARRAY(&ah->iniAdditional,
145 ar9331_1p2_xtal_25M, 113 ar9331_1p2_xtal_25M);
146 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
147 else 114 else
148 INIT_INI_ARRAY(&ah->iniAdditional, 115 INIT_INI_ARRAY(&ah->iniAdditional,
149 ar9331_1p2_xtal_40M, 116 ar9331_1p2_xtal_40M);
150 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
151 } else if (AR_SREV_9340(ah)) { 117 } else if (AR_SREV_9340(ah)) {
152 /* mac */ 118 /* mac */
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
154 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 119 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
155 ar9340_1p0_mac_core, 120 ar9340_1p0_mac_core);
156 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
157 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 121 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
158 ar9340_1p0_mac_postamble, 122 ar9340_1p0_mac_postamble);
159 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
160 123
161 /* bb */ 124 /* bb */
162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 125 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
164 ar9340_1p0_baseband_core, 126 ar9340_1p0_baseband_core);
165 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
166 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 127 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
167 ar9340_1p0_baseband_postamble, 128 ar9340_1p0_baseband_postamble);
168 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
169 129
170 /* radio */ 130 /* radio */
171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
172 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 131 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
173 ar9340_1p0_radio_core, 132 ar9340_1p0_radio_core);
174 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
175 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 133 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
176 ar9340_1p0_radio_postamble, 134 ar9340_1p0_radio_postamble);
177 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
178 135
179 /* soc */ 136 /* soc */
180 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 137 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
181 ar9340_1p0_soc_preamble, 138 ar9340_1p0_soc_preamble);
182 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
183 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
184 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 139 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
185 ar9340_1p0_soc_postamble, 140 ar9340_1p0_soc_postamble);
186 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
187 141
188 /* rx/tx gain */ 142 /* rx/tx gain */
189 INIT_INI_ARRAY(&ah->iniModesRxGain, 143 INIT_INI_ARRAY(&ah->iniModesRxGain,
190 ar9340Common_wo_xlna_rx_gain_table_1p0, 144 ar9340Common_wo_xlna_rx_gain_table_1p0);
191 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
192 5);
193 INIT_INI_ARRAY(&ah->iniModesTxGain, 145 INIT_INI_ARRAY(&ah->iniModesTxGain,
194 ar9340Modes_high_ob_db_tx_gain_table_1p0, 146 ar9340Modes_high_ob_db_tx_gain_table_1p0);
195 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
196 5);
197 147
198 INIT_INI_ARRAY(&ah->iniModesFastClock, 148 INIT_INI_ARRAY(&ah->iniModesFastClock,
199 ar9340Modes_fast_clock_1p0, 149 ar9340Modes_fast_clock_1p0);
200 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
201 3);
202 150
203 if (!ah->is_clk_25mhz) 151 if (!ah->is_clk_25mhz)
204 INIT_INI_ARRAY(&ah->iniAdditional, 152 INIT_INI_ARRAY(&ah->iniAdditional,
205 ar9340_1p0_radio_core_40M, 153 ar9340_1p0_radio_core_40M);
206 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
207 2);
208 } else if (AR_SREV_9485_11(ah)) { 154 } else if (AR_SREV_9485_11(ah)) {
209 /* mac */ 155 /* mac */
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
211 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 156 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
212 ar9485_1_1_mac_core, 157 ar9485_1_1_mac_core);
213 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
214 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 158 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
215 ar9485_1_1_mac_postamble, 159 ar9485_1_1_mac_postamble);
216 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
217 160
218 /* bb */ 161 /* bb */
219 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1, 162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
220 ARRAY_SIZE(ar9485_1_1), 2);
221 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
222 ar9485_1_1_baseband_core, 164 ar9485_1_1_baseband_core);
223 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
224 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
225 ar9485_1_1_baseband_postamble, 166 ar9485_1_1_baseband_postamble);
226 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
227 167
228 /* radio */ 168 /* radio */
229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
230 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 169 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
231 ar9485_1_1_radio_core, 170 ar9485_1_1_radio_core);
232 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
233 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
234 ar9485_1_1_radio_postamble, 172 ar9485_1_1_radio_postamble);
235 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
236 173
237 /* soc */ 174 /* soc */
238 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 175 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
239 ar9485_1_1_soc_preamble, 176 ar9485_1_1_soc_preamble);
240 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
241 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
242 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
243 177
244 /* rx/tx gain */ 178 /* rx/tx gain */
245 INIT_INI_ARRAY(&ah->iniModesRxGain, 179 INIT_INI_ARRAY(&ah->iniModesRxGain,
246 ar9485Common_wo_xlna_rx_gain_1_1, 180 ar9485Common_wo_xlna_rx_gain_1_1);
247 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
248 INIT_INI_ARRAY(&ah->iniModesTxGain, 181 INIT_INI_ARRAY(&ah->iniModesTxGain,
249 ar9485_modes_lowest_ob_db_tx_gain_1_1, 182 ar9485_modes_lowest_ob_db_tx_gain_1_1);
250 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
251 5);
252 183
253 /* Load PCIE SERDES settings from INI */ 184 /* Load PCIE SERDES settings from INI */
254 185
255 /* Awake Setting */ 186 /* Awake Setting */
256 187
257 INIT_INI_ARRAY(&ah->iniPcieSerdes, 188 INIT_INI_ARRAY(&ah->iniPcieSerdes,
258 ar9485_1_1_pcie_phy_clkreq_disable_L1, 189 ar9485_1_1_pcie_phy_clkreq_disable_L1);
259 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
260 2);
261 190
262 /* Sleep Setting */ 191 /* Sleep Setting */
263 192
264 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 193 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
265 ar9485_1_1_pcie_phy_clkreq_disable_L1, 194 ar9485_1_1_pcie_phy_clkreq_disable_L1);
266 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
267 2);
268 } else if (AR_SREV_9462_20(ah)) { 195 } else if (AR_SREV_9462_20(ah)) {
269 196
270 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 197 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
272 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
273 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 198 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
274 ar9462_2p0_mac_postamble, 199 ar9462_2p0_mac_postamble);
275 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
276 200
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
278 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 201 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
279 ar9462_2p0_baseband_core, 202 ar9462_2p0_baseband_core);
280 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 203 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
282 ar9462_2p0_baseband_postamble, 204 ar9462_2p0_baseband_postamble);
283 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
284 205
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 206 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
287 ar9462_2p0_radio_core, 207 ar9462_2p0_radio_core);
288 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 208 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
290 ar9462_2p0_radio_postamble, 209 ar9462_2p0_radio_postamble);
291 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
292 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 210 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
293 ar9462_2p0_radio_postamble_sys2ant, 211 ar9462_2p0_radio_postamble_sys2ant);
294 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
295 5);
296 212
297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 213 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
298 ar9462_2p0_soc_preamble, 214 ar9462_2p0_soc_preamble);
299 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
300 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
301 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 215 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
302 ar9462_2p0_soc_postamble, 216 ar9462_2p0_soc_postamble);
303 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
304 217
305 INIT_INI_ARRAY(&ah->iniModesRxGain, 218 INIT_INI_ARRAY(&ah->iniModesRxGain,
306 ar9462_common_rx_gain_table_2p0, 219 ar9462_common_rx_gain_table_2p0);
307 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
308 220
309 /* Awake -> Sleep Setting */ 221 /* Awake -> Sleep Setting */
310 INIT_INI_ARRAY(&ah->iniPcieSerdes, 222 INIT_INI_ARRAY(&ah->iniPcieSerdes,
311 PCIE_PLL_ON_CREQ_DIS_L1_2P0, 223 PCIE_PLL_ON_CREQ_DIS_L1_2P0);
312 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
313 2);
314 /* Sleep -> Awake Setting */ 224 /* Sleep -> Awake Setting */
315 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 225 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
316 PCIE_PLL_ON_CREQ_DIS_L1_2P0, 226 PCIE_PLL_ON_CREQ_DIS_L1_2P0);
317 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
318 2);
319 227
320 /* Fast clock modal settings */ 228 /* Fast clock modal settings */
321 INIT_INI_ARRAY(&ah->iniModesFastClock, 229 INIT_INI_ARRAY(&ah->iniModesFastClock,
322 ar9462_modes_fast_clock_2p0, 230 ar9462_modes_fast_clock_2p0);
323 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
324 231
325 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
326 AR9462_BB_CTX_COEFJ(2p0), 233 AR9462_BB_CTX_COEFJ(2p0));
327 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
328 234
329 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ, 235 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
330 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
331 } else if (AR_SREV_9550(ah)) { 236 } else if (AR_SREV_9550(ah)) {
332 /* mac */ 237 /* mac */
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 238 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
335 ar955x_1p0_mac_core, 239 ar955x_1p0_mac_core);
336 ARRAY_SIZE(ar955x_1p0_mac_core), 2);
337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 240 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
338 ar955x_1p0_mac_postamble, 241 ar955x_1p0_mac_postamble);
339 ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
340 242
341 /* bb */ 243 /* bb */
342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 244 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
344 ar955x_1p0_baseband_core, 245 ar955x_1p0_baseband_core);
345 ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
346 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 246 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
347 ar955x_1p0_baseband_postamble, 247 ar955x_1p0_baseband_postamble);
348 ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
349 248
350 /* radio */ 249 /* radio */
351 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
352 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 250 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
353 ar955x_1p0_radio_core, 251 ar955x_1p0_radio_core);
354 ARRAY_SIZE(ar955x_1p0_radio_core), 2);
355 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 252 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
356 ar955x_1p0_radio_postamble, 253 ar955x_1p0_radio_postamble);
357 ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
358 254
359 /* soc */ 255 /* soc */
360 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 256 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
361 ar955x_1p0_soc_preamble, 257 ar955x_1p0_soc_preamble);
362 ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
363 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
364 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 258 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
365 ar955x_1p0_soc_postamble, 259 ar955x_1p0_soc_postamble);
366 ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
367 260
368 /* rx/tx gain */ 261 /* rx/tx gain */
369 INIT_INI_ARRAY(&ah->iniModesRxGain, 262 INIT_INI_ARRAY(&ah->iniModesRxGain,
370 ar955x_1p0_common_wo_xlna_rx_gain_table, 263 ar955x_1p0_common_wo_xlna_rx_gain_table);
371 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
372 2);
373 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 264 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
374 ar955x_1p0_common_wo_xlna_rx_gain_bounds, 265 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
375 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
376 5);
377 INIT_INI_ARRAY(&ah->iniModesTxGain, 266 INIT_INI_ARRAY(&ah->iniModesTxGain,
378 ar955x_1p0_modes_xpa_tx_gain_table, 267 ar955x_1p0_modes_xpa_tx_gain_table);
379 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
380 9);
381 268
382 /* Fast clock modal settings */ 269 /* Fast clock modal settings */
383 INIT_INI_ARRAY(&ah->iniModesFastClock, 270 INIT_INI_ARRAY(&ah->iniModesFastClock,
384 ar955x_1p0_modes_fast_clock, 271 ar955x_1p0_modes_fast_clock);
385 ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
386 } else if (AR_SREV_9580(ah)) { 272 } else if (AR_SREV_9580(ah)) {
387 /* mac */ 273 /* mac */
388 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
389 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 274 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
390 ar9580_1p0_mac_core, 275 ar9580_1p0_mac_core);
391 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
392 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 276 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
393 ar9580_1p0_mac_postamble, 277 ar9580_1p0_mac_postamble);
394 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
395 278
396 /* bb */ 279 /* bb */
397 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
398 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 280 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
399 ar9580_1p0_baseband_core, 281 ar9580_1p0_baseband_core);
400 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
401 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 282 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
402 ar9580_1p0_baseband_postamble, 283 ar9580_1p0_baseband_postamble);
403 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
404 284
405 /* radio */ 285 /* radio */
406 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
407 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
408 ar9580_1p0_radio_core, 287 ar9580_1p0_radio_core);
409 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
410 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 288 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
411 ar9580_1p0_radio_postamble, 289 ar9580_1p0_radio_postamble);
412 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
413 290
414 /* soc */ 291 /* soc */
415 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 292 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
416 ar9580_1p0_soc_preamble, 293 ar9580_1p0_soc_preamble);
417 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
418 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
419 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 294 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
420 ar9580_1p0_soc_postamble, 295 ar9580_1p0_soc_postamble);
421 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
422 296
423 /* rx/tx gain */ 297 /* rx/tx gain */
424 INIT_INI_ARRAY(&ah->iniModesRxGain, 298 INIT_INI_ARRAY(&ah->iniModesRxGain,
425 ar9580_1p0_rx_gain_table, 299 ar9580_1p0_rx_gain_table);
426 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
427 INIT_INI_ARRAY(&ah->iniModesTxGain, 300 INIT_INI_ARRAY(&ah->iniModesTxGain,
428 ar9580_1p0_low_ob_db_tx_gain_table, 301 ar9580_1p0_low_ob_db_tx_gain_table);
429 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
430 5);
431 302
432 INIT_INI_ARRAY(&ah->iniModesFastClock, 303 INIT_INI_ARRAY(&ah->iniModesFastClock,
433 ar9580_1p0_modes_fast_clock, 304 ar9580_1p0_modes_fast_clock);
434 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
435 3);
436 } else { 305 } else {
437 /* mac */ 306 /* mac */
438 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
439 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 307 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
440 ar9300_2p2_mac_core, 308 ar9300_2p2_mac_core);
441 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
442 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 309 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
443 ar9300_2p2_mac_postamble, 310 ar9300_2p2_mac_postamble);
444 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
445 311
446 /* bb */ 312 /* bb */
447 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
448 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 313 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
449 ar9300_2p2_baseband_core, 314 ar9300_2p2_baseband_core);
450 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
451 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 315 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
452 ar9300_2p2_baseband_postamble, 316 ar9300_2p2_baseband_postamble);
453 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
454 317
455 /* radio */ 318 /* radio */
456 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
457 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 319 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
458 ar9300_2p2_radio_core, 320 ar9300_2p2_radio_core);
459 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
460 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 321 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
461 ar9300_2p2_radio_postamble, 322 ar9300_2p2_radio_postamble);
462 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
463 323
464 /* soc */ 324 /* soc */
465 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 325 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
466 ar9300_2p2_soc_preamble, 326 ar9300_2p2_soc_preamble);
467 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
469 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 327 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
470 ar9300_2p2_soc_postamble, 328 ar9300_2p2_soc_postamble);
471 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
472 329
473 /* rx/tx gain */ 330 /* rx/tx gain */
474 INIT_INI_ARRAY(&ah->iniModesRxGain, 331 INIT_INI_ARRAY(&ah->iniModesRxGain,
475 ar9300Common_rx_gain_table_2p2, 332 ar9300Common_rx_gain_table_2p2);
476 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
477 INIT_INI_ARRAY(&ah->iniModesTxGain, 333 INIT_INI_ARRAY(&ah->iniModesTxGain,
478 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 334 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
479 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
480 5);
481 335
482 /* Load PCIE SERDES settings from INI */ 336 /* Load PCIE SERDES settings from INI */
483 337
484 /* Awake Setting */ 338 /* Awake Setting */
485 339
486 INIT_INI_ARRAY(&ah->iniPcieSerdes, 340 INIT_INI_ARRAY(&ah->iniPcieSerdes,
487 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 341 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
488 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
489 2);
490 342
491 /* Sleep Setting */ 343 /* Sleep Setting */
492 344
493 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 345 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
494 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 346 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
495 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
496 2);
497 347
498 /* Fast clock modal settings */ 348 /* Fast clock modal settings */
499 INIT_INI_ARRAY(&ah->iniModesFastClock, 349 INIT_INI_ARRAY(&ah->iniModesFastClock,
500 ar9300Modes_fast_clock_2p2, 350 ar9300Modes_fast_clock_2p2);
501 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
502 3);
503 } 351 }
504} 352}
505 353
@@ -507,156 +355,110 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
507{ 355{
508 if (AR_SREV_9330_12(ah)) 356 if (AR_SREV_9330_12(ah))
509 INIT_INI_ARRAY(&ah->iniModesTxGain, 357 INIT_INI_ARRAY(&ah->iniModesTxGain,
510 ar9331_modes_lowest_ob_db_tx_gain_1p2, 358 ar9331_modes_lowest_ob_db_tx_gain_1p2);
511 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
512 5);
513 else if (AR_SREV_9330_11(ah)) 359 else if (AR_SREV_9330_11(ah))
514 INIT_INI_ARRAY(&ah->iniModesTxGain, 360 INIT_INI_ARRAY(&ah->iniModesTxGain,
515 ar9331_modes_lowest_ob_db_tx_gain_1p1, 361 ar9331_modes_lowest_ob_db_tx_gain_1p1);
516 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
517 5);
518 else if (AR_SREV_9340(ah)) 362 else if (AR_SREV_9340(ah))
519 INIT_INI_ARRAY(&ah->iniModesTxGain, 363 INIT_INI_ARRAY(&ah->iniModesTxGain,
520 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 364 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
521 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
522 5);
523 else if (AR_SREV_9485_11(ah)) 365 else if (AR_SREV_9485_11(ah))
524 INIT_INI_ARRAY(&ah->iniModesTxGain, 366 INIT_INI_ARRAY(&ah->iniModesTxGain,
525 ar9485_modes_lowest_ob_db_tx_gain_1_1, 367 ar9485_modes_lowest_ob_db_tx_gain_1_1);
526 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
527 5);
528 else if (AR_SREV_9550(ah)) 368 else if (AR_SREV_9550(ah))
529 INIT_INI_ARRAY(&ah->iniModesTxGain, 369 INIT_INI_ARRAY(&ah->iniModesTxGain,
530 ar955x_1p0_modes_xpa_tx_gain_table, 370 ar955x_1p0_modes_xpa_tx_gain_table);
531 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
532 9);
533 else if (AR_SREV_9580(ah)) 371 else if (AR_SREV_9580(ah))
534 INIT_INI_ARRAY(&ah->iniModesTxGain, 372 INIT_INI_ARRAY(&ah->iniModesTxGain,
535 ar9580_1p0_lowest_ob_db_tx_gain_table, 373 ar9580_1p0_lowest_ob_db_tx_gain_table);
536 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
537 5);
538 else if (AR_SREV_9462_20(ah)) 374 else if (AR_SREV_9462_20(ah))
539 INIT_INI_ARRAY(&ah->iniModesTxGain, 375 INIT_INI_ARRAY(&ah->iniModesTxGain,
540 ar9462_modes_low_ob_db_tx_gain_table_2p0, 376 ar9462_modes_low_ob_db_tx_gain_table_2p0);
541 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
542 5);
543 else 377 else
544 INIT_INI_ARRAY(&ah->iniModesTxGain, 378 INIT_INI_ARRAY(&ah->iniModesTxGain,
545 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 379 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
546 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
547 5);
548} 380}
549 381
550static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 382static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
551{ 383{
552 if (AR_SREV_9330_12(ah)) 384 if (AR_SREV_9330_12(ah))
553 INIT_INI_ARRAY(&ah->iniModesTxGain, 385 INIT_INI_ARRAY(&ah->iniModesTxGain,
554 ar9331_modes_high_ob_db_tx_gain_1p2, 386 ar9331_modes_high_ob_db_tx_gain_1p2);
555 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
556 5);
557 else if (AR_SREV_9330_11(ah)) 387 else if (AR_SREV_9330_11(ah))
558 INIT_INI_ARRAY(&ah->iniModesTxGain, 388 INIT_INI_ARRAY(&ah->iniModesTxGain,
559 ar9331_modes_high_ob_db_tx_gain_1p1, 389 ar9331_modes_high_ob_db_tx_gain_1p1);
560 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
561 5);
562 else if (AR_SREV_9340(ah)) 390 else if (AR_SREV_9340(ah))
563 INIT_INI_ARRAY(&ah->iniModesTxGain, 391 INIT_INI_ARRAY(&ah->iniModesTxGain,
564 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 392 ar9340Modes_high_ob_db_tx_gain_table_1p0);
565 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
566 5);
567 else if (AR_SREV_9485_11(ah)) 393 else if (AR_SREV_9485_11(ah))
568 INIT_INI_ARRAY(&ah->iniModesTxGain, 394 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9485Modes_high_ob_db_tx_gain_1_1, 395 ar9485Modes_high_ob_db_tx_gain_1_1);
570 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
571 5);
572 else if (AR_SREV_9580(ah)) 396 else if (AR_SREV_9580(ah))
573 INIT_INI_ARRAY(&ah->iniModesTxGain, 397 INIT_INI_ARRAY(&ah->iniModesTxGain,
574 ar9580_1p0_high_ob_db_tx_gain_table, 398 ar9580_1p0_high_ob_db_tx_gain_table);
575 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
576 5);
577 else if (AR_SREV_9550(ah)) 399 else if (AR_SREV_9550(ah))
578 INIT_INI_ARRAY(&ah->iniModesTxGain, 400 INIT_INI_ARRAY(&ah->iniModesTxGain,
579 ar955x_1p0_modes_no_xpa_tx_gain_table, 401 ar955x_1p0_modes_no_xpa_tx_gain_table);
580 ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
581 9);
582 else if (AR_SREV_9462_20(ah)) 402 else if (AR_SREV_9462_20(ah))
583 INIT_INI_ARRAY(&ah->iniModesTxGain, 403 INIT_INI_ARRAY(&ah->iniModesTxGain,
584 ar9462_modes_high_ob_db_tx_gain_table_2p0, 404 ar9462_modes_high_ob_db_tx_gain_table_2p0);
585 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
586 5);
587 else 405 else
588 INIT_INI_ARRAY(&ah->iniModesTxGain, 406 INIT_INI_ARRAY(&ah->iniModesTxGain,
589 ar9300Modes_high_ob_db_tx_gain_table_2p2, 407 ar9300Modes_high_ob_db_tx_gain_table_2p2);
590 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
591 5);
592} 408}
593 409
594static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 410static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
595{ 411{
596 if (AR_SREV_9330_12(ah)) 412 if (AR_SREV_9330_12(ah))
597 INIT_INI_ARRAY(&ah->iniModesTxGain, 413 INIT_INI_ARRAY(&ah->iniModesTxGain,
598 ar9331_modes_low_ob_db_tx_gain_1p2, 414 ar9331_modes_low_ob_db_tx_gain_1p2);
599 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
600 5);
601 else if (AR_SREV_9330_11(ah)) 415 else if (AR_SREV_9330_11(ah))
602 INIT_INI_ARRAY(&ah->iniModesTxGain, 416 INIT_INI_ARRAY(&ah->iniModesTxGain,
603 ar9331_modes_low_ob_db_tx_gain_1p1, 417 ar9331_modes_low_ob_db_tx_gain_1p1);
604 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
605 5);
606 else if (AR_SREV_9340(ah)) 418 else if (AR_SREV_9340(ah))
607 INIT_INI_ARRAY(&ah->iniModesTxGain, 419 INIT_INI_ARRAY(&ah->iniModesTxGain,
608 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 420 ar9340Modes_low_ob_db_tx_gain_table_1p0);
609 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
610 5);
611 else if (AR_SREV_9485_11(ah)) 421 else if (AR_SREV_9485_11(ah))
612 INIT_INI_ARRAY(&ah->iniModesTxGain, 422 INIT_INI_ARRAY(&ah->iniModesTxGain,
613 ar9485Modes_low_ob_db_tx_gain_1_1, 423 ar9485Modes_low_ob_db_tx_gain_1_1);
614 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
615 5);
616 else if (AR_SREV_9580(ah)) 424 else if (AR_SREV_9580(ah))
617 INIT_INI_ARRAY(&ah->iniModesTxGain, 425 INIT_INI_ARRAY(&ah->iniModesTxGain,
618 ar9580_1p0_low_ob_db_tx_gain_table, 426 ar9580_1p0_low_ob_db_tx_gain_table);
619 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
620 5);
621 else 427 else
622 INIT_INI_ARRAY(&ah->iniModesTxGain, 428 INIT_INI_ARRAY(&ah->iniModesTxGain,
623 ar9300Modes_low_ob_db_tx_gain_table_2p2, 429 ar9300Modes_low_ob_db_tx_gain_table_2p2);
624 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
625 5);
626} 430}
627 431
628static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 432static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
629{ 433{
630 if (AR_SREV_9330_12(ah)) 434 if (AR_SREV_9330_12(ah))
631 INIT_INI_ARRAY(&ah->iniModesTxGain, 435 INIT_INI_ARRAY(&ah->iniModesTxGain,
632 ar9331_modes_high_power_tx_gain_1p2, 436 ar9331_modes_high_power_tx_gain_1p2);
633 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
634 5);
635 else if (AR_SREV_9330_11(ah)) 437 else if (AR_SREV_9330_11(ah))
636 INIT_INI_ARRAY(&ah->iniModesTxGain, 438 INIT_INI_ARRAY(&ah->iniModesTxGain,
637 ar9331_modes_high_power_tx_gain_1p1, 439 ar9331_modes_high_power_tx_gain_1p1);
638 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
639 5);
640 else if (AR_SREV_9340(ah)) 440 else if (AR_SREV_9340(ah))
641 INIT_INI_ARRAY(&ah->iniModesTxGain, 441 INIT_INI_ARRAY(&ah->iniModesTxGain,
642 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 442 ar9340Modes_high_power_tx_gain_table_1p0);
643 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
644 5);
645 else if (AR_SREV_9485_11(ah)) 443 else if (AR_SREV_9485_11(ah))
646 INIT_INI_ARRAY(&ah->iniModesTxGain, 444 INIT_INI_ARRAY(&ah->iniModesTxGain,
647 ar9485Modes_high_power_tx_gain_1_1, 445 ar9485Modes_high_power_tx_gain_1_1);
648 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
649 5);
650 else if (AR_SREV_9580(ah)) 446 else if (AR_SREV_9580(ah))
651 INIT_INI_ARRAY(&ah->iniModesTxGain, 447 INIT_INI_ARRAY(&ah->iniModesTxGain,
652 ar9580_1p0_high_power_tx_gain_table, 448 ar9580_1p0_high_power_tx_gain_table);
653 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
654 5);
655 else 449 else
656 INIT_INI_ARRAY(&ah->iniModesTxGain, 450 INIT_INI_ARRAY(&ah->iniModesTxGain,
657 ar9300Modes_high_power_tx_gain_table_2p2, 451 ar9300Modes_high_power_tx_gain_table_2p2);
658 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2), 452}
659 5); 453
454static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
455{
456 if (AR_SREV_9340(ah))
457 INIT_INI_ARRAY(&ah->iniModesTxGain,
458 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
459 else if (AR_SREV_9580(ah))
460 INIT_INI_ARRAY(&ah->iniModesTxGain,
461 ar9580_1p0_mixed_ob_db_tx_gain_table);
660} 462}
661 463
662static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 464static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
@@ -675,6 +477,9 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
675 case 3: 477 case 3:
676 ar9003_tx_gain_table_mode3(ah); 478 ar9003_tx_gain_table_mode3(ah);
677 break; 479 break;
480 case 4:
481 ar9003_tx_gain_table_mode4(ah);
482 break;
678 } 483 }
679} 484}
680 485
@@ -682,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
682{ 487{
683 if (AR_SREV_9330_12(ah)) 488 if (AR_SREV_9330_12(ah))
684 INIT_INI_ARRAY(&ah->iniModesRxGain, 489 INIT_INI_ARRAY(&ah->iniModesRxGain,
685 ar9331_common_rx_gain_1p2, 490 ar9331_common_rx_gain_1p2);
686 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
687 2);
688 else if (AR_SREV_9330_11(ah)) 491 else if (AR_SREV_9330_11(ah))
689 INIT_INI_ARRAY(&ah->iniModesRxGain, 492 INIT_INI_ARRAY(&ah->iniModesRxGain,
690 ar9331_common_rx_gain_1p1, 493 ar9331_common_rx_gain_1p1);
691 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
692 2);
693 else if (AR_SREV_9340(ah)) 494 else if (AR_SREV_9340(ah))
694 INIT_INI_ARRAY(&ah->iniModesRxGain, 495 INIT_INI_ARRAY(&ah->iniModesRxGain,
695 ar9340Common_rx_gain_table_1p0, 496 ar9340Common_rx_gain_table_1p0);
696 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
697 2);
698 else if (AR_SREV_9485_11(ah)) 497 else if (AR_SREV_9485_11(ah))
699 INIT_INI_ARRAY(&ah->iniModesRxGain, 498 INIT_INI_ARRAY(&ah->iniModesRxGain,
700 ar9485Common_wo_xlna_rx_gain_1_1, 499 ar9485Common_wo_xlna_rx_gain_1_1);
701 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
702 2);
703 else if (AR_SREV_9550(ah)) { 500 else if (AR_SREV_9550(ah)) {
704 INIT_INI_ARRAY(&ah->iniModesRxGain, 501 INIT_INI_ARRAY(&ah->iniModesRxGain,
705 ar955x_1p0_common_rx_gain_table, 502 ar955x_1p0_common_rx_gain_table);
706 ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
707 2);
708 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 503 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
709 ar955x_1p0_common_rx_gain_bounds, 504 ar955x_1p0_common_rx_gain_bounds);
710 ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
711 5);
712 } else if (AR_SREV_9580(ah)) 505 } else if (AR_SREV_9580(ah))
713 INIT_INI_ARRAY(&ah->iniModesRxGain, 506 INIT_INI_ARRAY(&ah->iniModesRxGain,
714 ar9580_1p0_rx_gain_table, 507 ar9580_1p0_rx_gain_table);
715 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
716 2);
717 else if (AR_SREV_9462_20(ah)) 508 else if (AR_SREV_9462_20(ah))
718 INIT_INI_ARRAY(&ah->iniModesRxGain, 509 INIT_INI_ARRAY(&ah->iniModesRxGain,
719 ar9462_common_rx_gain_table_2p0, 510 ar9462_common_rx_gain_table_2p0);
720 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
721 2);
722 else 511 else
723 INIT_INI_ARRAY(&ah->iniModesRxGain, 512 INIT_INI_ARRAY(&ah->iniModesRxGain,
724 ar9300Common_rx_gain_table_2p2, 513 ar9300Common_rx_gain_table_2p2);
725 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
726 2);
727} 514}
728 515
729static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 516static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
730{ 517{
731 if (AR_SREV_9330_12(ah)) 518 if (AR_SREV_9330_12(ah))
732 INIT_INI_ARRAY(&ah->iniModesRxGain, 519 INIT_INI_ARRAY(&ah->iniModesRxGain,
733 ar9331_common_wo_xlna_rx_gain_1p2, 520 ar9331_common_wo_xlna_rx_gain_1p2);
734 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
735 2);
736 else if (AR_SREV_9330_11(ah)) 521 else if (AR_SREV_9330_11(ah))
737 INIT_INI_ARRAY(&ah->iniModesRxGain, 522 INIT_INI_ARRAY(&ah->iniModesRxGain,
738 ar9331_common_wo_xlna_rx_gain_1p1, 523 ar9331_common_wo_xlna_rx_gain_1p1);
739 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
740 2);
741 else if (AR_SREV_9340(ah)) 524 else if (AR_SREV_9340(ah))
742 INIT_INI_ARRAY(&ah->iniModesRxGain, 525 INIT_INI_ARRAY(&ah->iniModesRxGain,
743 ar9340Common_wo_xlna_rx_gain_table_1p0, 526 ar9340Common_wo_xlna_rx_gain_table_1p0);
744 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
745 2);
746 else if (AR_SREV_9485_11(ah)) 527 else if (AR_SREV_9485_11(ah))
747 INIT_INI_ARRAY(&ah->iniModesRxGain, 528 INIT_INI_ARRAY(&ah->iniModesRxGain,
748 ar9485Common_wo_xlna_rx_gain_1_1, 529 ar9485Common_wo_xlna_rx_gain_1_1);
749 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
750 2);
751 else if (AR_SREV_9462_20(ah)) 530 else if (AR_SREV_9462_20(ah))
752 INIT_INI_ARRAY(&ah->iniModesRxGain, 531 INIT_INI_ARRAY(&ah->iniModesRxGain,
753 ar9462_common_wo_xlna_rx_gain_table_2p0, 532 ar9462_common_wo_xlna_rx_gain_table_2p0);
754 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
755 2);
756 else if (AR_SREV_9550(ah)) { 533 else if (AR_SREV_9550(ah)) {
757 INIT_INI_ARRAY(&ah->iniModesRxGain, 534 INIT_INI_ARRAY(&ah->iniModesRxGain,
758 ar955x_1p0_common_wo_xlna_rx_gain_table, 535 ar955x_1p0_common_wo_xlna_rx_gain_table);
759 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
760 2);
761 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 536 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
762 ar955x_1p0_common_wo_xlna_rx_gain_bounds, 537 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
763 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
764 5);
765 } else if (AR_SREV_9580(ah)) 538 } else if (AR_SREV_9580(ah))
766 INIT_INI_ARRAY(&ah->iniModesRxGain, 539 INIT_INI_ARRAY(&ah->iniModesRxGain,
767 ar9580_1p0_wo_xlna_rx_gain_table, 540 ar9580_1p0_wo_xlna_rx_gain_table);
768 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
769 2);
770 else 541 else
771 INIT_INI_ARRAY(&ah->iniModesRxGain, 542 INIT_INI_ARRAY(&ah->iniModesRxGain,
772 ar9300Common_wo_xlna_rx_gain_table_2p2, 543 ar9300Common_wo_xlna_rx_gain_table_2p2);
773 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
774 2);
775} 544}
776 545
777static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 546static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
778{ 547{
779 if (AR_SREV_9462_20(ah)) 548 if (AR_SREV_9462_20(ah))
780 INIT_INI_ARRAY(&ah->iniModesRxGain, 549 INIT_INI_ARRAY(&ah->iniModesRxGain,
781 ar9462_common_mixed_rx_gain_table_2p0, 550 ar9462_common_mixed_rx_gain_table_2p0);
782 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
783} 551}
784 552
785static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 553static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index d2346dbad6cd..e476f9f92ce3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -117,8 +117,8 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
117 ah->is_clk_25mhz) { 117 ah->is_clk_25mhz) {
118 u32 chan_frac; 118 u32 chan_frac;
119 119
120 channelSel = (freq * 2) / 75; 120 channelSel = freq / 75;
121 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 121 chan_frac = ((freq % 75) * 0x20000) / 75;
122 channelSel = (channelSel << 17) | chan_frac; 122 channelSel = (channelSel << 17) | chan_frac;
123 } else { 123 } else {
124 channelSel = CHANSEL_5G(freq); 124 channelSel = CHANSEL_5G(freq);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 751c83b21493..7bfbaf065a43 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -633,6 +633,8 @@
633#define AR_PHY_65NM_CH0_BIAS2 0x160c4 633#define AR_PHY_65NM_CH0_BIAS2 0x160c4
634#define AR_PHY_65NM_CH0_BIAS4 0x160cc 634#define AR_PHY_65NM_CH0_BIAS4 0x160cc
635#define AR_PHY_65NM_CH0_RXTX4 0x1610c 635#define AR_PHY_65NM_CH0_RXTX4 0x1610c
636#define AR_PHY_65NM_CH1_RXTX4 0x1650c
637#define AR_PHY_65NM_CH2_RXTX4 0x1690c
636 638
637#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 639#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
638 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280))) 640 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
@@ -876,6 +878,9 @@
876#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 878#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
877#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 879#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
878 880
881#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
882#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
883
879/* 884/*
880 * Channel 1 Register Map 885 * Channel 1 Register Map
881 */ 886 */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 79840d6deef2..b09285c36c4a 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -297,6 +297,8 @@ struct ath_tx {
297 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 297 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
298 struct ath_descdma txdma; 298 struct ath_descdma txdma;
299 struct ath_txq *txq_map[WME_NUM_AC]; 299 struct ath_txq *txq_map[WME_NUM_AC];
300 u32 txq_max_pending[WME_NUM_AC];
301 u16 max_aggr_framelen[WME_NUM_AC][4][32];
300}; 302};
301 303
302struct ath_rx_edma { 304struct ath_rx_edma {
@@ -341,6 +343,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs);
341void ath_tx_cleanup(struct ath_softc *sc); 343void ath_tx_cleanup(struct ath_softc *sc);
342int ath_txq_update(struct ath_softc *sc, int qnum, 344int ath_txq_update(struct ath_softc *sc, int qnum,
343 struct ath9k_tx_queue_info *q); 345 struct ath9k_tx_queue_info *q);
346void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
344int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 347int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
345 struct ath_tx_control *txctl); 348 struct ath_tx_control *txctl);
346void ath_tx_tasklet(struct ath_softc *sc); 349void ath_tx_tasklet(struct ath_softc *sc);
@@ -360,7 +363,7 @@ void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
360 363
361struct ath_vif { 364struct ath_vif {
362 int av_bslot; 365 int av_bslot;
363 bool is_bslot_active, primary_sta_vif; 366 bool primary_sta_vif;
364 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 367 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
365 struct ath_buf *av_bcbuf; 368 struct ath_buf *av_bcbuf;
366}; 369};
@@ -386,6 +389,7 @@ struct ath_beacon_config {
386 u16 dtim_period; 389 u16 dtim_period;
387 u16 bmiss_timeout; 390 u16 bmiss_timeout;
388 u8 dtim_count; 391 u8 dtim_count;
392 bool enable_beacon;
389}; 393};
390 394
391struct ath_beacon { 395struct ath_beacon {
@@ -397,7 +401,6 @@ struct ath_beacon {
397 401
398 u32 beaconq; 402 u32 beaconq;
399 u32 bmisscnt; 403 u32 bmisscnt;
400 u32 ast_be_xmit;
401 u32 bc_tstamp; 404 u32 bc_tstamp;
402 struct ieee80211_vif *bslot[ATH_BCBUF]; 405 struct ieee80211_vif *bslot[ATH_BCBUF];
403 int slottime; 406 int slottime;
@@ -411,12 +414,14 @@ struct ath_beacon {
411 bool tx_last; 414 bool tx_last;
412}; 415};
413 416
414void ath_beacon_tasklet(unsigned long data); 417void ath9k_beacon_tasklet(unsigned long data);
415void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 418bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
416int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif); 419void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
417void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 420 u32 changed);
418int ath_beaconq_config(struct ath_softc *sc); 421void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
419void ath_set_beacon(struct ath_softc *sc); 422void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
423void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
424void ath9k_set_beacon(struct ath_softc *sc);
420void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); 425void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
421 426
422/*******************/ 427/*******************/
@@ -442,9 +447,12 @@ void ath_rx_poll(unsigned long data);
442void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 447void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
443void ath_paprd_calibrate(struct work_struct *work); 448void ath_paprd_calibrate(struct work_struct *work);
444void ath_ani_calibrate(unsigned long data); 449void ath_ani_calibrate(unsigned long data);
445void ath_start_ani(struct ath_common *common); 450void ath_start_ani(struct ath_softc *sc);
451void ath_stop_ani(struct ath_softc *sc);
452void ath_check_ani(struct ath_softc *sc);
446int ath_update_survey_stats(struct ath_softc *sc); 453int ath_update_survey_stats(struct ath_softc *sc);
447void ath_update_survey_nf(struct ath_softc *sc, int channel); 454void ath_update_survey_nf(struct ath_softc *sc, int channel);
455void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
448 456
449/**********/ 457/**********/
450/* BTCOEX */ 458/* BTCOEX */
@@ -510,6 +518,12 @@ static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
510} 518}
511#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 519#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
512 520
521struct ath9k_wow_pattern {
522 u8 pattern_bytes[MAX_PATTERN_SIZE];
523 u8 mask_bytes[MAX_PATTERN_SIZE];
524 u32 pattern_len;
525};
526
513/********************/ 527/********************/
514/* LED Control */ 528/* LED Control */
515/********************/ 529/********************/
@@ -613,7 +627,6 @@ enum sc_op_flags {
613 SC_OP_INVALID, 627 SC_OP_INVALID,
614 SC_OP_BEACONS, 628 SC_OP_BEACONS,
615 SC_OP_RXFLUSH, 629 SC_OP_RXFLUSH,
616 SC_OP_TSF_RESET,
617 SC_OP_ANI_RUN, 630 SC_OP_ANI_RUN,
618 SC_OP_PRIM_STA_VIF, 631 SC_OP_PRIM_STA_VIF,
619 SC_OP_HW_RESET, 632 SC_OP_HW_RESET,
@@ -711,6 +724,13 @@ struct ath_softc {
711 struct ath_ant_comb ant_comb; 724 struct ath_ant_comb ant_comb;
712 u8 ant_tx, ant_rx; 725 u8 ant_tx, ant_rx;
713 struct dfs_pattern_detector *dfs_detector; 726 struct dfs_pattern_detector *dfs_detector;
727 u32 wow_enabled;
728
729#ifdef CONFIG_PM_SLEEP
730 atomic_t wow_got_bmiss_intr;
731 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
732 u32 wow_intr_before_sleep;
733#endif
714}; 734};
715 735
716void ath9k_tasklet(unsigned long data); 736void ath9k_tasklet(unsigned long data);
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 40775da8941e..76f07d8c272d 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -30,7 +30,7 @@ static void ath9k_reset_beacon_status(struct ath_softc *sc)
30 * the operating mode of the station (AP or AdHoc). Parameters are AIFS 30 * the operating mode of the station (AP or AdHoc). Parameters are AIFS
31 * settings and channel width min/max 31 * settings and channel width min/max
32*/ 32*/
33int ath_beaconq_config(struct ath_softc *sc) 33static void ath9k_beaconq_config(struct ath_softc *sc)
34{ 34{
35 struct ath_hw *ah = sc->sc_ah; 35 struct ath_hw *ah = sc->sc_ah;
36 struct ath_common *common = ath9k_hw_common(ah); 36 struct ath_common *common = ath9k_hw_common(ah);
@@ -38,6 +38,7 @@ int ath_beaconq_config(struct ath_softc *sc)
38 struct ath_txq *txq; 38 struct ath_txq *txq;
39 39
40 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); 40 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
41
41 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { 42 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
42 /* Always burst out beacon and CAB traffic. */ 43 /* Always burst out beacon and CAB traffic. */
43 qi.tqi_aifs = 1; 44 qi.tqi_aifs = 1;
@@ -56,12 +57,9 @@ int ath_beaconq_config(struct ath_softc *sc)
56 } 57 }
57 58
58 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 59 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
59 ath_err(common, 60 ath_err(common, "Unable to update h/w beacon queue parameters\n");
60 "Unable to update h/w beacon queue parameters\n");
61 return 0;
62 } else { 61 } else {
63 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); 62 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
64 return 1;
65 } 63 }
66} 64}
67 65
@@ -70,7 +68,7 @@ int ath_beaconq_config(struct ath_softc *sc)
70 * up rate codes, and channel flags. Beacons are always sent out at the 68 * up rate codes, and channel flags. Beacons are always sent out at the
71 * lowest rate, and are not retried. 69 * lowest rate, and are not retried.
72*/ 70*/
73static void ath_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif, 71static void ath9k_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
74 struct ath_buf *bf, int rateidx) 72 struct ath_buf *bf, int rateidx)
75{ 73{
76 struct sk_buff *skb = bf->bf_mpdu; 74 struct sk_buff *skb = bf->bf_mpdu;
@@ -81,8 +79,6 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
81 u8 chainmask = ah->txchainmask; 79 u8 chainmask = ah->txchainmask;
82 u8 rate = 0; 80 u8 rate = 0;
83 81
84 ath9k_reset_beacon_status(sc);
85
86 sband = &sc->sbands[common->hw->conf.channel->band]; 82 sband = &sc->sbands[common->hw->conf.channel->band];
87 rate = sband->bitrates[rateidx].hw_value; 83 rate = sband->bitrates[rateidx].hw_value;
88 if (vif->bss_conf.use_short_preamble) 84 if (vif->bss_conf.use_short_preamble)
@@ -111,7 +107,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
111 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 107 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
112} 108}
113 109
114static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) 110static void ath9k_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
115{ 111{
116 struct ath_softc *sc = hw->priv; 112 struct ath_softc *sc = hw->priv;
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -128,28 +124,22 @@ static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
128 } 124 }
129} 125}
130 126
131static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, 127static struct ath_buf *ath9k_beacon_generate(struct ieee80211_hw *hw,
132 struct ieee80211_vif *vif) 128 struct ieee80211_vif *vif)
133{ 129{
134 struct ath_softc *sc = hw->priv; 130 struct ath_softc *sc = hw->priv;
135 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 131 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
136 struct ath_buf *bf; 132 struct ath_buf *bf;
137 struct ath_vif *avp; 133 struct ath_vif *avp = (void *)vif->drv_priv;
138 struct sk_buff *skb; 134 struct sk_buff *skb;
139 struct ath_txq *cabq; 135 struct ath_txq *cabq = sc->beacon.cabq;
140 struct ieee80211_tx_info *info; 136 struct ieee80211_tx_info *info;
137 struct ieee80211_mgmt *mgmt_hdr;
141 int cabq_depth; 138 int cabq_depth;
142 139
143 ath9k_reset_beacon_status(sc); 140 if (avp->av_bcbuf == NULL)
144
145 avp = (void *)vif->drv_priv;
146 cabq = sc->beacon.cabq;
147
148 if ((avp->av_bcbuf == NULL) || !avp->is_bslot_active)
149 return NULL; 141 return NULL;
150 142
151 /* Release the old beacon first */
152
153 bf = avp->av_bcbuf; 143 bf = avp->av_bcbuf;
154 skb = bf->bf_mpdu; 144 skb = bf->bf_mpdu;
155 if (skb) { 145 if (skb) {
@@ -159,14 +149,14 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
159 bf->bf_buf_addr = 0; 149 bf->bf_buf_addr = 0;
160 } 150 }
161 151
162 /* Get a new beacon from mac80211 */
163
164 skb = ieee80211_beacon_get(hw, vif); 152 skb = ieee80211_beacon_get(hw, vif);
165 bf->bf_mpdu = skb;
166 if (skb == NULL) 153 if (skb == NULL)
167 return NULL; 154 return NULL;
168 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = 155
169 avp->tsf_adjust; 156 bf->bf_mpdu = skb;
157
158 mgmt_hdr = (struct ieee80211_mgmt *)skb->data;
159 mgmt_hdr->u.beacon.timestamp = avp->tsf_adjust;
170 160
171 info = IEEE80211_SKB_CB(skb); 161 info = IEEE80211_SKB_CB(skb);
172 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 162 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
@@ -212,61 +202,52 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
212 } 202 }
213 } 203 }
214 204
215 ath_beacon_setup(sc, vif, bf, info->control.rates[0].idx); 205 ath9k_beacon_setup(sc, vif, bf, info->control.rates[0].idx);
216 206
217 while (skb) { 207 while (skb) {
218 ath_tx_cabq(hw, skb); 208 ath9k_tx_cabq(hw, skb);
219 skb = ieee80211_get_buffered_bc(hw, vif); 209 skb = ieee80211_get_buffered_bc(hw, vif);
220 } 210 }
221 211
222 return bf; 212 return bf;
223} 213}
224 214
225int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif) 215void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif)
226{ 216{
227 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 217 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
228 struct ath_vif *avp; 218 struct ath_vif *avp = (void *)vif->drv_priv;
229 struct ath_buf *bf; 219 int slot;
230 struct sk_buff *skb; 220
231 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 221 avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf, struct ath_buf, list);
232 __le64 tstamp; 222 list_del(&avp->av_bcbuf->list);
233 223
234 avp = (void *)vif->drv_priv; 224 for (slot = 0; slot < ATH_BCBUF; slot++) {
235 225 if (sc->beacon.bslot[slot] == NULL) {
236 /* Allocate a beacon descriptor if we haven't done so. */ 226 avp->av_bslot = slot;
237 if (!avp->av_bcbuf) { 227 break;
238 /* Allocate beacon state for hostap/ibss. We know
239 * a buffer is available. */
240 avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf,
241 struct ath_buf, list);
242 list_del(&avp->av_bcbuf->list);
243
244 if (ath9k_uses_beacons(vif->type)) {
245 int slot;
246 /*
247 * Assign the vif to a beacon xmit slot. As
248 * above, this cannot fail to find one.
249 */
250 avp->av_bslot = 0;
251 for (slot = 0; slot < ATH_BCBUF; slot++)
252 if (sc->beacon.bslot[slot] == NULL) {
253 avp->av_bslot = slot;
254 avp->is_bslot_active = false;
255
256 /* NB: keep looking for a double slot */
257 if (slot == 0 || !sc->beacon.bslot[slot-1])
258 break;
259 }
260 BUG_ON(sc->beacon.bslot[avp->av_bslot] != NULL);
261 sc->beacon.bslot[avp->av_bslot] = vif;
262 sc->nbcnvifs++;
263 } 228 }
264 } 229 }
265 230
266 /* release the previous beacon frame, if it already exists. */ 231 sc->beacon.bslot[avp->av_bslot] = vif;
267 bf = avp->av_bcbuf; 232 sc->nbcnvifs++;
268 if (bf->bf_mpdu != NULL) { 233
269 skb = bf->bf_mpdu; 234 ath_dbg(common, CONFIG, "Added interface at beacon slot: %d\n",
235 avp->av_bslot);
236}
237
238void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif)
239{
240 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
241 struct ath_vif *avp = (void *)vif->drv_priv;
242 struct ath_buf *bf = avp->av_bcbuf;
243
244 ath_dbg(common, CONFIG, "Removing interface at beacon slot: %d\n",
245 avp->av_bslot);
246
247 tasklet_disable(&sc->bcon_tasklet);
248
249 if (bf && bf->bf_mpdu) {
250 struct sk_buff *skb = bf->bf_mpdu;
270 dma_unmap_single(sc->dev, bf->bf_buf_addr, 251 dma_unmap_single(sc->dev, bf->bf_buf_addr,
271 skb->len, DMA_TO_DEVICE); 252 skb->len, DMA_TO_DEVICE);
272 dev_kfree_skb_any(skb); 253 dev_kfree_skb_any(skb);
@@ -274,99 +255,74 @@ int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
274 bf->bf_buf_addr = 0; 255 bf->bf_buf_addr = 0;
275 } 256 }
276 257
277 /* NB: the beacon data buffer must be 32-bit aligned. */ 258 avp->av_bcbuf = NULL;
278 skb = ieee80211_beacon_get(sc->hw, vif); 259 sc->beacon.bslot[avp->av_bslot] = NULL;
279 if (skb == NULL) 260 sc->nbcnvifs--;
280 return -ENOMEM; 261 list_add_tail(&bf->list, &sc->beacon.bbuf);
281 262
282 tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; 263 tasklet_enable(&sc->bcon_tasklet);
283 sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp); 264}
284 /* Calculate a TSF adjustment factor required for staggered beacons. */
285 if (avp->av_bslot > 0) {
286 u64 tsfadjust;
287 int intval;
288
289 intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
290 265
291 /* 266static int ath9k_beacon_choose_slot(struct ath_softc *sc)
292 * Calculate the TSF offset for this beacon slot, i.e., the 267{
293 * number of usecs that need to be added to the timestamp field 268 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
294 * in Beacon and Probe Response frames. Beacon slot 0 is 269 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
295 * processed at the correct offset, so it does not require TSF 270 u16 intval;
296 * adjustment. Other slots are adjusted to get the timestamp 271 u32 tsftu;
297 * close to the TBTT for the BSS. 272 u64 tsf;
298 */ 273 int slot;
299 tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
300 avp->tsf_adjust = cpu_to_le64(tsfadjust);
301 274
302 ath_dbg(common, BEACON, 275 if (sc->sc_ah->opmode != NL80211_IFTYPE_AP) {
303 "stagger beacons, bslot %d intval %u tsfadjust %llu\n", 276 ath_dbg(common, BEACON, "slot 0, tsf: %llu\n",
304 avp->av_bslot, intval, (unsigned long long)tsfadjust); 277 ath9k_hw_gettsf64(sc->sc_ah));
278 return 0;
279 }
305 280
306 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = 281 intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
307 avp->tsf_adjust; 282 tsf = ath9k_hw_gettsf64(sc->sc_ah);
308 } else 283 tsf += TU_TO_USEC(sc->sc_ah->config.sw_beacon_response_time);
309 avp->tsf_adjust = cpu_to_le64(0); 284 tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
285 slot = (tsftu % (intval * ATH_BCBUF)) / intval;
310 286
311 bf->bf_mpdu = skb; 287 ath_dbg(common, BEACON, "slot: %d tsf: %llu tsftu: %u\n",
312 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 288 slot, tsf, tsftu / ATH_BCBUF);
313 skb->len, DMA_TO_DEVICE);
314 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
315 dev_kfree_skb_any(skb);
316 bf->bf_mpdu = NULL;
317 bf->bf_buf_addr = 0;
318 ath_err(common, "dma_mapping_error on beacon alloc\n");
319 return -ENOMEM;
320 }
321 avp->is_bslot_active = true;
322 289
323 return 0; 290 return slot;
324} 291}
325 292
326void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp) 293void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
327{ 294{
328 if (avp->av_bcbuf != NULL) { 295 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
329 struct ath_buf *bf; 296 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
330 297 struct ath_vif *avp = (void *)vif->drv_priv;
331 avp->is_bslot_active = false; 298 u64 tsfadjust;
332 if (avp->av_bslot != -1) {
333 sc->beacon.bslot[avp->av_bslot] = NULL;
334 sc->nbcnvifs--;
335 avp->av_bslot = -1;
336 }
337 299
338 bf = avp->av_bcbuf; 300 if (avp->av_bslot == 0)
339 if (bf->bf_mpdu != NULL) { 301 return;
340 struct sk_buff *skb = bf->bf_mpdu;
341 dma_unmap_single(sc->dev, bf->bf_buf_addr,
342 skb->len, DMA_TO_DEVICE);
343 dev_kfree_skb_any(skb);
344 bf->bf_mpdu = NULL;
345 bf->bf_buf_addr = 0;
346 }
347 list_add_tail(&bf->list, &sc->beacon.bbuf);
348 302
349 avp->av_bcbuf = NULL; 303 tsfadjust = cur_conf->beacon_interval * avp->av_bslot / ATH_BCBUF;
350 } 304 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
305
306 ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
307 (unsigned long long)tsfadjust, avp->av_bslot);
351} 308}
352 309
353void ath_beacon_tasklet(unsigned long data) 310void ath9k_beacon_tasklet(unsigned long data)
354{ 311{
355 struct ath_softc *sc = (struct ath_softc *)data; 312 struct ath_softc *sc = (struct ath_softc *)data;
356 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
357 struct ath_hw *ah = sc->sc_ah; 313 struct ath_hw *ah = sc->sc_ah;
358 struct ath_common *common = ath9k_hw_common(ah); 314 struct ath_common *common = ath9k_hw_common(ah);
359 struct ath_buf *bf = NULL; 315 struct ath_buf *bf = NULL;
360 struct ieee80211_vif *vif; 316 struct ieee80211_vif *vif;
361 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 317 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
362 int slot; 318 int slot;
363 u32 bfaddr, bc = 0;
364 319
365 if (work_pending(&sc->hw_reset_work)) { 320 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
366 ath_dbg(common, RESET, 321 ath_dbg(common, RESET,
367 "reset work is pending, skip beaconing now\n"); 322 "reset work is pending, skip beaconing now\n");
368 return; 323 return;
369 } 324 }
325
370 /* 326 /*
371 * Check if the previous beacon has gone out. If 327 * Check if the previous beacon has gone out. If
372 * not don't try to post another, skip this period 328 * not don't try to post another, skip this period
@@ -390,55 +346,25 @@ void ath_beacon_tasklet(unsigned long data)
390 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 346 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
391 ath_dbg(common, BSTUCK, "beacon is officially stuck\n"); 347 ath_dbg(common, BSTUCK, "beacon is officially stuck\n");
392 sc->beacon.bmisscnt = 0; 348 sc->beacon.bmisscnt = 0;
393 set_bit(SC_OP_TSF_RESET, &sc->sc_flags); 349 ath9k_queue_reset(sc, RESET_TYPE_BEACON_STUCK);
394 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
395 } 350 }
396 351
397 return; 352 return;
398 } 353 }
399 354
400 /* 355 slot = ath9k_beacon_choose_slot(sc);
401 * Generate beacon frames. we are sending frames 356 vif = sc->beacon.bslot[slot];
402 * staggered so calculate the slot for this frame based
403 * on the tsf to safeguard against missing an swba.
404 */
405
406
407 if (ah->opmode == NL80211_IFTYPE_AP) {
408 u16 intval;
409 u32 tsftu;
410 u64 tsf;
411
412 intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
413 tsf = ath9k_hw_gettsf64(ah);
414 tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
415 tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
416 slot = (tsftu % (intval * ATH_BCBUF)) / intval;
417 vif = sc->beacon.bslot[slot];
418
419 ath_dbg(common, BEACON,
420 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
421 slot, tsf, tsftu / ATH_BCBUF, intval, vif);
422 } else {
423 slot = 0;
424 vif = sc->beacon.bslot[slot];
425 }
426 357
358 if (!vif || !vif->bss_conf.enable_beacon)
359 return;
427 360
428 bfaddr = 0; 361 bf = ath9k_beacon_generate(sc->hw, vif);
429 if (vif) { 362 WARN_ON(!bf);
430 bf = ath_beacon_generate(sc->hw, vif);
431 if (bf != NULL) {
432 bfaddr = bf->bf_daddr;
433 bc = 1;
434 }
435 363
436 if (sc->beacon.bmisscnt != 0) { 364 if (sc->beacon.bmisscnt != 0) {
437 ath_dbg(common, BSTUCK, 365 ath_dbg(common, BSTUCK, "resume beacon xmit after %u misses\n",
438 "resume beacon xmit after %u misses\n", 366 sc->beacon.bmisscnt);
439 sc->beacon.bmisscnt); 367 sc->beacon.bmisscnt = 0;
440 sc->beacon.bmisscnt = 0;
441 }
442 } 368 }
443 369
444 /* 370 /*
@@ -458,39 +384,40 @@ void ath_beacon_tasklet(unsigned long data)
458 * set to ATH_BCBUF so this check is a noop. 384 * set to ATH_BCBUF so this check is a noop.
459 */ 385 */
460 if (sc->beacon.updateslot == UPDATE) { 386 if (sc->beacon.updateslot == UPDATE) {
461 sc->beacon.updateslot = COMMIT; /* commit next beacon */ 387 sc->beacon.updateslot = COMMIT;
462 sc->beacon.slotupdate = slot; 388 sc->beacon.slotupdate = slot;
463 } else if (sc->beacon.updateslot == COMMIT && sc->beacon.slotupdate == slot) { 389 } else if (sc->beacon.updateslot == COMMIT &&
390 sc->beacon.slotupdate == slot) {
464 ah->slottime = sc->beacon.slottime; 391 ah->slottime = sc->beacon.slottime;
465 ath9k_hw_init_global_settings(ah); 392 ath9k_hw_init_global_settings(ah);
466 sc->beacon.updateslot = OK; 393 sc->beacon.updateslot = OK;
467 } 394 }
468 if (bfaddr != 0) { 395
396 if (bf) {
397 ath9k_reset_beacon_status(sc);
398
399 ath_dbg(common, BEACON,
400 "Transmitting beacon for slot: %d\n", slot);
401
469 /* NB: cabq traffic should already be queued and primed */ 402 /* NB: cabq traffic should already be queued and primed */
470 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr); 403 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
471 404
472 if (!edma) 405 if (!edma)
473 ath9k_hw_txstart(ah, sc->beacon.beaconq); 406 ath9k_hw_txstart(ah, sc->beacon.beaconq);
474
475 sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */
476 } 407 }
477} 408}
478 409
479static void ath9k_beacon_init(struct ath_softc *sc, 410static void ath9k_beacon_init(struct ath_softc *sc, u32 nexttbtt, u32 intval)
480 u32 next_beacon,
481 u32 beacon_period)
482{ 411{
483 if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) { 412 struct ath_hw *ah = sc->sc_ah;
484 ath9k_ps_wakeup(sc);
485 ath9k_hw_reset_tsf(sc->sc_ah);
486 }
487
488 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
489 413
490 if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) { 414 ath9k_hw_disable_interrupts(ah);
491 ath9k_ps_restore(sc); 415 ath9k_hw_reset_tsf(ah);
492 clear_bit(SC_OP_TSF_RESET, &sc->sc_flags); 416 ath9k_beaconq_config(sc);
493 } 417 ath9k_hw_beaconinit(ah, nexttbtt, intval);
418 sc->beacon.bmisscnt = 0;
419 ath9k_hw_set_interrupts(ah);
420 ath9k_hw_enable_interrupts(ah);
494} 421}
495 422
496/* 423/*
@@ -498,32 +425,27 @@ static void ath9k_beacon_init(struct ath_softc *sc,
498 * burst together. For the former arrange for the SWBA to be delivered for each 425 * burst together. For the former arrange for the SWBA to be delivered for each
499 * slot. Slots that are not occupied will generate nothing. 426 * slot. Slots that are not occupied will generate nothing.
500 */ 427 */
501static void ath_beacon_config_ap(struct ath_softc *sc, 428static void ath9k_beacon_config_ap(struct ath_softc *sc,
502 struct ath_beacon_config *conf) 429 struct ath_beacon_config *conf)
503{ 430{
504 struct ath_hw *ah = sc->sc_ah; 431 struct ath_hw *ah = sc->sc_ah;
432 struct ath_common *common = ath9k_hw_common(ah);
505 u32 nexttbtt, intval; 433 u32 nexttbtt, intval;
506 434
507 /* NB: the beacon interval is kept internally in TU's */ 435 /* NB: the beacon interval is kept internally in TU's */
508 intval = TU_TO_USEC(conf->beacon_interval); 436 intval = TU_TO_USEC(conf->beacon_interval);
509 intval /= ATH_BCBUF; /* for staggered beacons */ 437 intval /= ATH_BCBUF;
510 nexttbtt = intval; 438 nexttbtt = intval;
511 439
512 /* 440 if (conf->enable_beacon)
513 * In AP mode we enable the beacon timers and SWBA interrupts to 441 ah->imask |= ATH9K_INT_SWBA;
514 * prepare beacon frames. 442 else
515 */ 443 ah->imask &= ~ATH9K_INT_SWBA;
516 ah->imask |= ATH9K_INT_SWBA;
517 ath_beaconq_config(sc);
518 444
519 /* Set the computed AP beacon timers */ 445 ath_dbg(common, BEACON, "AP nexttbtt: %u intval: %u conf_intval: %u\n",
446 nexttbtt, intval, conf->beacon_interval);
520 447
521 ath9k_hw_disable_interrupts(ah);
522 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
523 ath9k_beacon_init(sc, nexttbtt, intval); 448 ath9k_beacon_init(sc, nexttbtt, intval);
524 sc->beacon.bmisscnt = 0;
525 ath9k_hw_set_interrupts(ah);
526 ath9k_hw_enable_interrupts(ah);
527} 449}
528 450
529/* 451/*
@@ -534,8 +456,8 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
534 * we'll receive a BMISS interrupt when we stop seeing beacons from the AP 456 * we'll receive a BMISS interrupt when we stop seeing beacons from the AP
535 * we've associated with. 457 * we've associated with.
536 */ 458 */
537static void ath_beacon_config_sta(struct ath_softc *sc, 459static void ath9k_beacon_config_sta(struct ath_softc *sc,
538 struct ath_beacon_config *conf) 460 struct ath_beacon_config *conf)
539{ 461{
540 struct ath_hw *ah = sc->sc_ah; 462 struct ath_hw *ah = sc->sc_ah;
541 struct ath_common *common = ath9k_hw_common(ah); 463 struct ath_common *common = ath9k_hw_common(ah);
@@ -547,7 +469,7 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
547 int num_beacons, offset, dtim_dec_count, cfp_dec_count; 469 int num_beacons, offset, dtim_dec_count, cfp_dec_count;
548 470
549 /* No need to configure beacon if we are not associated */ 471 /* No need to configure beacon if we are not associated */
550 if (!common->curaid) { 472 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
551 ath_dbg(common, BEACON, 473 ath_dbg(common, BEACON,
552 "STA is not yet associated..skipping beacon config\n"); 474 "STA is not yet associated..skipping beacon config\n");
553 return; 475 return;
@@ -654,97 +576,65 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
654 ath9k_hw_enable_interrupts(ah); 576 ath9k_hw_enable_interrupts(ah);
655} 577}
656 578
657static void ath_beacon_config_adhoc(struct ath_softc *sc, 579static void ath9k_beacon_config_adhoc(struct ath_softc *sc,
658 struct ath_beacon_config *conf) 580 struct ath_beacon_config *conf)
659{ 581{
660 struct ath_hw *ah = sc->sc_ah; 582 struct ath_hw *ah = sc->sc_ah;
661 struct ath_common *common = ath9k_hw_common(ah); 583 struct ath_common *common = ath9k_hw_common(ah);
662 u32 tsf, intval, nexttbtt; 584 u32 intval, nexttbtt;
663 585
664 ath9k_reset_beacon_status(sc); 586 ath9k_reset_beacon_status(sc);
665 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
666 ath9k_hw_settsf64(ah, sc->beacon.bc_tstamp);
667 587
668 intval = TU_TO_USEC(conf->beacon_interval); 588 intval = TU_TO_USEC(conf->beacon_interval);
669 tsf = roundup(ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE), intval); 589 nexttbtt = intval;
670 nexttbtt = tsf + intval;
671
672 ath_dbg(common, BEACON, "IBSS nexttbtt %u intval %u (%u)\n",
673 nexttbtt, intval, conf->beacon_interval);
674
675 /*
676 * In IBSS mode enable the beacon timers but only enable SWBA interrupts
677 * if we need to manually prepare beacon frames. Otherwise we use a
678 * self-linked tx descriptor and let the hardware deal with things.
679 */
680 ah->imask |= ATH9K_INT_SWBA;
681 590
682 ath_beaconq_config(sc); 591 if (conf->enable_beacon)
592 ah->imask |= ATH9K_INT_SWBA;
593 else
594 ah->imask &= ~ATH9K_INT_SWBA;
683 595
684 /* Set the computed ADHOC beacon timers */ 596 ath_dbg(common, BEACON, "IBSS nexttbtt: %u intval: %u conf_intval: %u\n",
597 nexttbtt, intval, conf->beacon_interval);
685 598
686 ath9k_hw_disable_interrupts(ah);
687 ath9k_beacon_init(sc, nexttbtt, intval); 599 ath9k_beacon_init(sc, nexttbtt, intval);
688 sc->beacon.bmisscnt = 0;
689
690 ath9k_hw_set_interrupts(ah);
691 ath9k_hw_enable_interrupts(ah);
692} 600}
693 601
694static bool ath9k_allow_beacon_config(struct ath_softc *sc, 602bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
695 struct ieee80211_vif *vif)
696{ 603{
697 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
698 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 604 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
699 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
700 struct ath_vif *avp = (void *)vif->drv_priv; 605 struct ath_vif *avp = (void *)vif->drv_priv;
701 606
702 /* 607 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
703 * Can not have different beacon interval on multiple 608 if ((vif->type != NL80211_IFTYPE_AP) ||
704 * AP interface case 609 (sc->nbcnvifs > 1)) {
705 */ 610 ath_dbg(common, CONFIG,
706 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) && 611 "An AP interface is already present !\n");
707 (sc->nbcnvifs > 1) && 612 return false;
708 (vif->type == NL80211_IFTYPE_AP) && 613 }
709 (cur_conf->beacon_interval != bss_conf->beacon_int)) {
710 ath_dbg(common, CONFIG,
711 "Changing beacon interval of multiple AP interfaces !\n");
712 return false;
713 }
714 /*
715 * Can not configure station vif's beacon config
716 * while on AP opmode
717 */
718 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
719 (vif->type != NL80211_IFTYPE_AP)) {
720 ath_dbg(common, CONFIG,
721 "STA vif's beacon not allowed on AP mode\n");
722 return false;
723 } 614 }
724 /* 615
725 * Do not allow beacon config if HW was already configured 616 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
726 * with another STA vif 617 if ((vif->type == NL80211_IFTYPE_STATION) &&
727 */ 618 test_bit(SC_OP_BEACONS, &sc->sc_flags) &&
728 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && 619 !avp->primary_sta_vif) {
729 (vif->type == NL80211_IFTYPE_STATION) && 620 ath_dbg(common, CONFIG,
730 test_bit(SC_OP_BEACONS, &sc->sc_flags) && 621 "Beacon already configured for a station interface\n");
731 !avp->primary_sta_vif) { 622 return false;
732 ath_dbg(common, CONFIG, 623 }
733 "Beacon already configured for a station interface\n");
734 return false;
735 } 624 }
625
736 return true; 626 return true;
737} 627}
738 628
739void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) 629static void ath9k_cache_beacon_config(struct ath_softc *sc,
630 struct ieee80211_bss_conf *bss_conf)
740{ 631{
632 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
741 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 633 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
742 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
743 634
744 if (!ath9k_allow_beacon_config(sc, vif)) 635 ath_dbg(common, BEACON,
745 return; 636 "Caching beacon data for BSS: %pM\n", bss_conf->bssid);
746 637
747 /* Setup the beacon configuration parameters */
748 cur_conf->beacon_interval = bss_conf->beacon_int; 638 cur_conf->beacon_interval = bss_conf->beacon_int;
749 cur_conf->dtim_period = bss_conf->dtim_period; 639 cur_conf->dtim_period = bss_conf->dtim_period;
750 cur_conf->listen_interval = 1; 640 cur_conf->listen_interval = 1;
@@ -769,73 +659,62 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
769 if (cur_conf->dtim_period == 0) 659 if (cur_conf->dtim_period == 0)
770 cur_conf->dtim_period = 1; 660 cur_conf->dtim_period = 1;
771 661
772 ath_set_beacon(sc);
773} 662}
774 663
775static bool ath_has_valid_bslot(struct ath_softc *sc) 664void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
665 u32 changed)
776{ 666{
777 struct ath_vif *avp; 667 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
778 int slot; 668 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
779 bool found = false;
780 669
781 for (slot = 0; slot < ATH_BCBUF; slot++) { 670 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
782 if (sc->beacon.bslot[slot]) { 671 ath9k_cache_beacon_config(sc, bss_conf);
783 avp = (void *)sc->beacon.bslot[slot]->drv_priv; 672 ath9k_set_beacon(sc);
784 if (avp->is_bslot_active) { 673 set_bit(SC_OP_BEACONS, &sc->sc_flags);
785 found = true; 674 } else {
786 break; 675 /*
676 * Take care of multiple interfaces when
677 * enabling/disabling SWBA.
678 */
679 if (changed & BSS_CHANGED_BEACON_ENABLED) {
680 if (!bss_conf->enable_beacon &&
681 (sc->nbcnvifs <= 1)) {
682 cur_conf->enable_beacon = false;
683 } else if (bss_conf->enable_beacon) {
684 cur_conf->enable_beacon = true;
685 ath9k_cache_beacon_config(sc, bss_conf);
787 } 686 }
788 } 687 }
688
689 if (cur_conf->beacon_interval) {
690 ath9k_set_beacon(sc);
691
692 if (cur_conf->enable_beacon)
693 set_bit(SC_OP_BEACONS, &sc->sc_flags);
694 else
695 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
696 }
789 } 697 }
790 return found;
791} 698}
792 699
793 700void ath9k_set_beacon(struct ath_softc *sc)
794void ath_set_beacon(struct ath_softc *sc)
795{ 701{
796 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 702 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
797 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 703 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
798 704
799 switch (sc->sc_ah->opmode) { 705 switch (sc->sc_ah->opmode) {
800 case NL80211_IFTYPE_AP: 706 case NL80211_IFTYPE_AP:
801 if (ath_has_valid_bslot(sc)) 707 ath9k_beacon_config_ap(sc, cur_conf);
802 ath_beacon_config_ap(sc, cur_conf);
803 break; 708 break;
804 case NL80211_IFTYPE_ADHOC: 709 case NL80211_IFTYPE_ADHOC:
805 case NL80211_IFTYPE_MESH_POINT: 710 case NL80211_IFTYPE_MESH_POINT:
806 ath_beacon_config_adhoc(sc, cur_conf); 711 ath9k_beacon_config_adhoc(sc, cur_conf);
807 break; 712 break;
808 case NL80211_IFTYPE_STATION: 713 case NL80211_IFTYPE_STATION:
809 ath_beacon_config_sta(sc, cur_conf); 714 ath9k_beacon_config_sta(sc, cur_conf);
810 break; 715 break;
811 default: 716 default:
812 ath_dbg(common, CONFIG, "Unsupported beaconing mode\n"); 717 ath_dbg(common, CONFIG, "Unsupported beaconing mode\n");
813 return; 718 return;
814 } 719 }
815
816 set_bit(SC_OP_BEACONS, &sc->sc_flags);
817}
818
819void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
820{
821 struct ath_hw *ah = sc->sc_ah;
822
823 if (!ath_has_valid_bslot(sc)) {
824 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
825 return;
826 }
827
828 ath9k_ps_wakeup(sc);
829 if (status) {
830 /* Re-enable beaconing */
831 ah->imask |= ATH9K_INT_SWBA;
832 ath9k_hw_set_interrupts(ah);
833 } else {
834 /* Disable SWBA interrupt */
835 ah->imask &= ~ATH9K_INT_SWBA;
836 ath9k_hw_set_interrupts(ah);
837 tasklet_kill(&sc->bcon_tasklet);
838 ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
839 }
840 ath9k_ps_restore(sc);
841} 720}
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 3b33996d97df..1060c19a5012 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -30,10 +30,10 @@ struct ar5416IniArray {
30 u32 ia_columns; 30 u32 ia_columns;
31}; 31};
32 32
33#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 33#define INIT_INI_ARRAY(iniarray, array) do { \
34 (iniarray)->ia_array = (u32 *)(array); \ 34 (iniarray)->ia_array = (u32 *)(array); \
35 (iniarray)->ia_rows = (rows); \ 35 (iniarray)->ia_rows = ARRAY_SIZE(array); \
36 (iniarray)->ia_columns = (columns); \ 36 (iniarray)->ia_columns = ARRAY_SIZE(array[0]); \
37 } while (0) 37 } while (0)
38 38
39#define INI_RA(iniarray, row, column) \ 39#define INI_RA(iniarray, row, column) \
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 5c3192ffc196..68b643c8943c 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -206,10 +206,9 @@ static ssize_t write_file_disable_ani(struct file *file,
206 206
207 if (disable_ani) { 207 if (disable_ani) {
208 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags); 208 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
209 del_timer_sync(&common->ani.timer); 209 ath_stop_ani(sc);
210 } else { 210 } else {
211 set_bit(SC_OP_ANI_RUN, &sc->sc_flags); 211 ath_check_ani(sc);
212 ath_start_ani(common);
213 } 212 }
214 213
215 return count; 214 return count;
@@ -1556,6 +1555,14 @@ int ath9k_init_debug(struct ath_hw *ah)
1556 &fops_interrupt); 1555 &fops_interrupt);
1557 debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc, 1556 debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
1558 &fops_xmit); 1557 &fops_xmit);
1558 debugfs_create_u32("qlen_bk", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1559 &sc->tx.txq_max_pending[WME_AC_BK]);
1560 debugfs_create_u32("qlen_be", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1561 &sc->tx.txq_max_pending[WME_AC_BE]);
1562 debugfs_create_u32("qlen_vi", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1563 &sc->tx.txq_max_pending[WME_AC_VI]);
1564 debugfs_create_u32("qlen_vo", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1565 &sc->tx.txq_max_pending[WME_AC_VO]);
1559 debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc, 1566 debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
1560 &fops_stations); 1567 &fops_stations);
1561 debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc, 1568 debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index d0f851cea43a..8b9d080d89da 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -32,6 +32,19 @@ struct ath_buf;
32#define RESET_STAT_INC(sc, type) do { } while (0) 32#define RESET_STAT_INC(sc, type) do { } while (0)
33#endif 33#endif
34 34
35enum ath_reset_type {
36 RESET_TYPE_BB_HANG,
37 RESET_TYPE_BB_WATCHDOG,
38 RESET_TYPE_FATAL_INT,
39 RESET_TYPE_TX_ERROR,
40 RESET_TYPE_TX_HANG,
41 RESET_TYPE_PLL_HANG,
42 RESET_TYPE_MAC_HANG,
43 RESET_TYPE_BEACON_STUCK,
44 RESET_TYPE_MCI,
45 __RESET_TYPE_MAX
46};
47
35#ifdef CONFIG_ATH9K_DEBUGFS 48#ifdef CONFIG_ATH9K_DEBUGFS
36 49
37/** 50/**
@@ -209,17 +222,6 @@ struct ath_rx_stats {
209 u32 rx_frags; 222 u32 rx_frags;
210}; 223};
211 224
212enum ath_reset_type {
213 RESET_TYPE_BB_HANG,
214 RESET_TYPE_BB_WATCHDOG,
215 RESET_TYPE_FATAL_INT,
216 RESET_TYPE_TX_ERROR,
217 RESET_TYPE_TX_HANG,
218 RESET_TYPE_PLL_HANG,
219 RESET_TYPE_MAC_HANG,
220 __RESET_TYPE_MAX
221};
222
223struct ath_stats { 225struct ath_stats {
224 struct ath_interrupt_stats istats; 226 struct ath_interrupt_stats istats;
225 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 227 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 33acb920ed3f..484b31305906 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -241,16 +241,12 @@ enum eeprom_param {
241 EEP_TEMPSENSE_SLOPE, 241 EEP_TEMPSENSE_SLOPE,
242 EEP_TEMPSENSE_SLOPE_PAL_ON, 242 EEP_TEMPSENSE_SLOPE_PAL_ON,
243 EEP_PWR_TABLE_OFFSET, 243 EEP_PWR_TABLE_OFFSET,
244 EEP_DRIVE_STRENGTH,
245 EEP_INTERNAL_REGULATOR,
246 EEP_SWREG,
247 EEP_PAPRD, 244 EEP_PAPRD,
248 EEP_MODAL_VER, 245 EEP_MODAL_VER,
249 EEP_ANT_DIV_CTL1, 246 EEP_ANT_DIV_CTL1,
250 EEP_CHAIN_MASK_REDUCE, 247 EEP_CHAIN_MASK_REDUCE,
251 EEP_ANTENNA_GAIN_2G, 248 EEP_ANTENNA_GAIN_2G,
252 EEP_ANTENNA_GAIN_5G, 249 EEP_ANTENNA_GAIN_5G,
253 EEP_QUICK_DROP
254}; 250};
255 251
256enum ar5416_rates { 252enum ar5416_rates {
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 374c32ed905a..c785129692ff 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -1111,7 +1111,7 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
1111 1111
1112 if ((priv->ah->opmode == NL80211_IFTYPE_AP) && 1112 if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
1113 !test_bit(OP_ANI_RUNNING, &priv->op_flags)) { 1113 !test_bit(OP_ANI_RUNNING, &priv->op_flags)) {
1114 ath9k_hw_set_tsfadjust(priv->ah, 1); 1114 ath9k_hw_set_tsfadjust(priv->ah, true);
1115 ath9k_htc_start_ani(priv); 1115 ath9k_htc_start_ani(priv);
1116 } 1116 }
1117 1117
@@ -1351,7 +1351,7 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw,
1351 qi.tqi_aifs = params->aifs; 1351 qi.tqi_aifs = params->aifs;
1352 qi.tqi_cwmin = params->cw_min; 1352 qi.tqi_cwmin = params->cw_min;
1353 qi.tqi_cwmax = params->cw_max; 1353 qi.tqi_cwmax = params->cw_max;
1354 qi.tqi_burstTime = params->txop; 1354 qi.tqi_burstTime = params->txop * 32;
1355 1355
1356 qnum = get_hw_qnum(queue, priv->hwq_map); 1356 qnum = get_hw_qnum(queue, priv->hwq_map);
1357 1357
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index c1659d079513..cfa91ab7acf8 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -671,10 +671,6 @@ static int __ath9k_hw_init(struct ath_hw *ah)
671 if (!AR_SREV_9300_20_OR_LATER(ah)) 671 if (!AR_SREV_9300_20_OR_LATER(ah))
672 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 672 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
673 673
674 /* disable ANI for 9340 */
675 if (AR_SREV_9340(ah))
676 ah->config.enable_ani = false;
677
678 ath9k_hw_init_mode_regs(ah); 674 ath9k_hw_init_mode_regs(ah);
679 675
680 if (!ah->is_pciexpress) 676 if (!ah->is_pciexpress)
@@ -2589,6 +2585,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2589 } 2585 }
2590 2586
2591 2587
2588 if (AR_SREV_9280_20_OR_LATER(ah)) {
2589 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
2590 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
2591
2592 if (AR_SREV_9280(ah))
2593 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
2594 }
2595
2592 return 0; 2596 return 0;
2593} 2597}
2594 2598
@@ -2908,9 +2912,9 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
2908} 2912}
2909EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2913EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2910 2914
2911void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2915void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2912{ 2916{
2913 if (setting) 2917 if (set)
2914 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2918 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2915 else 2919 else
2916 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2920 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 26da1732978d..dd0c146d81dc 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -180,6 +180,37 @@
180#define PAPRD_TABLE_SZ 24 180#define PAPRD_TABLE_SZ 24
181#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 181#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
182 182
183/*
184 * Wake on Wireless
185 */
186
187/* Keep Alive Frame */
188#define KAL_FRAME_LEN 28
189#define KAL_FRAME_TYPE 0x2 /* data frame */
190#define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
191#define KAL_DURATION_ID 0x3d
192#define KAL_NUM_DATA_WORDS 6
193#define KAL_NUM_DESC_WORDS 12
194#define KAL_ANTENNA_MODE 1
195#define KAL_TO_DS 1
196#define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
197#define KAL_TIMEOUT 900
198
199#define MAX_PATTERN_SIZE 256
200#define MAX_PATTERN_MASK_SIZE 32
201#define MAX_NUM_PATTERN 8
202#define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
203 deauthenticate packets */
204
205/*
206 * WoW trigger mapping to hardware code
207 */
208
209#define AH_WOW_USER_PATTERN_EN BIT(0)
210#define AH_WOW_MAGIC_PATTERN_EN BIT(1)
211#define AH_WOW_LINK_CHANGE BIT(2)
212#define AH_WOW_BEACON_MISS BIT(3)
213
183enum ath_hw_txq_subtype { 214enum ath_hw_txq_subtype {
184 ATH_TXQ_AC_BE = 0, 215 ATH_TXQ_AC_BE = 0,
185 ATH_TXQ_AC_BK = 1, 216 ATH_TXQ_AC_BK = 1,
@@ -212,8 +243,22 @@ enum ath9k_hw_caps {
212 ATH9K_HW_CAP_RTT = BIT(14), 243 ATH9K_HW_CAP_RTT = BIT(14),
213 ATH9K_HW_CAP_MCI = BIT(15), 244 ATH9K_HW_CAP_MCI = BIT(15),
214 ATH9K_HW_CAP_DFS = BIT(16), 245 ATH9K_HW_CAP_DFS = BIT(16),
246 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
247 ATH9K_HW_WOW_PATTERN_MATCH_EXACT = BIT(18),
248 ATH9K_HW_WOW_PATTERN_MATCH_DWORD = BIT(19),
215}; 249};
216 250
251/*
252 * WoW device capabilities
253 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
254 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
255 * an exact user defined pattern or de-authentication/disassoc pattern.
256 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
257 * bytes of the pattern for user defined pattern, de-authentication and
258 * disassociation patterns for all types of possible frames recieved
259 * of those types.
260 */
261
217struct ath9k_hw_capabilities { 262struct ath9k_hw_capabilities {
218 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 263 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
219 u16 rts_aggr_limit; 264 u16 rts_aggr_limit;
@@ -815,6 +860,9 @@ struct ath_hw {
815 struct ar5416IniArray iniBank7; 860 struct ar5416IniArray iniBank7;
816 struct ar5416IniArray iniAddac; 861 struct ar5416IniArray iniAddac;
817 struct ar5416IniArray iniPcieSerdes; 862 struct ar5416IniArray iniPcieSerdes;
863#ifdef CONFIG_PM_SLEEP
864 struct ar5416IniArray iniPcieSerdesWow;
865#endif
818 struct ar5416IniArray iniPcieSerdesLowPower; 866 struct ar5416IniArray iniPcieSerdesLowPower;
819 struct ar5416IniArray iniModesFastClock; 867 struct ar5416IniArray iniModesFastClock;
820 struct ar5416IniArray iniAdditional; 868 struct ar5416IniArray iniAdditional;
@@ -863,6 +911,9 @@ struct ath_hw {
863 /* Enterprise mode cap */ 911 /* Enterprise mode cap */
864 u32 ent_mode; 912 u32 ent_mode;
865 913
914#ifdef CONFIG_PM_SLEEP
915 u32 wow_event_mask;
916#endif
866 bool is_clk_25mhz; 917 bool is_clk_25mhz;
867 int (*get_mac_revision)(void); 918 int (*get_mac_revision)(void);
868 int (*external_reset)(void); 919 int (*external_reset)(void);
@@ -943,7 +994,7 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah);
943u64 ath9k_hw_gettsf64(struct ath_hw *ah); 994u64 ath9k_hw_gettsf64(struct ath_hw *ah);
944void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 995void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
945void ath9k_hw_reset_tsf(struct ath_hw *ah); 996void ath9k_hw_reset_tsf(struct ath_hw *ah);
946void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 997void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
947void ath9k_hw_init_global_settings(struct ath_hw *ah); 998void ath9k_hw_init_global_settings(struct ath_hw *ah);
948u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 999u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
949void ath9k_hw_set11nmac2040(struct ath_hw *ah); 1000void ath9k_hw_set11nmac2040(struct ath_hw *ah);
@@ -1061,6 +1112,37 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1061} 1112}
1062#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1113#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1063 1114
1115
1116#ifdef CONFIG_PM_SLEEP
1117const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1118void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1119 u8 *user_mask, int pattern_count,
1120 int pattern_len);
1121u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1122void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1123#else
1124static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1125{
1126 return NULL;
1127}
1128static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1129 u8 *user_pattern,
1130 u8 *user_mask,
1131 int pattern_count,
1132 int pattern_len)
1133{
1134}
1135static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1136{
1137 return 0;
1138}
1139static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1140{
1141}
1142#endif
1143
1144
1145
1064#define ATH9K_CLOCK_RATE_CCK 22 1146#define ATH9K_CLOCK_RATE_CCK 22
1065#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1147#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1066#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1148#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 9dfce1a69c73..f33712140fa5 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -434,6 +434,7 @@ static int ath9k_init_queues(struct ath_softc *sc)
434 for (i = 0; i < WME_NUM_AC; i++) { 434 for (i = 0; i < WME_NUM_AC; i++) {
435 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 435 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
436 sc->tx.txq_map[i]->mac80211_qnum = i; 436 sc->tx.txq_map[i]->mac80211_qnum = i;
437 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
437 } 438 }
438 return 0; 439 return 0;
439} 440}
@@ -558,7 +559,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
558 spin_lock_init(&sc->debug.samp_lock); 559 spin_lock_init(&sc->debug.samp_lock);
559#endif 560#endif
560 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 561 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
561 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, 562 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
562 (unsigned long)sc); 563 (unsigned long)sc);
563 564
564 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 565 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
@@ -713,6 +714,24 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
713 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 714 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
714 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 715 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
715 716
717#ifdef CONFIG_PM_SLEEP
718
719 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
720 device_can_wakeup(sc->dev)) {
721
722 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
723 WIPHY_WOWLAN_DISCONNECT;
724 hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN;
725 hw->wiphy->wowlan.pattern_min_len = 1;
726 hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE;
727
728 }
729
730 atomic_set(&sc->wow_sleep_proc_intr, -1);
731 atomic_set(&sc->wow_got_bmiss_intr, -1);
732
733#endif
734
716 hw->queues = 4; 735 hw->queues = 4;
717 hw->max_rates = 4; 736 hw->max_rates = 4;
718 hw->channel_change_time = 5000; 737 hw->channel_change_time = 5000;
diff --git a/drivers/net/wireless/ath/ath9k/link.c b/drivers/net/wireless/ath/ath9k/link.c
index 91650fe50461..d4549e9aac5c 100644
--- a/drivers/net/wireless/ath/ath9k/link.c
+++ b/drivers/net/wireless/ath/ath9k/link.c
@@ -50,8 +50,7 @@ void ath_tx_complete_poll_work(struct work_struct *work)
50 if (needreset) { 50 if (needreset) {
51 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, 51 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
52 "tx hung, resetting the chip\n"); 52 "tx hung, resetting the chip\n");
53 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG); 53 ath9k_queue_reset(sc, RESET_TYPE_TX_HANG);
54 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
55 return; 54 return;
56 } 55 }
57 56
@@ -69,6 +68,7 @@ void ath_hw_check(struct work_struct *work)
69 unsigned long flags; 68 unsigned long flags;
70 int busy; 69 int busy;
71 u8 is_alive, nbeacon = 1; 70 u8 is_alive, nbeacon = 1;
71 enum ath_reset_type type;
72 72
73 ath9k_ps_wakeup(sc); 73 ath9k_ps_wakeup(sc);
74 is_alive = ath9k_hw_check_alive(sc->sc_ah); 74 is_alive = ath9k_hw_check_alive(sc->sc_ah);
@@ -78,7 +78,7 @@ void ath_hw_check(struct work_struct *work)
78 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) { 78 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
79 ath_dbg(common, RESET, 79 ath_dbg(common, RESET,
80 "DCU stuck is detected. Schedule chip reset\n"); 80 "DCU stuck is detected. Schedule chip reset\n");
81 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG); 81 type = RESET_TYPE_MAC_HANG;
82 goto sched_reset; 82 goto sched_reset;
83 } 83 }
84 84
@@ -90,7 +90,7 @@ void ath_hw_check(struct work_struct *work)
90 busy, sc->hw_busy_count + 1); 90 busy, sc->hw_busy_count + 1);
91 if (busy >= 99) { 91 if (busy >= 99) {
92 if (++sc->hw_busy_count >= 3) { 92 if (++sc->hw_busy_count >= 3) {
93 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG); 93 type = RESET_TYPE_BB_HANG;
94 goto sched_reset; 94 goto sched_reset;
95 } 95 }
96 } else if (busy >= 0) { 96 } else if (busy >= 0) {
@@ -102,7 +102,7 @@ void ath_hw_check(struct work_struct *work)
102 goto out; 102 goto out;
103 103
104sched_reset: 104sched_reset:
105 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 105 ath9k_queue_reset(sc, type);
106out: 106out:
107 ath9k_ps_restore(sc); 107 ath9k_ps_restore(sc);
108} 108}
@@ -119,8 +119,7 @@ static bool ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
119 count++; 119 count++;
120 if (count == 3) { 120 if (count == 3) {
121 ath_dbg(common, RESET, "PLL WAR, resetting the chip\n"); 121 ath_dbg(common, RESET, "PLL WAR, resetting the chip\n");
122 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG); 122 ath9k_queue_reset(sc, RESET_TYPE_PLL_HANG);
123 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
124 count = 0; 123 count = 0;
125 return true; 124 return true;
126 } 125 }
@@ -432,26 +431,72 @@ set_timer:
432 } 431 }
433} 432}
434 433
435void ath_start_ani(struct ath_common *common) 434void ath_start_ani(struct ath_softc *sc)
436{ 435{
437 struct ath_hw *ah = common->ah; 436 struct ath_hw *ah = sc->sc_ah;
437 struct ath_common *common = ath9k_hw_common(ah);
438 unsigned long timestamp = jiffies_to_msecs(jiffies); 438 unsigned long timestamp = jiffies_to_msecs(jiffies);
439 struct ath_softc *sc = (struct ath_softc *) common->priv;
440
441 if (!test_bit(SC_OP_ANI_RUN, &sc->sc_flags))
442 return;
443 439
444 if (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 440 if (common->disable_ani ||
441 !test_bit(SC_OP_ANI_RUN, &sc->sc_flags) ||
442 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
445 return; 443 return;
446 444
447 common->ani.longcal_timer = timestamp; 445 common->ani.longcal_timer = timestamp;
448 common->ani.shortcal_timer = timestamp; 446 common->ani.shortcal_timer = timestamp;
449 common->ani.checkani_timer = timestamp; 447 common->ani.checkani_timer = timestamp;
450 448
449 ath_dbg(common, ANI, "Starting ANI\n");
451 mod_timer(&common->ani.timer, 450 mod_timer(&common->ani.timer,
452 jiffies + msecs_to_jiffies((u32)ah->config.ani_poll_interval)); 451 jiffies + msecs_to_jiffies((u32)ah->config.ani_poll_interval));
453} 452}
454 453
454void ath_stop_ani(struct ath_softc *sc)
455{
456 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
457
458 ath_dbg(common, ANI, "Stopping ANI\n");
459 del_timer_sync(&common->ani.timer);
460}
461
462void ath_check_ani(struct ath_softc *sc)
463{
464 struct ath_hw *ah = sc->sc_ah;
465 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
466
467 /*
468 * Check for the various conditions in which ANI has to
469 * be stopped.
470 */
471 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
472 if (!cur_conf->enable_beacon)
473 goto stop_ani;
474 } else if (ah->opmode == NL80211_IFTYPE_AP) {
475 if (!cur_conf->enable_beacon) {
476 /*
477 * Disable ANI only when there are no
478 * associated stations.
479 */
480 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
481 goto stop_ani;
482 }
483 } else if (ah->opmode == NL80211_IFTYPE_STATION) {
484 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
485 goto stop_ani;
486 }
487
488 if (!test_bit(SC_OP_ANI_RUN, &sc->sc_flags)) {
489 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
490 ath_start_ani(sc);
491 }
492
493 return;
494
495stop_ani:
496 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
497 ath_stop_ani(sc);
498}
499
455void ath_update_survey_nf(struct ath_softc *sc, int channel) 500void ath_update_survey_nf(struct ath_softc *sc, int channel)
456{ 501{
457 struct ath_hw *ah = sc->sc_ah; 502 struct ath_hw *ah = sc->sc_ah;
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 248e5b24acfa..6049d8b82855 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -19,6 +19,9 @@
19#include "ath9k.h" 19#include "ath9k.h"
20#include "btcoex.h" 20#include "btcoex.h"
21 21
22static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
22u8 ath9k_parse_mpdudensity(u8 mpdudensity) 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23{ 26{
24 /* 27 /*
@@ -167,8 +170,6 @@ static void ath_cancel_work(struct ath_softc *sc)
167 170
168static void ath_restart_work(struct ath_softc *sc) 171static void ath_restart_work(struct ath_softc *sc)
169{ 172{
170 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
171
172 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 173 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
173 174
174 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || 175 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
@@ -177,21 +178,18 @@ static void ath_restart_work(struct ath_softc *sc)
177 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 178 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
178 179
179 ath_start_rx_poll(sc, 3); 180 ath_start_rx_poll(sc, 3);
180 181 ath_start_ani(sc);
181 if (!common->disable_ani)
182 ath_start_ani(common);
183} 182}
184 183
185static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) 184static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
186{ 185{
187 struct ath_hw *ah = sc->sc_ah; 186 struct ath_hw *ah = sc->sc_ah;
188 struct ath_common *common = ath9k_hw_common(ah);
189 bool ret = true; 187 bool ret = true;
190 188
191 ieee80211_stop_queues(sc->hw); 189 ieee80211_stop_queues(sc->hw);
192 190
193 sc->hw_busy_count = 0; 191 sc->hw_busy_count = 0;
194 del_timer_sync(&common->ani.timer); 192 ath_stop_ani(sc);
195 del_timer_sync(&sc->rx_poll_timer); 193 del_timer_sync(&sc->rx_poll_timer);
196 194
197 ath9k_debug_samp_bb_mac(sc); 195 ath9k_debug_samp_bb_mac(sc);
@@ -236,7 +234,7 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
236 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 234 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
237 goto work; 235 goto work;
238 236
239 ath_set_beacon(sc); 237 ath9k_set_beacon(sc);
240 238
241 if (ah->opmode == NL80211_IFTYPE_STATION && 239 if (ah->opmode == NL80211_IFTYPE_STATION &&
242 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 240 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
@@ -365,6 +363,7 @@ void ath9k_tasklet(unsigned long data)
365 struct ath_softc *sc = (struct ath_softc *)data; 363 struct ath_softc *sc = (struct ath_softc *)data;
366 struct ath_hw *ah = sc->sc_ah; 364 struct ath_hw *ah = sc->sc_ah;
367 struct ath_common *common = ath9k_hw_common(ah); 365 struct ath_common *common = ath9k_hw_common(ah);
366 enum ath_reset_type type;
368 unsigned long flags; 367 unsigned long flags;
369 u32 status = sc->intrstatus; 368 u32 status = sc->intrstatus;
370 u32 rxmask; 369 u32 rxmask;
@@ -374,18 +373,13 @@ void ath9k_tasklet(unsigned long data)
374 373
375 if ((status & ATH9K_INT_FATAL) || 374 if ((status & ATH9K_INT_FATAL) ||
376 (status & ATH9K_INT_BB_WATCHDOG)) { 375 (status & ATH9K_INT_BB_WATCHDOG)) {
377#ifdef CONFIG_ATH9K_DEBUGFS
378 enum ath_reset_type type;
379 376
380 if (status & ATH9K_INT_FATAL) 377 if (status & ATH9K_INT_FATAL)
381 type = RESET_TYPE_FATAL_INT; 378 type = RESET_TYPE_FATAL_INT;
382 else 379 else
383 type = RESET_TYPE_BB_WATCHDOG; 380 type = RESET_TYPE_BB_WATCHDOG;
384 381
385 RESET_STAT_INC(sc, type); 382 ath9k_queue_reset(sc, type);
386#endif
387 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
388 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
389 goto out; 383 goto out;
390 } 384 }
391 385
@@ -493,6 +487,17 @@ irqreturn_t ath_isr(int irq, void *dev)
493 if (status & SCHED_INTR) 487 if (status & SCHED_INTR)
494 sched = true; 488 sched = true;
495 489
490#ifdef CONFIG_PM_SLEEP
491 if (status & ATH9K_INT_BMISS) {
492 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
493 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
494 atomic_inc(&sc->wow_got_bmiss_intr);
495 atomic_dec(&sc->wow_sleep_proc_intr);
496 }
497 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
498 }
499#endif
500
496 /* 501 /*
497 * If a FATAL or RXORN interrupt is received, we have to reset the 502 * If a FATAL or RXORN interrupt is received, we have to reset the
498 * chip immediately. 503 * chip immediately.
@@ -575,6 +580,15 @@ static int ath_reset(struct ath_softc *sc, bool retry_tx)
575 return r; 580 return r;
576} 581}
577 582
583void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
584{
585#ifdef CONFIG_ATH9K_DEBUGFS
586 RESET_STAT_INC(sc, type);
587#endif
588 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
589 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
590}
591
578void ath_reset_work(struct work_struct *work) 592void ath_reset_work(struct work_struct *work)
579{ 593{
580 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 594 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
@@ -841,16 +855,6 @@ bool ath9k_uses_beacons(int type)
841 } 855 }
842} 856}
843 857
844static void ath9k_reclaim_beacon(struct ath_softc *sc,
845 struct ieee80211_vif *vif)
846{
847 struct ath_vif *avp = (void *)vif->drv_priv;
848
849 ath9k_set_beaconing_status(sc, false);
850 ath_beacon_return(sc, avp);
851 ath9k_set_beaconing_status(sc, true);
852}
853
854static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 858static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
855{ 859{
856 struct ath9k_vif_iter_data *iter_data = data; 860 struct ath9k_vif_iter_data *iter_data = data;
@@ -882,6 +886,18 @@ static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
882 } 886 }
883} 887}
884 888
889static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
890{
891 struct ath_softc *sc = data;
892 struct ath_vif *avp = (void *)vif->drv_priv;
893
894 if (vif->type != NL80211_IFTYPE_STATION)
895 return;
896
897 if (avp->primary_sta_vif)
898 ath9k_set_assoc_state(sc, vif);
899}
900
885/* Called with sc->mutex held. */ 901/* Called with sc->mutex held. */
886void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 902void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
887 struct ieee80211_vif *vif, 903 struct ieee80211_vif *vif,
@@ -915,21 +931,18 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
915 struct ath_hw *ah = sc->sc_ah; 931 struct ath_hw *ah = sc->sc_ah;
916 struct ath_common *common = ath9k_hw_common(ah); 932 struct ath_common *common = ath9k_hw_common(ah);
917 struct ath9k_vif_iter_data iter_data; 933 struct ath9k_vif_iter_data iter_data;
934 enum nl80211_iftype old_opmode = ah->opmode;
918 935
919 ath9k_calculate_iter_data(hw, vif, &iter_data); 936 ath9k_calculate_iter_data(hw, vif, &iter_data);
920 937
921 /* Set BSSID mask. */
922 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 938 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
923 ath_hw_setbssidmask(common); 939 ath_hw_setbssidmask(common);
924 940
925 /* Set op-mode & TSF */
926 if (iter_data.naps > 0) { 941 if (iter_data.naps > 0) {
927 ath9k_hw_set_tsfadjust(ah, 1); 942 ath9k_hw_set_tsfadjust(ah, true);
928 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
929 ah->opmode = NL80211_IFTYPE_AP; 943 ah->opmode = NL80211_IFTYPE_AP;
930 } else { 944 } else {
931 ath9k_hw_set_tsfadjust(ah, 0); 945 ath9k_hw_set_tsfadjust(ah, false);
932 clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
933 946
934 if (iter_data.nmeshes) 947 if (iter_data.nmeshes)
935 ah->opmode = NL80211_IFTYPE_MESH_POINT; 948 ah->opmode = NL80211_IFTYPE_MESH_POINT;
@@ -941,9 +954,8 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
941 ah->opmode = NL80211_IFTYPE_STATION; 954 ah->opmode = NL80211_IFTYPE_STATION;
942 } 955 }
943 956
944 /* 957 ath9k_hw_setopmode(ah);
945 * Enable MIB interrupts when there are hardware phy counters. 958
946 */
947 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 959 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
948 ah->imask |= ATH9K_INT_TSFOOR; 960 ah->imask |= ATH9K_INT_TSFOOR;
949 else 961 else
@@ -951,34 +963,15 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
951 963
952 ath9k_hw_set_interrupts(ah); 964 ath9k_hw_set_interrupts(ah);
953 965
954 /* Set up ANI */ 966 /*
955 if (iter_data.naps > 0) { 967 * If we are changing the opmode to STATION,
956 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 968 * a beacon sync needs to be done.
957 969 */
958 if (!common->disable_ani) { 970 if (ah->opmode == NL80211_IFTYPE_STATION &&
959 set_bit(SC_OP_ANI_RUN, &sc->sc_flags); 971 old_opmode == NL80211_IFTYPE_AP &&
960 ath_start_ani(common); 972 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
961 } 973 ieee80211_iterate_active_interfaces_atomic(sc->hw,
962 974 ath9k_sta_vif_iter, sc);
963 } else {
964 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
965 del_timer_sync(&common->ani.timer);
966 }
967}
968
969/* Called with sc->mutex held, vif counts set up properly. */
970static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
971 struct ieee80211_vif *vif)
972{
973 struct ath_softc *sc = hw->priv;
974
975 ath9k_calculate_summary_state(hw, vif);
976
977 if (ath9k_uses_beacons(vif->type)) {
978 /* Reserve a beacon slot for the vif */
979 ath9k_set_beaconing_status(sc, false);
980 ath_beacon_alloc(sc, vif);
981 ath9k_set_beaconing_status(sc, true);
982 } 975 }
983} 976}
984 977
@@ -1021,7 +1014,10 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
1021 1014
1022 sc->nvifs++; 1015 sc->nvifs++;
1023 1016
1024 ath9k_do_vif_add_setup(hw, vif); 1017 ath9k_calculate_summary_state(hw, vif);
1018 if (ath9k_uses_beacons(vif->type))
1019 ath9k_beacon_assign_slot(sc, vif);
1020
1025out: 1021out:
1026 mutex_unlock(&sc->mutex); 1022 mutex_unlock(&sc->mutex);
1027 ath9k_ps_restore(sc); 1023 ath9k_ps_restore(sc);
@@ -1038,6 +1034,7 @@ static int ath9k_change_interface(struct ieee80211_hw *hw,
1038 int ret = 0; 1034 int ret = 0;
1039 1035
1040 ath_dbg(common, CONFIG, "Change Interface\n"); 1036 ath_dbg(common, CONFIG, "Change Interface\n");
1037
1041 mutex_lock(&sc->mutex); 1038 mutex_lock(&sc->mutex);
1042 ath9k_ps_wakeup(sc); 1039 ath9k_ps_wakeup(sc);
1043 1040
@@ -1050,15 +1047,16 @@ static int ath9k_change_interface(struct ieee80211_hw *hw,
1050 } 1047 }
1051 } 1048 }
1052 1049
1053 /* Clean up old vif stuff */
1054 if (ath9k_uses_beacons(vif->type)) 1050 if (ath9k_uses_beacons(vif->type))
1055 ath9k_reclaim_beacon(sc, vif); 1051 ath9k_beacon_remove_slot(sc, vif);
1056 1052
1057 /* Add new settings */
1058 vif->type = new_type; 1053 vif->type = new_type;
1059 vif->p2p = p2p; 1054 vif->p2p = p2p;
1060 1055
1061 ath9k_do_vif_add_setup(hw, vif); 1056 ath9k_calculate_summary_state(hw, vif);
1057 if (ath9k_uses_beacons(vif->type))
1058 ath9k_beacon_assign_slot(sc, vif);
1059
1062out: 1060out:
1063 ath9k_ps_restore(sc); 1061 ath9k_ps_restore(sc);
1064 mutex_unlock(&sc->mutex); 1062 mutex_unlock(&sc->mutex);
@@ -1078,9 +1076,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
1078 1076
1079 sc->nvifs--; 1077 sc->nvifs--;
1080 1078
1081 /* Reclaim beacon resources */
1082 if (ath9k_uses_beacons(vif->type)) 1079 if (ath9k_uses_beacons(vif->type))
1083 ath9k_reclaim_beacon(sc, vif); 1080 ath9k_beacon_remove_slot(sc, vif);
1084 1081
1085 ath9k_calculate_summary_state(hw, NULL); 1082 ath9k_calculate_summary_state(hw, NULL);
1086 1083
@@ -1377,21 +1374,18 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
1377 qi.tqi_aifs = params->aifs; 1374 qi.tqi_aifs = params->aifs;
1378 qi.tqi_cwmin = params->cw_min; 1375 qi.tqi_cwmin = params->cw_min;
1379 qi.tqi_cwmax = params->cw_max; 1376 qi.tqi_cwmax = params->cw_max;
1380 qi.tqi_burstTime = params->txop; 1377 qi.tqi_burstTime = params->txop * 32;
1381 1378
1382 ath_dbg(common, CONFIG, 1379 ath_dbg(common, CONFIG,
1383 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1380 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1384 queue, txq->axq_qnum, params->aifs, params->cw_min, 1381 queue, txq->axq_qnum, params->aifs, params->cw_min,
1385 params->cw_max, params->txop); 1382 params->cw_max, params->txop);
1386 1383
1384 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1387 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1385 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1388 if (ret) 1386 if (ret)
1389 ath_err(common, "TXQ Update failed\n"); 1387 ath_err(common, "TXQ Update failed\n");
1390 1388
1391 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1392 if (queue == WME_AC_BE && !ret)
1393 ath_beaconq_config(sc);
1394
1395 mutex_unlock(&sc->mutex); 1389 mutex_unlock(&sc->mutex);
1396 ath9k_ps_restore(sc); 1390 ath9k_ps_restore(sc);
1397 1391
@@ -1460,86 +1454,53 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
1460 1454
1461 return ret; 1455 return ret;
1462} 1456}
1463static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1457
1458static void ath9k_set_assoc_state(struct ath_softc *sc,
1459 struct ieee80211_vif *vif)
1464{ 1460{
1465 struct ath_softc *sc = data;
1466 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1461 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1467 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1468 struct ath_vif *avp = (void *)vif->drv_priv; 1462 struct ath_vif *avp = (void *)vif->drv_priv;
1463 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1469 unsigned long flags; 1464 unsigned long flags;
1465
1466 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1467 avp->primary_sta_vif = true;
1468
1470 /* 1469 /*
1471 * Skip iteration if primary station vif's bss info 1470 * Set the AID, BSSID and do beacon-sync only when
1472 * was not changed 1471 * the HW opmode is STATION.
1472 *
1473 * But the primary bit is set above in any case.
1473 */ 1474 */
1474 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1475 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1475 return; 1476 return;
1476 1477
1477 if (bss_conf->assoc) { 1478 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1478 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1479 common->curaid = bss_conf->aid;
1479 avp->primary_sta_vif = true; 1480 ath9k_hw_write_associd(sc->sc_ah);
1480 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1481 common->curaid = bss_conf->aid;
1482 ath9k_hw_write_associd(sc->sc_ah);
1483 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1484 bss_conf->aid, common->curbssid);
1485 ath_beacon_config(sc, vif);
1486 /*
1487 * Request a re-configuration of Beacon related timers
1488 * on the receipt of the first Beacon frame (i.e.,
1489 * after time sync with the AP).
1490 */
1491 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1492 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1493 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1494
1495 /* Reset rssi stats */
1496 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1497 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1498 1481
1499 ath_start_rx_poll(sc, 3); 1482 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1483 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1500 1484
1501 if (!common->disable_ani) { 1485 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1502 set_bit(SC_OP_ANI_RUN, &sc->sc_flags); 1486 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1503 ath_start_ani(common); 1487 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1504 }
1505 1488
1506 } 1489 ath_dbg(common, CONFIG,
1490 "Primary Station interface: %pM, BSSID: %pM\n",
1491 vif->addr, common->curbssid);
1507} 1492}
1508 1493
1509static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) 1494static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1510{ 1495{
1511 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1496 struct ath_softc *sc = data;
1512 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1497 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1513 struct ath_vif *avp = (void *)vif->drv_priv;
1514 1498
1515 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1499 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1516 return; 1500 return;
1517 1501
1518 /* Reconfigure bss info */ 1502 if (bss_conf->assoc)
1519 if (avp->primary_sta_vif && !bss_conf->assoc) { 1503 ath9k_set_assoc_state(sc, vif);
1520 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
1521 common->curaid, common->curbssid);
1522 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1523 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1524 avp->primary_sta_vif = false;
1525 memset(common->curbssid, 0, ETH_ALEN);
1526 common->curaid = 0;
1527 }
1528
1529 ieee80211_iterate_active_interfaces_atomic(
1530 sc->hw, ath9k_bss_iter, sc);
1531
1532 /*
1533 * None of station vifs are associated.
1534 * Clear bssid & aid
1535 */
1536 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
1537 ath9k_hw_write_associd(sc->sc_ah);
1538 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1539 del_timer_sync(&common->ani.timer);
1540 del_timer_sync(&sc->rx_poll_timer);
1541 memset(&sc->caldata, 0, sizeof(sc->caldata));
1542 }
1543} 1504}
1544 1505
1545static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1506static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
@@ -1547,6 +1508,11 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1547 struct ieee80211_bss_conf *bss_conf, 1508 struct ieee80211_bss_conf *bss_conf,
1548 u32 changed) 1509 u32 changed)
1549{ 1510{
1511#define CHECK_ANI \
1512 (BSS_CHANGED_ASSOC | \
1513 BSS_CHANGED_IBSS | \
1514 BSS_CHANGED_BEACON_ENABLED)
1515
1550 struct ath_softc *sc = hw->priv; 1516 struct ath_softc *sc = hw->priv;
1551 struct ath_hw *ah = sc->sc_ah; 1517 struct ath_hw *ah = sc->sc_ah;
1552 struct ath_common *common = ath9k_hw_common(ah); 1518 struct ath_common *common = ath9k_hw_common(ah);
@@ -1557,53 +1523,41 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1557 mutex_lock(&sc->mutex); 1523 mutex_lock(&sc->mutex);
1558 1524
1559 if (changed & BSS_CHANGED_ASSOC) { 1525 if (changed & BSS_CHANGED_ASSOC) {
1560 ath9k_config_bss(sc, vif); 1526 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1527 bss_conf->bssid, bss_conf->assoc);
1561 1528
1562 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n", 1529 if (avp->primary_sta_vif && !bss_conf->assoc) {
1563 common->curbssid, common->curaid); 1530 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1531 avp->primary_sta_vif = false;
1532
1533 if (ah->opmode == NL80211_IFTYPE_STATION)
1534 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1535 }
1536
1537 ieee80211_iterate_active_interfaces_atomic(sc->hw,
1538 ath9k_bss_assoc_iter, sc);
1539
1540 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1541 ah->opmode == NL80211_IFTYPE_STATION) {
1542 memset(common->curbssid, 0, ETH_ALEN);
1543 common->curaid = 0;
1544 ath9k_hw_write_associd(sc->sc_ah);
1545 }
1564 } 1546 }
1565 1547
1566 if (changed & BSS_CHANGED_IBSS) { 1548 if (changed & BSS_CHANGED_IBSS) {
1567 /* There can be only one vif available */
1568 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1549 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1569 common->curaid = bss_conf->aid; 1550 common->curaid = bss_conf->aid;
1570 ath9k_hw_write_associd(sc->sc_ah); 1551 ath9k_hw_write_associd(sc->sc_ah);
1571
1572 if (bss_conf->ibss_joined) {
1573 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1574
1575 if (!common->disable_ani) {
1576 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1577 ath_start_ani(common);
1578 }
1579
1580 } else {
1581 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1582 del_timer_sync(&common->ani.timer);
1583 del_timer_sync(&sc->rx_poll_timer);
1584 }
1585 } 1552 }
1586 1553
1587 /* 1554 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1588 * In case of AP mode, the HW TSF has to be reset 1555 (changed & BSS_CHANGED_BEACON_INT)) {
1589 * when the beacon interval changes. 1556 if (ah->opmode == NL80211_IFTYPE_AP &&
1590 */ 1557 bss_conf->enable_beacon)
1591 if ((changed & BSS_CHANGED_BEACON_INT) && 1558 ath9k_set_tsfadjust(sc, vif);
1592 (vif->type == NL80211_IFTYPE_AP)) 1559 if (ath9k_allow_beacon_config(sc, vif))
1593 set_bit(SC_OP_TSF_RESET, &sc->sc_flags); 1560 ath9k_beacon_config(sc, vif, changed);
1594
1595 /* Configure beaconing (AP, IBSS, MESH) */
1596 if (ath9k_uses_beacons(vif->type) &&
1597 ((changed & BSS_CHANGED_BEACON) ||
1598 (changed & BSS_CHANGED_BEACON_ENABLED) ||
1599 (changed & BSS_CHANGED_BEACON_INT))) {
1600 ath9k_set_beaconing_status(sc, false);
1601 if (bss_conf->enable_beacon)
1602 ath_beacon_alloc(sc, vif);
1603 else
1604 avp->is_bslot_active = false;
1605 ath_beacon_config(sc, vif);
1606 ath9k_set_beaconing_status(sc, true);
1607 } 1561 }
1608 1562
1609 if (changed & BSS_CHANGED_ERP_SLOT) { 1563 if (changed & BSS_CHANGED_ERP_SLOT) {
@@ -1625,8 +1579,13 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1625 } 1579 }
1626 } 1580 }
1627 1581
1582 if (changed & CHECK_ANI)
1583 ath_check_ani(sc);
1584
1628 mutex_unlock(&sc->mutex); 1585 mutex_unlock(&sc->mutex);
1629 ath9k_ps_restore(sc); 1586 ath9k_ps_restore(sc);
1587
1588#undef CHECK_ANI
1630} 1589}
1631 1590
1632static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1591static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
@@ -1855,10 +1814,11 @@ static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1855 if (!vif) 1814 if (!vif)
1856 return 0; 1815 return 0;
1857 1816
1858 avp = (void *)vif->drv_priv; 1817 if (!vif->bss_conf.enable_beacon)
1859 if (!avp->is_bslot_active)
1860 return 0; 1818 return 0;
1861 1819
1820 avp = (void *)vif->drv_priv;
1821
1862 if (!sc->beacon.tx_processed && !edma) { 1822 if (!sc->beacon.tx_processed && !edma) {
1863 tasklet_disable(&sc->bcon_tasklet); 1823 tasklet_disable(&sc->bcon_tasklet);
1864 1824
@@ -1912,12 +1872,29 @@ static u32 fill_chainmask(u32 cap, u32 new)
1912 return filled; 1872 return filled;
1913} 1873}
1914 1874
1875static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1876{
1877 switch (val & 0x7) {
1878 case 0x1:
1879 case 0x3:
1880 case 0x7:
1881 return true;
1882 case 0x2:
1883 return (ah->caps.rx_chainmask == 1);
1884 default:
1885 return false;
1886 }
1887}
1888
1915static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1889static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1916{ 1890{
1917 struct ath_softc *sc = hw->priv; 1891 struct ath_softc *sc = hw->priv;
1918 struct ath_hw *ah = sc->sc_ah; 1892 struct ath_hw *ah = sc->sc_ah;
1919 1893
1920 if (!rx_ant || !tx_ant) 1894 if (ah->caps.rx_chainmask != 1)
1895 rx_ant |= tx_ant;
1896
1897 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1921 return -EINVAL; 1898 return -EINVAL;
1922 1899
1923 sc->ant_rx = rx_ant; 1900 sc->ant_rx = rx_ant;
@@ -2075,6 +2052,362 @@ static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2075#endif 2052#endif
2076 2053
2077 2054
2055#ifdef CONFIG_PM_SLEEP
2056
2057static void ath9k_wow_map_triggers(struct ath_softc *sc,
2058 struct cfg80211_wowlan *wowlan,
2059 u32 *wow_triggers)
2060{
2061 if (wowlan->disconnect)
2062 *wow_triggers |= AH_WOW_LINK_CHANGE |
2063 AH_WOW_BEACON_MISS;
2064 if (wowlan->magic_pkt)
2065 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2066
2067 if (wowlan->n_patterns)
2068 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2069
2070 sc->wow_enabled = *wow_triggers;
2071
2072}
2073
2074static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2075{
2076 struct ath_hw *ah = sc->sc_ah;
2077 struct ath_common *common = ath9k_hw_common(ah);
2078 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2079 int pattern_count = 0;
2080 int i, byte_cnt;
2081 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2082 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2083
2084 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2085 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2086
2087 /*
2088 * Create Dissassociate / Deauthenticate packet filter
2089 *
2090 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2091 * +--------------+----------+---------+--------+--------+----
2092 * + Frame Control+ Duration + DA + SA + BSSID +
2093 * +--------------+----------+---------+--------+--------+----
2094 *
2095 * The above is the management frame format for disassociate/
2096 * deauthenticate pattern, from this we need to match the first byte
2097 * of 'Frame Control' and DA, SA, and BSSID fields
2098 * (skipping 2nd byte of FC and Duration feild.
2099 *
2100 * Disassociate pattern
2101 * --------------------
2102 * Frame control = 00 00 1010
2103 * DA, SA, BSSID = x:x:x:x:x:x
2104 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2105 * | x:x:x:x:x:x -- 22 bytes
2106 *
2107 * Deauthenticate pattern
2108 * ----------------------
2109 * Frame control = 00 00 1100
2110 * DA, SA, BSSID = x:x:x:x:x:x
2111 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2112 * | x:x:x:x:x:x -- 22 bytes
2113 */
2114
2115 /* Create Disassociate Pattern first */
2116
2117 byte_cnt = 0;
2118
2119 /* Fill out the mask with all FF's */
2120
2121 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2122 dis_deauth_mask[i] = 0xff;
2123
2124 /* copy the first byte of frame control field */
2125 dis_deauth_pattern[byte_cnt] = 0xa0;
2126 byte_cnt++;
2127
2128 /* skip 2nd byte of frame control and Duration field */
2129 byte_cnt += 3;
2130
2131 /*
2132 * need not match the destination mac address, it can be a broadcast
2133 * mac address or an unicast to this station
2134 */
2135 byte_cnt += 6;
2136
2137 /* copy the source mac address */
2138 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2139
2140 byte_cnt += 6;
2141
2142 /* copy the bssid, its same as the source mac address */
2143
2144 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2145
2146 /* Create Disassociate pattern mask */
2147
2148 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2149
2150 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2151 /*
2152 * for AR9280, because of hardware limitation, the
2153 * first 4 bytes have to be matched for all patterns.
2154 * the mask for disassociation and de-auth pattern
2155 * matching need to enable the first 4 bytes.
2156 * also the duration field needs to be filled.
2157 */
2158 dis_deauth_mask[0] = 0xf0;
2159
2160 /*
2161 * fill in duration field
2162 FIXME: what is the exact value ?
2163 */
2164 dis_deauth_pattern[2] = 0xff;
2165 dis_deauth_pattern[3] = 0xff;
2166 } else {
2167 dis_deauth_mask[0] = 0xfe;
2168 }
2169
2170 dis_deauth_mask[1] = 0x03;
2171 dis_deauth_mask[2] = 0xc0;
2172 } else {
2173 dis_deauth_mask[0] = 0xef;
2174 dis_deauth_mask[1] = 0x3f;
2175 dis_deauth_mask[2] = 0x00;
2176 dis_deauth_mask[3] = 0xfc;
2177 }
2178
2179 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2180
2181 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2182 pattern_count, byte_cnt);
2183
2184 pattern_count++;
2185 /*
2186 * for de-authenticate pattern, only the first byte of the frame
2187 * control field gets changed from 0xA0 to 0xC0
2188 */
2189 dis_deauth_pattern[0] = 0xC0;
2190
2191 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2192 pattern_count, byte_cnt);
2193
2194}
2195
2196static void ath9k_wow_add_pattern(struct ath_softc *sc,
2197 struct cfg80211_wowlan *wowlan)
2198{
2199 struct ath_hw *ah = sc->sc_ah;
2200 struct ath9k_wow_pattern *wow_pattern = NULL;
2201 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2202 int mask_len;
2203 s8 i = 0;
2204
2205 if (!wowlan->n_patterns)
2206 return;
2207
2208 /*
2209 * Add the new user configured patterns
2210 */
2211 for (i = 0; i < wowlan->n_patterns; i++) {
2212
2213 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2214
2215 if (!wow_pattern)
2216 return;
2217
2218 /*
2219 * TODO: convert the generic user space pattern to
2220 * appropriate chip specific/802.11 pattern.
2221 */
2222
2223 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2224 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2225 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2226 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2227 patterns[i].pattern_len);
2228 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2229 wow_pattern->pattern_len = patterns[i].pattern_len;
2230
2231 /*
2232 * just need to take care of deauth and disssoc pattern,
2233 * make sure we don't overwrite them.
2234 */
2235
2236 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2237 wow_pattern->mask_bytes,
2238 i + 2,
2239 wow_pattern->pattern_len);
2240 kfree(wow_pattern);
2241
2242 }
2243
2244}
2245
2246static int ath9k_suspend(struct ieee80211_hw *hw,
2247 struct cfg80211_wowlan *wowlan)
2248{
2249 struct ath_softc *sc = hw->priv;
2250 struct ath_hw *ah = sc->sc_ah;
2251 struct ath_common *common = ath9k_hw_common(ah);
2252 u32 wow_triggers_enabled = 0;
2253 int ret = 0;
2254
2255 mutex_lock(&sc->mutex);
2256
2257 ath_cancel_work(sc);
2258 del_timer_sync(&common->ani.timer);
2259 del_timer_sync(&sc->rx_poll_timer);
2260
2261 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2262 ath_dbg(common, ANY, "Device not present\n");
2263 ret = -EINVAL;
2264 goto fail_wow;
2265 }
2266
2267 if (WARN_ON(!wowlan)) {
2268 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2269 ret = -EINVAL;
2270 goto fail_wow;
2271 }
2272
2273 if (!device_can_wakeup(sc->dev)) {
2274 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2275 ret = 1;
2276 goto fail_wow;
2277 }
2278
2279 /*
2280 * none of the sta vifs are associated
2281 * and we are not currently handling multivif
2282 * cases, for instance we have to seperately
2283 * configure 'keep alive frame' for each
2284 * STA.
2285 */
2286
2287 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2288 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2289 ret = 1;
2290 goto fail_wow;
2291 }
2292
2293 if (sc->nvifs > 1) {
2294 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2295 ret = 1;
2296 goto fail_wow;
2297 }
2298
2299 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2300
2301 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2302 wow_triggers_enabled);
2303
2304 ath9k_ps_wakeup(sc);
2305
2306 ath9k_stop_btcoex(sc);
2307
2308 /*
2309 * Enable wake up on recieving disassoc/deauth
2310 * frame by default.
2311 */
2312 ath9k_wow_add_disassoc_deauth_pattern(sc);
2313
2314 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2315 ath9k_wow_add_pattern(sc, wowlan);
2316
2317 spin_lock_bh(&sc->sc_pcu_lock);
2318 /*
2319 * To avoid false wake, we enable beacon miss interrupt only
2320 * when we go to sleep. We save the current interrupt mask
2321 * so we can restore it after the system wakes up
2322 */
2323 sc->wow_intr_before_sleep = ah->imask;
2324 ah->imask &= ~ATH9K_INT_GLOBAL;
2325 ath9k_hw_disable_interrupts(ah);
2326 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2327 ath9k_hw_set_interrupts(ah);
2328 ath9k_hw_enable_interrupts(ah);
2329
2330 spin_unlock_bh(&sc->sc_pcu_lock);
2331
2332 /*
2333 * we can now sync irq and kill any running tasklets, since we already
2334 * disabled interrupts and not holding a spin lock
2335 */
2336 synchronize_irq(sc->irq);
2337 tasklet_kill(&sc->intr_tq);
2338
2339 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2340
2341 ath9k_ps_restore(sc);
2342 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2343 atomic_inc(&sc->wow_sleep_proc_intr);
2344
2345fail_wow:
2346 mutex_unlock(&sc->mutex);
2347 return ret;
2348}
2349
2350static int ath9k_resume(struct ieee80211_hw *hw)
2351{
2352 struct ath_softc *sc = hw->priv;
2353 struct ath_hw *ah = sc->sc_ah;
2354 struct ath_common *common = ath9k_hw_common(ah);
2355 u32 wow_status;
2356
2357 mutex_lock(&sc->mutex);
2358
2359 ath9k_ps_wakeup(sc);
2360
2361 spin_lock_bh(&sc->sc_pcu_lock);
2362
2363 ath9k_hw_disable_interrupts(ah);
2364 ah->imask = sc->wow_intr_before_sleep;
2365 ath9k_hw_set_interrupts(ah);
2366 ath9k_hw_enable_interrupts(ah);
2367
2368 spin_unlock_bh(&sc->sc_pcu_lock);
2369
2370 wow_status = ath9k_hw_wow_wakeup(ah);
2371
2372 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2373 /*
2374 * some devices may not pick beacon miss
2375 * as the reason they woke up so we add
2376 * that here for that shortcoming.
2377 */
2378 wow_status |= AH_WOW_BEACON_MISS;
2379 atomic_dec(&sc->wow_got_bmiss_intr);
2380 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2381 }
2382
2383 atomic_dec(&sc->wow_sleep_proc_intr);
2384
2385 if (wow_status) {
2386 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2387 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2388 }
2389
2390 ath_restart_work(sc);
2391 ath9k_start_btcoex(sc);
2392
2393 ath9k_ps_restore(sc);
2394 mutex_unlock(&sc->mutex);
2395
2396 return 0;
2397}
2398
2399static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2400{
2401 struct ath_softc *sc = hw->priv;
2402
2403 mutex_lock(&sc->mutex);
2404 device_init_wakeup(sc->dev, 1);
2405 device_set_wakeup_enable(sc->dev, enabled);
2406 mutex_unlock(&sc->mutex);
2407}
2408
2409#endif
2410
2078struct ieee80211_ops ath9k_ops = { 2411struct ieee80211_ops ath9k_ops = {
2079 .tx = ath9k_tx, 2412 .tx = ath9k_tx,
2080 .start = ath9k_start, 2413 .start = ath9k_start,
@@ -2104,6 +2437,12 @@ struct ieee80211_ops ath9k_ops = {
2104 .set_antenna = ath9k_set_antenna, 2437 .set_antenna = ath9k_set_antenna,
2105 .get_antenna = ath9k_get_antenna, 2438 .get_antenna = ath9k_get_antenna,
2106 2439
2440#ifdef CONFIG_PM_SLEEP
2441 .suspend = ath9k_suspend,
2442 .resume = ath9k_resume,
2443 .set_wakeup = ath9k_set_wakeup,
2444#endif
2445
2107#ifdef CONFIG_ATH9K_DEBUGFS 2446#ifdef CONFIG_ATH9K_DEBUGFS
2108 .get_et_sset_count = ath9k_get_et_sset_count, 2447 .get_et_sset_count = ath9k_get_et_sset_count,
2109 .get_et_stats = ath9k_get_et_stats, 2448 .get_et_stats = ath9k_get_et_stats,
diff --git a/drivers/net/wireless/ath/ath9k/mci.c b/drivers/net/wireless/ath/ath9k/mci.c
index 87acff7fdaae..fb536e7e661b 100644
--- a/drivers/net/wireless/ath/ath9k/mci.c
+++ b/drivers/net/wireless/ath/ath9k/mci.c
@@ -202,7 +202,7 @@ static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
202 case MCI_GPM_BT_CAL_REQ: 202 case MCI_GPM_BT_CAL_REQ:
203 if (mci_hw->bt_state == MCI_BT_AWAKE) { 203 if (mci_hw->bt_state == MCI_BT_AWAKE) {
204 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START); 204 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START);
205 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 205 ath9k_queue_reset(sc, RESET_TYPE_MCI);
206 } 206 }
207 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state); 207 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
208 break; 208 break;
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index aa0e83ac51f4..87b89d55e637 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -313,6 +313,9 @@ static int ath_pci_suspend(struct device *device)
313 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 313 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
314 struct ath_softc *sc = hw->priv; 314 struct ath_softc *sc = hw->priv;
315 315
316 if (sc->wow_enabled)
317 return 0;
318
316 /* The device has to be moved to FULLSLEEP forcibly. 319 /* The device has to be moved to FULLSLEEP forcibly.
317 * Otherwise the chip never moved to full sleep, 320 * Otherwise the chip never moved to full sleep,
318 * when no interface is up. 321 * when no interface is up.
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 11f3703a420a..12aca02228c2 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -553,7 +553,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
553 sc->ps_flags &= ~PS_BEACON_SYNC; 553 sc->ps_flags &= ~PS_BEACON_SYNC;
554 ath_dbg(common, PS, 554 ath_dbg(common, PS,
555 "Reconfigure Beacon timers based on timestamp from the AP\n"); 555 "Reconfigure Beacon timers based on timestamp from the AP\n");
556 ath_set_beacon(sc); 556 ath9k_set_beacon(sc);
557 } 557 }
558 558
559 if (ath_beacon_dtim_pending_cab(skb)) { 559 if (ath_beacon_dtim_pending_cab(skb)) {
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 6592c07ac646..87cac8eb7834 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -696,9 +696,12 @@
696#define AR_WA_BIT7 (1 << 7) 696#define AR_WA_BIT7 (1 << 7)
697#define AR_WA_BIT23 (1 << 23) 697#define AR_WA_BIT23 (1 << 23)
698#define AR_WA_D3_L1_DISABLE (1 << 14) 698#define AR_WA_D3_L1_DISABLE (1 << 14)
699#define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset
700 to POR (power-on-reset) */
699#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) 701#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16)
700#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) 702#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17)
701#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ 703#define AR_WA_RESET_EN (1 << 18) /* Enable PCI-Reset to
704 POR (bit 15) */
702#define AR_WA_ANALOG_SHIFT (1 << 20) 705#define AR_WA_ANALOG_SHIFT (1 << 20)
703#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 706#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */
704#define AR_WA_BIT22 (1 << 22) 707#define AR_WA_BIT22 (1 << 22)
@@ -1032,6 +1035,8 @@ enum {
1032#define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014) 1035#define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
1033#define AR_PCIE_PM_CTRL_ENA 0x00080000 1036#define AR_PCIE_PM_CTRL_ENA 0x00080000
1034 1037
1038#define AR_PCIE_PHY_REG3 0x18c08
1039
1035#define AR_NUM_GPIO 14 1040#define AR_NUM_GPIO 14
1036#define AR928X_NUM_GPIO 10 1041#define AR928X_NUM_GPIO 10
1037#define AR9285_NUM_GPIO 12 1042#define AR9285_NUM_GPIO 12
@@ -1235,6 +1240,8 @@ enum {
1235#define AR_RTC_PLL_CLKSEL 0x00000300 1240#define AR_RTC_PLL_CLKSEL 0x00000300
1236#define AR_RTC_PLL_CLKSEL_S 8 1241#define AR_RTC_PLL_CLKSEL_S 8
1237#define AR_RTC_PLL_BYPASS 0x00010000 1242#define AR_RTC_PLL_BYPASS 0x00010000
1243#define AR_RTC_PLL_NOPWD 0x00040000
1244#define AR_RTC_PLL_NOPWD_S 18
1238 1245
1239#define PLL3 0x16188 1246#define PLL3 0x16188
1240#define PLL3_DO_MEAS_MASK 0x40000000 1247#define PLL3_DO_MEAS_MASK 0x40000000
@@ -1887,6 +1894,8 @@ enum {
1887#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1894#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000
1888#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 1895#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000
1889 1896
1897#define AR_PCU_MISC_MODE3 0x83d0
1898
1890#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 1899#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358
1891#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1900#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400
1892#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1901#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000
@@ -1909,6 +1918,140 @@ enum {
1909#define AR_RATE_DURATION_32 0x8780 1918#define AR_RATE_DURATION_32 0x8780
1910#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 1919#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2))
1911 1920
1921/* WoW - Wake On Wireless */
1922
1923#define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */
1924#define AR_PMCTRL_D3COLD_VAUX 0x00800000
1925#define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW
1926 event */
1927#define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */
1928#define AR_PMCTRL_PWR_STATE_MASK 0x0f000000 /* Power State Mask */
1929#define AR_PMCTRL_PWR_STATE_D1D3 0x0f000000 /* Activate D1 and D3 */
1930#define AR_PMCTRL_PWR_STATE_D1D3_REAL 0x0f000000 /* Activate D1 and D3 */
1931#define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */
1932#define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power mgmt */
1933
1934#define AR_WOW_BEACON_TIMO_MAX 0xffffffff
1935
1936/*
1937 * MAC WoW Registers
1938 */
1939
1940#define AR_WOW_PATTERN 0x825C
1941#define AR_WOW_COUNT 0x8260
1942#define AR_WOW_BCN_EN 0x8270
1943#define AR_WOW_BCN_TIMO 0x8274
1944#define AR_WOW_KEEP_ALIVE_TIMO 0x8278
1945#define AR_WOW_KEEP_ALIVE 0x827c
1946#define AR_WOW_US_SCALAR 0x8284
1947#define AR_WOW_KEEP_ALIVE_DELAY 0x8288
1948#define AR_WOW_PATTERN_MATCH 0x828c
1949#define AR_WOW_PATTERN_OFF1 0x8290 /* pattern bytes 0 -> 3 */
1950#define AR_WOW_PATTERN_OFF2 0x8294 /* pattern bytes 4 -> 7 */
1951
1952/* for AR9285 or later version of chips */
1953#define AR_WOW_EXACT 0x829c
1954#define AR_WOW_LENGTH1 0x8360
1955#define AR_WOW_LENGTH2 0X8364
1956/* register to enable match for less than 256 bytes packets */
1957#define AR_WOW_PATTERN_MATCH_LT_256B 0x8368
1958
1959#define AR_SW_WOW_CONTROL 0x20018
1960#define AR_SW_WOW_ENABLE 0x1
1961#define AR_SWITCH_TO_REFCLK 0x2
1962#define AR_RESET_CONTROL 0x4
1963#define AR_RESET_VALUE_MASK 0x8
1964#define AR_HW_WOW_DISABLE 0x10
1965#define AR_CLR_MAC_INTERRUPT 0x20
1966#define AR_CLR_KA_INTERRUPT 0x40
1967
1968/* AR_WOW_PATTERN register values */
1969#define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 28) /* in usecs */
1970#define AR_WOW_MAC_INTR_EN 0x00040000
1971#define AR_WOW_MAGIC_EN 0x00010000
1972#define AR_WOW_PATTERN_EN(x) (x & 0xff)
1973#define AR_WOW_PAT_FOUND_SHIFT 8
1974#define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PAT_FOUND_SHIFT))
1975#define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PAT_FOUND_SHIFT)
1976#define AR_WOW_MAGIC_PAT_FOUND 0x00020000
1977#define AR_WOW_MAC_INTR 0x00080000
1978#define AR_WOW_KEEP_ALIVE_FAIL 0x00100000
1979#define AR_WOW_BEACON_FAIL 0x00200000
1980
1981#define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | \
1982 AR_WOW_MAGIC_PAT_FOUND | \
1983 AR_WOW_KEEP_ALIVE_FAIL | \
1984 AR_WOW_BEACON_FAIL))
1985#define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \
1986 AR_WOW_MAGIC_EN | \
1987 AR_WOW_MAC_INTR_EN | \
1988 AR_WOW_BEACON_FAIL | \
1989 AR_WOW_KEEP_ALIVE_FAIL))
1990
1991/* AR_WOW_COUNT register values */
1992#define AR_WOW_AIFS_CNT(x) (x & 0xff)
1993#define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8)
1994#define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16)
1995
1996/* AR_WOW_BCN_EN register */
1997#define AR_WOW_BEACON_FAIL_EN 0x00000001
1998
1999/* AR_WOW_BCN_TIMO rgister */
2000#define AR_WOW_BEACON_TIMO 0x40000000 /* valid if BCN_EN is set */
2001
2002/* AR_WOW_KEEP_ALIVE_TIMO register */
2003#define AR_WOW_KEEP_ALIVE_TIMO_VALUE
2004#define AR_WOW_KEEP_ALIVE_NEVER 0xffffffff
2005
2006/* AR_WOW_KEEP_ALIVE register */
2007#define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001
2008#define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002
2009
2010/* AR_WOW_KEEP_ALIVE_DELAY register */
2011#define AR_WOW_KEEP_ALIVE_DELAY_VALUE 0x000003e8 /* 1 msec */
2012
2013
2014/*
2015 * keep it long for beacon workaround - ensure no false alarm
2016 */
2017#define AR_WOW_BMISSTHRESHOLD 0x20
2018
2019/* AR_WOW_PATTERN_MATCH register */
2020#define AR_WOW_PAT_END_OF_PKT(x) (x & 0xf)
2021#define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8)
2022
2023/*
2024 * default values for Wow Configuration for backoff, aifs, slot, keep-alive
2025 * to be programmed into various registers.
2026 */
2027#define AR_WOW_PAT_BACKOFF 0x00000004 /* AR_WOW_PATTERN_REG */
2028#define AR_WOW_CNT_AIFS_CNT 0x00000022 /* AR_WOW_COUNT_REG */
2029#define AR_WOW_CNT_SLOT_CNT 0x00000009 /* AR_WOW_COUNT_REG */
2030/*
2031 * Keepalive count applicable for AR9280 2.0 and above.
2032 */
2033#define AR_WOW_CNT_KA_CNT 0x00000008 /* AR_WOW_COUNT register */
2034
2035/* WoW - Transmit buffer for keep alive frames */
2036#define AR_WOW_TRANSMIT_BUFFER 0xe000 /* E000 - EFFC */
2037
2038#define AR_WOW_TXBUF(i) (AR_WOW_TRANSMIT_BUFFER + ((i) << 2))
2039
2040#define AR_WOW_KA_DESC_WORD2 0xe000
2041
2042#define AR_WOW_KA_DATA_WORD0 0xe030
2043
2044/* WoW Transmit Buffer for patterns */
2045#define AR_WOW_TB_PATTERN(i) (0xe100 + (i << 8))
2046#define AR_WOW_TB_MASK(i) (0xec00 + (i << 5))
2047
2048/* Currently Pattern 0-7 are supported - so bit 0-7 are set */
2049#define AR_WOW_PATTERN_SUPPORTED 0xff
2050#define AR_WOW_LENGTH_MAX 0xff
2051#define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3)
2052#define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i))
2053#define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3)
2054#define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i))
1912 2055
1913#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 2056#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1914#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 2057#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
diff --git a/drivers/net/wireless/ath/ath9k/wow.c b/drivers/net/wireless/ath/ath9k/wow.c
new file mode 100644
index 000000000000..44a08eb53c62
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/wow.c
@@ -0,0 +1,532 @@
1/*
2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/export.h>
18#include "ath9k.h"
19#include "reg.h"
20#include "hw-ops.h"
21
22const char *ath9k_hw_wow_event_to_string(u32 wow_event)
23{
24 if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
25 return "Magic pattern";
26 if (wow_event & AH_WOW_USER_PATTERN_EN)
27 return "User pattern";
28 if (wow_event & AH_WOW_LINK_CHANGE)
29 return "Link change";
30 if (wow_event & AH_WOW_BEACON_MISS)
31 return "Beacon miss";
32
33 return "unknown reason";
34}
35EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
36
37static void ath9k_hw_config_serdes_wow_sleep(struct ath_hw *ah)
38{
39 int i;
40
41 for (i = 0; i < ah->iniPcieSerdesWow.ia_rows; i++)
42 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdesWow, i, 0),
43 INI_RA(&ah->iniPcieSerdesWow, i, 1));
44
45 usleep_range(1000, 1500);
46}
47
48static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
49{
50 struct ath_common *common = ath9k_hw_common(ah);
51
52 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
53
54 /* set rx disable bit */
55 REG_WRITE(ah, AR_CR, AR_CR_RXD);
56
57 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
58 ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
59 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
60 return;
61 } else {
62 if (!AR_SREV_9300_20_OR_LATER(ah))
63 REG_WRITE(ah, AR_RXDP, 0x0);
64 }
65
66 /* AR9280 WoW has sleep issue, do not set it to sleep */
67 if (AR_SREV_9280_20(ah))
68 return;
69
70 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
71}
72
73static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
74{
75 struct ath_common *common = ath9k_hw_common(ah);
76 u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
77 u32 ctl[13] = {0};
78 u32 data_word[KAL_NUM_DATA_WORDS];
79 u8 i;
80 u32 wow_ka_data_word0;
81
82 memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
83 memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
84
85 /* set the transmit buffer */
86 ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
87
88 if (!(AR_SREV_9300_20_OR_LATER(ah)))
89 ctl[0] += (KAL_ANTENNA_MODE << 25);
90
91 ctl[1] = 0;
92 ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
93 ctl[4] = 0;
94 ctl[7] = (ah->txchainmask) << 2;
95
96 if (AR_SREV_9300_20_OR_LATER(ah))
97 ctl[2] = 0xf << 16; /* tx_tries 0 */
98 else
99 ctl[2] = 0x7 << 16; /* tx_tries 0 */
100
101
102 for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
103 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
104
105 /* for AR9300 family 13 descriptor words */
106 if (AR_SREV_9300_20_OR_LATER(ah))
107 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
108
109 data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
110 (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
111 data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
112 (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
113 data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
114 (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
115 data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
116 (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
117 data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
118 (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
119 data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
120
121 if (AR_SREV_9462_20_OR_LATER(ah)) {
122 /* AR9462 2.0 has an extra descriptor word (time based
123 * discard) compared to other chips */
124 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
125 wow_ka_data_word0 = AR_WOW_TXBUF(13);
126 } else {
127 wow_ka_data_word0 = AR_WOW_TXBUF(12);
128 }
129
130 for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
131 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
132
133}
134
135void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
136 u8 *user_mask, int pattern_count,
137 int pattern_len)
138{
139 int i;
140 u32 pattern_val, mask_val;
141 u32 set, clr;
142
143 /* FIXME: should check count by querying the hardware capability */
144 if (pattern_count >= MAX_NUM_PATTERN)
145 return;
146
147 REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
148
149 /* set the registers for pattern */
150 for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
151 memcpy(&pattern_val, user_pattern, 4);
152 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
153 pattern_val);
154 user_pattern += 4;
155 }
156
157 /* set the registers for mask */
158 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
159 memcpy(&mask_val, user_mask, 4);
160 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
161 user_mask += 4;
162 }
163
164 /* set the pattern length to be matched
165 *
166 * AR_WOW_LENGTH1_REG1
167 * bit 31:24 pattern 0 length
168 * bit 23:16 pattern 1 length
169 * bit 15:8 pattern 2 length
170 * bit 7:0 pattern 3 length
171 *
172 * AR_WOW_LENGTH1_REG2
173 * bit 31:24 pattern 4 length
174 * bit 23:16 pattern 5 length
175 * bit 15:8 pattern 6 length
176 * bit 7:0 pattern 7 length
177 *
178 * the below logic writes out the new
179 * pattern length for the corresponding
180 * pattern_count, while masking out the
181 * other fields
182 */
183
184 ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
185
186 if (!AR_SREV_9285_12_OR_LATER(ah))
187 return;
188
189 if (pattern_count < 4) {
190 /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
191 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
192 AR_WOW_LEN1_SHIFT(pattern_count);
193 clr = AR_WOW_LENGTH1_MASK(pattern_count);
194 REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
195 } else {
196 /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
197 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
198 AR_WOW_LEN2_SHIFT(pattern_count);
199 clr = AR_WOW_LENGTH2_MASK(pattern_count);
200 REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
201 }
202
203}
204EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
205
206u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
207{
208 u32 wow_status = 0;
209 u32 val = 0, rval;
210 /*
211 * read the WoW status register to know
212 * the wakeup reason
213 */
214 rval = REG_READ(ah, AR_WOW_PATTERN);
215 val = AR_WOW_STATUS(rval);
216
217 /*
218 * mask only the WoW events that we have enabled. Sometimes
219 * we have spurious WoW events from the AR_WOW_PATTERN
220 * register. This mask will clean it up.
221 */
222
223 val &= ah->wow_event_mask;
224
225 if (val) {
226
227 if (val & AR_WOW_MAGIC_PAT_FOUND)
228 wow_status |= AH_WOW_MAGIC_PATTERN_EN;
229
230 if (AR_WOW_PATTERN_FOUND(val))
231 wow_status |= AH_WOW_USER_PATTERN_EN;
232
233 if (val & AR_WOW_KEEP_ALIVE_FAIL)
234 wow_status |= AH_WOW_LINK_CHANGE;
235
236 if (val & AR_WOW_BEACON_FAIL)
237 wow_status |= AH_WOW_BEACON_MISS;
238
239 }
240
241 /*
242 * set and clear WOW_PME_CLEAR registers for the chip to
243 * generate next wow signal.
244 * disable D3 before accessing other registers ?
245 */
246
247 /* do we need to check the bit value 0x01000000 (7-10) ?? */
248 REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
249 AR_PMCTRL_PWR_STATE_D1D3);
250
251 /*
252 * clear all events
253 */
254 REG_WRITE(ah, AR_WOW_PATTERN,
255 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
256
257 /*
258 * tie reset register for AR9002 family of chipsets
259 * NB: not tieing it back might have some repurcussions.
260 */
261
262 if (!AR_SREV_9300_20_OR_LATER(ah)) {
263 REG_SET_BIT(ah, AR_WA, AR_WA_UNTIE_RESET_EN |
264 AR_WA_POR_SHORT | AR_WA_RESET_EN);
265 }
266
267
268 /*
269 * restore the beacon threshold to init value
270 */
271 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
272
273 /*
274 * Restore the way the PCI-E reset, Power-On-Reset, external
275 * PCIE_POR_SHORT pins are tied to its original value.
276 * Previously just before WoW sleep, we untie the PCI-E
277 * reset to our Chip's Power On Reset so that any PCI-E
278 * reset from the bus will not reset our chip
279 */
280
281 if (AR_SREV_9280_20_OR_LATER(ah) && ah->is_pciexpress)
282 ath9k_hw_configpcipowersave(ah, false);
283
284 ah->wow_event_mask = 0;
285
286 return wow_status;
287}
288EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
289
290void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
291{
292 u32 wow_event_mask;
293 u32 set, clr;
294
295 /*
296 * wow_event_mask is a mask to the AR_WOW_PATTERN register to
297 * indicate which WoW events we have enabled. The WoW events
298 * are from the 'pattern_enable' in this function and
299 * 'pattern_count' of ath9k_hw_wow_apply_pattern()
300 */
301
302 wow_event_mask = ah->wow_event_mask;
303
304 /*
305 * Untie Power-on-Reset from the PCI-E-Reset. When we are in
306 * WOW sleep, we do want the Reset from the PCI-E to disturb
307 * our hw state
308 */
309
310 if (ah->is_pciexpress) {
311
312 /*
313 * we need to untie the internal POR (power-on-reset)
314 * to the external PCI-E reset. We also need to tie
315 * the PCI-E Phy reset to the PCI-E reset.
316 */
317
318 if (AR_SREV_9300_20_OR_LATER(ah)) {
319 set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
320 clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
321 REG_RMW(ah, AR_WA, set, clr);
322 } else {
323 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
324 set = AR9285_WA_DEFAULT;
325 else
326 set = AR9280_WA_DEFAULT;
327
328 /*
329 * In AR9280 and AR9285, bit 14 in WA register
330 * (disable L1) should only be set when device
331 * enters D3 state and be cleared when device
332 * comes back to D0
333 */
334
335 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
336 set |= AR_WA_D3_L1_DISABLE;
337
338 clr = AR_WA_UNTIE_RESET_EN;
339 set |= AR_WA_RESET_EN | AR_WA_POR_SHORT;
340 REG_RMW(ah, AR_WA, set, clr);
341
342 /*
343 * for WoW sleep, we reprogram the SerDes so that the
344 * PLL and CLK REQ are both enabled. This uses more
345 * power but otherwise WoW sleep is unstable and the
346 * chip may disappear.
347 */
348
349 if (AR_SREV_9285_12_OR_LATER(ah))
350 ath9k_hw_config_serdes_wow_sleep(ah);
351
352 }
353 }
354
355 /*
356 * set the power states appropriately and enable PME
357 */
358 set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
359 AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
360
361 /*
362 * set and clear WOW_PME_CLEAR registers for the chip
363 * to generate next wow signal.
364 */
365 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
366 clr = AR_PMCTRL_WOW_PME_CLR;
367 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
368
369 /*
370 * Setup for:
371 * - beacon misses
372 * - magic pattern
373 * - keep alive timeout
374 * - pattern matching
375 */
376
377 /*
378 * Program default values for pattern backoff, aifs/slot/KAL count,
379 * beacon miss timeout, KAL timeout, etc.
380 */
381
382 set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
383 REG_SET_BIT(ah, AR_WOW_PATTERN, set);
384
385 set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
386 AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
387 AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
388 REG_SET_BIT(ah, AR_WOW_COUNT, set);
389
390 if (pattern_enable & AH_WOW_BEACON_MISS)
391 set = AR_WOW_BEACON_TIMO;
392 /* We are not using beacon miss, program a large value */
393 else
394 set = AR_WOW_BEACON_TIMO_MAX;
395
396 REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
397
398 /*
399 * Keep alive timo in ms except AR9280
400 */
401 if (!pattern_enable || AR_SREV_9280(ah))
402 set = AR_WOW_KEEP_ALIVE_NEVER;
403 else
404 set = KAL_TIMEOUT * 32;
405
406 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
407
408 /*
409 * Keep alive delay in us. based on 'power on clock',
410 * therefore in usec
411 */
412 set = KAL_DELAY * 1000;
413 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
414
415 /*
416 * Create keep alive pattern to respond to beacons
417 */
418 ath9k_wow_create_keep_alive_pattern(ah);
419
420 /*
421 * Configure MAC WoW Registers
422 */
423
424 set = 0;
425 /* Send keep alive timeouts anyway */
426 clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
427
428 if (pattern_enable & AH_WOW_LINK_CHANGE)
429 wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
430 else
431 set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
432
433 /*
434 * FIXME: For now disable keep alive frame
435 * failure. This seems to sometimes trigger
436 * unnecessary wake up with AR9485 chipsets.
437 */
438 set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
439
440 REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
441
442
443 /*
444 * we are relying on a bmiss failure. ensure we have
445 * enough threshold to prevent false positives
446 */
447 REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
448 AR_WOW_BMISSTHRESHOLD);
449
450 set = 0;
451 clr = 0;
452
453 if (pattern_enable & AH_WOW_BEACON_MISS) {
454 set = AR_WOW_BEACON_FAIL_EN;
455 wow_event_mask |= AR_WOW_BEACON_FAIL;
456 } else {
457 clr = AR_WOW_BEACON_FAIL_EN;
458 }
459
460 REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
461
462 set = 0;
463 clr = 0;
464 /*
465 * Enable the magic packet registers
466 */
467 if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
468 set = AR_WOW_MAGIC_EN;
469 wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
470 } else {
471 clr = AR_WOW_MAGIC_EN;
472 }
473 set |= AR_WOW_MAC_INTR_EN;
474 REG_RMW(ah, AR_WOW_PATTERN, set, clr);
475
476 /*
477 * For AR9285 and later version of chipsets
478 * enable WoW pattern match for packets less
479 * than 256 bytes for all patterns
480 */
481 if (AR_SREV_9285_12_OR_LATER(ah))
482 REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
483 AR_WOW_PATTERN_SUPPORTED);
484
485 /*
486 * Set the power states appropriately and enable PME
487 */
488 clr = 0;
489 set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
490 AR_PMCTRL_PWR_PM_CTRL_ENA;
491 /*
492 * This is needed for AR9300 chipsets to wake-up
493 * the host.
494 */
495 if (AR_SREV_9300_20_OR_LATER(ah))
496 clr = AR_PCIE_PM_CTRL_ENA;
497
498 REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
499
500 if (AR_SREV_9462(ah)) {
501 /*
502 * this is needed to prevent the chip waking up
503 * the host within 3-4 seconds with certain
504 * platform/BIOS. The fix is to enable
505 * D1 & D3 to match original definition and
506 * also match the OTP value. Anyway this
507 * is more related to SW WOW.
508 */
509 clr = AR_PMCTRL_PWR_STATE_D1D3;
510 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
511
512 set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
513 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
514 }
515
516
517
518 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
519
520 if (AR_SREV_9300_20_OR_LATER(ah)) {
521 /* to bring down WOW power low margin */
522 set = BIT(13);
523 REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
524 /* HW WoW */
525 clr = BIT(5);
526 REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
527 }
528
529 ath9k_hw_set_powermode_wow_sleep(ah);
530 ah->wow_event_mask = wow_event_mask;
531}
532EXPORT_SYMBOL(ath9k_hw_wow_enable);
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index cafb4a09729a..2c9da6b2ecb1 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -29,6 +29,8 @@
29#define HT_LTF(_ns) (4 * (_ns)) 29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
32#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 36
@@ -74,33 +76,6 @@ enum {
74 MCS_HT40_SGI, 76 MCS_HT40_SGI,
75}; 77};
76 78
77static int ath_max_4ms_framelen[4][32] = {
78 [MCS_HT20] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
83 },
84 [MCS_HT20_SGI] = {
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
89 },
90 [MCS_HT40] = {
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
95 },
96 [MCS_HT40_SGI] = {
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
101 }
102};
103
104/*********************/ 79/*********************/
105/* Aggregation logic */ 80/* Aggregation logic */
106/*********************/ 81/*********************/
@@ -614,10 +589,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
614 589
615 rcu_read_unlock(); 590 rcu_read_unlock();
616 591
617 if (needreset) { 592 if (needreset)
618 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR); 593 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
619 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
620 }
621} 594}
622 595
623static bool ath_lookup_legacy(struct ath_buf *bf) 596static bool ath_lookup_legacy(struct ath_buf *bf)
@@ -650,6 +623,7 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
650 struct ieee80211_tx_rate *rates; 623 struct ieee80211_tx_rate *rates;
651 u32 max_4ms_framelen, frmlen; 624 u32 max_4ms_framelen, frmlen;
652 u16 aggr_limit, bt_aggr_limit, legacy = 0; 625 u16 aggr_limit, bt_aggr_limit, legacy = 0;
626 int q = tid->ac->txq->mac80211_qnum;
653 int i; 627 int i;
654 628
655 skb = bf->bf_mpdu; 629 skb = bf->bf_mpdu;
@@ -658,8 +632,7 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
658 632
659 /* 633 /*
660 * Find the lowest frame length among the rate series that will have a 634 * Find the lowest frame length among the rate series that will have a
661 * 4ms transmit duration. 635 * 4ms (or TXOP limited) transmit duration.
662 * TODO - TXOP limit needs to be considered.
663 */ 636 */
664 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 637 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
665 638
@@ -682,7 +655,7 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
682 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 655 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
683 modeidx++; 656 modeidx++;
684 657
685 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; 658 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
686 max_4ms_framelen = min(max_4ms_framelen, frmlen); 659 max_4ms_framelen = min(max_4ms_framelen, frmlen);
687 } 660 }
688 661
@@ -929,6 +902,44 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
929 return duration; 902 return duration;
930} 903}
931 904
905static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
906{
907 int streams = HT_RC_2_STREAMS(mcs);
908 int symbols, bits;
909 int bytes = 0;
910
911 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
912 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
913 bits -= OFDM_PLCP_BITS;
914 bytes = bits / 8;
915 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
916 if (bytes > 65532)
917 bytes = 65532;
918
919 return bytes;
920}
921
922void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
923{
924 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
925 int mcs;
926
927 /* 4ms is the default (and maximum) duration */
928 if (!txop || txop > 4096)
929 txop = 4096;
930
931 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
932 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
933 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
934 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
935 for (mcs = 0; mcs < 32; mcs++) {
936 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
937 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
938 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
939 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
940 }
941}
942
932static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 943static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
933 struct ath_tx_info *info, int len) 944 struct ath_tx_info *info, int len)
934{ 945{
@@ -1403,16 +1414,6 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
1403 int error = 0; 1414 int error = 0;
1404 struct ath9k_tx_queue_info qi; 1415 struct ath9k_tx_queue_info qi;
1405 1416
1406 if (qnum == sc->beacon.beaconq) {
1407 /*
1408 * XXX: for beacon queue, we just save the parameter.
1409 * It will be picked up by ath_beaconq_config when
1410 * it's necessary.
1411 */
1412 sc->beacon.beacon_qi = *qinfo;
1413 return 0;
1414 }
1415
1416 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1417 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1417 1418
1418 ath9k_hw_get_txq_props(ah, qnum, &qi); 1419 ath9k_hw_get_txq_props(ah, qnum, &qi);
@@ -1586,7 +1587,8 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1586 struct ath_atx_ac *ac, *ac_tmp, *last_ac; 1587 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1587 struct ath_atx_tid *tid, *last_tid; 1588 struct ath_atx_tid *tid, *last_tid;
1588 1589
1589 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) || 1590 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1591 list_empty(&txq->axq_acq) ||
1590 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1592 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1591 return; 1593 return;
1592 1594
@@ -1988,7 +1990,8 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1988 1990
1989 ath_txq_lock(sc, txq); 1991 ath_txq_lock(sc, txq);
1990 if (txq == sc->tx.txq_map[q] && 1992 if (txq == sc->tx.txq_map[q] &&
1991 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) { 1993 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
1994 !txq->stopped) {
1992 ieee80211_stop_queue(sc->hw, q); 1995 ieee80211_stop_queue(sc->hw, q);
1993 txq->stopped = true; 1996 txq->stopped = true;
1994 } 1997 }
@@ -2047,7 +2050,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2047 if (WARN_ON(--txq->pending_frames < 0)) 2050 if (WARN_ON(--txq->pending_frames < 0))
2048 txq->pending_frames = 0; 2051 txq->pending_frames = 0;
2049 2052
2050 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) { 2053 if (txq->stopped &&
2054 txq->pending_frames < sc->tx.txq_max_pending[q]) {
2051 ieee80211_wake_queue(sc->hw, q); 2055 ieee80211_wake_queue(sc->hw, q);
2052 txq->stopped = false; 2056 txq->stopped = false;
2053 } 2057 }
@@ -2191,7 +2195,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2191 2195
2192 ath_txq_lock(sc, txq); 2196 ath_txq_lock(sc, txq);
2193 for (;;) { 2197 for (;;) {
2194 if (work_pending(&sc->hw_reset_work)) 2198 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2195 break; 2199 break;
2196 2200
2197 if (list_empty(&txq->axq_q)) { 2201 if (list_empty(&txq->axq_q)) {
@@ -2274,7 +2278,7 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
2274 int status; 2278 int status;
2275 2279
2276 for (;;) { 2280 for (;;) {
2277 if (work_pending(&sc->hw_reset_work)) 2281 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2278 break; 2282 break;
2279 2283
2280 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2284 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 19:17:11 -0500