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authorSujith <Sujith.Manoharan@atheros.com>2008-11-28 11:48:05 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-12-05 09:35:08 -0500
commit04bd4638097c767278fdf12d50fecc8b60194d39 (patch)
tree8bad1080889360aa06ffc967bb2625eecd3db26e /drivers/net/wireless/ath9k/core.h
parentd9a1f48648edbe99fa432626ce6964a1b58f7281 (diff)
ath9k: Use cleaner debug masks
Remove all the useless __func__ prefixes in debug messages, and replace the DPRINTF macro with a function. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/core.h')
-rw-r--r--drivers/net/wireless/ath9k/core.h157
1 files changed, 58 insertions, 99 deletions
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h
index f0c54377dfe6..ae32b2c4ef16 100644
--- a/drivers/net/wireless/ath9k/core.h
+++ b/drivers/net/wireless/ath9k/core.h
@@ -84,52 +84,33 @@ struct ath_node;
84 84
85static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 85static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
86 86
87/*************/
88/* Debugging */
89/*************/
90
91enum ATH_DEBUG { 87enum ATH_DEBUG {
92 ATH_DBG_RESET = 0x00000001, 88 ATH_DBG_RESET = 0x00000001,
93 ATH_DBG_PHY_IO = 0x00000002, 89 ATH_DBG_REG_IO = 0x00000002,
94 ATH_DBG_REG_IO = 0x00000004, 90 ATH_DBG_QUEUE = 0x00000004,
95 ATH_DBG_QUEUE = 0x00000008, 91 ATH_DBG_EEPROM = 0x00000008,
96 ATH_DBG_EEPROM = 0x00000010, 92 ATH_DBG_CALIBRATE = 0x00000010,
97 ATH_DBG_NF_CAL = 0x00000020, 93 ATH_DBG_CHANNEL = 0x00000020,
98 ATH_DBG_CALIBRATE = 0x00000040, 94 ATH_DBG_INTERRUPT = 0x00000040,
99 ATH_DBG_CHANNEL = 0x00000080, 95 ATH_DBG_REGULATORY = 0x00000080,
100 ATH_DBG_INTERRUPT = 0x00000100, 96 ATH_DBG_ANI = 0x00000100,
101 ATH_DBG_REGULATORY = 0x00000200, 97 ATH_DBG_POWER_MGMT = 0x00000200,
102 ATH_DBG_ANI = 0x00000400, 98 ATH_DBG_XMIT = 0x00000400,
103 ATH_DBG_POWER_MGMT = 0x00000800, 99 ATH_DBG_BEACON = 0x00001000,
104 ATH_DBG_XMIT = 0x00001000, 100 ATH_DBG_CONFIG = 0x00002000,
105 ATH_DBG_BEACON = 0x00002000, 101 ATH_DBG_KEYCACHE = 0x00004000,
106 ATH_DBG_RATE = 0x00004000, 102 ATH_DBG_FATAL = 0x00008000,
107 ATH_DBG_CONFIG = 0x00008000,
108 ATH_DBG_KEYCACHE = 0x00010000,
109 ATH_DBG_AGGR = 0x00020000,
110 ATH_DBG_FATAL = 0x00040000,
111 ATH_DBG_ANY = 0xffffffff 103 ATH_DBG_ANY = 0xffffffff
112}; 104};
113 105
114#define DBG_DEFAULT (ATH_DBG_FATAL) 106#define DBG_DEFAULT (ATH_DBG_FATAL)
115 107
116#define DPRINTF(sc, _m, _fmt, ...) do { \
117 if (sc->sc_debug & (_m)) \
118 printk(_fmt , ##__VA_ARGS__); \
119 } while (0)
120
121/***************************/
122/* Load-time Configuration */
123/***************************/
124
125/* Per-instance load-time (note: NOT run-time) configurations
126 * for Atheros Device */
127struct ath_config { 108struct ath_config {
128 u32 ath_aggr_prot; 109 u32 ath_aggr_prot;
129 u16 txpowlimit; 110 u16 txpowlimit;
130 u16 txpowlimit_override; 111 u16 txpowlimit_override;
131 u8 cabqReadytime; /* Cabq Readytime % */ 112 u8 cabqReadytime;
132 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */ 113 u8 swBeaconProcess;
133}; 114};
134 115
135/*************************/ 116/*************************/
@@ -160,14 +141,13 @@ enum buffer_type {
160}; 141};
161 142
162struct ath_buf_state { 143struct ath_buf_state {
163 int bfs_nframes; /* # frames in aggregate */ 144 int bfs_nframes; /* # frames in aggregate */
164 u16 bfs_al; /* length of aggregate */ 145 u16 bfs_al; /* length of aggregate */
165 u16 bfs_frmlen; /* length of frame */ 146 u16 bfs_frmlen; /* length of frame */
166 int bfs_seqno; /* sequence number */ 147 int bfs_seqno; /* sequence number */
167 int bfs_tidno; /* tid of this frame */ 148 int bfs_tidno; /* tid of this frame */
168 int bfs_retries; /* current retries */ 149 int bfs_retries; /* current retries */
169 u32 bf_type; /* BUF_* (enum buffer_type) */ 150 u32 bf_type; /* BUF_* (enum buffer_type) */
170 /* key type use to encrypt this frame */
171 u32 bfs_keyix; 151 u32 bfs_keyix;
172 enum ath9k_key_type bfs_keytype; 152 enum ath9k_key_type bfs_keytype;
173}; 153};
@@ -213,13 +193,6 @@ struct ath_buf {
213 dma_addr_t bf_dmacontext; 193 dma_addr_t bf_dmacontext;
214}; 194};
215 195
216/*
217 * reset the rx buffer.
218 * any new fields added to the athbuf and require
219 * reset need to be added to this macro.
220 * currently bf_status is the only one requires that
221 * requires reset.
222 */
223#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) 196#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
224 197
225/* hw processing complete, desc processed by hal */ 198/* hw processing complete, desc processed by hal */
@@ -263,11 +236,8 @@ void ath_rx_cleanup(struct ath_softc *sc);
263int ath_rx_tasklet(struct ath_softc *sc, int flush); 236int ath_rx_tasklet(struct ath_softc *sc, int flush);
264 237
265#define ATH_TXBUF 512 238#define ATH_TXBUF 512
266/* max number of transmit attempts (tries) */
267#define ATH_TXMAXTRY 13 239#define ATH_TXMAXTRY 13
268/* max number of 11n transmit attempts (tries) */
269#define ATH_11N_TXMAXTRY 10 240#define ATH_11N_TXMAXTRY 10
270/* max number of tries for management and control frames */
271#define ATH_MGT_TXMAXTRY 4 241#define ATH_MGT_TXMAXTRY 4
272#define WME_BA_BMP_SIZE 64 242#define WME_BA_BMP_SIZE 64
273#define WME_MAX_BA WME_BA_BMP_SIZE 243#define WME_MAX_BA WME_BA_BMP_SIZE
@@ -279,22 +249,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush);
279 WME_AC_VO) 249 WME_AC_VO)
280 250
281 251
282/* Wireless Multimedia Extension Defines */ 252#define WME_AC_BE 0
283#define WME_AC_BE 0 /* best effort */ 253#define WME_AC_BK 1
284#define WME_AC_BK 1 /* background */ 254#define WME_AC_VI 2
285#define WME_AC_VI 2 /* video */ 255#define WME_AC_VO 3
286#define WME_AC_VO 3 /* voice */ 256#define WME_NUM_AC 4
287#define WME_NUM_AC 4
288 257
289/*
290 * Data transmit queue state. One of these exists for each
291 * hardware transmit queue. Packets sent to us from above
292 * are assigned to queues based on their priority. Not all
293 * devices support a complete set of hardware transmit queues.
294 * For those devices the array sc_ac2q will map multiple
295 * priorities to fewer hardware queues (typically all to one
296 * hardware queue).
297 */
298struct ath_txq { 258struct ath_txq {
299 u32 axq_qnum; /* hardware q number */ 259 u32 axq_qnum; /* hardware q number */
300 u32 *axq_link; /* link ptr in last TX desc */ 260 u32 *axq_link; /* link ptr in last TX desc */
@@ -372,14 +332,15 @@ struct ath_xmit_status {
372#define ATH_TX_BAR 0x04 332#define ATH_TX_BAR 0x04
373}; 333};
374 334
335/* All RSSI values are noise floor adjusted */
375struct ath_tx_stat { 336struct ath_tx_stat {
376 int rssi; /* RSSI (noise floor ajusted) */ 337 int rssi;
377 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 338 int rssictl[ATH_MAX_ANTENNA];
378 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 339 int rssiextn[ATH_MAX_ANTENNA];
379 int rateieee; /* data rate xmitted (IEEE rate code) */ 340 int rateieee;
380 int rateKbps; /* data rate xmitted (Kbps) */ 341 int rateKbps;
381 int ratecode; /* phy rate code */ 342 int ratecode;
382 int flags; /* validity flags */ 343 int flags;
383/* if any of ctl,extn chain rssis are valid */ 344/* if any of ctl,extn chain rssis are valid */
384#define ATH_TX_CHAIN_RSSI_VALID 0x01 345#define ATH_TX_CHAIN_RSSI_VALID 0x01
385/* if extn chain rssis are valid */ 346/* if extn chain rssis are valid */
@@ -415,7 +376,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
415/**********************/ 376/**********************/
416 377
417#define ADDBA_EXCHANGE_ATTEMPTS 10 378#define ADDBA_EXCHANGE_ATTEMPTS 10
418#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ 379#define ATH_AGGR_DELIM_SZ 4
419#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 380#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
420/* number of delimiters for encryption padding */ 381/* number of delimiters for encryption padding */
421#define ATH_AGGR_ENCRYPTDELIM 10 382#define ATH_AGGR_ENCRYPTDELIM 10
@@ -466,10 +427,9 @@ struct aggr_rifs_param {
466 427
467/* Per-node aggregation state */ 428/* Per-node aggregation state */
468struct ath_node_aggr { 429struct ath_node_aggr {
469 struct ath_atx tx; /* node transmit state */ 430 struct ath_atx tx;
470}; 431};
471 432
472/* driver-specific node state */
473struct ath_node { 433struct ath_node {
474 struct ath_softc *an_sc; 434 struct ath_softc *an_sc;
475 struct ath_node_aggr an_aggr; 435 struct ath_node_aggr an_aggr;
@@ -500,12 +460,11 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
500#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ 460#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
501 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) 461 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
502 462
503/* driver-specific vap state */
504struct ath_vap { 463struct ath_vap {
505 int av_bslot; /* beacon slot index */ 464 int av_bslot;
506 enum ath9k_opmode av_opmode; /* VAP operational mode */ 465 enum ath9k_opmode av_opmode;
507 struct ath_buf *av_bcbuf; /* beacon buffer */ 466 struct ath_buf *av_bcbuf;
508 struct ath_tx_control av_btxctl; /* txctl information for beacon */ 467 struct ath_tx_control av_btxctl;
509}; 468};
510 469
511/*******************/ 470/*******************/
@@ -518,12 +477,11 @@ struct ath_vap {
518 * number of beacon intervals, the game's up. 477 * number of beacon intervals, the game's up.
519 */ 478 */
520#define BSTUCK_THRESH (9 * ATH_BCBUF) 479#define BSTUCK_THRESH (9 * ATH_BCBUF)
521#define ATH_BCBUF 4 /* number of beacon buffers */ 480#define ATH_BCBUF 4
522#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */ 481#define ATH_DEFAULT_BINTVAL 100 /* TU */
523#define ATH_DEFAULT_BMISS_LIMIT 10 482#define ATH_DEFAULT_BMISS_LIMIT 10
524#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 483#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
525 484
526/* beacon configuration */
527struct ath_beacon_config { 485struct ath_beacon_config {
528 u16 beacon_interval; 486 u16 beacon_interval;
529 u16 listen_interval; 487 u16 listen_interval;
@@ -674,18 +632,18 @@ struct ath_softc {
674 u8 sc_tx_chainmask; 632 u8 sc_tx_chainmask;
675 u8 sc_rx_chainmask; 633 u8 sc_rx_chainmask;
676 enum ath9k_int sc_imask; 634 enum ath9k_int sc_imask;
677 enum wireless_mode sc_curmode; /* current phy mode */ 635 enum wireless_mode sc_curmode;
678 enum PROT_MODE sc_protmode; 636 enum PROT_MODE sc_protmode;
679 637
680 u8 sc_nbcnvaps; /* # of vaps sending beacons */ 638 u8 sc_nbcnvaps;
681 u16 sc_nvaps; /* # of active virtual ap's */ 639 u16 sc_nvaps;
682 struct ieee80211_vif *sc_vaps[ATH_BCBUF]; 640 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
683 641
684 u8 sc_mcastantenna; 642 u8 sc_mcastantenna;
685 u8 sc_defant; /* current default antenna */ 643 u8 sc_defant;
686 u8 sc_rxotherant; /* rx's on non-default antenna */ 644 u8 sc_rxotherant;
687 645
688 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ 646 struct ath9k_node_stats sc_halstats;
689 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 647 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
690 enum ath9k_ht_macmode tx_chan_width; 648 enum ath9k_ht_macmode tx_chan_width;
691 649
@@ -699,22 +657,22 @@ struct ath_softc {
699 } sc_updateslot; /* slot time update fsm */ 657 } sc_updateslot; /* slot time update fsm */
700 658
701 /* Crypto */ 659 /* Crypto */
702 u32 sc_keymax; /* size of key cache */ 660 u32 sc_keymax;
703 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */ 661 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
704 u8 sc_splitmic; /* split TKIP MIC keys */ 662 u8 sc_splitmic; /* split TKIP MIC keys */
705 663
706 /* RX */ 664 /* RX */
707 struct list_head sc_rxbuf; 665 struct list_head sc_rxbuf;
708 struct ath_descdma sc_rxdma; 666 struct ath_descdma sc_rxdma;
709 int sc_rxbufsize; /* rx size based on mtu */ 667 int sc_rxbufsize;
710 u32 *sc_rxlink; /* link ptr in last RX desc */ 668 u32 *sc_rxlink;
711 669
712 /* TX */ 670 /* TX */
713 struct list_head sc_txbuf; 671 struct list_head sc_txbuf;
714 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; 672 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
715 struct ath_descdma sc_txdma; 673 struct ath_descdma sc_txdma;
716 u32 sc_txqsetup; 674 u32 sc_txqsetup;
717 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */ 675 int sc_haltype2q[ATH9K_WME_AC_VO+1];
718 u16 seq_no; /* TX sequence number */ 676 u16 seq_no; /* TX sequence number */
719 677
720 /* Beacon */ 678 /* Beacon */
@@ -724,13 +682,13 @@ struct ath_softc {
724 struct list_head sc_bbuf; 682 struct list_head sc_bbuf;
725 u32 sc_bhalq; 683 u32 sc_bhalq;
726 u32 sc_bmisscount; 684 u32 sc_bmisscount;
727 u32 ast_be_xmit; /* beacons transmitted */ 685 u32 ast_be_xmit;
728 u64 bc_tstamp; 686 u64 bc_tstamp;
729 687
730 /* Rate */ 688 /* Rate */
731 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 689 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
732 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 690 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
733 u8 sc_protrix; /* protection rate index */ 691 u8 sc_protrix;
734 692
735 /* Channel, Band */ 693 /* Channel, Band */
736 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX]; 694 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
@@ -755,6 +713,7 @@ struct ath_softc {
755 struct ath_ani sc_ani; 713 struct ath_ani sc_ani;
756}; 714};
757 715
716void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
758int ath_reset(struct ath_softc *sc, bool retry_tx); 717int ath_reset(struct ath_softc *sc, bool retry_tx);
759int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); 718int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
760int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); 719int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);