diff options
author | Sujith <Sujith.Manoharan@atheros.com> | 2009-02-09 02:57:12 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-02-13 13:45:05 -0500 |
commit | cbe61d8a41210600bc76b212edcd4dc0f55c014f (patch) | |
tree | d8bd8e43d3556c58d410f1bef0d2ca3bf7d75c92 /drivers/net/wireless/ath9k/ani.c | |
parent | ba52da58be0acf3b7775972b2b5234ce64388c79 (diff) |
ath9k: Merge ath_hal and ath_hal_5416 structures
Finally, merge these structures and have a single
HW specific data structure.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/ani.c')
-rw-r--r-- | drivers/net/wireless/ath9k/ani.c | 232 |
1 files changed, 106 insertions, 126 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index 9cebf0e78a76..6bd2d5766019 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c | |||
@@ -16,18 +16,17 @@ | |||
16 | 16 | ||
17 | #include "ath9k.h" | 17 | #include "ath9k.h" |
18 | 18 | ||
19 | static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, | 19 | static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, |
20 | struct ath9k_channel *chan) | 20 | struct ath9k_channel *chan) |
21 | { | 21 | { |
22 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
23 | int i; | 22 | int i; |
24 | 23 | ||
25 | for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { | 24 | for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { |
26 | if (ahp->ah_ani[i].c && | 25 | if (ah->ah_ani[i].c && |
27 | ahp->ah_ani[i].c->channel == chan->channel) | 26 | ah->ah_ani[i].c->channel == chan->channel) |
28 | return i; | 27 | return i; |
29 | if (ahp->ah_ani[i].c == NULL) { | 28 | if (ah->ah_ani[i].c == NULL) { |
30 | ahp->ah_ani[i].c = chan; | 29 | ah->ah_ani[i].c = chan; |
31 | return i; | 30 | return i; |
32 | } | 31 | } |
33 | } | 32 | } |
@@ -38,41 +37,40 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, | |||
38 | return 0; | 37 | return 0; |
39 | } | 38 | } |
40 | 39 | ||
41 | static bool ath9k_hw_ani_control(struct ath_hal *ah, | 40 | static bool ath9k_hw_ani_control(struct ath_hw *ah, |
42 | enum ath9k_ani_cmd cmd, int param) | 41 | enum ath9k_ani_cmd cmd, int param) |
43 | { | 42 | { |
44 | struct ath_hal_5416 *ahp = AH5416(ah); | 43 | struct ar5416AniState *aniState = ah->ah_curani; |
45 | struct ar5416AniState *aniState = ahp->ah_curani; | ||
46 | 44 | ||
47 | switch (cmd & ahp->ah_ani_function) { | 45 | switch (cmd & ah->ah_ani_function) { |
48 | case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ | 46 | case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ |
49 | u32 level = param; | 47 | u32 level = param; |
50 | 48 | ||
51 | if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { | 49 | if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) { |
52 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 50 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
53 | "level out of range (%u > %u)\n", | 51 | "level out of range (%u > %u)\n", |
54 | level, | 52 | level, |
55 | (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); | 53 | (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired)); |
56 | return false; | 54 | return false; |
57 | } | 55 | } |
58 | 56 | ||
59 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | 57 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, |
60 | AR_PHY_DESIRED_SZ_TOT_DES, | 58 | AR_PHY_DESIRED_SZ_TOT_DES, |
61 | ahp->ah_totalSizeDesired[level]); | 59 | ah->ah_totalSizeDesired[level]); |
62 | REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, | 60 | REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, |
63 | AR_PHY_AGC_CTL1_COARSE_LOW, | 61 | AR_PHY_AGC_CTL1_COARSE_LOW, |
64 | ahp->ah_coarseLow[level]); | 62 | ah->ah_coarseLow[level]); |
65 | REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, | 63 | REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, |
66 | AR_PHY_AGC_CTL1_COARSE_HIGH, | 64 | AR_PHY_AGC_CTL1_COARSE_HIGH, |
67 | ahp->ah_coarseHigh[level]); | 65 | ah->ah_coarseHigh[level]); |
68 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | 66 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, |
69 | AR_PHY_FIND_SIG_FIRPWR, | 67 | AR_PHY_FIND_SIG_FIRPWR, |
70 | ahp->ah_firpwr[level]); | 68 | ah->ah_firpwr[level]); |
71 | 69 | ||
72 | if (level > aniState->noiseImmunityLevel) | 70 | if (level > aniState->noiseImmunityLevel) |
73 | ahp->ah_stats.ast_ani_niup++; | 71 | ah->ah_stats.ast_ani_niup++; |
74 | else if (level < aniState->noiseImmunityLevel) | 72 | else if (level < aniState->noiseImmunityLevel) |
75 | ahp->ah_stats.ast_ani_nidown++; | 73 | ah->ah_stats.ast_ani_nidown++; |
76 | aniState->noiseImmunityLevel = level; | 74 | aniState->noiseImmunityLevel = level; |
77 | break; | 75 | break; |
78 | } | 76 | } |
@@ -126,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
126 | 124 | ||
127 | if (!on != aniState->ofdmWeakSigDetectOff) { | 125 | if (!on != aniState->ofdmWeakSigDetectOff) { |
128 | if (on) | 126 | if (on) |
129 | ahp->ah_stats.ast_ani_ofdmon++; | 127 | ah->ah_stats.ast_ani_ofdmon++; |
130 | else | 128 | else |
131 | ahp->ah_stats.ast_ani_ofdmoff++; | 129 | ah->ah_stats.ast_ani_ofdmoff++; |
132 | aniState->ofdmWeakSigDetectOff = !on; | 130 | aniState->ofdmWeakSigDetectOff = !on; |
133 | } | 131 | } |
134 | break; | 132 | break; |
@@ -142,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
142 | weakSigThrCck[high]); | 140 | weakSigThrCck[high]); |
143 | if (high != aniState->cckWeakSigThreshold) { | 141 | if (high != aniState->cckWeakSigThreshold) { |
144 | if (high) | 142 | if (high) |
145 | ahp->ah_stats.ast_ani_cckhigh++; | 143 | ah->ah_stats.ast_ani_cckhigh++; |
146 | else | 144 | else |
147 | ahp->ah_stats.ast_ani_ccklow++; | 145 | ah->ah_stats.ast_ani_ccklow++; |
148 | aniState->cckWeakSigThreshold = high; | 146 | aniState->cckWeakSigThreshold = high; |
149 | } | 147 | } |
150 | break; | 148 | break; |
@@ -164,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
164 | AR_PHY_FIND_SIG_FIRSTEP, | 162 | AR_PHY_FIND_SIG_FIRSTEP, |
165 | firstep[level]); | 163 | firstep[level]); |
166 | if (level > aniState->firstepLevel) | 164 | if (level > aniState->firstepLevel) |
167 | ahp->ah_stats.ast_ani_stepup++; | 165 | ah->ah_stats.ast_ani_stepup++; |
168 | else if (level < aniState->firstepLevel) | 166 | else if (level < aniState->firstepLevel) |
169 | ahp->ah_stats.ast_ani_stepdown++; | 167 | ah->ah_stats.ast_ani_stepdown++; |
170 | aniState->firstepLevel = level; | 168 | aniState->firstepLevel = level; |
171 | break; | 169 | break; |
172 | } | 170 | } |
@@ -187,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
187 | AR_PHY_TIMING5_CYCPWR_THR1, | 185 | AR_PHY_TIMING5_CYCPWR_THR1, |
188 | cycpwrThr1[level]); | 186 | cycpwrThr1[level]); |
189 | if (level > aniState->spurImmunityLevel) | 187 | if (level > aniState->spurImmunityLevel) |
190 | ahp->ah_stats.ast_ani_spurup++; | 188 | ah->ah_stats.ast_ani_spurup++; |
191 | else if (level < aniState->spurImmunityLevel) | 189 | else if (level < aniState->spurImmunityLevel) |
192 | ahp->ah_stats.ast_ani_spurdown++; | 190 | ah->ah_stats.ast_ani_spurdown++; |
193 | aniState->spurImmunityLevel = level; | 191 | aniState->spurImmunityLevel = level; |
194 | break; | 192 | break; |
195 | } | 193 | } |
@@ -220,7 +218,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
220 | return true; | 218 | return true; |
221 | } | 219 | } |
222 | 220 | ||
223 | static void ath9k_hw_update_mibstats(struct ath_hal *ah, | 221 | static void ath9k_hw_update_mibstats(struct ath_hw *ah, |
224 | struct ath9k_mib_stats *stats) | 222 | struct ath9k_mib_stats *stats) |
225 | { | 223 | { |
226 | stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); | 224 | stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); |
@@ -230,18 +228,17 @@ static void ath9k_hw_update_mibstats(struct ath_hal *ah, | |||
230 | stats->beacons += REG_READ(ah, AR_BEACON_CNT); | 228 | stats->beacons += REG_READ(ah, AR_BEACON_CNT); |
231 | } | 229 | } |
232 | 230 | ||
233 | static void ath9k_ani_restart(struct ath_hal *ah) | 231 | static void ath9k_ani_restart(struct ath_hw *ah) |
234 | { | 232 | { |
235 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
236 | struct ar5416AniState *aniState; | 233 | struct ar5416AniState *aniState; |
237 | 234 | ||
238 | if (!DO_ANI(ah)) | 235 | if (!DO_ANI(ah)) |
239 | return; | 236 | return; |
240 | 237 | ||
241 | aniState = ahp->ah_curani; | 238 | aniState = ah->ah_curani; |
242 | 239 | ||
243 | aniState->listenTime = 0; | 240 | aniState->listenTime = 0; |
244 | if (ahp->ah_hasHwPhyCounters) { | 241 | if (ah->ah_hasHwPhyCounters) { |
245 | if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { | 242 | if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { |
246 | aniState->ofdmPhyErrBase = 0; | 243 | aniState->ofdmPhyErrBase = 0; |
247 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 244 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
@@ -267,15 +264,14 @@ static void ath9k_ani_restart(struct ath_hal *ah) | |||
267 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); | 264 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
268 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | 265 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
269 | 266 | ||
270 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | 267 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
271 | } | 268 | } |
272 | aniState->ofdmPhyErrCount = 0; | 269 | aniState->ofdmPhyErrCount = 0; |
273 | aniState->cckPhyErrCount = 0; | 270 | aniState->cckPhyErrCount = 0; |
274 | } | 271 | } |
275 | 272 | ||
276 | static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) | 273 | static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) |
277 | { | 274 | { |
278 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
279 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; | 275 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
280 | struct ar5416AniState *aniState; | 276 | struct ar5416AniState *aniState; |
281 | int32_t rssi; | 277 | int32_t rssi; |
@@ -283,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) | |||
283 | if (!DO_ANI(ah)) | 279 | if (!DO_ANI(ah)) |
284 | return; | 280 | return; |
285 | 281 | ||
286 | aniState = ahp->ah_curani; | 282 | aniState = ah->ah_curani; |
287 | 283 | ||
288 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { | 284 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { |
289 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | 285 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, |
@@ -306,7 +302,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) | |||
306 | } | 302 | } |
307 | return; | 303 | return; |
308 | } | 304 | } |
309 | rssi = BEACON_RSSI(ahp); | 305 | rssi = BEACON_RSSI(ah); |
310 | if (rssi > aniState->rssiThrHigh) { | 306 | if (rssi > aniState->rssiThrHigh) { |
311 | if (!aniState->ofdmWeakSigDetectOff) { | 307 | if (!aniState->ofdmWeakSigDetectOff) { |
312 | if (ath9k_hw_ani_control(ah, | 308 | if (ath9k_hw_ani_control(ah, |
@@ -345,9 +341,8 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) | |||
345 | } | 341 | } |
346 | } | 342 | } |
347 | 343 | ||
348 | static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) | 344 | static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) |
349 | { | 345 | { |
350 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
351 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; | 346 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
352 | struct ar5416AniState *aniState; | 347 | struct ar5416AniState *aniState; |
353 | int32_t rssi; | 348 | int32_t rssi; |
@@ -355,7 +350,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) | |||
355 | if (!DO_ANI(ah)) | 350 | if (!DO_ANI(ah)) |
356 | return; | 351 | return; |
357 | 352 | ||
358 | aniState = ahp->ah_curani; | 353 | aniState = ah->ah_curani; |
359 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { | 354 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { |
360 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | 355 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, |
361 | aniState->noiseImmunityLevel + 1)) { | 356 | aniState->noiseImmunityLevel + 1)) { |
@@ -369,7 +364,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) | |||
369 | } | 364 | } |
370 | return; | 365 | return; |
371 | } | 366 | } |
372 | rssi = BEACON_RSSI(ahp); | 367 | rssi = BEACON_RSSI(ah); |
373 | if (rssi > aniState->rssiThrLow) { | 368 | if (rssi > aniState->rssiThrLow) { |
374 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) | 369 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) |
375 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | 370 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
@@ -383,13 +378,12 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) | |||
383 | } | 378 | } |
384 | } | 379 | } |
385 | 380 | ||
386 | static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) | 381 | static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) |
387 | { | 382 | { |
388 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
389 | struct ar5416AniState *aniState; | 383 | struct ar5416AniState *aniState; |
390 | int32_t rssi; | 384 | int32_t rssi; |
391 | 385 | ||
392 | aniState = ahp->ah_curani; | 386 | aniState = ah->ah_curani; |
393 | 387 | ||
394 | if (ah->ah_opmode == NL80211_IFTYPE_AP) { | 388 | if (ah->ah_opmode == NL80211_IFTYPE_AP) { |
395 | if (aniState->firstepLevel > 0) { | 389 | if (aniState->firstepLevel > 0) { |
@@ -398,7 +392,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) | |||
398 | return; | 392 | return; |
399 | } | 393 | } |
400 | } else { | 394 | } else { |
401 | rssi = BEACON_RSSI(ahp); | 395 | rssi = BEACON_RSSI(ah); |
402 | if (rssi > aniState->rssiThrHigh) { | 396 | if (rssi > aniState->rssiThrHigh) { |
403 | /* XXX: Handle me */ | 397 | /* XXX: Handle me */ |
404 | } else if (rssi > aniState->rssiThrLow) { | 398 | } else if (rssi > aniState->rssiThrLow) { |
@@ -437,9 +431,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) | |||
437 | } | 431 | } |
438 | } | 432 | } |
439 | 433 | ||
440 | static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) | 434 | static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) |
441 | { | 435 | { |
442 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
443 | struct ar5416AniState *aniState; | 436 | struct ar5416AniState *aniState; |
444 | u32 txFrameCount, rxFrameCount, cycleCount; | 437 | u32 txFrameCount, rxFrameCount, cycleCount; |
445 | int32_t listenTime; | 438 | int32_t listenTime; |
@@ -448,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) | |||
448 | rxFrameCount = REG_READ(ah, AR_RFCNT); | 441 | rxFrameCount = REG_READ(ah, AR_RFCNT); |
449 | cycleCount = REG_READ(ah, AR_CCCNT); | 442 | cycleCount = REG_READ(ah, AR_CCCNT); |
450 | 443 | ||
451 | aniState = ahp->ah_curani; | 444 | aniState = ah->ah_curani; |
452 | if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { | 445 | if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { |
453 | 446 | ||
454 | listenTime = 0; | 447 | listenTime = 0; |
455 | ahp->ah_stats.ast_ani_lzero++; | 448 | ah->ah_stats.ast_ani_lzero++; |
456 | } else { | 449 | } else { |
457 | int32_t ccdelta = cycleCount - aniState->cycleCount; | 450 | int32_t ccdelta = cycleCount - aniState->cycleCount; |
458 | int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; | 451 | int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; |
@@ -466,9 +459,8 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) | |||
466 | return listenTime; | 459 | return listenTime; |
467 | } | 460 | } |
468 | 461 | ||
469 | void ath9k_ani_reset(struct ath_hal *ah) | 462 | void ath9k_ani_reset(struct ath_hw *ah) |
470 | { | 463 | { |
471 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
472 | struct ar5416AniState *aniState; | 464 | struct ar5416AniState *aniState; |
473 | struct ath9k_channel *chan = ah->ah_curchan; | 465 | struct ath9k_channel *chan = ah->ah_curchan; |
474 | int index; | 466 | int index; |
@@ -477,14 +469,14 @@ void ath9k_ani_reset(struct ath_hal *ah) | |||
477 | return; | 469 | return; |
478 | 470 | ||
479 | index = ath9k_hw_get_ani_channel_idx(ah, chan); | 471 | index = ath9k_hw_get_ani_channel_idx(ah, chan); |
480 | aniState = &ahp->ah_ani[index]; | 472 | aniState = &ah->ah_ani[index]; |
481 | ahp->ah_curani = aniState; | 473 | ah->ah_curani = aniState; |
482 | 474 | ||
483 | if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION | 475 | if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION |
484 | && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { | 476 | && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { |
485 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 477 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
486 | "Reset ANI state opmode %u\n", ah->ah_opmode); | 478 | "Reset ANI state opmode %u\n", ah->ah_opmode); |
487 | ahp->ah_stats.ast_ani_reset++; | 479 | ah->ah_stats.ast_ani_reset++; |
488 | 480 | ||
489 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); | 481 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); |
490 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); | 482 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); |
@@ -498,13 +490,13 @@ void ath9k_ani_reset(struct ath_hal *ah) | |||
498 | ATH9K_RX_FILTER_PHYERR); | 490 | ATH9K_RX_FILTER_PHYERR); |
499 | 491 | ||
500 | if (ah->ah_opmode == NL80211_IFTYPE_AP) { | 492 | if (ah->ah_opmode == NL80211_IFTYPE_AP) { |
501 | ahp->ah_curani->ofdmTrigHigh = | 493 | ah->ah_curani->ofdmTrigHigh = |
502 | ah->ah_config.ofdm_trig_high; | 494 | ah->ah_config.ofdm_trig_high; |
503 | ahp->ah_curani->ofdmTrigLow = | 495 | ah->ah_curani->ofdmTrigLow = |
504 | ah->ah_config.ofdm_trig_low; | 496 | ah->ah_config.ofdm_trig_low; |
505 | ahp->ah_curani->cckTrigHigh = | 497 | ah->ah_curani->cckTrigHigh = |
506 | ah->ah_config.cck_trig_high; | 498 | ah->ah_config.cck_trig_high; |
507 | ahp->ah_curani->cckTrigLow = | 499 | ah->ah_curani->cckTrigLow = |
508 | ah->ah_config.cck_trig_low; | 500 | ah->ah_config.cck_trig_low; |
509 | } | 501 | } |
510 | ath9k_ani_restart(ah); | 502 | ath9k_ani_restart(ah); |
@@ -526,7 +518,7 @@ void ath9k_ani_reset(struct ath_hal *ah) | |||
526 | if (aniState->firstepLevel != 0) | 518 | if (aniState->firstepLevel != 0) |
527 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | 519 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
528 | aniState->firstepLevel); | 520 | aniState->firstepLevel); |
529 | if (ahp->ah_hasHwPhyCounters) { | 521 | if (ah->ah_hasHwPhyCounters) { |
530 | ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & | 522 | ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & |
531 | ~ATH9K_RX_FILTER_PHYERR); | 523 | ~ATH9K_RX_FILTER_PHYERR); |
532 | ath9k_ani_restart(ah); | 524 | ath9k_ani_restart(ah); |
@@ -540,34 +532,33 @@ void ath9k_ani_reset(struct ath_hal *ah) | |||
540 | } | 532 | } |
541 | } | 533 | } |
542 | 534 | ||
543 | void ath9k_hw_ani_monitor(struct ath_hal *ah, | 535 | void ath9k_hw_ani_monitor(struct ath_hw *ah, |
544 | const struct ath9k_node_stats *stats, | 536 | const struct ath9k_node_stats *stats, |
545 | struct ath9k_channel *chan) | 537 | struct ath9k_channel *chan) |
546 | { | 538 | { |
547 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
548 | struct ar5416AniState *aniState; | 539 | struct ar5416AniState *aniState; |
549 | int32_t listenTime; | 540 | int32_t listenTime; |
550 | 541 | ||
551 | if (!DO_ANI(ah)) | 542 | if (!DO_ANI(ah)) |
552 | return; | 543 | return; |
553 | 544 | ||
554 | aniState = ahp->ah_curani; | 545 | aniState = ah->ah_curani; |
555 | ahp->ah_stats.ast_nodestats = *stats; | 546 | ah->ah_stats.ast_nodestats = *stats; |
556 | 547 | ||
557 | listenTime = ath9k_hw_ani_get_listen_time(ah); | 548 | listenTime = ath9k_hw_ani_get_listen_time(ah); |
558 | if (listenTime < 0) { | 549 | if (listenTime < 0) { |
559 | ahp->ah_stats.ast_ani_lneg++; | 550 | ah->ah_stats.ast_ani_lneg++; |
560 | ath9k_ani_restart(ah); | 551 | ath9k_ani_restart(ah); |
561 | return; | 552 | return; |
562 | } | 553 | } |
563 | 554 | ||
564 | aniState->listenTime += listenTime; | 555 | aniState->listenTime += listenTime; |
565 | 556 | ||
566 | if (ahp->ah_hasHwPhyCounters) { | 557 | if (ah->ah_hasHwPhyCounters) { |
567 | u32 phyCnt1, phyCnt2; | 558 | u32 phyCnt1, phyCnt2; |
568 | u32 ofdmPhyErrCnt, cckPhyErrCnt; | 559 | u32 ofdmPhyErrCnt, cckPhyErrCnt; |
569 | 560 | ||
570 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | 561 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
571 | 562 | ||
572 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); | 563 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); |
573 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | 564 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); |
@@ -600,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, | |||
600 | } | 591 | } |
601 | 592 | ||
602 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; | 593 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; |
603 | ahp->ah_stats.ast_ani_ofdmerrs += | 594 | ah->ah_stats.ast_ani_ofdmerrs += |
604 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; | 595 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; |
605 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; | 596 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; |
606 | 597 | ||
607 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; | 598 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; |
608 | ahp->ah_stats.ast_ani_cckerrs += | 599 | ah->ah_stats.ast_ani_cckerrs += |
609 | cckPhyErrCnt - aniState->cckPhyErrCount; | 600 | cckPhyErrCnt - aniState->cckPhyErrCount; |
610 | aniState->cckPhyErrCount = cckPhyErrCnt; | 601 | aniState->cckPhyErrCount = cckPhyErrCnt; |
611 | } | 602 | } |
612 | 603 | ||
613 | if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { | 604 | if (aniState->listenTime > 5 * ah->ah_aniPeriod) { |
614 | if (aniState->ofdmPhyErrCount <= aniState->listenTime * | 605 | if (aniState->ofdmPhyErrCount <= aniState->listenTime * |
615 | aniState->ofdmTrigLow / 1000 && | 606 | aniState->ofdmTrigLow / 1000 && |
616 | aniState->cckPhyErrCount <= aniState->listenTime * | 607 | aniState->cckPhyErrCount <= aniState->listenTime * |
617 | aniState->cckTrigLow / 1000) | 608 | aniState->cckTrigLow / 1000) |
618 | ath9k_hw_ani_lower_immunity(ah); | 609 | ath9k_hw_ani_lower_immunity(ah); |
619 | ath9k_ani_restart(ah); | 610 | ath9k_ani_restart(ah); |
620 | } else if (aniState->listenTime > ahp->ah_aniPeriod) { | 611 | } else if (aniState->listenTime > ah->ah_aniPeriod) { |
621 | if (aniState->ofdmPhyErrCount > aniState->listenTime * | 612 | if (aniState->ofdmPhyErrCount > aniState->listenTime * |
622 | aniState->ofdmTrigHigh / 1000) { | 613 | aniState->ofdmTrigHigh / 1000) { |
623 | ath9k_hw_ani_ofdm_err_trigger(ah); | 614 | ath9k_hw_ani_ofdm_err_trigger(ah); |
@@ -631,20 +622,16 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, | |||
631 | } | 622 | } |
632 | } | 623 | } |
633 | 624 | ||
634 | bool ath9k_hw_phycounters(struct ath_hal *ah) | 625 | bool ath9k_hw_phycounters(struct ath_hw *ah) |
635 | { | 626 | { |
636 | struct ath_hal_5416 *ahp = AH5416(ah); | 627 | return ah->ah_hasHwPhyCounters ? true : false; |
637 | |||
638 | return ahp->ah_hasHwPhyCounters ? true : false; | ||
639 | } | 628 | } |
640 | 629 | ||
641 | void ath9k_enable_mib_counters(struct ath_hal *ah) | 630 | void ath9k_enable_mib_counters(struct ath_hw *ah) |
642 | { | 631 | { |
643 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
644 | |||
645 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); | 632 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); |
646 | 633 | ||
647 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | 634 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
648 | 635 | ||
649 | REG_WRITE(ah, AR_FILT_OFDM, 0); | 636 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
650 | REG_WRITE(ah, AR_FILT_CCK, 0); | 637 | REG_WRITE(ah, AR_FILT_CCK, 0); |
@@ -655,21 +642,19 @@ void ath9k_enable_mib_counters(struct ath_hal *ah) | |||
655 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | 642 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
656 | } | 643 | } |
657 | 644 | ||
658 | void ath9k_hw_disable_mib_counters(struct ath_hal *ah) | 645 | void ath9k_hw_disable_mib_counters(struct ath_hw *ah) |
659 | { | 646 | { |
660 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
661 | |||
662 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); | 647 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); |
663 | 648 | ||
664 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); | 649 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); |
665 | 650 | ||
666 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | 651 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
667 | 652 | ||
668 | REG_WRITE(ah, AR_FILT_OFDM, 0); | 653 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
669 | REG_WRITE(ah, AR_FILT_CCK, 0); | 654 | REG_WRITE(ah, AR_FILT_CCK, 0); |
670 | } | 655 | } |
671 | 656 | ||
672 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, | 657 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, |
673 | u32 *rxc_pcnt, | 658 | u32 *rxc_pcnt, |
674 | u32 *rxf_pcnt, | 659 | u32 *rxf_pcnt, |
675 | u32 *txf_pcnt) | 660 | u32 *txf_pcnt) |
@@ -714,10 +699,9 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, | |||
714 | * any of the MIB counters overflow/trigger so don't assume we're | 699 | * any of the MIB counters overflow/trigger so don't assume we're |
715 | * here because a PHY error counter triggered. | 700 | * here because a PHY error counter triggered. |
716 | */ | 701 | */ |
717 | void ath9k_hw_procmibevent(struct ath_hal *ah, | 702 | void ath9k_hw_procmibevent(struct ath_hw *ah, |
718 | const struct ath9k_node_stats *stats) | 703 | const struct ath9k_node_stats *stats) |
719 | { | 704 | { |
720 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
721 | u32 phyCnt1, phyCnt2; | 705 | u32 phyCnt1, phyCnt2; |
722 | 706 | ||
723 | /* Reset these counters regardless */ | 707 | /* Reset these counters regardless */ |
@@ -727,8 +711,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, | |||
727 | REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); | 711 | REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); |
728 | 712 | ||
729 | /* Clear the mib counters and save them in the stats */ | 713 | /* Clear the mib counters and save them in the stats */ |
730 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | 714 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
731 | ahp->ah_stats.ast_nodestats = *stats; | 715 | ah->ah_stats.ast_nodestats = *stats; |
732 | 716 | ||
733 | if (!DO_ANI(ah)) | 717 | if (!DO_ANI(ah)) |
734 | return; | 718 | return; |
@@ -738,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, | |||
738 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | 722 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); |
739 | if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || | 723 | if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || |
740 | ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { | 724 | ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { |
741 | struct ar5416AniState *aniState = ahp->ah_curani; | 725 | struct ar5416AniState *aniState = ah->ah_curani; |
742 | u32 ofdmPhyErrCnt, cckPhyErrCnt; | 726 | u32 ofdmPhyErrCnt, cckPhyErrCnt; |
743 | 727 | ||
744 | /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ | 728 | /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ |
745 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; | 729 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; |
746 | ahp->ah_stats.ast_ani_ofdmerrs += | 730 | ah->ah_stats.ast_ani_ofdmerrs += |
747 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; | 731 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; |
748 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; | 732 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; |
749 | 733 | ||
750 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; | 734 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; |
751 | ahp->ah_stats.ast_ani_cckerrs += | 735 | ah->ah_stats.ast_ani_cckerrs += |
752 | cckPhyErrCnt - aniState->cckPhyErrCount; | 736 | cckPhyErrCnt - aniState->cckPhyErrCount; |
753 | aniState->cckPhyErrCount = cckPhyErrCnt; | 737 | aniState->cckPhyErrCount = cckPhyErrCnt; |
754 | 738 | ||
@@ -767,9 +751,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, | |||
767 | } | 751 | } |
768 | } | 752 | } |
769 | 753 | ||
770 | void ath9k_hw_ani_setup(struct ath_hal *ah) | 754 | void ath9k_hw_ani_setup(struct ath_hw *ah) |
771 | { | 755 | { |
772 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
773 | int i; | 756 | int i; |
774 | 757 | ||
775 | const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; | 758 | const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; |
@@ -778,66 +761,63 @@ void ath9k_hw_ani_setup(struct ath_hal *ah) | |||
778 | const int firpwr[] = { -78, -78, -78, -78, -80 }; | 761 | const int firpwr[] = { -78, -78, -78, -78, -80 }; |
779 | 762 | ||
780 | for (i = 0; i < 5; i++) { | 763 | for (i = 0; i < 5; i++) { |
781 | ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; | 764 | ah->ah_totalSizeDesired[i] = totalSizeDesired[i]; |
782 | ahp->ah_coarseHigh[i] = coarseHigh[i]; | 765 | ah->ah_coarseHigh[i] = coarseHigh[i]; |
783 | ahp->ah_coarseLow[i] = coarseLow[i]; | 766 | ah->ah_coarseLow[i] = coarseLow[i]; |
784 | ahp->ah_firpwr[i] = firpwr[i]; | 767 | ah->ah_firpwr[i] = firpwr[i]; |
785 | } | 768 | } |
786 | } | 769 | } |
787 | 770 | ||
788 | void ath9k_hw_ani_attach(struct ath_hal *ah) | 771 | void ath9k_hw_ani_attach(struct ath_hw *ah) |
789 | { | 772 | { |
790 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
791 | int i; | 773 | int i; |
792 | 774 | ||
793 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); | 775 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); |
794 | 776 | ||
795 | ahp->ah_hasHwPhyCounters = 1; | 777 | ah->ah_hasHwPhyCounters = 1; |
796 | 778 | ||
797 | memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); | 779 | memset(ah->ah_ani, 0, sizeof(ah->ah_ani)); |
798 | for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { | 780 | for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { |
799 | ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; | 781 | ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; |
800 | ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; | 782 | ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; |
801 | ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; | 783 | ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; |
802 | ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; | 784 | ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; |
803 | ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; | 785 | ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; |
804 | ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; | 786 | ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; |
805 | ahp->ah_ani[i].ofdmWeakSigDetectOff = | 787 | ah->ah_ani[i].ofdmWeakSigDetectOff = |
806 | !ATH9K_ANI_USE_OFDM_WEAK_SIG; | 788 | !ATH9K_ANI_USE_OFDM_WEAK_SIG; |
807 | ahp->ah_ani[i].cckWeakSigThreshold = | 789 | ah->ah_ani[i].cckWeakSigThreshold = |
808 | ATH9K_ANI_CCK_WEAK_SIG_THR; | 790 | ATH9K_ANI_CCK_WEAK_SIG_THR; |
809 | ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; | 791 | ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; |
810 | ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; | 792 | ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; |
811 | if (ahp->ah_hasHwPhyCounters) { | 793 | if (ah->ah_hasHwPhyCounters) { |
812 | ahp->ah_ani[i].ofdmPhyErrBase = | 794 | ah->ah_ani[i].ofdmPhyErrBase = |
813 | AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; | 795 | AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; |
814 | ahp->ah_ani[i].cckPhyErrBase = | 796 | ah->ah_ani[i].cckPhyErrBase = |
815 | AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; | 797 | AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; |
816 | } | 798 | } |
817 | } | 799 | } |
818 | if (ahp->ah_hasHwPhyCounters) { | 800 | if (ah->ah_hasHwPhyCounters) { |
819 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 801 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
820 | "Setting OfdmErrBase = 0x%08x\n", | 802 | "Setting OfdmErrBase = 0x%08x\n", |
821 | ahp->ah_ani[0].ofdmPhyErrBase); | 803 | ah->ah_ani[0].ofdmPhyErrBase); |
822 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", | 804 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", |
823 | ahp->ah_ani[0].cckPhyErrBase); | 805 | ah->ah_ani[0].cckPhyErrBase); |
824 | 806 | ||
825 | REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); | 807 | REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase); |
826 | REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); | 808 | REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase); |
827 | ath9k_enable_mib_counters(ah); | 809 | ath9k_enable_mib_counters(ah); |
828 | } | 810 | } |
829 | ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; | 811 | ah->ah_aniPeriod = ATH9K_ANI_PERIOD; |
830 | if (ah->ah_config.enable_ani) | 812 | if (ah->ah_config.enable_ani) |
831 | ahp->ah_procPhyErr |= HAL_PROCESS_ANI; | 813 | ah->ah_procPhyErr |= HAL_PROCESS_ANI; |
832 | } | 814 | } |
833 | 815 | ||
834 | void ath9k_hw_ani_detach(struct ath_hal *ah) | 816 | void ath9k_hw_ani_detach(struct ath_hw *ah) |
835 | { | 817 | { |
836 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
837 | |||
838 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); | 818 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); |
839 | 819 | ||
840 | if (ahp->ah_hasHwPhyCounters) { | 820 | if (ah->ah_hasHwPhyCounters) { |
841 | ath9k_hw_disable_mib_counters(ah); | 821 | ath9k_hw_disable_mib_counters(ah); |
842 | REG_WRITE(ah, AR_PHY_ERR_1, 0); | 822 | REG_WRITE(ah, AR_PHY_ERR_1, 0); |
843 | REG_WRITE(ah, AR_PHY_ERR_2, 0); | 823 | REG_WRITE(ah, AR_PHY_ERR_2, 0); |