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authorNick Kossifidis <mick@madwifi.org>2008-07-19 23:36:52 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-08-01 15:31:32 -0400
commit2203d6be7ed17af81a1dc35a0af9806086743b02 (patch)
tree039240013629cb1efa38ab931ceee2a8a1936962 /drivers/net/wireless/ath5k
parente5a4ad0dda8f79a984ba6391af65274b482b6703 (diff)
ath5k: Misc hw_reset updates
* Update hw_reset to calculate some of the values we were using as static * Increase activation to rx delay Changes-licensed-under: ISC Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath5k')
-rw-r--r--drivers/net/wireless/ath5k/hw.c31
1 files changed, 27 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
index 8cd8659e9128..dc51b844c62d 100644
--- a/drivers/net/wireless/ath5k/hw.c
+++ b/drivers/net/wireless/ath5k/hw.c
@@ -847,7 +847,22 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
847 else 847 else
848 ath5k_hw_reg_write(ah, 0x00000000, 0x994c); 848 ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
849 849
850 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); 850 /* Some bits are disabled here, we know nothing about
851 * register 0xa228 yet, most of the times this ends up
852 * with a value 0x9b5 -haven't seen any dump with
853 * a different value- */
854 /* Got this from decompiling binary HAL */
855 data = ath5k_hw_reg_read(ah, 0xa228);
856 data &= 0xfffffdff;
857 ath5k_hw_reg_write(ah, data, 0xa228);
858
859 data = ath5k_hw_reg_read(ah, 0xa228);
860 data &= 0xfffe03ff;
861 ath5k_hw_reg_write(ah, data, 0xa228);
862 data = 0;
863
864 /* Just write 0x9b5 ? */
865 /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */
851 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); 866 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
852 ath5k_hw_reg_write(ah, 0x00000000, 0xa254); 867 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
853 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL); 868 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
@@ -864,6 +879,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
864 else 879 else
865 data = 0xffb80d20; 880 data = 0xffb80d20;
866 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); 881 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
882 data = 0;
867 } 883 }
868 884
869 /* 885 /*
@@ -883,7 +899,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
883 899
884 /* 900 /*
885 * Write RF registers 901 * Write RF registers
886 * TODO:Does this work on 5211 (5111) ?
887 */ 902 */
888 ret = ath5k_hw_rfregs(ah, channel, mode); 903 ret = ath5k_hw_rfregs(ah, channel, mode);
889 if (ret) 904 if (ret)
@@ -1048,7 +1063,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
1048 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1063 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1049 1064
1050 /* 1065 /*
1051 * 5111/5112 Specific 1066 * On 5211+ read activation -> rx delay
1067 * and use it.
1052 */ 1068 */
1053 if (ah->ah_version != AR5K_AR5210) { 1069 if (ah->ah_version != AR5K_AR5210) {
1054 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 1070 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
@@ -1056,7 +1072,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
1056 data = (channel->hw_value & CHANNEL_CCK) ? 1072 data = (channel->hw_value & CHANNEL_CCK) ?
1057 ((data << 2) / 22) : (data / 10); 1073 ((data << 2) / 22) : (data / 10);
1058 1074
1059 udelay(100 + data); 1075 udelay(100 + (2 * data));
1076 data = 0;
1060 } else { 1077 } else {
1061 mdelay(1); 1078 mdelay(1);
1062 } 1079 }
@@ -1139,6 +1156,12 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
1139 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); 1156 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1140 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); 1157 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
1141 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING); 1158 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
1159
1160 data = ath5k_hw_reg_read(ah, AR5K_USEC_5211) & 0xffffc07f ;
1161 data |= (ah->ah_phy_spending == AR5K_PHY_SPENDING_18) ?
1162 0x00000f80 : 0x00001380 ;
1163 ath5k_hw_reg_write(ah, data, AR5K_USEC_5211);
1164 data = 0;
1142 } 1165 }
1143 1166
1144 if (ah->ah_version == AR5K_AR5212) { 1167 if (ah->ah_version == AR5K_AR5212) {