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authorSujith Manoharan <c_manoha@qca.qualcomm.com>2015-03-09 04:50:06 -0400
committerKalle Valo <kvalo@codeaurora.org>2015-03-13 09:19:28 -0400
commite519f78f1191007604c056dfcb372d4fe3a4b05b (patch)
tree4afce2fa31bf040487ab4c09f8286307b925f49a /drivers/net/wireless/ath/ath9k
parent02beaf1a5b8f05ead295d781522b1684dc5e7263 (diff)
ath9k: Add PCIE powersave macros
These will be used to handle chip-specific power save configuration. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 29a25d92add7..2bb3b334a23f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -309,6 +309,12 @@ enum ath9k_hw_hang_checks {
309 HW_MAC_HANG = BIT(5), 309 HW_MAC_HANG = BIT(5),
310}; 310};
311 311
312#define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
313#define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
314#define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
315#define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
316#define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
317
312struct ath9k_ops_config { 318struct ath9k_ops_config {
313 int dma_beacon_response_time; 319 int dma_beacon_response_time;
314 int sw_beacon_response_time; 320 int sw_beacon_response_time;