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authorSujith Manoharan <c_manoha@qca.qualcomm.com>2013-07-23 06:55:17 -0400
committerJohn W. Linville <linville@tuxdriver.com>2013-07-24 11:02:39 -0400
commitc2b8359d7878f75584ed68b7a2b930bd9bea814d (patch)
tree491257b9955fb717733f8b4874484d5588ec059d /drivers/net/wireless/ath/ath9k
parenta4df8f56e92104c5e7be82cc2c471e600ea3f9ef (diff)
ath9k: Fix diversity combining for AR9285
When antenna diversity combining is enabled in the EEPROM, the initial values for the MAIN/ALT config have to be programmed correctly. This patch adds it for AR9285. Since the diversity combining macros are common to all chip families, remove the redundant AR9285 macros and move the definitions to phy.h. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h5
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h7
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c19
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h7
7 files changed, 30 insertions, 20 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
index f9eb2c357169..d3f09287d1d0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
@@ -317,10 +317,6 @@
317#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 317#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
318#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 318#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
319#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 319#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
320#define AR_PHY_9285_ANT_DIV_LNA1 2
321#define AR_PHY_9285_ANT_DIV_LNA2 1
322#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
323#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
324#define AR_PHY_9285_ANT_DIV_GAINTB_0 0 320#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
325#define AR_PHY_9285_ANT_DIV_GAINTB_1 1 321#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
326 322
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index d105e43d22e1..a98e6a3dd8a1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3673,9 +3673,9 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3673 AR_PHY_ANT_DIV_ALT_GAINTB | 3673 AR_PHY_ANT_DIV_ALT_GAINTB |
3674 AR_PHY_ANT_DIV_MAIN_GAINTB)); 3674 AR_PHY_ANT_DIV_MAIN_GAINTB));
3675 /* by default use LNA1 for the main antenna */ 3675 /* by default use LNA1 for the main antenna */
3676 regval |= (AR_PHY_ANT_DIV_LNA1 << 3676 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
3677 AR_PHY_ANT_DIV_MAIN_LNACONF_S); 3677 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
3678 regval |= (AR_PHY_ANT_DIV_LNA2 << 3678 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
3679 AR_PHY_ANT_DIV_ALT_LNACONF_S); 3679 AR_PHY_ANT_DIV_ALT_LNACONF_S);
3680 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3680 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3681 } 3681 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 2db4ddf74bc2..3ec33ce7be66 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1465,8 +1465,8 @@ static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1465 AR_PHY_ANT_DIV_ALT_LNACONF | 1465 AR_PHY_ANT_DIV_ALT_LNACONF |
1466 AR_PHY_ANT_DIV_MAIN_GAINTB | 1466 AR_PHY_ANT_DIV_MAIN_GAINTB |
1467 AR_PHY_ANT_DIV_ALT_GAINTB); 1467 AR_PHY_ANT_DIV_ALT_GAINTB);
1468 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S); 1468 regval |= (ATH_ANT_DIV_COMB_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1469 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S); 1469 regval |= (ATH_ANT_DIV_COMB_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1470 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1470 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1471 } 1471 }
1472} 1472}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index d4d39f305a0b..23c019d0d9aa 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -296,11 +296,6 @@
296#define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000 296#define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000
297#define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30 297#define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30
298 298
299#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2 0x0
300#define AR_PHY_ANT_DIV_LNA2 0x1
301#define AR_PHY_ANT_DIV_LNA1 0x2
302#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2 0x3
303
304#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) 299#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
305#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) 300#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
306#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34) 301#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index c1224b5a257b..76e38d3540c0 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -591,13 +591,6 @@ static inline void ath_fill_led_pin(struct ath_softc *sc)
591#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 591#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
592#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 592#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
593 593
594enum ath9k_ant_div_comb_lna_conf {
595 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
596 ATH_ANT_DIV_COMB_LNA2,
597 ATH_ANT_DIV_COMB_LNA1,
598 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
599};
600
601struct ath_ant_comb { 594struct ath_ant_comb {
602 u16 count; 595 u16 count;
603 u16 total_pkt_count; 596 u16 total_pkt_count;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index c2bfd748eed8..9ea8e4b779c9 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -812,6 +812,7 @@ static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
812static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 812static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
813 struct ath9k_channel *chan) 813 struct ath9k_channel *chan)
814{ 814{
815 struct ath9k_hw_capabilities *pCap = &ah->caps;
815 struct modal_eep_4k_header *pModal; 816 struct modal_eep_4k_header *pModal;
816 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 817 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
817 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 818 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
@@ -858,6 +859,24 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
858 859
859 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 860 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
860 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 861 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
862
863 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
864 /*
865 * If diversity combining is enabled,
866 * set MAIN to LNA1 and ALT to LNA2 initially.
867 */
868 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
869 regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
870 AR_PHY_9285_ANT_DIV_ALT_LNACONF));
871
872 regVal |= (ATH_ANT_DIV_COMB_LNA1 <<
873 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S);
874 regVal |= (ATH_ANT_DIV_COMB_LNA2 <<
875 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S);
876 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));
877 regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);
878 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
879 }
861 } 880 }
862 881
863 if (pModal->version >= 2) { 882 if (pModal->version >= 2) {
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 8b380305b0fc..4a1b99238ec2 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -48,4 +48,11 @@
48#define AR_PHY_PLL_CONTROL 0x16180 48#define AR_PHY_PLL_CONTROL 0x16180
49#define AR_PHY_PLL_MODE 0x16184 49#define AR_PHY_PLL_MODE 0x16184
50 50
51enum ath9k_ant_div_comb_lna_conf {
52 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
53 ATH_ANT_DIV_COMB_LNA2,
54 ATH_ANT_DIV_COMB_LNA1,
55 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
56};
57
51#endif 58#endif