aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/ath/ath9k/reg.h
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 19:29:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 19:29:25 -0400
commit7a6362800cb7d1d618a697a650c7aaed3eb39320 (patch)
tree087f9bc6c13ef1fad4b392c5cf9325cd28fa8523 /drivers/net/wireless/ath/ath9k/reg.h
parent6445ced8670f37cfc2c5e24a9de9b413dbfc788d (diff)
parentceda86a108671294052cbf51660097b6534672f5 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1480 commits) bonding: enable netpoll without checking link status xfrm: Refcount destination entry on xfrm_lookup net: introduce rx_handler results and logic around that bonding: get rid of IFF_SLAVE_INACTIVE netdev->priv_flag bonding: wrap slave state work net: get rid of multiple bond-related netdevice->priv_flags bonding: register slave pointer for rx_handler be2net: Bump up the version number be2net: Copyright notice change. Update to Emulex instead of ServerEngines e1000e: fix kconfig for crc32 dependency netfilter ebtables: fix xt_AUDIT to work with ebtables xen network backend driver bonding: Improve syslog message at device creation time bonding: Call netif_carrier_off after register_netdevice bonding: Incorrect TX queue offset net_sched: fix ip_tos2prio xfrm: fix __xfrm_route_forward() be2net: Fix UDP packet detected status in RX compl Phonet: fix aligned-mode pipe socket buffer header reserve netxen: support for GbE port settings ... Fix up conflicts in drivers/staging/brcm80211/brcmsmac/wl_mac80211.c with the staging updates.
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/reg.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 4df5659c6c16..8fa8acfde62e 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -789,6 +789,7 @@
789#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 789#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
790#define AR_SREV_VERSION_9485 0x240 790#define AR_SREV_VERSION_9485 0x240
791#define AR_SREV_REVISION_9485_10 0 791#define AR_SREV_REVISION_9485_10 0
792#define AR_SREV_REVISION_9485_11 1
792 793
793#define AR_SREV_5416(_ah) \ 794#define AR_SREV_5416(_ah) \
794 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 795 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -866,6 +867,9 @@
866#define AR_SREV_9485_10(_ah) \ 867#define AR_SREV_9485_10(_ah) \
867 (AR_SREV_9485(_ah) && \ 868 (AR_SREV_9485(_ah) && \
868 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10)) 869 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
870#define AR_SREV_9485_11(_ah) \
871 (AR_SREV_9485(_ah) && \
872 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
869 873
870#define AR_SREV_9285E_20(_ah) \ 874#define AR_SREV_9285E_20(_ah) \
871 (AR_SREV_9285_12_OR_LATER(_ah) && \ 875 (AR_SREV_9285_12_OR_LATER(_ah) && \
@@ -874,6 +878,7 @@
874enum ath_usb_dev { 878enum ath_usb_dev {
875 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */ 879 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
876 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */ 880 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
881 STORAGE_DEVICE = 3,
877}; 882};
878 883
879#define AR_DEVID_7010(_ah) \ 884#define AR_DEVID_7010(_ah) \
@@ -1083,6 +1088,17 @@ enum {
1083#define AR_ENT_OTP 0x40d8 1088#define AR_ENT_OTP 0x40d8
1084#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 1089#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
1085#define AR_ENT_OTP_MPSD 0x00800000 1090#define AR_ENT_OTP_MPSD 0x00800000
1091#define AR_CH0_BB_DPLL2 0x16184
1092#define AR_CH0_BB_DPLL3 0x16188
1093#define AR_CH0_DDR_DPLL2 0x16244
1094#define AR_CH0_DDR_DPLL3 0x16248
1095#define AR_CH0_DPLL2_KD 0x03F80000
1096#define AR_CH0_DPLL2_KD_S 19
1097#define AR_CH0_DPLL2_KI 0x3C000000
1098#define AR_CH0_DPLL2_KI_S 26
1099#define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000
1100#define AR_CH0_DPLL3_PHASE_SHIFT_S 23
1101#define AR_PHY_CCA_NOM_VAL_2GHZ -118
1086 1102
1087#define AR_RTC_9300_PLL_DIV 0x000003ff 1103#define AR_RTC_9300_PLL_DIV 0x000003ff
1088#define AR_RTC_9300_PLL_DIV_S 0 1104#define AR_RTC_9300_PLL_DIV_S 0
@@ -1129,6 +1145,12 @@ enum {
1129#define AR_RTC_PLL_CLKSEL 0x00000300 1145#define AR_RTC_PLL_CLKSEL 0x00000300
1130#define AR_RTC_PLL_CLKSEL_S 8 1146#define AR_RTC_PLL_CLKSEL_S 8
1131 1147
1148#define PLL3 0x16188
1149#define PLL3_DO_MEAS_MASK 0x40000000
1150#define PLL4 0x1618c
1151#define PLL4_MEAS_DONE 0x8
1152#define SQSUM_DVC_MASK 0x007ffff8
1153
1132#define AR_RTC_RESET \ 1154#define AR_RTC_RESET \
1133 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 1155 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
1134#define AR_RTC_RESET_EN (0x00000001) 1156#define AR_RTC_RESET_EN (0x00000001)