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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-15 12:40:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-15 12:40:05 -0400
commit2ed0e21b30b53d3a94e204196e523e6c8f732b56 (patch)
treede2635426477d86338a9469ce09ba0626052288f /drivers/net/wireless/ath/ath9k/hw.c
parent0fa213310cd8fa7a51071cdcf130e26fa56e9549 (diff)
parent9cbc1cb8cd46ce1f7645b9de249b2ce8460129bb (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1244 commits) pkt_sched: Rename PSCHED_US2NS and PSCHED_NS2US ipv4: Fix fib_trie rebalancing Bluetooth: Fix issue with uninitialized nsh.type in DTL-1 driver Bluetooth: Fix Kconfig issue with RFKILL integration PIM-SM: namespace changes ipv4: update ARPD help text net: use a deferred timer in rt_check_expire ieee802154: fix kconfig bool/tristate muckup bonding: initialization rework bonding: use is_zero_ether_addr bonding: network device names are case sensative bonding: elminate bad refcount code bonding: fix style issues bonding: fix destructor bonding: remove bonding read/write semaphore bonding: initialize before registration bonding: bond_create always called with default parameters x_tables: Convert printk to pr_err netfilter: conntrack: optional reliable conntrack event delivery list_nulls: add hlist_nulls_add_head and hlist_nulls_del ...
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c3873
1 files changed, 3873 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
new file mode 100644
index 000000000000..1579c9407ed5
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -0,0 +1,3873 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
20#include "ath9k.h"
21#include "initvals.h"
22
23static int btcoex_enable;
24module_param(btcoex_enable, bool, 0);
25MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27#define ATH9K_CLOCK_RATE_CCK 22
28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40/********************/
41/* Helper Functions */
42/********************/
43
44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45{
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54}
55
56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57{
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64}
65
66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67{
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75}
76
77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78{
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85}
86
87/*
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
92 * from happening.
93 */
94
95void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96{
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98 unsigned long flags;
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102 } else
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
104}
105
106unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107{
108 u32 val;
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110 unsigned long flags;
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114 } else
115 val = ioread32(ah->ah_sc->mem + reg_offset);
116 return val;
117}
118
119bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120{
121 int i;
122
123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
131
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
135
136 return false;
137}
138
139u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140{
141 u32 retval;
142 int i;
143
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
146 val >>= 1;
147 }
148 return retval;
149}
150
151bool ath9k_get_channel_edges(struct ath_hw *ah,
152 u16 flags, u16 *low,
153 u16 *high)
154{
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
160 return true;
161 }
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
165 return true;
166 }
167 return false;
168}
169
170u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174{
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176 u32 kbps;
177
178 kbps = rates->info[rateix].ratekbps;
179
180 if (kbps == 0)
181 return 0;
182
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
187 phyTime >>= 1;
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190 break;
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207 } else {
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
213 }
214 break;
215 default:
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
219 txTime = 0;
220 break;
221 }
222
223 return txTime;
224}
225
226void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
229{
230 int8_t extoff;
231
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
235 return;
236 }
237
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 extoff = 1;
243 } else {
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 extoff = -1;
247 }
248
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
255}
256
257/******************/
258/* Chip Revisions */
259/******************/
260
261static void ath9k_hw_read_revisions(struct ath_hw *ah)
262{
263 u32 val;
264
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267 if (val == 0xFF) {
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273 } else {
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
281 }
282}
283
284static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285{
286 u32 val;
287 int i;
288
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296 return ath9k_hw_reverse_bits(val, 8);
297}
298
299/************************************/
300/* HW Attach, Detach, Init Routines */
301/************************************/
302
303static void ath9k_hw_disablepcie(struct ath_hw *ah)
304{
305 if (AR_SREV_9100(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319}
320
321static bool ath9k_hw_chip_test(struct ath_hw *ah)
322{
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324 u32 regHold[2];
325 u32 patternData[4] = { 0x55555555,
326 0xaaaaaaaa,
327 0x66666666,
328 0x99999999 };
329 int i, j;
330
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
333 u32 wrData, rdData;
334
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
345 return false;
346 }
347 }
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
357 return false;
358 }
359 }
360 REG_WRITE(ah, regAddr[i], regHold[i]);
361 }
362 udelay(100);
363
364 return true;
365}
366
367static const char *ath9k_hw_devname(u16 devid)
368{
369 switch (devid) {
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 }
384
385 return NULL;
386}
387
388static void ath9k_hw_set_defaults(struct ath_hw *ah)
389{
390 int i;
391
392 ah->config.dma_beacon_response_time = 2;
393 ah->config.sw_beacon_response_time = 10;
394 ah->config.additional_swba_backoff = 0;
395 ah->config.ack_6mb = 0x0;
396 ah->config.cwm_ignore_extcca = 0;
397 ah->config.pcie_powersave_enable = 0;
398 ah->config.pcie_clock_req = 0;
399 ah->config.pcie_waen = 0;
400 ah->config.analog_shiftreg = 1;
401 ah->config.ht_enable = 1;
402 ah->config.ofdm_trig_low = 200;
403 ah->config.ofdm_trig_high = 500;
404 ah->config.cck_trig_high = 200;
405 ah->config.cck_trig_low = 100;
406 ah->config.enable_ani = 1;
407 ah->config.diversity_control = 0;
408 ah->config.antenna_switch_swap = 0;
409
410 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
411 ah->config.spurchans[i][0] = AR_NO_SPUR;
412 ah->config.spurchans[i][1] = AR_NO_SPUR;
413 }
414
415 ah->config.intr_mitigation = true;
416
417 /*
418 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
419 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
420 * This means we use it for all AR5416 devices, and the few
421 * minor PCI AR9280 devices out there.
422 *
423 * Serialization is required because these devices do not handle
424 * well the case of two concurrent reads/writes due to the latency
425 * involved. During one read/write another read/write can be issued
426 * on another CPU while the previous read/write may still be working
427 * on our hardware, if we hit this case the hardware poops in a loop.
428 * We prevent this by serializing reads and writes.
429 *
430 * This issue is not present on PCI-Express devices or pre-AR5416
431 * devices (legacy, 802.11abg).
432 */
433 if (num_possible_cpus() > 1)
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
435}
436
437static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
438 int *status)
439{
440 struct ath_hw *ah;
441
442 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
443 if (ah == NULL) {
444 DPRINTF(sc, ATH_DBG_FATAL,
445 "Cannot allocate memory for state block\n");
446 *status = -ENOMEM;
447 return NULL;
448 }
449
450 ah->ah_sc = sc;
451 ah->hw_version.magic = AR5416_MAGIC;
452 ah->regulatory.country_code = CTRY_DEFAULT;
453 ah->hw_version.devid = devid;
454 ah->hw_version.subvendorid = 0;
455
456 ah->ah_flags = 0;
457 if ((devid == AR5416_AR9100_DEVID))
458 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
459 if (!AR_SREV_9100(ah))
460 ah->ah_flags = AH_USE_EEPROM;
461
462 ah->regulatory.power_limit = MAX_RATE_POWER;
463 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
464 ah->atim_window = 0;
465 ah->diversity_control = ah->config.diversity_control;
466 ah->antenna_switch_swap =
467 ah->config.antenna_switch_swap;
468 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
469 ah->beacon_interval = 100;
470 ah->enable_32kHz_clock = DONT_USE_32KHZ;
471 ah->slottime = (u32) -1;
472 ah->acktimeout = (u32) -1;
473 ah->ctstimeout = (u32) -1;
474 ah->globaltxtimeout = (u32) -1;
475
476 ah->gbeacon_rate = 0;
477
478 return ah;
479}
480
481static int ath9k_hw_rfattach(struct ath_hw *ah)
482{
483 bool rfStatus = false;
484 int ecode = 0;
485
486 rfStatus = ath9k_hw_init_rf(ah, &ecode);
487 if (!rfStatus) {
488 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
489 "RF setup failed, status: %u\n", ecode);
490 return ecode;
491 }
492
493 return 0;
494}
495
496static int ath9k_hw_rf_claim(struct ath_hw *ah)
497{
498 u32 val;
499
500 REG_WRITE(ah, AR_PHY(0), 0x00000007);
501
502 val = ath9k_hw_get_radiorev(ah);
503 switch (val & AR_RADIO_SREV_MAJOR) {
504 case 0:
505 val = AR_RAD5133_SREV_MAJOR;
506 break;
507 case AR_RAD5133_SREV_MAJOR:
508 case AR_RAD5122_SREV_MAJOR:
509 case AR_RAD2133_SREV_MAJOR:
510 case AR_RAD2122_SREV_MAJOR:
511 break;
512 default:
513 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
514 "Radio Chip Rev 0x%02X not supported\n",
515 val & AR_RADIO_SREV_MAJOR);
516 return -EOPNOTSUPP;
517 }
518
519 ah->hw_version.analog5GhzRev = val;
520
521 return 0;
522}
523
524static int ath9k_hw_init_macaddr(struct ath_hw *ah)
525{
526 u32 sum;
527 int i;
528 u16 eeval;
529
530 sum = 0;
531 for (i = 0; i < 3; i++) {
532 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
533 sum += eeval;
534 ah->macaddr[2 * i] = eeval >> 8;
535 ah->macaddr[2 * i + 1] = eeval & 0xff;
536 }
537 if (sum == 0 || sum == 0xffff * 3)
538 return -EADDRNOTAVAIL;
539
540 return 0;
541}
542
543static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
544{
545 u32 rxgain_type;
546
547 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
548 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
549
550 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
551 INIT_INI_ARRAY(&ah->iniModesRxGain,
552 ar9280Modes_backoff_13db_rxgain_9280_2,
553 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
554 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
555 INIT_INI_ARRAY(&ah->iniModesRxGain,
556 ar9280Modes_backoff_23db_rxgain_9280_2,
557 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
558 else
559 INIT_INI_ARRAY(&ah->iniModesRxGain,
560 ar9280Modes_original_rxgain_9280_2,
561 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
562 } else {
563 INIT_INI_ARRAY(&ah->iniModesRxGain,
564 ar9280Modes_original_rxgain_9280_2,
565 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
566 }
567}
568
569static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
570{
571 u32 txgain_type;
572
573 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
574 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
575
576 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
577 INIT_INI_ARRAY(&ah->iniModesTxGain,
578 ar9280Modes_high_power_tx_gain_9280_2,
579 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
580 else
581 INIT_INI_ARRAY(&ah->iniModesTxGain,
582 ar9280Modes_original_tx_gain_9280_2,
583 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
584 } else {
585 INIT_INI_ARRAY(&ah->iniModesTxGain,
586 ar9280Modes_original_tx_gain_9280_2,
587 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
588 }
589}
590
591static int ath9k_hw_post_attach(struct ath_hw *ah)
592{
593 int ecode;
594
595 if (!ath9k_hw_chip_test(ah))
596 return -ENODEV;
597
598 ecode = ath9k_hw_rf_claim(ah);
599 if (ecode != 0)
600 return ecode;
601
602 ecode = ath9k_hw_eeprom_attach(ah);
603 if (ecode != 0)
604 return ecode;
605
606 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
607 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
608
609 ecode = ath9k_hw_rfattach(ah);
610 if (ecode != 0)
611 return ecode;
612
613 if (!AR_SREV_9100(ah)) {
614 ath9k_hw_ani_setup(ah);
615 ath9k_hw_ani_attach(ah);
616 }
617
618 return 0;
619}
620
621static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
622 int *status)
623{
624 struct ath_hw *ah;
625 int ecode;
626 u32 i, j;
627
628 ah = ath9k_hw_newstate(devid, sc, status);
629 if (ah == NULL)
630 return NULL;
631
632 ath9k_hw_set_defaults(ah);
633
634 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
635 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
636 ecode = -EIO;
637 goto bad;
638 }
639
640 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
641 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
642 ecode = -EIO;
643 goto bad;
644 }
645
646 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
647 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
648 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
649 ah->config.serialize_regmode =
650 SER_REG_MODE_ON;
651 } else {
652 ah->config.serialize_regmode =
653 SER_REG_MODE_OFF;
654 }
655 }
656
657 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
658 ah->config.serialize_regmode);
659
660 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
661 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
662 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
663 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
664 DPRINTF(sc, ATH_DBG_FATAL,
665 "Mac Chip Rev 0x%02x.%x is not supported by "
666 "this driver\n", ah->hw_version.macVersion,
667 ah->hw_version.macRev);
668 ecode = -EOPNOTSUPP;
669 goto bad;
670 }
671
672 if (AR_SREV_9100(ah)) {
673 ah->iq_caldata.calData = &iq_cal_multi_sample;
674 ah->supp_cals = IQ_MISMATCH_CAL;
675 ah->is_pciexpress = false;
676 }
677 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
678
679 if (AR_SREV_9160_10_OR_LATER(ah)) {
680 if (AR_SREV_9280_10_OR_LATER(ah)) {
681 ah->iq_caldata.calData = &iq_cal_single_sample;
682 ah->adcgain_caldata.calData =
683 &adc_gain_cal_single_sample;
684 ah->adcdc_caldata.calData =
685 &adc_dc_cal_single_sample;
686 ah->adcdc_calinitdata.calData =
687 &adc_init_dc_cal;
688 } else {
689 ah->iq_caldata.calData = &iq_cal_multi_sample;
690 ah->adcgain_caldata.calData =
691 &adc_gain_cal_multi_sample;
692 ah->adcdc_caldata.calData =
693 &adc_dc_cal_multi_sample;
694 ah->adcdc_calinitdata.calData =
695 &adc_init_dc_cal;
696 }
697 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
698 }
699
700 ah->ani_function = ATH9K_ANI_ALL;
701 if (AR_SREV_9280_10_OR_LATER(ah))
702 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
703
704 if (AR_SREV_9285_12_OR_LATER(ah)) {
705
706 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
707 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
708 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
709 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
710
711 if (ah->config.pcie_clock_req) {
712 INIT_INI_ARRAY(&ah->iniPcieSerdes,
713 ar9285PciePhy_clkreq_off_L1_9285_1_2,
714 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
715 } else {
716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
717 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
718 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
719 2);
720 }
721 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
722 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
723 ARRAY_SIZE(ar9285Modes_9285), 6);
724 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
725 ARRAY_SIZE(ar9285Common_9285), 2);
726
727 if (ah->config.pcie_clock_req) {
728 INIT_INI_ARRAY(&ah->iniPcieSerdes,
729 ar9285PciePhy_clkreq_off_L1_9285,
730 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
731 } else {
732 INIT_INI_ARRAY(&ah->iniPcieSerdes,
733 ar9285PciePhy_clkreq_always_on_L1_9285,
734 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
735 }
736 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
737 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
738 ARRAY_SIZE(ar9280Modes_9280_2), 6);
739 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
740 ARRAY_SIZE(ar9280Common_9280_2), 2);
741
742 if (ah->config.pcie_clock_req) {
743 INIT_INI_ARRAY(&ah->iniPcieSerdes,
744 ar9280PciePhy_clkreq_off_L1_9280,
745 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
746 } else {
747 INIT_INI_ARRAY(&ah->iniPcieSerdes,
748 ar9280PciePhy_clkreq_always_on_L1_9280,
749 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
750 }
751 INIT_INI_ARRAY(&ah->iniModesAdditional,
752 ar9280Modes_fast_clock_9280_2,
753 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
754 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
756 ARRAY_SIZE(ar9280Modes_9280), 6);
757 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
758 ARRAY_SIZE(ar9280Common_9280), 2);
759 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
760 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
761 ARRAY_SIZE(ar5416Modes_9160), 6);
762 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
763 ARRAY_SIZE(ar5416Common_9160), 2);
764 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
765 ARRAY_SIZE(ar5416Bank0_9160), 2);
766 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
767 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
768 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
769 ARRAY_SIZE(ar5416Bank1_9160), 2);
770 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
771 ARRAY_SIZE(ar5416Bank2_9160), 2);
772 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
773 ARRAY_SIZE(ar5416Bank3_9160), 3);
774 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
775 ARRAY_SIZE(ar5416Bank6_9160), 3);
776 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
777 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
778 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
779 ARRAY_SIZE(ar5416Bank7_9160), 2);
780 if (AR_SREV_9160_11(ah)) {
781 INIT_INI_ARRAY(&ah->iniAddac,
782 ar5416Addac_91601_1,
783 ARRAY_SIZE(ar5416Addac_91601_1), 2);
784 } else {
785 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
786 ARRAY_SIZE(ar5416Addac_9160), 2);
787 }
788 } else if (AR_SREV_9100_OR_LATER(ah)) {
789 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
790 ARRAY_SIZE(ar5416Modes_9100), 6);
791 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
792 ARRAY_SIZE(ar5416Common_9100), 2);
793 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
794 ARRAY_SIZE(ar5416Bank0_9100), 2);
795 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
796 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
797 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
798 ARRAY_SIZE(ar5416Bank1_9100), 2);
799 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
800 ARRAY_SIZE(ar5416Bank2_9100), 2);
801 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
802 ARRAY_SIZE(ar5416Bank3_9100), 3);
803 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
804 ARRAY_SIZE(ar5416Bank6_9100), 3);
805 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
806 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
807 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
808 ARRAY_SIZE(ar5416Bank7_9100), 2);
809 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
810 ARRAY_SIZE(ar5416Addac_9100), 2);
811 } else {
812 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
813 ARRAY_SIZE(ar5416Modes), 6);
814 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
815 ARRAY_SIZE(ar5416Common), 2);
816 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
817 ARRAY_SIZE(ar5416Bank0), 2);
818 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
819 ARRAY_SIZE(ar5416BB_RfGain), 3);
820 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
821 ARRAY_SIZE(ar5416Bank1), 2);
822 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
823 ARRAY_SIZE(ar5416Bank2), 2);
824 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
825 ARRAY_SIZE(ar5416Bank3), 3);
826 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
827 ARRAY_SIZE(ar5416Bank6), 3);
828 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
829 ARRAY_SIZE(ar5416Bank6TPC), 3);
830 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
831 ARRAY_SIZE(ar5416Bank7), 2);
832 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
833 ARRAY_SIZE(ar5416Addac), 2);
834 }
835
836 if (ah->is_pciexpress)
837 ath9k_hw_configpcipowersave(ah, 0);
838 else
839 ath9k_hw_disablepcie(ah);
840
841 ecode = ath9k_hw_post_attach(ah);
842 if (ecode != 0)
843 goto bad;
844
845 if (AR_SREV_9285_12_OR_LATER(ah)) {
846 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
847
848 /* txgain table */
849 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
850 INIT_INI_ARRAY(&ah->iniModesTxGain,
851 ar9285Modes_high_power_tx_gain_9285_1_2,
852 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
853 } else {
854 INIT_INI_ARRAY(&ah->iniModesTxGain,
855 ar9285Modes_original_tx_gain_9285_1_2,
856 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
857 }
858
859 }
860
861 /* rxgain table */
862 if (AR_SREV_9280_20(ah))
863 ath9k_hw_init_rxgain_ini(ah);
864
865 /* txgain table */
866 if (AR_SREV_9280_20(ah))
867 ath9k_hw_init_txgain_ini(ah);
868
869 ath9k_hw_fill_cap_info(ah);
870
871 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
872 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
873
874 /* EEPROM Fixup */
875 for (i = 0; i < ah->iniModes.ia_rows; i++) {
876 u32 reg = INI_RA(&ah->iniModes, i, 0);
877
878 for (j = 1; j < ah->iniModes.ia_columns; j++) {
879 u32 val = INI_RA(&ah->iniModes, i, j);
880
881 INI_RA(&ah->iniModes, i, j) =
882 ath9k_hw_ini_fixup(ah,
883 &ah->eeprom.def,
884 reg, val);
885 }
886 }
887 }
888
889 ecode = ath9k_hw_init_macaddr(ah);
890 if (ecode != 0) {
891 DPRINTF(sc, ATH_DBG_FATAL,
892 "Failed to initialize MAC address\n");
893 goto bad;
894 }
895
896 if (AR_SREV_9285(ah))
897 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
898 else
899 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
900
901 ath9k_init_nfcal_hist_buffer(ah);
902
903 return ah;
904bad:
905 if (ah)
906 ath9k_hw_detach(ah);
907 if (status)
908 *status = ecode;
909
910 return NULL;
911}
912
913static void ath9k_hw_init_bb(struct ath_hw *ah,
914 struct ath9k_channel *chan)
915{
916 u32 synthDelay;
917
918 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
919 if (IS_CHAN_B(chan))
920 synthDelay = (4 * synthDelay) / 22;
921 else
922 synthDelay /= 10;
923
924 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
925
926 udelay(synthDelay + BASE_ACTIVATE_DELAY);
927}
928
929static void ath9k_hw_init_qos(struct ath_hw *ah)
930{
931 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
932 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
933
934 REG_WRITE(ah, AR_QOS_NO_ACK,
935 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
936 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
937 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
938
939 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
940 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
941 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
942 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
943 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
944}
945
946static void ath9k_hw_init_pll(struct ath_hw *ah,
947 struct ath9k_channel *chan)
948{
949 u32 pll;
950
951 if (AR_SREV_9100(ah)) {
952 if (chan && IS_CHAN_5GHZ(chan))
953 pll = 0x1450;
954 else
955 pll = 0x1458;
956 } else {
957 if (AR_SREV_9280_10_OR_LATER(ah)) {
958 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
959
960 if (chan && IS_CHAN_HALF_RATE(chan))
961 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
962 else if (chan && IS_CHAN_QUARTER_RATE(chan))
963 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
964
965 if (chan && IS_CHAN_5GHZ(chan)) {
966 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
967
968
969 if (AR_SREV_9280_20(ah)) {
970 if (((chan->channel % 20) == 0)
971 || ((chan->channel % 10) == 0))
972 pll = 0x2850;
973 else
974 pll = 0x142c;
975 }
976 } else {
977 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
978 }
979
980 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
981
982 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
983
984 if (chan && IS_CHAN_HALF_RATE(chan))
985 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
986 else if (chan && IS_CHAN_QUARTER_RATE(chan))
987 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
988
989 if (chan && IS_CHAN_5GHZ(chan))
990 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
991 else
992 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
993 } else {
994 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
995
996 if (chan && IS_CHAN_HALF_RATE(chan))
997 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
998 else if (chan && IS_CHAN_QUARTER_RATE(chan))
999 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1000
1001 if (chan && IS_CHAN_5GHZ(chan))
1002 pll |= SM(0xa, AR_RTC_PLL_DIV);
1003 else
1004 pll |= SM(0xb, AR_RTC_PLL_DIV);
1005 }
1006 }
1007 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1008
1009 udelay(RTC_PLL_SETTLE_DELAY);
1010
1011 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1012}
1013
1014static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1015{
1016 int rx_chainmask, tx_chainmask;
1017
1018 rx_chainmask = ah->rxchainmask;
1019 tx_chainmask = ah->txchainmask;
1020
1021 switch (rx_chainmask) {
1022 case 0x5:
1023 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1024 AR_PHY_SWAP_ALT_CHAIN);
1025 case 0x3:
1026 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1027 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1028 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1029 break;
1030 }
1031 case 0x1:
1032 case 0x2:
1033 case 0x7:
1034 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1035 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1036 break;
1037 default:
1038 break;
1039 }
1040
1041 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1042 if (tx_chainmask == 0x5) {
1043 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044 AR_PHY_SWAP_ALT_CHAIN);
1045 }
1046 if (AR_SREV_9100(ah))
1047 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1048 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1049}
1050
1051static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1052 enum nl80211_iftype opmode)
1053{
1054 ah->mask_reg = AR_IMR_TXERR |
1055 AR_IMR_TXURN |
1056 AR_IMR_RXERR |
1057 AR_IMR_RXORN |
1058 AR_IMR_BCNMISC;
1059
1060 if (ah->config.intr_mitigation)
1061 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1062 else
1063 ah->mask_reg |= AR_IMR_RXOK;
1064
1065 ah->mask_reg |= AR_IMR_TXOK;
1066
1067 if (opmode == NL80211_IFTYPE_AP)
1068 ah->mask_reg |= AR_IMR_MIB;
1069
1070 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1071 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1072
1073 if (!AR_SREV_9100(ah)) {
1074 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1075 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1076 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1077 }
1078}
1079
1080static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1081{
1082 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1084 ah->acktimeout = (u32) -1;
1085 return false;
1086 } else {
1087 REG_RMW_FIELD(ah, AR_TIME_OUT,
1088 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1089 ah->acktimeout = us;
1090 return true;
1091 }
1092}
1093
1094static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1095{
1096 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1097 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1098 ah->ctstimeout = (u32) -1;
1099 return false;
1100 } else {
1101 REG_RMW_FIELD(ah, AR_TIME_OUT,
1102 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1103 ah->ctstimeout = us;
1104 return true;
1105 }
1106}
1107
1108static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1109{
1110 if (tu > 0xFFFF) {
1111 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1112 "bad global tx timeout %u\n", tu);
1113 ah->globaltxtimeout = (u32) -1;
1114 return false;
1115 } else {
1116 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1117 ah->globaltxtimeout = tu;
1118 return true;
1119 }
1120}
1121
1122static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1123{
1124 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1125 ah->misc_mode);
1126
1127 if (ah->misc_mode != 0)
1128 REG_WRITE(ah, AR_PCU_MISC,
1129 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1130 if (ah->slottime != (u32) -1)
1131 ath9k_hw_setslottime(ah, ah->slottime);
1132 if (ah->acktimeout != (u32) -1)
1133 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1134 if (ah->ctstimeout != (u32) -1)
1135 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1136 if (ah->globaltxtimeout != (u32) -1)
1137 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1138}
1139
1140const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1141{
1142 return vendorid == ATHEROS_VENDOR_ID ?
1143 ath9k_hw_devname(devid) : NULL;
1144}
1145
1146void ath9k_hw_detach(struct ath_hw *ah)
1147{
1148 if (!AR_SREV_9100(ah))
1149 ath9k_hw_ani_detach(ah);
1150
1151 ath9k_hw_rfdetach(ah);
1152 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1153 kfree(ah);
1154}
1155
1156struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1157{
1158 struct ath_hw *ah = NULL;
1159
1160 switch (devid) {
1161 case AR5416_DEVID_PCI:
1162 case AR5416_DEVID_PCIE:
1163 case AR5416_AR9100_DEVID:
1164 case AR9160_DEVID_PCI:
1165 case AR9280_DEVID_PCI:
1166 case AR9280_DEVID_PCIE:
1167 case AR9285_DEVID_PCIE:
1168 ah = ath9k_hw_do_attach(devid, sc, error);
1169 break;
1170 default:
1171 *error = -ENXIO;
1172 break;
1173 }
1174
1175 return ah;
1176}
1177
1178/*******/
1179/* INI */
1180/*******/
1181
1182static void ath9k_hw_override_ini(struct ath_hw *ah,
1183 struct ath9k_channel *chan)
1184{
1185 /*
1186 * Set the RX_ABORT and RX_DIS and clear if off only after
1187 * RXE is set for MAC. This prevents frames with corrupted
1188 * descriptor status.
1189 */
1190 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1191
1192
1193 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1194 AR_SREV_9280_10_OR_LATER(ah))
1195 return;
1196
1197 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1198}
1199
1200static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1201 struct ar5416_eeprom_def *pEepData,
1202 u32 reg, u32 value)
1203{
1204 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1205
1206 switch (ah->hw_version.devid) {
1207 case AR9280_DEVID_PCI:
1208 if (reg == 0x7894) {
1209 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1210 "ini VAL: %x EEPROM: %x\n", value,
1211 (pBase->version & 0xff));
1212
1213 if ((pBase->version & 0xff) > 0x0a) {
1214 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1215 "PWDCLKIND: %d\n",
1216 pBase->pwdclkind);
1217 value &= ~AR_AN_TOP2_PWDCLKIND;
1218 value |= AR_AN_TOP2_PWDCLKIND &
1219 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1220 } else {
1221 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1222 "PWDCLKIND Earlier Rev\n");
1223 }
1224
1225 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1226 "final ini VAL: %x\n", value);
1227 }
1228 break;
1229 }
1230
1231 return value;
1232}
1233
1234static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1235 struct ar5416_eeprom_def *pEepData,
1236 u32 reg, u32 value)
1237{
1238 if (ah->eep_map == EEP_MAP_4KBITS)
1239 return value;
1240 else
1241 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1242}
1243
1244static void ath9k_olc_init(struct ath_hw *ah)
1245{
1246 u32 i;
1247
1248 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1249 ah->originalGain[i] =
1250 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1251 AR_PHY_TX_GAIN);
1252 ah->PDADCdelta = 0;
1253}
1254
1255static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1256 struct ath9k_channel *chan)
1257{
1258 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1259
1260 if (IS_CHAN_B(chan))
1261 ctl |= CTL_11B;
1262 else if (IS_CHAN_G(chan))
1263 ctl |= CTL_11G;
1264 else
1265 ctl |= CTL_11A;
1266
1267 return ctl;
1268}
1269
1270static int ath9k_hw_process_ini(struct ath_hw *ah,
1271 struct ath9k_channel *chan,
1272 enum ath9k_ht_macmode macmode)
1273{
1274 int i, regWrites = 0;
1275 struct ieee80211_channel *channel = chan->chan;
1276 u32 modesIndex, freqIndex;
1277
1278 switch (chan->chanmode) {
1279 case CHANNEL_A:
1280 case CHANNEL_A_HT20:
1281 modesIndex = 1;
1282 freqIndex = 1;
1283 break;
1284 case CHANNEL_A_HT40PLUS:
1285 case CHANNEL_A_HT40MINUS:
1286 modesIndex = 2;
1287 freqIndex = 1;
1288 break;
1289 case CHANNEL_G:
1290 case CHANNEL_G_HT20:
1291 case CHANNEL_B:
1292 modesIndex = 4;
1293 freqIndex = 2;
1294 break;
1295 case CHANNEL_G_HT40PLUS:
1296 case CHANNEL_G_HT40MINUS:
1297 modesIndex = 3;
1298 freqIndex = 2;
1299 break;
1300
1301 default:
1302 return -EINVAL;
1303 }
1304
1305 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1306 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1307 ah->eep_ops->set_addac(ah, chan);
1308
1309 if (AR_SREV_5416_22_OR_LATER(ah)) {
1310 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1311 } else {
1312 struct ar5416IniArray temp;
1313 u32 addacSize =
1314 sizeof(u32) * ah->iniAddac.ia_rows *
1315 ah->iniAddac.ia_columns;
1316
1317 memcpy(ah->addac5416_21,
1318 ah->iniAddac.ia_array, addacSize);
1319
1320 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1321
1322 temp.ia_array = ah->addac5416_21;
1323 temp.ia_columns = ah->iniAddac.ia_columns;
1324 temp.ia_rows = ah->iniAddac.ia_rows;
1325 REG_WRITE_ARRAY(&temp, 1, regWrites);
1326 }
1327
1328 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1329
1330 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1331 u32 reg = INI_RA(&ah->iniModes, i, 0);
1332 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1333
1334 REG_WRITE(ah, reg, val);
1335
1336 if (reg >= 0x7800 && reg < 0x78a0
1337 && ah->config.analog_shiftreg) {
1338 udelay(100);
1339 }
1340
1341 DO_DELAY(regWrites);
1342 }
1343
1344 if (AR_SREV_9280(ah))
1345 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1346
1347 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah))
1348 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1349
1350 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1351 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1352 u32 val = INI_RA(&ah->iniCommon, i, 1);
1353
1354 REG_WRITE(ah, reg, val);
1355
1356 if (reg >= 0x7800 && reg < 0x78a0
1357 && ah->config.analog_shiftreg) {
1358 udelay(100);
1359 }
1360
1361 DO_DELAY(regWrites);
1362 }
1363
1364 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1365
1366 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1367 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1368 regWrites);
1369 }
1370
1371 ath9k_hw_override_ini(ah, chan);
1372 ath9k_hw_set_regs(ah, chan, macmode);
1373 ath9k_hw_init_chain_masks(ah);
1374
1375 if (OLC_FOR_AR9280_20_LATER)
1376 ath9k_olc_init(ah);
1377
1378 ah->eep_ops->set_txpower(ah, chan,
1379 ath9k_regd_get_ctl(&ah->regulatory, chan),
1380 channel->max_antenna_gain * 2,
1381 channel->max_power * 2,
1382 min((u32) MAX_RATE_POWER,
1383 (u32) ah->regulatory.power_limit));
1384
1385 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1386 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1387 "ar5416SetRfRegs failed\n");
1388 return -EIO;
1389 }
1390
1391 return 0;
1392}
1393
1394/****************************************/
1395/* Reset and Channel Switching Routines */
1396/****************************************/
1397
1398static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1399{
1400 u32 rfMode = 0;
1401
1402 if (chan == NULL)
1403 return;
1404
1405 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1406 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1407
1408 if (!AR_SREV_9280_10_OR_LATER(ah))
1409 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1410 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1411
1412 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1413 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1414
1415 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1416}
1417
1418static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1419{
1420 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1421}
1422
1423static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1424{
1425 u32 regval;
1426
1427 regval = REG_READ(ah, AR_AHB_MODE);
1428 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1429
1430 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1431 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1432
1433 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1434
1435 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1436 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1437
1438 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1439
1440 if (AR_SREV_9285(ah)) {
1441 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1442 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1443 } else {
1444 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1445 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1446 }
1447}
1448
1449static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1450{
1451 u32 val;
1452
1453 val = REG_READ(ah, AR_STA_ID1);
1454 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1455 switch (opmode) {
1456 case NL80211_IFTYPE_AP:
1457 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1458 | AR_STA_ID1_KSRCH_MODE);
1459 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1460 break;
1461 case NL80211_IFTYPE_ADHOC:
1462 case NL80211_IFTYPE_MESH_POINT:
1463 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1464 | AR_STA_ID1_KSRCH_MODE);
1465 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1466 break;
1467 case NL80211_IFTYPE_STATION:
1468 case NL80211_IFTYPE_MONITOR:
1469 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1470 break;
1471 }
1472}
1473
1474static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1475 u32 coef_scaled,
1476 u32 *coef_mantissa,
1477 u32 *coef_exponent)
1478{
1479 u32 coef_exp, coef_man;
1480
1481 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1482 if ((coef_scaled >> coef_exp) & 0x1)
1483 break;
1484
1485 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1486
1487 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1488
1489 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1490 *coef_exponent = coef_exp - 16;
1491}
1492
1493static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1494 struct ath9k_channel *chan)
1495{
1496 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1497 u32 clockMhzScaled = 0x64000000;
1498 struct chan_centers centers;
1499
1500 if (IS_CHAN_HALF_RATE(chan))
1501 clockMhzScaled = clockMhzScaled >> 1;
1502 else if (IS_CHAN_QUARTER_RATE(chan))
1503 clockMhzScaled = clockMhzScaled >> 2;
1504
1505 ath9k_hw_get_channel_centers(ah, chan, &centers);
1506 coef_scaled = clockMhzScaled / centers.synth_center;
1507
1508 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1509 &ds_coef_exp);
1510
1511 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1512 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1513 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1514 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1515
1516 coef_scaled = (9 * coef_scaled) / 10;
1517
1518 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1519 &ds_coef_exp);
1520
1521 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1522 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1523 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1524 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1525}
1526
1527static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1528{
1529 u32 rst_flags;
1530 u32 tmpReg;
1531
1532 if (AR_SREV_9100(ah)) {
1533 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1534 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1535 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1536 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1537 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1538 }
1539
1540 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1541 AR_RTC_FORCE_WAKE_ON_INT);
1542
1543 if (AR_SREV_9100(ah)) {
1544 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1545 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1546 } else {
1547 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1548 if (tmpReg &
1549 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1550 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1551 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1552 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1553 } else {
1554 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1555 }
1556
1557 rst_flags = AR_RTC_RC_MAC_WARM;
1558 if (type == ATH9K_RESET_COLD)
1559 rst_flags |= AR_RTC_RC_MAC_COLD;
1560 }
1561
1562 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1563 udelay(50);
1564
1565 REG_WRITE(ah, AR_RTC_RC, 0);
1566 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1567 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1568 "RTC stuck in MAC reset\n");
1569 return false;
1570 }
1571
1572 if (!AR_SREV_9100(ah))
1573 REG_WRITE(ah, AR_RC, 0);
1574
1575 ath9k_hw_init_pll(ah, NULL);
1576
1577 if (AR_SREV_9100(ah))
1578 udelay(50);
1579
1580 return true;
1581}
1582
1583static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1584{
1585 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1586 AR_RTC_FORCE_WAKE_ON_INT);
1587
1588 REG_WRITE(ah, AR_RTC_RESET, 0);
1589 udelay(2);
1590 REG_WRITE(ah, AR_RTC_RESET, 1);
1591
1592 if (!ath9k_hw_wait(ah,
1593 AR_RTC_STATUS,
1594 AR_RTC_STATUS_M,
1595 AR_RTC_STATUS_ON,
1596 AH_WAIT_TIMEOUT)) {
1597 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1598 return false;
1599 }
1600
1601 ath9k_hw_read_revisions(ah);
1602
1603 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1604}
1605
1606static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1607{
1608 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1609 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1610
1611 switch (type) {
1612 case ATH9K_RESET_POWER_ON:
1613 return ath9k_hw_set_reset_power_on(ah);
1614 case ATH9K_RESET_WARM:
1615 case ATH9K_RESET_COLD:
1616 return ath9k_hw_set_reset(ah, type);
1617 default:
1618 return false;
1619 }
1620}
1621
1622static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1623 enum ath9k_ht_macmode macmode)
1624{
1625 u32 phymode;
1626 u32 enableDacFifo = 0;
1627
1628 if (AR_SREV_9285_10_OR_LATER(ah))
1629 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1630 AR_PHY_FC_ENABLE_DAC_FIFO);
1631
1632 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1633 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1634
1635 if (IS_CHAN_HT40(chan)) {
1636 phymode |= AR_PHY_FC_DYN2040_EN;
1637
1638 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1639 (chan->chanmode == CHANNEL_G_HT40PLUS))
1640 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1641
1642 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1643 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1644 }
1645 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1646
1647 ath9k_hw_set11nmac2040(ah, macmode);
1648
1649 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1650 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1651}
1652
1653static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1654 struct ath9k_channel *chan)
1655{
1656 if (OLC_FOR_AR9280_20_LATER) {
1657 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1658 return false;
1659 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1660 return false;
1661
1662 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1663 return false;
1664
1665 ah->chip_fullsleep = false;
1666 ath9k_hw_init_pll(ah, chan);
1667 ath9k_hw_set_rfmode(ah, chan);
1668
1669 return true;
1670}
1671
1672static bool ath9k_hw_channel_change(struct ath_hw *ah,
1673 struct ath9k_channel *chan,
1674 enum ath9k_ht_macmode macmode)
1675{
1676 struct ieee80211_channel *channel = chan->chan;
1677 u32 synthDelay, qnum;
1678
1679 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1680 if (ath9k_hw_numtxpending(ah, qnum)) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1682 "Transmit frames pending on queue %d\n", qnum);
1683 return false;
1684 }
1685 }
1686
1687 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1688 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1689 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1690 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1691 "Could not kill baseband RX\n");
1692 return false;
1693 }
1694
1695 ath9k_hw_set_regs(ah, chan, macmode);
1696
1697 if (AR_SREV_9280_10_OR_LATER(ah)) {
1698 ath9k_hw_ar9280_set_channel(ah, chan);
1699 } else {
1700 if (!(ath9k_hw_set_channel(ah, chan))) {
1701 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1702 "Failed to set channel\n");
1703 return false;
1704 }
1705 }
1706
1707 ah->eep_ops->set_txpower(ah, chan,
1708 ath9k_regd_get_ctl(&ah->regulatory, chan),
1709 channel->max_antenna_gain * 2,
1710 channel->max_power * 2,
1711 min((u32) MAX_RATE_POWER,
1712 (u32) ah->regulatory.power_limit));
1713
1714 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1715 if (IS_CHAN_B(chan))
1716 synthDelay = (4 * synthDelay) / 22;
1717 else
1718 synthDelay /= 10;
1719
1720 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1721
1722 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1723
1724 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1725 ath9k_hw_set_delta_slope(ah, chan);
1726
1727 if (AR_SREV_9280_10_OR_LATER(ah))
1728 ath9k_hw_9280_spur_mitigate(ah, chan);
1729 else
1730 ath9k_hw_spur_mitigate(ah, chan);
1731
1732 if (!chan->oneTimeCalsDone)
1733 chan->oneTimeCalsDone = true;
1734
1735 return true;
1736}
1737
1738static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1739{
1740 int bb_spur = AR_NO_SPUR;
1741 int freq;
1742 int bin, cur_bin;
1743 int bb_spur_off, spur_subchannel_sd;
1744 int spur_freq_sd;
1745 int spur_delta_phase;
1746 int denominator;
1747 int upper, lower, cur_vit_mask;
1748 int tmp, newVal;
1749 int i;
1750 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1751 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1752 };
1753 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1754 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1755 };
1756 int inc[4] = { 0, 100, 0, 0 };
1757 struct chan_centers centers;
1758
1759 int8_t mask_m[123];
1760 int8_t mask_p[123];
1761 int8_t mask_amt;
1762 int tmp_mask;
1763 int cur_bb_spur;
1764 bool is2GHz = IS_CHAN_2GHZ(chan);
1765
1766 memset(&mask_m, 0, sizeof(int8_t) * 123);
1767 memset(&mask_p, 0, sizeof(int8_t) * 123);
1768
1769 ath9k_hw_get_channel_centers(ah, chan, &centers);
1770 freq = centers.synth_center;
1771
1772 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1773 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1774 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1775
1776 if (is2GHz)
1777 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1778 else
1779 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1780
1781 if (AR_NO_SPUR == cur_bb_spur)
1782 break;
1783 cur_bb_spur = cur_bb_spur - freq;
1784
1785 if (IS_CHAN_HT40(chan)) {
1786 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1787 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1788 bb_spur = cur_bb_spur;
1789 break;
1790 }
1791 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1792 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1793 bb_spur = cur_bb_spur;
1794 break;
1795 }
1796 }
1797
1798 if (AR_NO_SPUR == bb_spur) {
1799 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1800 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1801 return;
1802 } else {
1803 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1804 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1805 }
1806
1807 bin = bb_spur * 320;
1808
1809 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1810
1811 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1812 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1813 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1814 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1815 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1816
1817 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1818 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1819 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1820 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1821 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1822 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1823
1824 if (IS_CHAN_HT40(chan)) {
1825 if (bb_spur < 0) {
1826 spur_subchannel_sd = 1;
1827 bb_spur_off = bb_spur + 10;
1828 } else {
1829 spur_subchannel_sd = 0;
1830 bb_spur_off = bb_spur - 10;
1831 }
1832 } else {
1833 spur_subchannel_sd = 0;
1834 bb_spur_off = bb_spur;
1835 }
1836
1837 if (IS_CHAN_HT40(chan))
1838 spur_delta_phase =
1839 ((bb_spur * 262144) /
1840 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1841 else
1842 spur_delta_phase =
1843 ((bb_spur * 524288) /
1844 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1845
1846 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1847 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1848
1849 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1850 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1851 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1852 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1853
1854 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1855 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1856
1857 cur_bin = -6000;
1858 upper = bin + 100;
1859 lower = bin - 100;
1860
1861 for (i = 0; i < 4; i++) {
1862 int pilot_mask = 0;
1863 int chan_mask = 0;
1864 int bp = 0;
1865 for (bp = 0; bp < 30; bp++) {
1866 if ((cur_bin > lower) && (cur_bin < upper)) {
1867 pilot_mask = pilot_mask | 0x1 << bp;
1868 chan_mask = chan_mask | 0x1 << bp;
1869 }
1870 cur_bin += 100;
1871 }
1872 cur_bin += inc[i];
1873 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1874 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1875 }
1876
1877 cur_vit_mask = 6100;
1878 upper = bin + 120;
1879 lower = bin - 120;
1880
1881 for (i = 0; i < 123; i++) {
1882 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1883
1884 /* workaround for gcc bug #37014 */
1885 volatile int tmp_v = abs(cur_vit_mask - bin);
1886
1887 if (tmp_v < 75)
1888 mask_amt = 1;
1889 else
1890 mask_amt = 0;
1891 if (cur_vit_mask < 0)
1892 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1893 else
1894 mask_p[cur_vit_mask / 100] = mask_amt;
1895 }
1896 cur_vit_mask -= 100;
1897 }
1898
1899 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1900 | (mask_m[48] << 26) | (mask_m[49] << 24)
1901 | (mask_m[50] << 22) | (mask_m[51] << 20)
1902 | (mask_m[52] << 18) | (mask_m[53] << 16)
1903 | (mask_m[54] << 14) | (mask_m[55] << 12)
1904 | (mask_m[56] << 10) | (mask_m[57] << 8)
1905 | (mask_m[58] << 6) | (mask_m[59] << 4)
1906 | (mask_m[60] << 2) | (mask_m[61] << 0);
1907 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1908 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1909
1910 tmp_mask = (mask_m[31] << 28)
1911 | (mask_m[32] << 26) | (mask_m[33] << 24)
1912 | (mask_m[34] << 22) | (mask_m[35] << 20)
1913 | (mask_m[36] << 18) | (mask_m[37] << 16)
1914 | (mask_m[48] << 14) | (mask_m[39] << 12)
1915 | (mask_m[40] << 10) | (mask_m[41] << 8)
1916 | (mask_m[42] << 6) | (mask_m[43] << 4)
1917 | (mask_m[44] << 2) | (mask_m[45] << 0);
1918 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1919 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1920
1921 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1922 | (mask_m[18] << 26) | (mask_m[18] << 24)
1923 | (mask_m[20] << 22) | (mask_m[20] << 20)
1924 | (mask_m[22] << 18) | (mask_m[22] << 16)
1925 | (mask_m[24] << 14) | (mask_m[24] << 12)
1926 | (mask_m[25] << 10) | (mask_m[26] << 8)
1927 | (mask_m[27] << 6) | (mask_m[28] << 4)
1928 | (mask_m[29] << 2) | (mask_m[30] << 0);
1929 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1930 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1931
1932 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1933 | (mask_m[2] << 26) | (mask_m[3] << 24)
1934 | (mask_m[4] << 22) | (mask_m[5] << 20)
1935 | (mask_m[6] << 18) | (mask_m[7] << 16)
1936 | (mask_m[8] << 14) | (mask_m[9] << 12)
1937 | (mask_m[10] << 10) | (mask_m[11] << 8)
1938 | (mask_m[12] << 6) | (mask_m[13] << 4)
1939 | (mask_m[14] << 2) | (mask_m[15] << 0);
1940 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1941 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1942
1943 tmp_mask = (mask_p[15] << 28)
1944 | (mask_p[14] << 26) | (mask_p[13] << 24)
1945 | (mask_p[12] << 22) | (mask_p[11] << 20)
1946 | (mask_p[10] << 18) | (mask_p[9] << 16)
1947 | (mask_p[8] << 14) | (mask_p[7] << 12)
1948 | (mask_p[6] << 10) | (mask_p[5] << 8)
1949 | (mask_p[4] << 6) | (mask_p[3] << 4)
1950 | (mask_p[2] << 2) | (mask_p[1] << 0);
1951 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1952 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1953
1954 tmp_mask = (mask_p[30] << 28)
1955 | (mask_p[29] << 26) | (mask_p[28] << 24)
1956 | (mask_p[27] << 22) | (mask_p[26] << 20)
1957 | (mask_p[25] << 18) | (mask_p[24] << 16)
1958 | (mask_p[23] << 14) | (mask_p[22] << 12)
1959 | (mask_p[21] << 10) | (mask_p[20] << 8)
1960 | (mask_p[19] << 6) | (mask_p[18] << 4)
1961 | (mask_p[17] << 2) | (mask_p[16] << 0);
1962 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1963 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1964
1965 tmp_mask = (mask_p[45] << 28)
1966 | (mask_p[44] << 26) | (mask_p[43] << 24)
1967 | (mask_p[42] << 22) | (mask_p[41] << 20)
1968 | (mask_p[40] << 18) | (mask_p[39] << 16)
1969 | (mask_p[38] << 14) | (mask_p[37] << 12)
1970 | (mask_p[36] << 10) | (mask_p[35] << 8)
1971 | (mask_p[34] << 6) | (mask_p[33] << 4)
1972 | (mask_p[32] << 2) | (mask_p[31] << 0);
1973 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1974 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1975
1976 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1977 | (mask_p[59] << 26) | (mask_p[58] << 24)
1978 | (mask_p[57] << 22) | (mask_p[56] << 20)
1979 | (mask_p[55] << 18) | (mask_p[54] << 16)
1980 | (mask_p[53] << 14) | (mask_p[52] << 12)
1981 | (mask_p[51] << 10) | (mask_p[50] << 8)
1982 | (mask_p[49] << 6) | (mask_p[48] << 4)
1983 | (mask_p[47] << 2) | (mask_p[46] << 0);
1984 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1985 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1986}
1987
1988static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1989{
1990 int bb_spur = AR_NO_SPUR;
1991 int bin, cur_bin;
1992 int spur_freq_sd;
1993 int spur_delta_phase;
1994 int denominator;
1995 int upper, lower, cur_vit_mask;
1996 int tmp, new;
1997 int i;
1998 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1999 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2000 };
2001 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2002 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2003 };
2004 int inc[4] = { 0, 100, 0, 0 };
2005
2006 int8_t mask_m[123];
2007 int8_t mask_p[123];
2008 int8_t mask_amt;
2009 int tmp_mask;
2010 int cur_bb_spur;
2011 bool is2GHz = IS_CHAN_2GHZ(chan);
2012
2013 memset(&mask_m, 0, sizeof(int8_t) * 123);
2014 memset(&mask_p, 0, sizeof(int8_t) * 123);
2015
2016 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2017 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2018 if (AR_NO_SPUR == cur_bb_spur)
2019 break;
2020 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2021 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2022 bb_spur = cur_bb_spur;
2023 break;
2024 }
2025 }
2026
2027 if (AR_NO_SPUR == bb_spur)
2028 return;
2029
2030 bin = bb_spur * 32;
2031
2032 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2033 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2034 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2035 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2036 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2037
2038 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2039
2040 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2041 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2042 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2043 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2044 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2045 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2046
2047 spur_delta_phase = ((bb_spur * 524288) / 100) &
2048 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2049
2050 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2051 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2052
2053 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2054 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2055 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2056 REG_WRITE(ah, AR_PHY_TIMING11, new);
2057
2058 cur_bin = -6000;
2059 upper = bin + 100;
2060 lower = bin - 100;
2061
2062 for (i = 0; i < 4; i++) {
2063 int pilot_mask = 0;
2064 int chan_mask = 0;
2065 int bp = 0;
2066 for (bp = 0; bp < 30; bp++) {
2067 if ((cur_bin > lower) && (cur_bin < upper)) {
2068 pilot_mask = pilot_mask | 0x1 << bp;
2069 chan_mask = chan_mask | 0x1 << bp;
2070 }
2071 cur_bin += 100;
2072 }
2073 cur_bin += inc[i];
2074 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2075 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2076 }
2077
2078 cur_vit_mask = 6100;
2079 upper = bin + 120;
2080 lower = bin - 120;
2081
2082 for (i = 0; i < 123; i++) {
2083 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2084
2085 /* workaround for gcc bug #37014 */
2086 volatile int tmp_v = abs(cur_vit_mask - bin);
2087
2088 if (tmp_v < 75)
2089 mask_amt = 1;
2090 else
2091 mask_amt = 0;
2092 if (cur_vit_mask < 0)
2093 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2094 else
2095 mask_p[cur_vit_mask / 100] = mask_amt;
2096 }
2097 cur_vit_mask -= 100;
2098 }
2099
2100 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2101 | (mask_m[48] << 26) | (mask_m[49] << 24)
2102 | (mask_m[50] << 22) | (mask_m[51] << 20)
2103 | (mask_m[52] << 18) | (mask_m[53] << 16)
2104 | (mask_m[54] << 14) | (mask_m[55] << 12)
2105 | (mask_m[56] << 10) | (mask_m[57] << 8)
2106 | (mask_m[58] << 6) | (mask_m[59] << 4)
2107 | (mask_m[60] << 2) | (mask_m[61] << 0);
2108 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2109 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2110
2111 tmp_mask = (mask_m[31] << 28)
2112 | (mask_m[32] << 26) | (mask_m[33] << 24)
2113 | (mask_m[34] << 22) | (mask_m[35] << 20)
2114 | (mask_m[36] << 18) | (mask_m[37] << 16)
2115 | (mask_m[48] << 14) | (mask_m[39] << 12)
2116 | (mask_m[40] << 10) | (mask_m[41] << 8)
2117 | (mask_m[42] << 6) | (mask_m[43] << 4)
2118 | (mask_m[44] << 2) | (mask_m[45] << 0);
2119 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2120 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2121
2122 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2123 | (mask_m[18] << 26) | (mask_m[18] << 24)
2124 | (mask_m[20] << 22) | (mask_m[20] << 20)
2125 | (mask_m[22] << 18) | (mask_m[22] << 16)
2126 | (mask_m[24] << 14) | (mask_m[24] << 12)
2127 | (mask_m[25] << 10) | (mask_m[26] << 8)
2128 | (mask_m[27] << 6) | (mask_m[28] << 4)
2129 | (mask_m[29] << 2) | (mask_m[30] << 0);
2130 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2131 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2132
2133 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2134 | (mask_m[2] << 26) | (mask_m[3] << 24)
2135 | (mask_m[4] << 22) | (mask_m[5] << 20)
2136 | (mask_m[6] << 18) | (mask_m[7] << 16)
2137 | (mask_m[8] << 14) | (mask_m[9] << 12)
2138 | (mask_m[10] << 10) | (mask_m[11] << 8)
2139 | (mask_m[12] << 6) | (mask_m[13] << 4)
2140 | (mask_m[14] << 2) | (mask_m[15] << 0);
2141 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2142 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2143
2144 tmp_mask = (mask_p[15] << 28)
2145 | (mask_p[14] << 26) | (mask_p[13] << 24)
2146 | (mask_p[12] << 22) | (mask_p[11] << 20)
2147 | (mask_p[10] << 18) | (mask_p[9] << 16)
2148 | (mask_p[8] << 14) | (mask_p[7] << 12)
2149 | (mask_p[6] << 10) | (mask_p[5] << 8)
2150 | (mask_p[4] << 6) | (mask_p[3] << 4)
2151 | (mask_p[2] << 2) | (mask_p[1] << 0);
2152 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2153 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2154
2155 tmp_mask = (mask_p[30] << 28)
2156 | (mask_p[29] << 26) | (mask_p[28] << 24)
2157 | (mask_p[27] << 22) | (mask_p[26] << 20)
2158 | (mask_p[25] << 18) | (mask_p[24] << 16)
2159 | (mask_p[23] << 14) | (mask_p[22] << 12)
2160 | (mask_p[21] << 10) | (mask_p[20] << 8)
2161 | (mask_p[19] << 6) | (mask_p[18] << 4)
2162 | (mask_p[17] << 2) | (mask_p[16] << 0);
2163 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2164 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2165
2166 tmp_mask = (mask_p[45] << 28)
2167 | (mask_p[44] << 26) | (mask_p[43] << 24)
2168 | (mask_p[42] << 22) | (mask_p[41] << 20)
2169 | (mask_p[40] << 18) | (mask_p[39] << 16)
2170 | (mask_p[38] << 14) | (mask_p[37] << 12)
2171 | (mask_p[36] << 10) | (mask_p[35] << 8)
2172 | (mask_p[34] << 6) | (mask_p[33] << 4)
2173 | (mask_p[32] << 2) | (mask_p[31] << 0);
2174 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2175 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2176
2177 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2178 | (mask_p[59] << 26) | (mask_p[58] << 24)
2179 | (mask_p[57] << 22) | (mask_p[56] << 20)
2180 | (mask_p[55] << 18) | (mask_p[54] << 16)
2181 | (mask_p[53] << 14) | (mask_p[52] << 12)
2182 | (mask_p[51] << 10) | (mask_p[50] << 8)
2183 | (mask_p[49] << 6) | (mask_p[48] << 4)
2184 | (mask_p[47] << 2) | (mask_p[46] << 0);
2185 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2186 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2187}
2188
2189int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2190 bool bChannelChange)
2191{
2192 u32 saveLedState;
2193 struct ath_softc *sc = ah->ah_sc;
2194 struct ath9k_channel *curchan = ah->curchan;
2195 u32 saveDefAntenna;
2196 u32 macStaId1;
2197 int i, rx_chainmask, r;
2198
2199 ah->extprotspacing = sc->ht_extprotspacing;
2200 ah->txchainmask = sc->tx_chainmask;
2201 ah->rxchainmask = sc->rx_chainmask;
2202
2203 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2204 return -EIO;
2205
2206 if (curchan)
2207 ath9k_hw_getnf(ah, curchan);
2208
2209 if (bChannelChange &&
2210 (ah->chip_fullsleep != true) &&
2211 (ah->curchan != NULL) &&
2212 (chan->channel != ah->curchan->channel) &&
2213 ((chan->channelFlags & CHANNEL_ALL) ==
2214 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2215 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2216 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2217
2218 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2219 ath9k_hw_loadnf(ah, ah->curchan);
2220 ath9k_hw_start_nfcal(ah);
2221 return 0;
2222 }
2223 }
2224
2225 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2226 if (saveDefAntenna == 0)
2227 saveDefAntenna = 1;
2228
2229 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2230
2231 saveLedState = REG_READ(ah, AR_CFG_LED) &
2232 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2233 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2234
2235 ath9k_hw_mark_phy_inactive(ah);
2236
2237 if (!ath9k_hw_chip_reset(ah, chan)) {
2238 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2239 return -EINVAL;
2240 }
2241
2242 if (AR_SREV_9280_10_OR_LATER(ah))
2243 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2244
2245 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2246 if (r)
2247 return r;
2248
2249 /* Setup MFP options for CCMP */
2250 if (AR_SREV_9280_20_OR_LATER(ah)) {
2251 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2252 * frames when constructing CCMP AAD. */
2253 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2254 0xc7ff);
2255 ah->sw_mgmt_crypto = false;
2256 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2257 /* Disable hardware crypto for management frames */
2258 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2259 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2260 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2261 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2262 ah->sw_mgmt_crypto = true;
2263 } else
2264 ah->sw_mgmt_crypto = true;
2265
2266 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2267 ath9k_hw_set_delta_slope(ah, chan);
2268
2269 if (AR_SREV_9280_10_OR_LATER(ah))
2270 ath9k_hw_9280_spur_mitigate(ah, chan);
2271 else
2272 ath9k_hw_spur_mitigate(ah, chan);
2273
2274 ah->eep_ops->set_board_values(ah, chan);
2275
2276 ath9k_hw_decrease_chain_power(ah, chan);
2277
2278 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2279 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2280 | macStaId1
2281 | AR_STA_ID1_RTS_USE_DEF
2282 | (ah->config.
2283 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2284 | ah->sta_id1_defaults);
2285 ath9k_hw_set_operating_mode(ah, ah->opmode);
2286
2287 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2288 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2289
2290 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2291
2292 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2293 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2294 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2295
2296 REG_WRITE(ah, AR_ISR, ~0);
2297
2298 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2299
2300 if (AR_SREV_9280_10_OR_LATER(ah))
2301 ath9k_hw_ar9280_set_channel(ah, chan);
2302 else
2303 if (!(ath9k_hw_set_channel(ah, chan)))
2304 return -EIO;
2305
2306 for (i = 0; i < AR_NUM_DCU; i++)
2307 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2308
2309 ah->intr_txqs = 0;
2310 for (i = 0; i < ah->caps.total_queues; i++)
2311 ath9k_hw_resettxqueue(ah, i);
2312
2313 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2314 ath9k_hw_init_qos(ah);
2315
2316#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2317 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2318 ath9k_enable_rfkill(ah);
2319#endif
2320 ath9k_hw_init_user_settings(ah);
2321
2322 REG_WRITE(ah, AR_STA_ID1,
2323 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2324
2325 ath9k_hw_set_dma(ah);
2326
2327 REG_WRITE(ah, AR_OBS, 8);
2328
2329 if (ah->config.intr_mitigation) {
2330 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2331 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2332 }
2333
2334 ath9k_hw_init_bb(ah, chan);
2335
2336 if (!ath9k_hw_init_cal(ah, chan))
2337 return -EIO;;
2338
2339 rx_chainmask = ah->rxchainmask;
2340 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2341 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2342 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2343 }
2344
2345 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2346
2347 if (AR_SREV_9100(ah)) {
2348 u32 mask;
2349 mask = REG_READ(ah, AR_CFG);
2350 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2351 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2352 "CFG Byte Swap Set 0x%x\n", mask);
2353 } else {
2354 mask =
2355 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2356 REG_WRITE(ah, AR_CFG, mask);
2357 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2358 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2359 }
2360 } else {
2361#ifdef __BIG_ENDIAN
2362 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2363#endif
2364 }
2365
2366 return 0;
2367}
2368
2369/************************/
2370/* Key Cache Management */
2371/************************/
2372
2373bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2374{
2375 u32 keyType;
2376
2377 if (entry >= ah->caps.keycache_size) {
2378 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2379 "keychache entry %u out of range\n", entry);
2380 return false;
2381 }
2382
2383 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2384
2385 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2386 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2387 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2388 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2389 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2390 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2391 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2392 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2393
2394 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2395 u16 micentry = entry + 64;
2396
2397 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2398 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2399 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2400 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2401
2402 }
2403
2404 if (ah->curchan == NULL)
2405 return true;
2406
2407 return true;
2408}
2409
2410bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2411{
2412 u32 macHi, macLo;
2413
2414 if (entry >= ah->caps.keycache_size) {
2415 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2416 "keychache entry %u out of range\n", entry);
2417 return false;
2418 }
2419
2420 if (mac != NULL) {
2421 macHi = (mac[5] << 8) | mac[4];
2422 macLo = (mac[3] << 24) |
2423 (mac[2] << 16) |
2424 (mac[1] << 8) |
2425 mac[0];
2426 macLo >>= 1;
2427 macLo |= (macHi & 1) << 31;
2428 macHi >>= 1;
2429 } else {
2430 macLo = macHi = 0;
2431 }
2432 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2433 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2434
2435 return true;
2436}
2437
2438bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2439 const struct ath9k_keyval *k,
2440 const u8 *mac)
2441{
2442 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2443 u32 key0, key1, key2, key3, key4;
2444 u32 keyType;
2445
2446 if (entry >= pCap->keycache_size) {
2447 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2448 "keycache entry %u out of range\n", entry);
2449 return false;
2450 }
2451
2452 switch (k->kv_type) {
2453 case ATH9K_CIPHER_AES_OCB:
2454 keyType = AR_KEYTABLE_TYPE_AES;
2455 break;
2456 case ATH9K_CIPHER_AES_CCM:
2457 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2458 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2459 "AES-CCM not supported by mac rev 0x%x\n",
2460 ah->hw_version.macRev);
2461 return false;
2462 }
2463 keyType = AR_KEYTABLE_TYPE_CCM;
2464 break;
2465 case ATH9K_CIPHER_TKIP:
2466 keyType = AR_KEYTABLE_TYPE_TKIP;
2467 if (ATH9K_IS_MIC_ENABLED(ah)
2468 && entry + 64 >= pCap->keycache_size) {
2469 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2470 "entry %u inappropriate for TKIP\n", entry);
2471 return false;
2472 }
2473 break;
2474 case ATH9K_CIPHER_WEP:
2475 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2476 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2477 "WEP key length %u too small\n", k->kv_len);
2478 return false;
2479 }
2480 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2481 keyType = AR_KEYTABLE_TYPE_40;
2482 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2483 keyType = AR_KEYTABLE_TYPE_104;
2484 else
2485 keyType = AR_KEYTABLE_TYPE_128;
2486 break;
2487 case ATH9K_CIPHER_CLR:
2488 keyType = AR_KEYTABLE_TYPE_CLR;
2489 break;
2490 default:
2491 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2492 "cipher %u not supported\n", k->kv_type);
2493 return false;
2494 }
2495
2496 key0 = get_unaligned_le32(k->kv_val + 0);
2497 key1 = get_unaligned_le16(k->kv_val + 4);
2498 key2 = get_unaligned_le32(k->kv_val + 6);
2499 key3 = get_unaligned_le16(k->kv_val + 10);
2500 key4 = get_unaligned_le32(k->kv_val + 12);
2501 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2502 key4 &= 0xff;
2503
2504 /*
2505 * Note: Key cache registers access special memory area that requires
2506 * two 32-bit writes to actually update the values in the internal
2507 * memory. Consequently, the exact order and pairs used here must be
2508 * maintained.
2509 */
2510
2511 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2512 u16 micentry = entry + 64;
2513
2514 /*
2515 * Write inverted key[47:0] first to avoid Michael MIC errors
2516 * on frames that could be sent or received at the same time.
2517 * The correct key will be written in the end once everything
2518 * else is ready.
2519 */
2520 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2521 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2522
2523 /* Write key[95:48] */
2524 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2525 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2526
2527 /* Write key[127:96] and key type */
2528 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2529 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2530
2531 /* Write MAC address for the entry */
2532 (void) ath9k_hw_keysetmac(ah, entry, mac);
2533
2534 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2535 /*
2536 * TKIP uses two key cache entries:
2537 * Michael MIC TX/RX keys in the same key cache entry
2538 * (idx = main index + 64):
2539 * key0 [31:0] = RX key [31:0]
2540 * key1 [15:0] = TX key [31:16]
2541 * key1 [31:16] = reserved
2542 * key2 [31:0] = RX key [63:32]
2543 * key3 [15:0] = TX key [15:0]
2544 * key3 [31:16] = reserved
2545 * key4 [31:0] = TX key [63:32]
2546 */
2547 u32 mic0, mic1, mic2, mic3, mic4;
2548
2549 mic0 = get_unaligned_le32(k->kv_mic + 0);
2550 mic2 = get_unaligned_le32(k->kv_mic + 4);
2551 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2552 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2553 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2554
2555 /* Write RX[31:0] and TX[31:16] */
2556 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2557 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2558
2559 /* Write RX[63:32] and TX[15:0] */
2560 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2561 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2562
2563 /* Write TX[63:32] and keyType(reserved) */
2564 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2565 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2566 AR_KEYTABLE_TYPE_CLR);
2567
2568 } else {
2569 /*
2570 * TKIP uses four key cache entries (two for group
2571 * keys):
2572 * Michael MIC TX/RX keys are in different key cache
2573 * entries (idx = main index + 64 for TX and
2574 * main index + 32 + 96 for RX):
2575 * key0 [31:0] = TX/RX MIC key [31:0]
2576 * key1 [31:0] = reserved
2577 * key2 [31:0] = TX/RX MIC key [63:32]
2578 * key3 [31:0] = reserved
2579 * key4 [31:0] = reserved
2580 *
2581 * Upper layer code will call this function separately
2582 * for TX and RX keys when these registers offsets are
2583 * used.
2584 */
2585 u32 mic0, mic2;
2586
2587 mic0 = get_unaligned_le32(k->kv_mic + 0);
2588 mic2 = get_unaligned_le32(k->kv_mic + 4);
2589
2590 /* Write MIC key[31:0] */
2591 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2592 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2593
2594 /* Write MIC key[63:32] */
2595 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2596 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2597
2598 /* Write TX[63:32] and keyType(reserved) */
2599 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2600 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2601 AR_KEYTABLE_TYPE_CLR);
2602 }
2603
2604 /* MAC address registers are reserved for the MIC entry */
2605 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2606 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2607
2608 /*
2609 * Write the correct (un-inverted) key[47:0] last to enable
2610 * TKIP now that all other registers are set with correct
2611 * values.
2612 */
2613 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2614 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2615 } else {
2616 /* Write key[47:0] */
2617 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2618 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2619
2620 /* Write key[95:48] */
2621 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2622 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2623
2624 /* Write key[127:96] and key type */
2625 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2626 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2627
2628 /* Write MAC address for the entry */
2629 (void) ath9k_hw_keysetmac(ah, entry, mac);
2630 }
2631
2632 return true;
2633}
2634
2635bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2636{
2637 if (entry < ah->caps.keycache_size) {
2638 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2639 if (val & AR_KEYTABLE_VALID)
2640 return true;
2641 }
2642 return false;
2643}
2644
2645/******************************/
2646/* Power Management (Chipset) */
2647/******************************/
2648
2649static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2650{
2651 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2652 if (setChip) {
2653 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2654 AR_RTC_FORCE_WAKE_EN);
2655 if (!AR_SREV_9100(ah))
2656 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2657
2658 REG_CLR_BIT(ah, (AR_RTC_RESET),
2659 AR_RTC_RESET_EN);
2660 }
2661}
2662
2663static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2664{
2665 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2666 if (setChip) {
2667 struct ath9k_hw_capabilities *pCap = &ah->caps;
2668
2669 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2670 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2671 AR_RTC_FORCE_WAKE_ON_INT);
2672 } else {
2673 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2674 AR_RTC_FORCE_WAKE_EN);
2675 }
2676 }
2677}
2678
2679static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2680{
2681 u32 val;
2682 int i;
2683
2684 if (setChip) {
2685 if ((REG_READ(ah, AR_RTC_STATUS) &
2686 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2687 if (ath9k_hw_set_reset_reg(ah,
2688 ATH9K_RESET_POWER_ON) != true) {
2689 return false;
2690 }
2691 }
2692 if (AR_SREV_9100(ah))
2693 REG_SET_BIT(ah, AR_RTC_RESET,
2694 AR_RTC_RESET_EN);
2695
2696 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2697 AR_RTC_FORCE_WAKE_EN);
2698 udelay(50);
2699
2700 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2701 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2702 if (val == AR_RTC_STATUS_ON)
2703 break;
2704 udelay(50);
2705 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2706 AR_RTC_FORCE_WAKE_EN);
2707 }
2708 if (i == 0) {
2709 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2710 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2711 return false;
2712 }
2713 }
2714
2715 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2716
2717 return true;
2718}
2719
2720bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2721{
2722 int status = true, setChip = true;
2723 static const char *modes[] = {
2724 "AWAKE",
2725 "FULL-SLEEP",
2726 "NETWORK SLEEP",
2727 "UNDEFINED"
2728 };
2729
2730 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2731 modes[ah->power_mode], modes[mode]);
2732
2733 switch (mode) {
2734 case ATH9K_PM_AWAKE:
2735 status = ath9k_hw_set_power_awake(ah, setChip);
2736 break;
2737 case ATH9K_PM_FULL_SLEEP:
2738 ath9k_set_power_sleep(ah, setChip);
2739 ah->chip_fullsleep = true;
2740 break;
2741 case ATH9K_PM_NETWORK_SLEEP:
2742 ath9k_set_power_network_sleep(ah, setChip);
2743 break;
2744 default:
2745 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2746 "Unknown power mode %u\n", mode);
2747 return false;
2748 }
2749 ah->power_mode = mode;
2750
2751 return status;
2752}
2753
2754/*
2755 * Helper for ASPM support.
2756 *
2757 * Disable PLL when in L0s as well as receiver clock when in L1.
2758 * This power saving option must be enabled through the SerDes.
2759 *
2760 * Programming the SerDes must go through the same 288 bit serial shift
2761 * register as the other analog registers. Hence the 9 writes.
2762 */
2763void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2764{
2765 u8 i;
2766
2767 if (ah->is_pciexpress != true)
2768 return;
2769
2770 /* Do not touch SerDes registers */
2771 if (ah->config.pcie_powersave_enable == 2)
2772 return;
2773
2774 /* Nothing to do on restore for 11N */
2775 if (restore)
2776 return;
2777
2778 if (AR_SREV_9280_20_OR_LATER(ah)) {
2779 /*
2780 * AR9280 2.0 or later chips use SerDes values from the
2781 * initvals.h initialized depending on chipset during
2782 * ath9k_hw_do_attach()
2783 */
2784 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2785 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2786 INI_RA(&ah->iniPcieSerdes, i, 1));
2787 }
2788 } else if (AR_SREV_9280(ah) &&
2789 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2790 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2791 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2792
2793 /* RX shut off when elecidle is asserted */
2794 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2795 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2796 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2797
2798 /* Shut off CLKREQ active in L1 */
2799 if (ah->config.pcie_clock_req)
2800 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2801 else
2802 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2803
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2805 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2806 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2807
2808 /* Load the new settings */
2809 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2810
2811 } else {
2812 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2813 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2814
2815 /* RX shut off when elecidle is asserted */
2816 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2817 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2818 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2819
2820 /*
2821 * Ignore ah->ah_config.pcie_clock_req setting for
2822 * pre-AR9280 11n
2823 */
2824 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2825
2826 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2827 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2828 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2829
2830 /* Load the new settings */
2831 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2832 }
2833
2834 udelay(1000);
2835
2836 /* set bit 19 to allow forcing of pcie core into L1 state */
2837 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2838
2839 /* Several PCIe massages to ensure proper behaviour */
2840 if (ah->config.pcie_waen) {
2841 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2842 } else {
2843 if (AR_SREV_9285(ah))
2844 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2845 /*
2846 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2847 * otherwise card may disappear.
2848 */
2849 else if (AR_SREV_9280(ah))
2850 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2851 else
2852 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2853 }
2854}
2855
2856/**********************/
2857/* Interrupt Handling */
2858/**********************/
2859
2860bool ath9k_hw_intrpend(struct ath_hw *ah)
2861{
2862 u32 host_isr;
2863
2864 if (AR_SREV_9100(ah))
2865 return true;
2866
2867 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2868 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2869 return true;
2870
2871 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2872 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2873 && (host_isr != AR_INTR_SPURIOUS))
2874 return true;
2875
2876 return false;
2877}
2878
2879bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2880{
2881 u32 isr = 0;
2882 u32 mask2 = 0;
2883 struct ath9k_hw_capabilities *pCap = &ah->caps;
2884 u32 sync_cause = 0;
2885 bool fatal_int = false;
2886
2887 if (!AR_SREV_9100(ah)) {
2888 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2889 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2890 == AR_RTC_STATUS_ON) {
2891 isr = REG_READ(ah, AR_ISR);
2892 }
2893 }
2894
2895 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2896 AR_INTR_SYNC_DEFAULT;
2897
2898 *masked = 0;
2899
2900 if (!isr && !sync_cause)
2901 return false;
2902 } else {
2903 *masked = 0;
2904 isr = REG_READ(ah, AR_ISR);
2905 }
2906
2907 if (isr) {
2908 if (isr & AR_ISR_BCNMISC) {
2909 u32 isr2;
2910 isr2 = REG_READ(ah, AR_ISR_S2);
2911 if (isr2 & AR_ISR_S2_TIM)
2912 mask2 |= ATH9K_INT_TIM;
2913 if (isr2 & AR_ISR_S2_DTIM)
2914 mask2 |= ATH9K_INT_DTIM;
2915 if (isr2 & AR_ISR_S2_DTIMSYNC)
2916 mask2 |= ATH9K_INT_DTIMSYNC;
2917 if (isr2 & (AR_ISR_S2_CABEND))
2918 mask2 |= ATH9K_INT_CABEND;
2919 if (isr2 & AR_ISR_S2_GTT)
2920 mask2 |= ATH9K_INT_GTT;
2921 if (isr2 & AR_ISR_S2_CST)
2922 mask2 |= ATH9K_INT_CST;
2923 if (isr2 & AR_ISR_S2_TSFOOR)
2924 mask2 |= ATH9K_INT_TSFOOR;
2925 }
2926
2927 isr = REG_READ(ah, AR_ISR_RAC);
2928 if (isr == 0xffffffff) {
2929 *masked = 0;
2930 return false;
2931 }
2932
2933 *masked = isr & ATH9K_INT_COMMON;
2934
2935 if (ah->config.intr_mitigation) {
2936 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2937 *masked |= ATH9K_INT_RX;
2938 }
2939
2940 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2941 *masked |= ATH9K_INT_RX;
2942 if (isr &
2943 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2944 AR_ISR_TXEOL)) {
2945 u32 s0_s, s1_s;
2946
2947 *masked |= ATH9K_INT_TX;
2948
2949 s0_s = REG_READ(ah, AR_ISR_S0_S);
2950 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2951 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2952
2953 s1_s = REG_READ(ah, AR_ISR_S1_S);
2954 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2955 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2956 }
2957
2958 if (isr & AR_ISR_RXORN) {
2959 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2960 "receive FIFO overrun interrupt\n");
2961 }
2962
2963 if (!AR_SREV_9100(ah)) {
2964 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2965 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2966 if (isr5 & AR_ISR_S5_TIM_TIMER)
2967 *masked |= ATH9K_INT_TIM_TIMER;
2968 }
2969 }
2970
2971 *masked |= mask2;
2972 }
2973
2974 if (AR_SREV_9100(ah))
2975 return true;
2976
2977 if (sync_cause) {
2978 fatal_int =
2979 (sync_cause &
2980 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2981 ? true : false;
2982
2983 if (fatal_int) {
2984 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2985 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2986 "received PCI FATAL interrupt\n");
2987 }
2988 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2989 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2990 "received PCI PERR interrupt\n");
2991 }
2992 *masked |= ATH9K_INT_FATAL;
2993 }
2994 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2995 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2996 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2997 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2998 REG_WRITE(ah, AR_RC, 0);
2999 *masked |= ATH9K_INT_FATAL;
3000 }
3001 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3002 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3003 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3004 }
3005
3006 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3007 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3008 }
3009
3010 return true;
3011}
3012
3013enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3014{
3015 return ah->mask_reg;
3016}
3017
3018enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3019{
3020 u32 omask = ah->mask_reg;
3021 u32 mask, mask2;
3022 struct ath9k_hw_capabilities *pCap = &ah->caps;
3023
3024 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3025
3026 if (omask & ATH9K_INT_GLOBAL) {
3027 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3028 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3029 (void) REG_READ(ah, AR_IER);
3030 if (!AR_SREV_9100(ah)) {
3031 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3032 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3033
3034 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3035 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3036 }
3037 }
3038
3039 mask = ints & ATH9K_INT_COMMON;
3040 mask2 = 0;
3041
3042 if (ints & ATH9K_INT_TX) {
3043 if (ah->txok_interrupt_mask)
3044 mask |= AR_IMR_TXOK;
3045 if (ah->txdesc_interrupt_mask)
3046 mask |= AR_IMR_TXDESC;
3047 if (ah->txerr_interrupt_mask)
3048 mask |= AR_IMR_TXERR;
3049 if (ah->txeol_interrupt_mask)
3050 mask |= AR_IMR_TXEOL;
3051 }
3052 if (ints & ATH9K_INT_RX) {
3053 mask |= AR_IMR_RXERR;
3054 if (ah->config.intr_mitigation)
3055 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3056 else
3057 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3058 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3059 mask |= AR_IMR_GENTMR;
3060 }
3061
3062 if (ints & (ATH9K_INT_BMISC)) {
3063 mask |= AR_IMR_BCNMISC;
3064 if (ints & ATH9K_INT_TIM)
3065 mask2 |= AR_IMR_S2_TIM;
3066 if (ints & ATH9K_INT_DTIM)
3067 mask2 |= AR_IMR_S2_DTIM;
3068 if (ints & ATH9K_INT_DTIMSYNC)
3069 mask2 |= AR_IMR_S2_DTIMSYNC;
3070 if (ints & ATH9K_INT_CABEND)
3071 mask2 |= AR_IMR_S2_CABEND;
3072 if (ints & ATH9K_INT_TSFOOR)
3073 mask2 |= AR_IMR_S2_TSFOOR;
3074 }
3075
3076 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3077 mask |= AR_IMR_BCNMISC;
3078 if (ints & ATH9K_INT_GTT)
3079 mask2 |= AR_IMR_S2_GTT;
3080 if (ints & ATH9K_INT_CST)
3081 mask2 |= AR_IMR_S2_CST;
3082 }
3083
3084 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3085 REG_WRITE(ah, AR_IMR, mask);
3086 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3087 AR_IMR_S2_DTIM |
3088 AR_IMR_S2_DTIMSYNC |
3089 AR_IMR_S2_CABEND |
3090 AR_IMR_S2_CABTO |
3091 AR_IMR_S2_TSFOOR |
3092 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3093 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3094 ah->mask_reg = ints;
3095
3096 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3097 if (ints & ATH9K_INT_TIM_TIMER)
3098 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3099 else
3100 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3101 }
3102
3103 if (ints & ATH9K_INT_GLOBAL) {
3104 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3105 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3106 if (!AR_SREV_9100(ah)) {
3107 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3108 AR_INTR_MAC_IRQ);
3109 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3110
3111
3112 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3113 AR_INTR_SYNC_DEFAULT);
3114 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3115 AR_INTR_SYNC_DEFAULT);
3116 }
3117 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3118 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3119 }
3120
3121 return omask;
3122}
3123
3124/*******************/
3125/* Beacon Handling */
3126/*******************/
3127
3128void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3129{
3130 int flags = 0;
3131
3132 ah->beacon_interval = beacon_period;
3133
3134 switch (ah->opmode) {
3135 case NL80211_IFTYPE_STATION:
3136 case NL80211_IFTYPE_MONITOR:
3137 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3138 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3139 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3140 flags |= AR_TBTT_TIMER_EN;
3141 break;
3142 case NL80211_IFTYPE_ADHOC:
3143 case NL80211_IFTYPE_MESH_POINT:
3144 REG_SET_BIT(ah, AR_TXCFG,
3145 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3146 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3147 TU_TO_USEC(next_beacon +
3148 (ah->atim_window ? ah->
3149 atim_window : 1)));
3150 flags |= AR_NDP_TIMER_EN;
3151 case NL80211_IFTYPE_AP:
3152 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3153 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3154 TU_TO_USEC(next_beacon -
3155 ah->config.
3156 dma_beacon_response_time));
3157 REG_WRITE(ah, AR_NEXT_SWBA,
3158 TU_TO_USEC(next_beacon -
3159 ah->config.
3160 sw_beacon_response_time));
3161 flags |=
3162 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3163 break;
3164 default:
3165 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3166 "%s: unsupported opmode: %d\n",
3167 __func__, ah->opmode);
3168 return;
3169 break;
3170 }
3171
3172 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3173 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3174 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3175 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3176
3177 beacon_period &= ~ATH9K_BEACON_ENA;
3178 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3179 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3180 ath9k_hw_reset_tsf(ah);
3181 }
3182
3183 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3184}
3185
3186void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3187 const struct ath9k_beacon_state *bs)
3188{
3189 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3190 struct ath9k_hw_capabilities *pCap = &ah->caps;
3191
3192 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3193
3194 REG_WRITE(ah, AR_BEACON_PERIOD,
3195 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3196 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3197 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3198
3199 REG_RMW_FIELD(ah, AR_RSSI_THR,
3200 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3201
3202 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3203
3204 if (bs->bs_sleepduration > beaconintval)
3205 beaconintval = bs->bs_sleepduration;
3206
3207 dtimperiod = bs->bs_dtimperiod;
3208 if (bs->bs_sleepduration > dtimperiod)
3209 dtimperiod = bs->bs_sleepduration;
3210
3211 if (beaconintval == dtimperiod)
3212 nextTbtt = bs->bs_nextdtim;
3213 else
3214 nextTbtt = bs->bs_nexttbtt;
3215
3216 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3217 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3218 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3219 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3220
3221 REG_WRITE(ah, AR_NEXT_DTIM,
3222 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3223 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3224
3225 REG_WRITE(ah, AR_SLEEP1,
3226 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3227 | AR_SLEEP1_ASSUME_DTIM);
3228
3229 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3230 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3231 else
3232 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3233
3234 REG_WRITE(ah, AR_SLEEP2,
3235 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3236
3237 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3238 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3239
3240 REG_SET_BIT(ah, AR_TIMER_MODE,
3241 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3242 AR_DTIM_TIMER_EN);
3243
3244 /* TSF Out of Range Threshold */
3245 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3246}
3247
3248/*******************/
3249/* HW Capabilities */
3250/*******************/
3251
3252void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3253{
3254 struct ath9k_hw_capabilities *pCap = &ah->caps;
3255 u16 capField = 0, eeval;
3256
3257 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3258 ah->regulatory.current_rd = eeval;
3259
3260 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3261 if (AR_SREV_9285_10_OR_LATER(ah))
3262 eeval |= AR9285_RDEXT_DEFAULT;
3263 ah->regulatory.current_rd_ext = eeval;
3264
3265 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3266
3267 if (ah->opmode != NL80211_IFTYPE_AP &&
3268 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3269 if (ah->regulatory.current_rd == 0x64 ||
3270 ah->regulatory.current_rd == 0x65)
3271 ah->regulatory.current_rd += 5;
3272 else if (ah->regulatory.current_rd == 0x41)
3273 ah->regulatory.current_rd = 0x43;
3274 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3275 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3276 }
3277
3278 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3279 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3280
3281 if (eeval & AR5416_OPFLAGS_11A) {
3282 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3283 if (ah->config.ht_enable) {
3284 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3285 set_bit(ATH9K_MODE_11NA_HT20,
3286 pCap->wireless_modes);
3287 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3288 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3289 pCap->wireless_modes);
3290 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3291 pCap->wireless_modes);
3292 }
3293 }
3294 }
3295
3296 if (eeval & AR5416_OPFLAGS_11G) {
3297 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3298 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3299 if (ah->config.ht_enable) {
3300 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3301 set_bit(ATH9K_MODE_11NG_HT20,
3302 pCap->wireless_modes);
3303 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3304 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3305 pCap->wireless_modes);
3306 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3307 pCap->wireless_modes);
3308 }
3309 }
3310 }
3311
3312 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3313 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3314 !(eeval & AR5416_OPFLAGS_11A))
3315 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3316 else
3317 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3318
3319 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3320 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3321
3322 pCap->low_2ghz_chan = 2312;
3323 pCap->high_2ghz_chan = 2732;
3324
3325 pCap->low_5ghz_chan = 4920;
3326 pCap->high_5ghz_chan = 6100;
3327
3328 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3329 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3330 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3331
3332 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3333 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3334 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3335
3336 if (ah->config.ht_enable)
3337 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3338 else
3339 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3340
3341 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3342 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3343 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3344 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3345
3346 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3347 pCap->total_queues =
3348 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3349 else
3350 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3351
3352 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3353 pCap->keycache_size =
3354 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3355 else
3356 pCap->keycache_size = AR_KEYTABLE_SIZE;
3357
3358 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3359 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3360
3361 if (AR_SREV_9285_10_OR_LATER(ah))
3362 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3363 else if (AR_SREV_9280_10_OR_LATER(ah))
3364 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3365 else
3366 pCap->num_gpio_pins = AR_NUM_GPIO;
3367
3368 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3369 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3370 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3371 } else {
3372 pCap->rts_aggr_limit = (8 * 1024);
3373 }
3374
3375 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3376
3377#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3378 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3379 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3380 ah->rfkill_gpio =
3381 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3382 ah->rfkill_polarity =
3383 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3384
3385 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3386 }
3387#endif
3388
3389 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3390 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3391 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3392 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3393 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3394 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3395 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3396 else
3397 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3398
3399 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3400 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3401 else
3402 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3403
3404 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3405 pCap->reg_cap =
3406 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3407 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3408 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3409 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3410 } else {
3411 pCap->reg_cap =
3412 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3413 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3414 }
3415
3416 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3417
3418 pCap->num_antcfg_5ghz =
3419 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3420 pCap->num_antcfg_2ghz =
3421 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3422
3423 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3424 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3425 ah->btactive_gpio = 6;
3426 ah->wlanactive_gpio = 5;
3427 }
3428}
3429
3430bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3431 u32 capability, u32 *result)
3432{
3433 switch (type) {
3434 case ATH9K_CAP_CIPHER:
3435 switch (capability) {
3436 case ATH9K_CIPHER_AES_CCM:
3437 case ATH9K_CIPHER_AES_OCB:
3438 case ATH9K_CIPHER_TKIP:
3439 case ATH9K_CIPHER_WEP:
3440 case ATH9K_CIPHER_MIC:
3441 case ATH9K_CIPHER_CLR:
3442 return true;
3443 default:
3444 return false;
3445 }
3446 case ATH9K_CAP_TKIP_MIC:
3447 switch (capability) {
3448 case 0:
3449 return true;
3450 case 1:
3451 return (ah->sta_id1_defaults &
3452 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3453 false;
3454 }
3455 case ATH9K_CAP_TKIP_SPLIT:
3456 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3457 false : true;
3458 case ATH9K_CAP_DIVERSITY:
3459 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3460 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3461 true : false;
3462 case ATH9K_CAP_MCAST_KEYSRCH:
3463 switch (capability) {
3464 case 0:
3465 return true;
3466 case 1:
3467 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3468 return false;
3469 } else {
3470 return (ah->sta_id1_defaults &
3471 AR_STA_ID1_MCAST_KSRCH) ? true :
3472 false;
3473 }
3474 }
3475 return false;
3476 case ATH9K_CAP_TXPOW:
3477 switch (capability) {
3478 case 0:
3479 return 0;
3480 case 1:
3481 *result = ah->regulatory.power_limit;
3482 return 0;
3483 case 2:
3484 *result = ah->regulatory.max_power_level;
3485 return 0;
3486 case 3:
3487 *result = ah->regulatory.tp_scale;
3488 return 0;
3489 }
3490 return false;
3491 case ATH9K_CAP_DS:
3492 return (AR_SREV_9280_20_OR_LATER(ah) &&
3493 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3494 ? false : true;
3495 default:
3496 return false;
3497 }
3498}
3499
3500bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3501 u32 capability, u32 setting, int *status)
3502{
3503 u32 v;
3504
3505 switch (type) {
3506 case ATH9K_CAP_TKIP_MIC:
3507 if (setting)
3508 ah->sta_id1_defaults |=
3509 AR_STA_ID1_CRPT_MIC_ENABLE;
3510 else
3511 ah->sta_id1_defaults &=
3512 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3513 return true;
3514 case ATH9K_CAP_DIVERSITY:
3515 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3516 if (setting)
3517 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3518 else
3519 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3520 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3521 return true;
3522 case ATH9K_CAP_MCAST_KEYSRCH:
3523 if (setting)
3524 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3525 else
3526 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3527 return true;
3528 default:
3529 return false;
3530 }
3531}
3532
3533/****************************/
3534/* GPIO / RFKILL / Antennae */
3535/****************************/
3536
3537static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3538 u32 gpio, u32 type)
3539{
3540 int addr;
3541 u32 gpio_shift, tmp;
3542
3543 if (gpio > 11)
3544 addr = AR_GPIO_OUTPUT_MUX3;
3545 else if (gpio > 5)
3546 addr = AR_GPIO_OUTPUT_MUX2;
3547 else
3548 addr = AR_GPIO_OUTPUT_MUX1;
3549
3550 gpio_shift = (gpio % 6) * 5;
3551
3552 if (AR_SREV_9280_20_OR_LATER(ah)
3553 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3554 REG_RMW(ah, addr, (type << gpio_shift),
3555 (0x1f << gpio_shift));
3556 } else {
3557 tmp = REG_READ(ah, addr);
3558 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3559 tmp &= ~(0x1f << gpio_shift);
3560 tmp |= (type << gpio_shift);
3561 REG_WRITE(ah, addr, tmp);
3562 }
3563}
3564
3565void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3566{
3567 u32 gpio_shift;
3568
3569 ASSERT(gpio < ah->caps.num_gpio_pins);
3570
3571 gpio_shift = gpio << 1;
3572
3573 REG_RMW(ah,
3574 AR_GPIO_OE_OUT,
3575 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3576 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3577}
3578
3579u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3580{
3581#define MS_REG_READ(x, y) \
3582 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3583
3584 if (gpio >= ah->caps.num_gpio_pins)
3585 return 0xffffffff;
3586
3587 if (AR_SREV_9285_10_OR_LATER(ah))
3588 return MS_REG_READ(AR9285, gpio) != 0;
3589 else if (AR_SREV_9280_10_OR_LATER(ah))
3590 return MS_REG_READ(AR928X, gpio) != 0;
3591 else
3592 return MS_REG_READ(AR, gpio) != 0;
3593}
3594
3595void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3596 u32 ah_signal_type)
3597{
3598 u32 gpio_shift;
3599
3600 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3601
3602 gpio_shift = 2 * gpio;
3603
3604 REG_RMW(ah,
3605 AR_GPIO_OE_OUT,
3606 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3607 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3608}
3609
3610void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3611{
3612 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3613 AR_GPIO_BIT(gpio));
3614}
3615
3616#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3617void ath9k_enable_rfkill(struct ath_hw *ah)
3618{
3619 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3620 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3621
3622 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3623 AR_GPIO_INPUT_MUX2_RFSILENT);
3624
3625 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3626 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3627}
3628#endif
3629
3630u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3631{
3632 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3633}
3634
3635void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3636{
3637 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3638}
3639
3640bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3641 enum ath9k_ant_setting settings,
3642 struct ath9k_channel *chan,
3643 u8 *tx_chainmask,
3644 u8 *rx_chainmask,
3645 u8 *antenna_cfgd)
3646{
3647 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3648
3649 if (AR_SREV_9280(ah)) {
3650 if (!tx_chainmask_cfg) {
3651
3652 tx_chainmask_cfg = *tx_chainmask;
3653 rx_chainmask_cfg = *rx_chainmask;
3654 }
3655
3656 switch (settings) {
3657 case ATH9K_ANT_FIXED_A:
3658 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3659 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3660 *antenna_cfgd = true;
3661 break;
3662 case ATH9K_ANT_FIXED_B:
3663 if (ah->caps.tx_chainmask >
3664 ATH9K_ANTENNA1_CHAINMASK) {
3665 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3666 }
3667 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3668 *antenna_cfgd = true;
3669 break;
3670 case ATH9K_ANT_VARIABLE:
3671 *tx_chainmask = tx_chainmask_cfg;
3672 *rx_chainmask = rx_chainmask_cfg;
3673 *antenna_cfgd = true;
3674 break;
3675 default:
3676 break;
3677 }
3678 } else {
3679 ah->diversity_control = settings;
3680 }
3681
3682 return true;
3683}
3684
3685/*********************/
3686/* General Operation */
3687/*********************/
3688
3689u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3690{
3691 u32 bits = REG_READ(ah, AR_RX_FILTER);
3692 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3693
3694 if (phybits & AR_PHY_ERR_RADAR)
3695 bits |= ATH9K_RX_FILTER_PHYRADAR;
3696 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3697 bits |= ATH9K_RX_FILTER_PHYERR;
3698
3699 return bits;
3700}
3701
3702void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3703{
3704 u32 phybits;
3705
3706 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3707 phybits = 0;
3708 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3709 phybits |= AR_PHY_ERR_RADAR;
3710 if (bits & ATH9K_RX_FILTER_PHYERR)
3711 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3712 REG_WRITE(ah, AR_PHY_ERR, phybits);
3713
3714 if (phybits)
3715 REG_WRITE(ah, AR_RXCFG,
3716 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3717 else
3718 REG_WRITE(ah, AR_RXCFG,
3719 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3720}
3721
3722bool ath9k_hw_phy_disable(struct ath_hw *ah)
3723{
3724 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3725}
3726
3727bool ath9k_hw_disable(struct ath_hw *ah)
3728{
3729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3730 return false;
3731
3732 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3733}
3734
3735void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3736{
3737 struct ath9k_channel *chan = ah->curchan;
3738 struct ieee80211_channel *channel = chan->chan;
3739
3740 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3741
3742 ah->eep_ops->set_txpower(ah, chan,
3743 ath9k_regd_get_ctl(&ah->regulatory, chan),
3744 channel->max_antenna_gain * 2,
3745 channel->max_power * 2,
3746 min((u32) MAX_RATE_POWER,
3747 (u32) ah->regulatory.power_limit));
3748}
3749
3750void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3751{
3752 memcpy(ah->macaddr, mac, ETH_ALEN);
3753}
3754
3755void ath9k_hw_setopmode(struct ath_hw *ah)
3756{
3757 ath9k_hw_set_operating_mode(ah, ah->opmode);
3758}
3759
3760void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3761{
3762 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3763 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3764}
3765
3766void ath9k_hw_setbssidmask(struct ath_softc *sc)
3767{
3768 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3769 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3770}
3771
3772void ath9k_hw_write_associd(struct ath_softc *sc)
3773{
3774 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3775 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3776 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3777}
3778
3779u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3780{
3781 u64 tsf;
3782
3783 tsf = REG_READ(ah, AR_TSF_U32);
3784 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3785
3786 return tsf;
3787}
3788
3789void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3790{
3791 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3792 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3793}
3794
3795void ath9k_hw_reset_tsf(struct ath_hw *ah)
3796{
3797 int count;
3798
3799 count = 0;
3800 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3801 count++;
3802 if (count > 10) {
3803 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3804 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3805 break;
3806 }
3807 udelay(10);
3808 }
3809 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3810}
3811
3812bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3813{
3814 if (setting)
3815 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3816 else
3817 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3818
3819 return true;
3820}
3821
3822bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3823{
3824 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3825 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3826 ah->slottime = (u32) -1;
3827 return false;
3828 } else {
3829 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3830 ah->slottime = us;
3831 return true;
3832 }
3833}
3834
3835void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3836{
3837 u32 macmode;
3838
3839 if (mode == ATH9K_HT_MACMODE_2040 &&
3840 !ah->config.cwm_ignore_extcca)
3841 macmode = AR_2040_JOINED_RX_CLEAR;
3842 else
3843 macmode = 0;
3844
3845 REG_WRITE(ah, AR_2040_MODE, macmode);
3846}
3847
3848/***************************/
3849/* Bluetooth Coexistence */
3850/***************************/
3851
3852void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3853{
3854 /* connect bt_active to baseband */
3855 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3856 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3857 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3858
3859 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3860 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3861
3862 /* Set input mux for bt_active to gpio pin */
3863 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3864 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3865 ah->btactive_gpio);
3866
3867 /* Configure the desired gpio port for input */
3868 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3869
3870 /* Configure the desired GPIO port for TX_FRAME output */
3871 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3872 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3873}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 17:51:52 -0500