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authorJ. Bruce Fields <bfields@redhat.com>2010-12-17 13:29:07 -0500
committerJ. Bruce Fields <bfields@redhat.com>2010-12-17 13:29:07 -0500
commitec66ee3797e5848356cf593c6ec7aabf30a00cf1 (patch)
tree7ed5c84cc914644ffa1cd1b6a2b45db53fc224e8 /drivers/net/wireless/ath/ath9k/eeprom.h
parent1205065764f2eda3216ebe213143f69891ee3460 (diff)
parentb0c3844d8af6b9f3f18f31e1b0502fbefa2166be (diff)
Merge commit 'v2.6.37-rc6' into for-2.6.38
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h27
1 files changed, 14 insertions, 13 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index dacb45e1b906..dd59f09441a3 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -233,6 +233,18 @@
233 233
234#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 234#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
235 235
236#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
237#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
238
239#define LNA_CTL_BUF_MODE BIT(0)
240#define LNA_CTL_ISEL_LO BIT(1)
241#define LNA_CTL_ISEL_HI BIT(2)
242#define LNA_CTL_BUF_IN BIT(3)
243#define LNA_CTL_FEM_BAND BIT(4)
244#define LNA_CTL_LOCAL_BIAS BIT(5)
245#define LNA_CTL_FORCE_XPA BIT(6)
246#define LNA_CTL_USE_ANT1 BIT(7)
247
236enum eeprom_param { 248enum eeprom_param {
237 EEP_NFTHRESH_5, 249 EEP_NFTHRESH_5,
238 EEP_NFTHRESH_2, 250 EEP_NFTHRESH_2,
@@ -378,10 +390,7 @@ struct modal_eep_header {
378 u8 xatten2Margin[AR5416_MAX_CHAINS]; 390 u8 xatten2Margin[AR5416_MAX_CHAINS];
379 u8 ob_ch1; 391 u8 ob_ch1;
380 u8 db_ch1; 392 u8 db_ch1;
381 u8 useAnt1:1, 393 u8 lna_ctl;
382 force_xpaon:1,
383 local_bias:1,
384 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
385 u8 miscBits; 394 u8 miscBits;
386 u16 xpaBiasLvlFreq[3]; 395 u16 xpaBiasLvlFreq[3];
387 u8 futureModal[6]; 396 u8 futureModal[6];
@@ -535,18 +544,10 @@ struct cal_target_power_ht {
535 u8 tPow2x[8]; 544 u8 tPow2x[8];
536} __packed; 545} __packed;
537 546
538
539#ifdef __BIG_ENDIAN_BITFIELD
540struct cal_ctl_edges {
541 u8 bChannel;
542 u8 flag:2, tPower:6;
543} __packed;
544#else
545struct cal_ctl_edges { 547struct cal_ctl_edges {
546 u8 bChannel; 548 u8 bChannel;
547 u8 tPower:6, flag:2; 549 u8 ctl;
548} __packed; 550} __packed;
549#endif
550 551
551struct cal_data_op_loop_ar9287 { 552struct cal_data_op_loop_ar9287 {
552 u8 pwrPdg[2][5]; 553 u8 pwrPdg[2][5];