diff options
author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-11-26 04:34:55 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2013-12-02 14:25:02 -0500 |
commit | dbb3e2fb4ab59e1b2c1d4d3a9b0ed4034ee349b9 (patch) | |
tree | d05b136b22cac407b38de67b7df16683c4cec81a /drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h | |
parent | 3777f7d121ffb8f75d7e98862f73ae8c2f2fa09a (diff) |
ath9k: Remove duplicate initvals for AR9462 v2.1
The initvals for AR9462 v2.1 are very similar to v2.0.
Identify duplicate arrays and reuse the values from v2.0
to reduce module size.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h index 5a10dcf2adf5..739094384369 100644 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h | |||
@@ -20,7 +20,7 @@ | |||
20 | 20 | ||
21 | /* AR9462 2.0 */ | 21 | /* AR9462 2.0 */ |
22 | 22 | ||
23 | static const u32 ar9462_modes_fast_clock_2p0[][3] = { | 23 | static const u32 ar9462_2p0_modes_fast_clock[][3] = { |
24 | /* Addr 5G_HT20 5G_HT40 */ | 24 | /* Addr 5G_HT20 5G_HT40 */ |
25 | {0x00001030, 0x00000268, 0x000004d0}, | 25 | {0x00001030, 0x00000268, 0x000004d0}, |
26 | {0x00001070, 0x0000018c, 0x00000318}, | 26 | {0x00001070, 0x0000018c, 0x00000318}, |
@@ -92,7 +92,7 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = { | |||
92 | {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, | 92 | {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, |
93 | }; | 93 | }; |
94 | 94 | ||
95 | static const u32 ar9462_common_rx_gain_table_2p0[][2] = { | 95 | static const u32 ar9462_2p0_common_rx_gain[][2] = { |
96 | /* Addr allmodes */ | 96 | /* Addr allmodes */ |
97 | {0x0000a000, 0x00010000}, | 97 | {0x0000a000, 0x00010000}, |
98 | {0x0000a004, 0x00030002}, | 98 | {0x0000a004, 0x00030002}, |
@@ -352,7 +352,7 @@ static const u32 ar9462_common_rx_gain_table_2p0[][2] = { | |||
352 | {0x0000b1fc, 0x00000196}, | 352 | {0x0000b1fc, 0x00000196}, |
353 | }; | 353 | }; |
354 | 354 | ||
355 | static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = { | 355 | static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = { |
356 | /* Addr allmodes */ | 356 | /* Addr allmodes */ |
357 | {0x00018c00, 0x18213ede}, | 357 | {0x00018c00, 0x18213ede}, |
358 | {0x00018c04, 0x000801d8}, | 358 | {0x00018c04, 0x000801d8}, |
@@ -366,7 +366,7 @@ static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = { | |||
366 | {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, | 366 | {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, |
367 | }; | 367 | }; |
368 | 368 | ||
369 | static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = { | 369 | static const u32 ar9462_2p0_common_wo_xlna_rx_gain[][2] = { |
370 | /* Addr allmodes */ | 370 | /* Addr allmodes */ |
371 | {0x0000a000, 0x00010000}, | 371 | {0x0000a000, 0x00010000}, |
372 | {0x0000a004, 0x00030002}, | 372 | {0x0000a004, 0x00030002}, |
@@ -633,7 +633,7 @@ static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { | |||
633 | {0x0000a3a0, 0xca9228ee}, | 633 | {0x0000a3a0, 0xca9228ee}, |
634 | }; | 634 | }; |
635 | 635 | ||
636 | static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = { | 636 | static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = { |
637 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | 637 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
638 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, | 638 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, |
639 | {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, | 639 | {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, |
@@ -865,7 +865,7 @@ static const u32 ar9462_2p0_radio_postamble[][5] = { | |||
865 | {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, | 865 | {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, |
866 | }; | 866 | }; |
867 | 867 | ||
868 | static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = { | 868 | static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = { |
869 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | 869 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
870 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, | 870 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, |
871 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | 871 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, |
@@ -928,7 +928,7 @@ static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = { | |||
928 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, | 928 | {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, |
929 | }; | 929 | }; |
930 | 930 | ||
931 | static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = { | 931 | static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = { |
932 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ | 932 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
933 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, | 933 | {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, |
934 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, | 934 | {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, |
@@ -1238,7 +1238,7 @@ static const u32 ar9462_2p0_mac_postamble[][5] = { | |||
1238 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, | 1238 | {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, |
1239 | }; | 1239 | }; |
1240 | 1240 | ||
1241 | static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = { | 1241 | static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = { |
1242 | /* Addr allmodes */ | 1242 | /* Addr allmodes */ |
1243 | {0x0000a000, 0x00010000}, | 1243 | {0x0000a000, 0x00010000}, |
1244 | {0x0000a004, 0x00030002}, | 1244 | {0x0000a004, 0x00030002}, |
@@ -1503,7 +1503,7 @@ static const u32 ar9462_2p0_baseband_postamble_5g_xlna[][5] = { | |||
1503 | {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, | 1503 | {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, |
1504 | }; | 1504 | }; |
1505 | 1505 | ||
1506 | static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = { | 1506 | static const u32 ar9462_2p0_common_5g_xlna_only_rxgain[][2] = { |
1507 | /* Addr allmodes */ | 1507 | /* Addr allmodes */ |
1508 | {0x0000a000, 0x00010000}, | 1508 | {0x0000a000, 0x00010000}, |
1509 | {0x0000a004, 0x00030002}, | 1509 | {0x0000a004, 0x00030002}, |