diff options
author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2012-02-22 02:10:55 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2012-02-27 14:06:35 -0500 |
commit | 5a1e273573d5e4a32aaa82a98a89b3fd711c74f0 (patch) | |
tree | 547222545225a5ce85a529d702e95366e99e51b8 /drivers/net/wireless/ath/ath9k/ar9003_mac.c | |
parent | d68475de9637a476ad8e5870060ccc69a80f2299 (diff) |
ath9k_hw: Use a helper function to get MCI ISR
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_mac.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_mac.c | 29 |
1 files changed, 2 insertions, 27 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index 39cb4829f292..575f36a296f4 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c | |||
@@ -180,7 +180,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
180 | u32 mask2 = 0; | 180 | u32 mask2 = 0; |
181 | struct ath9k_hw_capabilities *pCap = &ah->caps; | 181 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
182 | struct ath_common *common = ath9k_hw_common(ah); | 182 | struct ath_common *common = ath9k_hw_common(ah); |
183 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; | ||
184 | u32 sync_cause = 0, async_cause; | 183 | u32 sync_cause = 0, async_cause; |
185 | 184 | ||
186 | async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); | 185 | async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); |
@@ -302,32 +301,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
302 | ar9003_hw_bb_watchdog_read(ah); | 301 | ar9003_hw_bb_watchdog_read(ah); |
303 | } | 302 | } |
304 | 303 | ||
305 | if (async_cause & AR_INTR_ASYNC_MASK_MCI) { | 304 | if (async_cause & AR_INTR_ASYNC_MASK_MCI) |
306 | u32 raw_intr, rx_msg_intr; | 305 | ar9003_mci_get_isr(ah, masked); |
307 | |||
308 | rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); | ||
309 | raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); | ||
310 | |||
311 | if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) | ||
312 | ath_dbg(common, MCI, | ||
313 | "MCI gets 0xdeadbeef during MCI int processing new raw_intr=0x%08x, new rx_msg_raw=0x%08x, raw_intr=0x%08x, rx_msg_raw=0x%08x\n", | ||
314 | raw_intr, rx_msg_intr, mci->raw_intr, | ||
315 | mci->rx_msg_intr); | ||
316 | else { | ||
317 | mci->rx_msg_intr |= rx_msg_intr; | ||
318 | mci->raw_intr |= raw_intr; | ||
319 | *masked |= ATH9K_INT_MCI; | ||
320 | |||
321 | if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) | ||
322 | mci->cont_status = | ||
323 | REG_READ(ah, AR_MCI_CONT_STATUS); | ||
324 | |||
325 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); | ||
326 | REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); | ||
327 | ath_dbg(common, MCI, "AR_INTR_SYNC_MCI\n"); | ||
328 | |||
329 | } | ||
330 | } | ||
331 | 306 | ||
332 | if (sync_cause) { | 307 | if (sync_cause) { |
333 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | 308 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |