ath9k_hw: Initialize mode registers for AR9485

Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
author: Vasanthakumar Thiagarajan <vasanth@atheros.com> 2010-12-06 07:27:37 -0500
committer: John W. Linville <linville@tuxdriver.com> 2010-12-07 16:34:51 -0500
commit: c88457eb83fb6db7a3286a685ecc6e33a7aac49d (patch)
tree: bf3c19f7396c6743284f19e9920fad12b4e1445c /drivers/net/wireless/ath/ath9k/ar9003_hw.c
parent: 3050c9146b2a4c98a916192fac2867c0023ec2b1 (diff)
1 files changed, 129 insertions, 66 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 0e3e259df464..f01c2891f7c3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -17,6 +17,7 @@
 #include "hw.h"
 #include "ar9003_mac.h"
 #include "ar9003_2p2_initvals.h"
+#include "ar9485_initvals.h"
 /* General hardware code for the AR9003 hadware family */
@@ -39,72 +40,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
 */
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-        /* mac */
+        if (AR_SREV_9485(ah)) {
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                /* mac */
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-                       ar9300_2p2_mac_core,
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ARRAY_SIZE(ar9300_2p2_mac_core), 2);
+                                ar9485_1_0_mac_core,
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ARRAY_SIZE(ar9485_1_0_mac_core), 2);
-                       ar9300_2p2_mac_postamble,
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
-                       ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
+                                ar9485_1_0_mac_postamble,
+                                ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
-        /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
-                       ar9300_2p2_baseband_core,
+                                ARRAY_SIZE(ar9485_1_0), 2);
-                       ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9485_1_0_baseband_core,
-                       ar9300_2p2_baseband_postamble,
+                                ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
-                       ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9485_1_0_baseband_postamble,
-        /* radio */
+                                ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                /* radio */
-                       ar9300_2p2_radio_core,
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-                       ARRAY_SIZE(ar9300_2p2_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9485_1_0_radio_core,
-                       ar9300_2p2_radio_postamble,
+                                ARRAY_SIZE(ar9485_1_0_radio_core), 2);
-                       ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9485_1_0_radio_postamble,
-        /* soc */
+                                ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-                       ar9300_2p2_soc_preamble,
+                /* soc */
-                       ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                                ar9485_1_0_soc_preamble,
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
-                       ar9300_2p2_soc_postamble,
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
-                       ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
-        /* rx/tx gain */
+                /* rx/tx gain */
-        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
-                       ar9300Common_rx_gain_table_2p2,
+                                ar9485Common_rx_gain_1_0,
-                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
+                                ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
-        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
-                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+                                ar9485Modes_lowest_ob_db_tx_gain_1_0,
-                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+                                ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
-                       5);
+                                5);
-        /* Load PCIE SERDES settings from INI */
+                /* Load PCIE SERDES settings from INI */
-        /* Awake Setting */
+                /* Awake Setting */
-        INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                       ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
-                       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
-                       2);
+                                2);
-        /* Sleep Setting */
+                /* Sleep Setting */
-        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                       ar9300PciePhy_clkreq_enable_L1_2p2,
+                                ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
-                       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
+                                ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
-                       2);
+                                2);
+        } else {
-        /* Fast clock modal settings */
+                /* mac */
-        INIT_INI_ARRAY(&ah->iniModesAdditional,
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-                       ar9300Modes_fast_clock_2p2,
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+                                ar9300_2p2_mac_core,
-                       3);
+                                ARRAY_SIZE(ar9300_2p2_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9300_2p2_mac_postamble,
+                                ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9300_2p2_baseband_core,
+                                ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9300_2p2_baseband_postamble,
+                                ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9300_2p2_radio_core,
+                                ARRAY_SIZE(ar9300_2p2_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9300_2p2_radio_postamble,
+                                ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9300_2p2_soc_preamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ar9300_2p2_soc_postamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9300Common_rx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+                                5);
+                /* Load PCIE SERDES settings from INI */
+                /* Awake Setting */
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                2);
+                /* Sleep Setting */
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9300PciePhy_clkreq_enable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
+                                2);
+                /* Fast clock modal settings */
+                INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                ar9300Modes_fast_clock_2p2,
+                                ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+                                3);
+        }
 }
 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
author	Vasanthakumar Thiagarajan <vasanth@atheros.com>	2010-12-06 07:27:37 -0500
committer	John W. Linville <linville@tuxdriver.com>	2010-12-07 16:34:51 -0500
commit	c88457eb83fb6db7a3286a685ecc6e33a7aac49d (patch)
tree	bf3c19f7396c6743284f19e9920fad12b4e1445c /drivers/net/wireless/ath/ath9k/ar9003_hw.c
parent	3050c9146b2a4c98a916192fac2867c0023ec2b1 (diff)

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 0e3e259df464..f01c2891f7c3 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -17,6 +17,7 @@
17	#include "hw.h"	17	#include "hw.h"
18	#include "ar9003_mac.h"	18	#include "ar9003_mac.h"
19	#include "ar9003_2p2_initvals.h"	19	#include "ar9003_2p2_initvals.h"
		20	#include "ar9485_initvals.h"
20		21
21	/* General hardware code for the AR9003 hadware family */	22	/* General hardware code for the AR9003 hadware family */
22		23
@@ -39,72 +40,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
39	*/	40	*/
40	static void ar9003_hw_init_mode_regs(struct ath_hw *ah)	41	static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
41	{	42	{
42	/* mac */	43	if (AR_SREV_9485(ah)) {
43	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);	44	/* mac */
44	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],	45	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
45	ar9300_2p2_mac_core,	46	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
46	ARRAY_SIZE(ar9300_2p2_mac_core), 2);	47	ar9485_1_0_mac_core,
47	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],	48	ARRAY_SIZE(ar9485_1_0_mac_core), 2);
48	ar9300_2p2_mac_postamble,	49	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
49	ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);	50	ar9485_1_0_mac_postamble,
50		51	ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
51	/* bb */	52
52	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);	53	/* bb */
53	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],	54	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
54	ar9300_2p2_baseband_core,	55	ARRAY_SIZE(ar9485_1_0), 2);
55	ARRAY_SIZE(ar9300_2p2_baseband_core), 2);	56	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
56	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],	57	ar9485_1_0_baseband_core,
57	ar9300_2p2_baseband_postamble,	58	ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
58	ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);	59	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
59		60	ar9485_1_0_baseband_postamble,
60	/* radio */	61	ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
61	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);	62
62	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],	63	/* radio */
63	ar9300_2p2_radio_core,	64	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
64	ARRAY_SIZE(ar9300_2p2_radio_core), 2);	65	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
65	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],	66	ar9485_1_0_radio_core,
66	ar9300_2p2_radio_postamble,	67	ARRAY_SIZE(ar9485_1_0_radio_core), 2);
67	ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);	68	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
68		69	ar9485_1_0_radio_postamble,
69	/* soc */	70	ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
70	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],	71
71	ar9300_2p2_soc_preamble,	72	/* soc */
72	ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);	73	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
73	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);	74	ar9485_1_0_soc_preamble,
74	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],	75	ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
75	ar9300_2p2_soc_postamble,	76	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
76	ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);	77	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
77		78
78	/* rx/tx gain */	79	/* rx/tx gain */
79	INIT_INI_ARRAY(&ah->iniModesRxGain,	80	INIT_INI_ARRAY(&ah->iniModesRxGain,
80	ar9300Common_rx_gain_table_2p2,	81	ar9485Common_rx_gain_1_0,
81	ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);	82	ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
82	INIT_INI_ARRAY(&ah->iniModesTxGain,	83	INIT_INI_ARRAY(&ah->iniModesTxGain,
83	ar9300Modes_lowest_ob_db_tx_gain_table_2p2,	84	ar9485Modes_lowest_ob_db_tx_gain_1_0,
84	ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),	85	ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
85	5);	86	5);
86		87
87	/* Load PCIE SERDES settings from INI */	88	/* Load PCIE SERDES settings from INI */
88		89
89	/* Awake Setting */	90	/* Awake Setting */
90		91
91	INIT_INI_ARRAY(&ah->iniPcieSerdes,	92	INIT_INI_ARRAY(&ah->iniPcieSerdes,
92	ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,	93	ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
93	ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),	94	ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
94	2);	95	2);
95		96
96	/* Sleep Setting */	97	/* Sleep Setting */
97		98
98	INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,	99	INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
99	ar9300PciePhy_clkreq_enable_L1_2p2,	100	ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
100	ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),	101	ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
101	2);	102	2);
102		103	} else {
103	/* Fast clock modal settings */	104	/* mac */
104	INIT_INI_ARRAY(&ah->iniModesAdditional,	105	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
105	ar9300Modes_fast_clock_2p2,	106	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
106	ARRAY_SIZE(ar9300Modes_fast_clock_2p2),	107	ar9300_2p2_mac_core,
107	3);	108	ARRAY_SIZE(ar9300_2p2_mac_core), 2);
		109	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
		110	ar9300_2p2_mac_postamble,
		111	ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
		112
		113	/* bb */
		114	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
		115	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
		116	ar9300_2p2_baseband_core,
		117	ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
		118	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
		119	ar9300_2p2_baseband_postamble,
		120	ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
		121
		122	/* radio */
		123	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
		124	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
		125	ar9300_2p2_radio_core,
		126	ARRAY_SIZE(ar9300_2p2_radio_core), 2);
		127	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
		128	ar9300_2p2_radio_postamble,
		129	ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
		130
		131	/* soc */
		132	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
		133	ar9300_2p2_soc_preamble,
		134	ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
		135	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
		136	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
		137	ar9300_2p2_soc_postamble,
		138	ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
		139
		140	/* rx/tx gain */
		141	INIT_INI_ARRAY(&ah->iniModesRxGain,
		142	ar9300Common_rx_gain_table_2p2,
		143	ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
		144	INIT_INI_ARRAY(&ah->iniModesTxGain,
		145	ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
		146	ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
		147	5);
		148
		149	/* Load PCIE SERDES settings from INI */
		150
		151	/* Awake Setting */
		152
		153	INIT_INI_ARRAY(&ah->iniPcieSerdes,
		154	ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
		155	ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
		156	2);
		157
		158	/* Sleep Setting */
		159
		160	INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
		161	ar9300PciePhy_clkreq_enable_L1_2p2,
		162	ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
		163	2);
		164
		165	/* Fast clock modal settings */
		166	INIT_INI_ARRAY(&ah->iniModesAdditional,
		167	ar9300Modes_fast_clock_2p2,
		168	ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
		169	3);
		170	}
108	}	171	}
109		172
110	static void ar9003_tx_gain_table_apply(struct ath_hw *ah)	173	static void ar9003_tx_gain_table_apply(struct ath_hw *ah)