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authorFelix Fietkau <nbd@openwrt.org>2010-10-05 06:03:42 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-10-06 16:30:38 -0400
commit435c1610f46dc4d86a6633adb037b18109e6ffdc (patch)
tree1fed9f079db50cdd7305abe668848e53ef03223c /drivers/net/wireless/ath/ath9k/ani.c
parent9dbebc7fd07ab66341dce8d001272db400c11e03 (diff)
ath9k_hw: clean up register write buffering
Throughout the code, DISABLE_REGWRITE_BUFFER is always called right after REGWRITE_BUFFER_FLUSH. Since that's unlikely to change any time soon, that makes keeping those ops separate rather pointless, as it only increases code size and line number counts. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ani.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 3fba81e3a61f..a1894d240773 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -180,7 +180,6 @@ static void ath9k_ani_restart_old(struct ath_hw *ah)
180 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 180 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
181 181
182 REGWRITE_BUFFER_FLUSH(ah); 182 REGWRITE_BUFFER_FLUSH(ah);
183 DISABLE_REGWRITE_BUFFER(ah);
184 183
185 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 184 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
186 185
@@ -215,7 +214,6 @@ static void ath9k_ani_restart_new(struct ath_hw *ah)
215 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 214 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
216 215
217 REGWRITE_BUFFER_FLUSH(ah); 216 REGWRITE_BUFFER_FLUSH(ah);
218 DISABLE_REGWRITE_BUFFER(ah);
219 217
220 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 218 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
221 219
@@ -643,7 +641,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
643 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 641 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
644 642
645 REGWRITE_BUFFER_FLUSH(ah); 643 REGWRITE_BUFFER_FLUSH(ah);
646 DISABLE_REGWRITE_BUFFER(ah);
647} 644}
648 645
649/* 646/*
@@ -737,7 +734,6 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
737 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 734 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
738 735
739 REGWRITE_BUFFER_FLUSH(ah); 736 REGWRITE_BUFFER_FLUSH(ah);
740 DISABLE_REGWRITE_BUFFER(ah);
741} 737}
742 738
743static void ath9k_hw_ani_monitor_old(struct ath_hw *ah, 739static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
@@ -991,7 +987,6 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
991 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 987 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
992 988
993 REGWRITE_BUFFER_FLUSH(ah); 989 REGWRITE_BUFFER_FLUSH(ah);
994 DISABLE_REGWRITE_BUFFER(ah);
995} 990}
996 991
997/* Freeze the MIB counters, get the stats and then clear them */ 992/* Freeze the MIB counters, get the stats and then clear them */
@@ -1261,7 +1256,6 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
1261 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); 1256 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
1262 1257
1263 REGWRITE_BUFFER_FLUSH(ah); 1258 REGWRITE_BUFFER_FLUSH(ah);
1264 DISABLE_REGWRITE_BUFFER(ah);
1265 1259
1266 ath9k_enable_mib_counters(ah); 1260 ath9k_enable_mib_counters(ah);
1267 1261