diff options
author | Felix Fietkau <nbd@openwrt.org> | 2012-06-15 09:25:25 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2012-06-20 14:44:43 -0400 |
commit | 198823fd002a7f9784648c24c72b7e8c9e73fd14 (patch) | |
tree | d13b19b8f02e7c3872a10ed1c8eec13b8be4d571 /drivers/net/wireless/ath/ath9k/ani.c | |
parent | 465dce62cdb35f49bc0e859fb23787e1229b62a3 (diff) |
ath9k: remove MIB interrupt support
The new ANI implementation does not need it
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ani.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ani.c | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c index 7d5367676d4e..da73fa2a77d6 100644 --- a/drivers/net/wireless/ath/ath9k/ani.c +++ b/drivers/net/wireless/ath/ath9k/ani.c | |||
@@ -490,46 +490,6 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah) | |||
490 | } | 490 | } |
491 | EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); | 491 | EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); |
492 | 492 | ||
493 | /* | ||
494 | * Process a MIB interrupt. We may potentially be invoked because | ||
495 | * any of the MIB counters overflow/trigger so don't assume we're | ||
496 | * here because a PHY error counter triggered. | ||
497 | */ | ||
498 | void ath9k_hw_proc_mib_event(struct ath_hw *ah) | ||
499 | { | ||
500 | u32 phyCnt1, phyCnt2; | ||
501 | |||
502 | /* Reset these counters regardless */ | ||
503 | REG_WRITE(ah, AR_FILT_OFDM, 0); | ||
504 | REG_WRITE(ah, AR_FILT_CCK, 0); | ||
505 | if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) | ||
506 | REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); | ||
507 | |||
508 | /* Clear the mib counters and save them in the stats */ | ||
509 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); | ||
510 | |||
511 | if (!DO_ANI(ah)) { | ||
512 | /* | ||
513 | * We must always clear the interrupt cause by | ||
514 | * resetting the phy error regs. | ||
515 | */ | ||
516 | REG_WRITE(ah, AR_PHY_ERR_1, 0); | ||
517 | REG_WRITE(ah, AR_PHY_ERR_2, 0); | ||
518 | return; | ||
519 | } | ||
520 | |||
521 | /* NB: these are not reset-on-read */ | ||
522 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); | ||
523 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | ||
524 | if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || | ||
525 | ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { | ||
526 | |||
527 | /* NB: always restart to insure the h/w counters are reset */ | ||
528 | ath9k_ani_restart(ah); | ||
529 | } | ||
530 | } | ||
531 | EXPORT_SYMBOL(ath9k_hw_proc_mib_event); | ||
532 | |||
533 | void ath9k_hw_ani_setup(struct ath_hw *ah) | 493 | void ath9k_hw_ani_setup(struct ath_hw *ah) |
534 | { | 494 | { |
535 | int i; | 495 | int i; |