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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/tulip/de4x5.c
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/tulip/de4x5.c')
-rw-r--r--drivers/net/tulip/de4x5.c63
1 files changed, 32 insertions, 31 deletions
diff --git a/drivers/net/tulip/de4x5.c b/drivers/net/tulip/de4x5.c
index 75a64c88cf7a..efaa1d69b720 100644
--- a/drivers/net/tulip/de4x5.c
+++ b/drivers/net/tulip/de4x5.c
@@ -79,7 +79,7 @@
79 every usable DECchip board, I pinched Donald's 'next_module' field to 79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together. 80 link my modules together.
81 81
82 Upto 15 EISA cards can be supported under this driver, limited primarily 82 Up to 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of 83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a 84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ... 85 problem yet (provided you have at least depca.c v0.38) ...
@@ -517,7 +517,7 @@ struct mii_phy {
517 u_int mci; /* 21142 MII Connector Interrupt info */ 517 u_int mci; /* 21142 MII Connector Interrupt info */
518}; 518};
519 519
520#define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */ 520#define DE4X5_MAX_PHY 8 /* Allow up to 8 attached PHY devices per board */
521 521
522struct sia_phy { 522struct sia_phy {
523 u_char mc; /* Media Code */ 523 u_char mc; /* Media Code */
@@ -1436,7 +1436,7 @@ de4x5_sw_reset(struct net_device *dev)
1436 1436
1437 /* Poll for setup frame completion (adapter interrupts are disabled now) */ 1437 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1438 1438
1439 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */ 1439 for (j=0, i=0;(i<500) && (j==0);i++) { /* Up to 500ms delay */
1440 mdelay(1); 1440 mdelay(1);
1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1; 1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1442 } 1442 }
@@ -1448,7 +1448,7 @@ de4x5_sw_reset(struct net_device *dev)
1448 status = -EIO; 1448 status = -EIO;
1449 } 1449 }
1450 1450
1451 lp->tx_new = (++lp->tx_new) % lp->txRingSize; 1451 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1452 lp->tx_old = lp->tx_new; 1452 lp->tx_old = lp->tx_new;
1453 1453
1454 return status; 1454 return status;
@@ -1506,7 +1506,7 @@ de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1506 lp->stats.tx_bytes += skb->len; 1506 lp->stats.tx_bytes += skb->len;
1507 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */ 1507 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1508 1508
1509 lp->tx_new = (++lp->tx_new) % lp->txRingSize; 1509 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1510 1510
1511 if (TX_BUFFS_AVAIL) { 1511 if (TX_BUFFS_AVAIL) {
1512 netif_start_queue(dev); /* Another pkt may be queued */ 1512 netif_start_queue(dev); /* Another pkt may be queued */
@@ -1657,7 +1657,7 @@ de4x5_rx(struct net_device *dev)
1657 } 1657 }
1658 1658
1659 /* Change buffer ownership for this frame, back to the adapter */ 1659 /* Change buffer ownership for this frame, back to the adapter */
1660 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) { 1660 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1661 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN); 1661 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1662 barrier(); 1662 barrier();
1663 } 1663 }
@@ -1668,7 +1668,7 @@ de4x5_rx(struct net_device *dev)
1668 /* 1668 /*
1669 ** Update entry information 1669 ** Update entry information
1670 */ 1670 */
1671 lp->rx_new = (++lp->rx_new) % lp->rxRingSize; 1671 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1672 } 1672 }
1673 1673
1674 return 0; 1674 return 0;
@@ -1726,7 +1726,7 @@ de4x5_tx(struct net_device *dev)
1726 } 1726 }
1727 1727
1728 /* Update all the pointers */ 1728 /* Update all the pointers */
1729 lp->tx_old = (++lp->tx_old) % lp->txRingSize; 1729 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1730 } 1730 }
1731 1731
1732 /* Any resources available? */ 1732 /* Any resources available? */
@@ -1801,7 +1801,7 @@ de4x5_rx_ovfc(struct net_device *dev)
1801 1801
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) { 1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN); 1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (++lp->rx_new % lp->rxRingSize); 1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1805 } 1805 }
1806 1806
1807 outl(omr, DE4X5_OMR); 1807 outl(omr, DE4X5_OMR);
@@ -1932,7 +1932,7 @@ set_multicast_list(struct net_device *dev)
1932 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | 1932 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1933 SETUP_FRAME_LEN, (struct sk_buff *)1); 1933 SETUP_FRAME_LEN, (struct sk_buff *)1);
1934 1934
1935 lp->tx_new = (++lp->tx_new) % lp->txRingSize; 1935 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1936 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */ 1936 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1937 dev->trans_start = jiffies; /* prevent tx timeout */ 1937 dev->trans_start = jiffies; /* prevent tx timeout */
1938 } 1938 }
@@ -3119,7 +3119,7 @@ dc2114x_autoconf(struct net_device *dev)
3119 if (lp->media == _100Mb) { 3119 if (lp->media == _100Mb) {
3120 if ((slnk = test_for_100Mb(dev, 6500)) < 0) { 3120 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3121 lp->media = SPD_DET; 3121 lp->media = SPD_DET;
3122 return (slnk & ~TIMER_CB); 3122 return slnk & ~TIMER_CB;
3123 } 3123 }
3124 } else { 3124 } else {
3125 if (wait_for_link(dev) < 0) { 3125 if (wait_for_link(dev) < 0) {
@@ -3484,7 +3484,7 @@ is_spd_100(struct net_device *dev)
3484 spd = ((~gep_rd(dev)) & GEP_SLNK); 3484 spd = ((~gep_rd(dev)) & GEP_SLNK);
3485 } else { 3485 } else {
3486 if ((lp->ibn == 2) || !lp->asBitValid) 3486 if ((lp->ibn == 2) || !lp->asBitValid)
3487 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0); 3487 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3488 3488
3489 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) | 3489 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3490 (lp->linkOK & ~lp->asBitValid); 3490 (lp->linkOK & ~lp->asBitValid);
@@ -3502,15 +3502,15 @@ is_100_up(struct net_device *dev)
3502 if (lp->useMII) { 3502 if (lp->useMII) {
3503 /* Double read for sticky bits & temporary drops */ 3503 /* Double read for sticky bits & temporary drops */
3504 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); 3504 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3505 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS); 3505 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3506 } else if (!lp->useSROM) { /* de500-xa */ 3506 } else if (!lp->useSROM) { /* de500-xa */
3507 return ((~gep_rd(dev)) & GEP_SLNK); 3507 return (~gep_rd(dev)) & GEP_SLNK;
3508 } else { 3508 } else {
3509 if ((lp->ibn == 2) || !lp->asBitValid) 3509 if ((lp->ibn == 2) || !lp->asBitValid)
3510 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0); 3510 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3511 3511
3512 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | 3512 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3513 (lp->linkOK & ~lp->asBitValid)); 3513 (lp->linkOK & ~lp->asBitValid);
3514 } 3514 }
3515} 3515}
3516 3516
@@ -3523,17 +3523,17 @@ is_10_up(struct net_device *dev)
3523 if (lp->useMII) { 3523 if (lp->useMII) {
3524 /* Double read for sticky bits & temporary drops */ 3524 /* Double read for sticky bits & temporary drops */
3525 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); 3525 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3526 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS); 3526 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3527 } else if (!lp->useSROM) { /* de500-xa */ 3527 } else if (!lp->useSROM) { /* de500-xa */
3528 return ((~gep_rd(dev)) & GEP_LNP); 3528 return (~gep_rd(dev)) & GEP_LNP;
3529 } else { 3529 } else {
3530 if ((lp->ibn == 2) || !lp->asBitValid) 3530 if ((lp->ibn == 2) || !lp->asBitValid)
3531 return (((lp->chipset & ~0x00ff) == DC2114x) ? 3531 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3532 (~inl(DE4X5_SISR)&SISR_LS10): 3532 (~inl(DE4X5_SISR)&SISR_LS10):
3533 0); 3533 0;
3534 3534
3535 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | 3535 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3536 (lp->linkOK & ~lp->asBitValid)); 3536 (lp->linkOK & ~lp->asBitValid);
3537 } 3537 }
3538} 3538}
3539 3539
@@ -3544,7 +3544,7 @@ is_anc_capable(struct net_device *dev)
3544 u_long iobase = dev->base_addr; 3544 u_long iobase = dev->base_addr;
3545 3545
3546 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { 3546 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3547 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII)); 3547 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3548 } else if ((lp->chipset & ~0x00ff) == DC2114x) { 3548 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3549 return (inl(DE4X5_SISR) & SISR_LPN) >> 12; 3549 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3550 } else { 3550 } else {
@@ -3568,7 +3568,7 @@ ping_media(struct net_device *dev, int msec)
3568 3568
3569 lp->tmp = lp->tx_new; /* Remember the ring position */ 3569 lp->tmp = lp->tx_new; /* Remember the ring position */
3570 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1); 3570 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3571 lp->tx_new = (++lp->tx_new) % lp->txRingSize; 3571 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3572 outl(POLL_DEMAND, DE4X5_TPD); 3572 outl(POLL_DEMAND, DE4X5_TPD);
3573 } 3573 }
3574 3574
@@ -4930,7 +4930,7 @@ getfrom_mii(u32 command, u_long ioaddr)
4930 outl(command | MII_MDC, ioaddr); 4930 outl(command | MII_MDC, ioaddr);
4931 udelay(1); 4931 udelay(1);
4932 4932
4933 return ((inl(ioaddr) >> 19) & 1); 4933 return (inl(ioaddr) >> 19) & 1;
4934} 4934}
4935 4935
4936/* 4936/*
@@ -4975,8 +4975,8 @@ mii_get_oui(u_char phyaddr, u_long ioaddr)
4975 a.breg[0]=a.breg[1]; 4975 a.breg[0]=a.breg[1];
4976 a.breg[1]=i; 4976 a.breg[1]=i;
4977 4977
4978 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */ 4978 return (a.reg<<8)|ret; */ /* SEEQ and Cypress way */
4979/* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */ 4979/* return (r2<<6)|(u_int)(r3>>10); */ /* NATIONAL and BROADCOM way */
4980 return r2; /* (I did it) My way */ 4980 return r2; /* (I did it) My way */
4981} 4981}
4982 4982
@@ -5144,7 +5144,7 @@ gep_rd(struct net_device *dev)
5144 if (lp->chipset == DC21140) { 5144 if (lp->chipset == DC21140) {
5145 return inl(DE4X5_GEP); 5145 return inl(DE4X5_GEP);
5146 } else if ((lp->chipset & ~0x00ff) == DC2114x) { 5146 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5147 return (inl(DE4X5_SIGR) & 0x000fffff); 5147 return inl(DE4X5_SIGR) & 0x000fffff;
5148 } 5148 }
5149 5149
5150 return 0; 5150 return 0;
@@ -5417,7 +5417,7 @@ de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5417 /* Set up the descriptor and give ownership to the card */ 5417 /* Set up the descriptor and give ownership to the card */
5418 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | 5418 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5419 SETUP_FRAME_LEN, (struct sk_buff *)1); 5419 SETUP_FRAME_LEN, (struct sk_buff *)1);
5420 lp->tx_new = (++lp->tx_new) % lp->txRingSize; 5420 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5421 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */ 5421 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5422 netif_wake_queue(dev); /* Unlock the TX ring */ 5422 netif_wake_queue(dev); /* Unlock the TX ring */
5423 break; 5423 break;
@@ -5474,7 +5474,8 @@ de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5474 tmp.lval[6] = inl(DE4X5_STRR); j+=4; 5474 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5475 tmp.lval[7] = inl(DE4X5_SIGR); j+=4; 5475 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5476 ioc->len = j; 5476 ioc->len = j;
5477 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; 5477 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5478 return -EFAULT;
5478 break; 5479 break;
5479 5480
5480#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */ 5481#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */