Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 269 insertions, 119 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index be7ff138a7f9..5b3d2f34da7a 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -4,7 +4,7 @@
  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
  * Copyright (C) 2004 Sun Microsystems Inc.
- * Copyright (C) 2007-2010 Broadcom Corporation.
+ * Copyright (C) 2007-2011 Broadcom Corporation.
  */
 
 #ifndef _T3_H
@@ -23,10 +23,13 @@
 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
 #define TG3_BDINFO_SIZE                 0x10UL
 
-#define TG3_RX_INTERNAL_RING_SZ_5906    32
-
-#define RX_STD_MAX_SIZE_5705            512
-#define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
+#define TG3_RX_STD_MAX_SIZE_5700        512
+#define TG3_RX_STD_MAX_SIZE_5717        2048
+#define TG3_RX_JMB_MAX_SIZE_5700        256
+#define TG3_RX_JMB_MAX_SIZE_5717        1024
+#define TG3_RX_RET_MAX_SIZE_5700        1024
+#define TG3_RX_RET_MAX_SIZE_5705        512
+#define TG3_RX_RET_MAX_SIZE_5717        4096
 
 /* First 256 bytes are a mirror of PCI config space. */
 #define TG3PCI_VENDOR                   0x00000000
@@ -46,7 +49,6 @@
 #define  TG3PCI_DEVICE_TIGON3_5785_F     0x16a0 /* 10/100 only */
 #define  TG3PCI_DEVICE_TIGON3_5717       0x1655
 #define  TG3PCI_DEVICE_TIGON3_5718       0x1656
-#define  TG3PCI_DEVICE_TIGON3_5724       0x165c
 #define  TG3PCI_DEVICE_TIGON3_57781      0x16b1
 #define  TG3PCI_DEVICE_TIGON3_57785      0x16b5
 #define  TG3PCI_DEVICE_TIGON3_57761      0x16b0
@@ -54,6 +56,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
 #define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
 #define  TG3PCI_DEVICE_TIGON3_5719       0x1657
+#define  TG3PCI_DEVICE_TIGON3_5720       0x165f
 /* 0x04 --> 0x2c unused */
 #define TG3PCI_SUBVENDOR_ID_BROADCOM            PCI_VENDOR_ID_BROADCOM
 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6    0x1644
@@ -141,6 +144,8 @@
 #define  CHIPREV_ID_57780_A1             0x57780001
 #define  CHIPREV_ID_5717_A0              0x05717000
 #define  CHIPREV_ID_57765_A0             0x57785000
+#define  CHIPREV_ID_5719_A0              0x05719000
+#define  CHIPREV_ID_5720_A0              0x05720000
 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                  0x07
 #define   ASIC_REV_5701                  0x00
@@ -162,6 +167,7 @@
 #define   ASIC_REV_5717                  0x5717
 #define   ASIC_REV_57765                 0x57785
 #define   ASIC_REV_5719                  0x5719
+#define   ASIC_REV_5720                  0x5720
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -174,6 +180,7 @@
 #define   CHIPREV_5750_BX                0x41
 #define   CHIPREV_5784_AX                0x57840
 #define   CHIPREV_5761_AX                0x57610
+#define   CHIPREV_57765_AX               0x577650
 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                   0x00
 #define   METAL_REV_A1                   0x01
@@ -182,6 +189,7 @@
 #define   METAL_REV_B2                   0x02
 #define TG3PCI_DMA_RW_CTRL              0x0000006c
 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
+#define  DMA_RWCTRL_TAGGED_STAT_WA       0x00000080
 #define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
@@ -472,6 +480,8 @@
 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
 #define  TX_MODE_MBUF_LOCKUP_FIX         0x00000100
+#define  TX_MODE_JMB_FRM_LEN             0x00400000
+#define  TX_MODE_CNT_DN_MODE             0x00800000
 #define MAC_TX_STATUS                   0x00000460
 #define  TX_STATUS_XOFFED                0x00000001
 #define  TX_STATUS_SENT_XOFF             0x00000002
@@ -486,6 +496,8 @@
 #define  TX_LENGTHS_IPG_SHIFT            8
 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
+#define  TX_LENGTHS_JMB_FRM_LEN_MSK      0x00ff0000
+#define  TX_LENGTHS_CNT_DWN_VAL_MSK      0xff000000
 #define MAC_RX_MODE                     0x00000468
 #define  RX_MODE_RESET                   0x00000001
 #define  RX_MODE_ENABLE                  0x00000002
@@ -973,6 +985,7 @@
 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
+#define  RCVDBDI_MODE_LRG_RING_SZ        0x00010000
 #define RCVDBDI_STATUS                  0x00002404
 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
@@ -1077,6 +1090,9 @@
 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
 /* 0x3620 --> 0x3630 unused */
 
+#define TG3_CPMU_CLCK_ORIDE             0x00003624
+#define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN    0x80000000
+
 #define TG3_CPMU_CLCK_STAT              0x00003630
 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
@@ -1090,7 +1106,32 @@
 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
 #define TG3_CPMU_PHY_STRAP              0x00003664
 #define TG3_CPMU_PHY_STRAP_IS_SERDES     0x00000020
-/* 0x3664 --> 0x3800 unused */
+/* 0x3664 --> 0x36b0 unused */
+
+#define TG3_CPMU_EEE_MODE               0x000036b0
+#define  TG3_CPMU_EEEMD_APE_TX_DET_EN    0x00000004
+#define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET  0x00000008
+#define  TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040
+#define  TG3_CPMU_EEEMD_LPI_ENABLE       0x00000080
+#define  TG3_CPMU_EEEMD_LPI_IN_TX        0x00000100
+#define  TG3_CPMU_EEEMD_LPI_IN_RX        0x00000200
+#define  TG3_CPMU_EEEMD_EEE_ENABLE       0x00100000
+#define TG3_CPMU_EEE_DBTMR1             0x000036b4
+#define  TG3_CPMU_DBTMR1_PCIEXIT_2047US  0x07ff0000
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US  0x000070ff
+#define TG3_CPMU_EEE_DBTMR2             0x000036b8
+#define  TG3_CPMU_DBTMR2_APE_TX_2047US   0x07ff0000
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US  0x000070ff
+#define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
+#define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
+#define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004
+/* 0x36c0 --> 0x36d0 unused */
+
+#define TG3_CPMU_EEE_CTRL               0x000036d0
+#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d
+#define TG3_CPMU_EEE_CTRL_EXIT_36_US     0x00000384
+#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8
+/* 0x36d4 --> 0x3800 unused */
 
 /* Mbuf cluster free registers */
 #define MBFREE_MODE                     0x00003800
@@ -1161,6 +1202,7 @@
 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
 #define HOSTCC_FLOW_ATTN                0x00003c48
+#define HOSTCC_FLOW_ATTN_MBUF_LWM        0x00000040
 /* 0x3c4c --> 0x3c50 unused */
 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
 #define HOSTCC_STD_CON_IDX              0x00003c54
@@ -1225,6 +1267,7 @@
 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
 #define  BUFMGR_MODE_BM_TEST             0x00000008
 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
+#define  BUFMGR_MODE_NO_TX_UNDERRUN      0x80000000
 #define BUFMGR_STATUS                   0x00004404
 #define  BUFMGR_STATUS_ERROR             0x00000004
 #define  BUFMGR_STATUS_MBLOW             0x00000010
@@ -1293,6 +1336,7 @@
 #define  RDMAC_MODE_MULT_DMA_RD_DIS      0x01000000
 #define  RDMAC_MODE_IPV4_LSO_EN          0x08000000
 #define  RDMAC_MODE_IPV6_LSO_EN          0x10000000
+#define  RDMAC_MODE_H2BNC_VLAN_DET       0x20000000
 #define RDMAC_STATUS                    0x00004804
 #define  RDMAC_STATUS_TGTABORT           0x00000004
 #define  RDMAC_STATUS_MSTABORT           0x00000008
@@ -1302,7 +1346,22 @@
 #define  RDMAC_STATUS_FIFOURUN           0x00000080
 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
 #define  RDMAC_STATUS_LNGREAD            0x00000200
-/* 0x4808 --> 0x4c00 unused */
+/* 0x4808 --> 0x4900 unused */
+
+#define TG3_RDMA_RSRVCTRL_REG           0x00004900
+#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX  0x00000004
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K  0x00000c00
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK  0x00000ff0
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K  0x000c0000
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK  0x000ff000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_320B    0x28000000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK    0xffe00000
+/* 0x4904 --> 0x4910 unused */
+
+#define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
+#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
+#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
+/* 0x4914 --> 0x4c00 unused */
 
 /* Write DMA control registers */
 #define WDMAC_MODE                      0x00004c00
@@ -1554,6 +1613,7 @@
 #define  MSGINT_MODE_ONE_SHOT_DISABLE    0x00000020
 #define  MSGINT_MODE_MULTIVEC_EN         0x00000080
 #define MSGINT_STATUS                   0x00006004
+#define  MSGINT_STATUS_MSI_REQ           0x00000001
 #define MSGINT_FIFO                     0x00006008
 /* 0x600c --> 0x6400 unused */
 
@@ -1570,6 +1630,8 @@
 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
 #define  GRC_MODE_BSWAP_DATA            0x00000010
 #define  GRC_MODE_WSWAP_DATA            0x00000020
+#define  GRC_MODE_BYTE_SWAP_B2HRX_DATA  0x00000040
+#define  GRC_MODE_WORD_SWAP_B2HRX_DATA  0x00000080
 #define  GRC_MODE_SPLITHDR              0x00000100
 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
 #define  GRC_MODE_INCL_CRC              0x00000400
@@ -1577,8 +1639,10 @@
 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
+#define  GRC_MODE_B2HRX_ENABLE          0x00008000
 #define  GRC_MODE_HOST_STACKUP          0x00010000
 #define  GRC_MODE_HOST_SENDBDS          0x00020000
+#define  GRC_MODE_HTX2B_ENABLE          0x00040000
 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
 #define  GRC_MODE_PCIE_TL_SEL           0x00000000
@@ -1775,6 +1839,38 @@
 #define  FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
 #define  FLASH_5717VENDOR_ST_25USPT      0x03400002
 #define  FLASH_5717VENDOR_ST_45USPT      0x03400001
+#define  FLASH_5720_EEPROM_HD            0x00000001
+#define  FLASH_5720_EEPROM_LD            0x00000003
+#define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
+#define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
+#define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
+#define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
+#define  FLASH_5720VENDOR_M_ST_M25PE10   0x02000000
+#define  FLASH_5720VENDOR_M_ST_M25PE20   0x02000002
+#define  FLASH_5720VENDOR_M_ST_M25PE40   0x02000001
+#define  FLASH_5720VENDOR_M_ST_M25PE80   0x02000003
+#define  FLASH_5720VENDOR_M_ST_M45PE10   0x03000000
+#define  FLASH_5720VENDOR_M_ST_M45PE20   0x03000002
+#define  FLASH_5720VENDOR_M_ST_M45PE40   0x03000001
+#define  FLASH_5720VENDOR_M_ST_M45PE80   0x03000003
+#define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
+#define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
+#define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
+#define  FLASH_5720VENDOR_A_ST_M25PE10   0x02800000
+#define  FLASH_5720VENDOR_A_ST_M25PE20   0x02800002
+#define  FLASH_5720VENDOR_A_ST_M25PE40   0x02800001
+#define  FLASH_5720VENDOR_A_ST_M25PE80   0x02800003
+#define  FLASH_5720VENDOR_A_ST_M45PE10   0x02c00000
+#define  FLASH_5720VENDOR_A_ST_M45PE20   0x02c00002
+#define  FLASH_5720VENDOR_A_ST_M45PE40   0x02c00001
+#define  FLASH_5720VENDOR_A_ST_M45PE80   0x02c00003
+#define  FLASH_5720VENDOR_ATMEL_45USPT   0x03c00000
+#define  FLASH_5720VENDOR_ST_25USPT      0x03c00002
+#define  FLASH_5720VENDOR_ST_45USPT      0x03c00001
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
 #define  FLASH_5752PAGE_SIZE_256         0x00000000
 #define  FLASH_5752PAGE_SIZE_512         0x10000000
@@ -1856,11 +1952,16 @@
 
 /* Alternate PCIE definitions */
 #define TG3_PCIE_TLDLPL_PORT            0x00007c00
+#define TG3_PCIE_DL_LO_FTSMAX           0x0000000c
+#define TG3_PCIE_DL_LO_FTSMAX_MSK       0x000000ff
+#define TG3_PCIE_DL_LO_FTSMAX_VAL       0x0000002c
 #define TG3_PCIE_PL_LO_PHYCTL1           0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN         0x00001000
 #define TG3_PCIE_PL_LO_PHYCTL5           0x00000014
 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ       0x80000000
 
+#define TG3_REG_BLK_SIZE                0x00008000
+
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK             0x000000e0
 #define TG3_OTP_AGCTGT_SHIFT            1
@@ -1904,6 +2005,7 @@
 #define TG3_EEPROM_SB_REVISION_3        0x00030000
 #define TG3_EEPROM_SB_REVISION_4        0x00040000
 #define TG3_EEPROM_SB_REVISION_5        0x00050000
+#define TG3_EEPROM_SB_REVISION_6        0x00060000
 #define TG3_EEPROM_MAGIC_HW             0xabcd
 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
 
@@ -1911,7 +2013,9 @@
 #define TG3_NVM_DIR_END                 0x78
 #define TG3_NVM_DIRENT_SIZE             0xc
 #define TG3_NVM_DIRTYPE_SHIFT           24
+#define TG3_NVM_DIRTYPE_LENMSK          0x003fffff
 #define TG3_NVM_DIRTYPE_ASFINI          1
+#define TG3_NVM_DIRTYPE_EXTVPD          20
 #define TG3_NVM_PTREV_BCVER             0x94
 #define TG3_NVM_BCVER_MAJMSK            0x0000ff00
 #define TG3_NVM_BCVER_MAJSFT            8
@@ -1923,6 +2027,7 @@
 #define TG3_EEPROM_SB_F1R3_EDH_OFF      0x18
 #define TG3_EEPROM_SB_F1R4_EDH_OFF      0x1c
 #define TG3_EEPROM_SB_F1R5_EDH_OFF      0x20
+#define TG3_EEPROM_SB_F1R6_EDH_OFF      0x4c
 #define TG3_EEPROM_SB_EDH_MAJ_MASK      0x00000700
 #define TG3_EEPROM_SB_EDH_MAJ_SHFT      8
 #define TG3_EEPROM_SB_EDH_MIN_MASK      0x000000ff
@@ -2034,6 +2139,13 @@
 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
 
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700       128
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755       64
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906       32
+
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700       64
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717       16
+
 
 /* Currently this is fixed. */
 #define TG3_PHY_MII_ADDR                0x01
@@ -2048,6 +2160,10 @@
 #define  MII_TG3_CTRL_AS_MASTER         0x0800
 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
 
+#define MII_TG3_MMD_CTRL                0x0d /* MMD Access Control register */
+#define MII_TG3_MMD_CTRL_DATA_NOINC     0x4000
+#define MII_TG3_MMD_ADDRESS             0x0e /* MMD Address Data register */
+
 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
@@ -2064,7 +2180,13 @@
 
 #define MII_TG3_DSP_TAP1                0x0001
 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
+#define MII_TG3_DSP_TAP26               0x001a
+#define  MII_TG3_DSP_TAP26_ALNOKO       0x0001
+#define  MII_TG3_DSP_TAP26_RMRXSTO      0x0002
+#define  MII_TG3_DSP_TAP26_OPCSINPT     0x0004
 #define MII_TG3_DSP_AADJ1CH0            0x001f
+#define MII_TG3_DSP_CH34TP2             0x4022
+#define MII_TG3_DSP_CH34TP2_HIBW01      0x017b
 #define MII_TG3_DSP_AADJ1CH3            0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
@@ -2075,23 +2197,30 @@
 #define MII_TG3_DSP_EXP96               0x0f96
 #define MII_TG3_DSP_EXP97               0x0f97
 
-#define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
+#define MII_TG3_AUX_CTRL                0x18 /* auxiliary control register */
 
+#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
+#define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
+#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
+#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN   0x4000
+
+#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
+#define MII_TG3_AUXCTL_PCTL_WOL_EN      0x0008
 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
+#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
 #define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
-#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
 
-#define MII_TG3_AUXCTL_MISC_WREN        0x8000
-#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
-#define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
+#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
+
 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
+#define MII_TG3_AUXCTL_MISC_WIRESPD_EN  0x0010
+#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
+#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
+#define MII_TG3_AUXCTL_MISC_WREN        0x8000
 
-#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
-#define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
-#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
 
-#define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
+#define MII_TG3_AUX_STAT                0x19 /* auxiliary status register */
 #define MII_TG3_AUX_STAT_LPASS          0x0004
 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
 #define MII_TG3_AUX_STAT_10HALF         0x0100
@@ -2131,6 +2260,11 @@
 #define MII_TG3_TEST1_TRIM_EN           0x0010
 #define MII_TG3_TEST1_CRC_EN            0x8000
 
+/* Clause 45 expansion registers */
+#define TG3_CL45_D7_EEERES_STAT         0x803e
+#define TG3_CL45_D7_EEERES_STAT_LP_100TX        0x0002
+#define TG3_CL45_D7_EEERES_STAT_LP_1000T        0x0004
+
 
 /* Fast Ethernet Tranceiver definitions */
 #define MII_TG3_FET_PTEST               0x17
@@ -2176,7 +2310,7 @@
 #define TG3_APE_HOST_SEG_SIG            0x4200
 #define  APE_HOST_SEG_SIG_MAGIC          0x484f5354
 #define TG3_APE_HOST_SEG_LEN            0x4204
-#define  APE_HOST_SEG_LEN_MAGIC          0x0000001c
+#define  APE_HOST_SEG_LEN_MAGIC          0x00000020
 #define TG3_APE_HOST_INIT_COUNT         0x4208
 #define TG3_APE_HOST_DRIVER_ID          0x420c
 #define  APE_HOST_DRIVER_ID_LINUX        0xf0000000
@@ -2188,6 +2322,12 @@
 #define  APE_HOST_HEARTBEAT_INT_DISABLE  0
 #define  APE_HOST_HEARTBEAT_INT_5SEC     5000
 #define TG3_APE_HOST_HEARTBEAT_COUNT    0x4218
+#define TG3_APE_HOST_DRVR_STATE         0x421c
+#define TG3_APE_HOST_DRVR_STATE_START    0x00000001
+#define TG3_APE_HOST_DRVR_STATE_UNLOAD   0x00000002
+#define TG3_APE_HOST_DRVR_STATE_WOL      0x00000003
+#define TG3_APE_HOST_WOL_SPEED          0x4224
+#define TG3_APE_HOST_WOL_SPEED_AUTO      0x00008000
 
 #define TG3_APE_EVENT_STATUS            0x4300
 
@@ -2498,7 +2638,12 @@ struct tg3_hw_stats {
         tg3_stat64_t                    nic_avoided_irqs;
         tg3_stat64_t                    nic_tx_threshold_hit;
 
-        u8                              __reserved4[0xb00-0x9c0];
+        /* NOT a part of the hardware statistics block format.
+         * These stats are here as storage for tg3_periodic_fetch_stats().
+         */
+        tg3_stat64_t                    mbuf_lwm_thresh_hit;
+
+        u8                              __reserved4[0xb00-0x9c8];
 };
 
 /* 'mapping' is superfluous as the chip does not write into
@@ -2510,10 +2655,6 @@ struct ring_info {
         DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
-struct tg3_config_info {
-        u32                             flags;
-};
-
 struct tg3_link_config {
         /* Describes what we're trying to get. */
         u32                             advertising;
@@ -2634,6 +2775,8 @@ struct tg3_ethtool_stats {
         u64             nic_irqs;
         u64             nic_avoided_irqs;
         u64             nic_tx_threshold_hit;
+
+        u64             mbuf_lwm_thresh_hit;
 };
 
 struct tg3_rx_prodring_set {
@@ -2649,7 +2792,8 @@ struct tg3_rx_prodring_set {
         dma_addr_t                      rx_jmb_mapping;
 };
 
-#define TG3_IRQ_MAX_VECS 5
+#define TG3_IRQ_MAX_VECS_RSS            5
+#define TG3_IRQ_MAX_VECS                TG3_IRQ_MAX_VECS_RSS
 
 struct tg3_napi {
         struct napi_struct              napi    ____cacheline_aligned;
@@ -2660,17 +2804,17 @@ struct tg3_napi {
         u32                             last_irq_tag;
         u32                             int_mbox;
         u32                             coal_now;
-        u32                             tx_prod;
-        u32                             tx_cons;
-        u32                             tx_pending;
-        u32                             prodmbox;
 
-        u32                             consmbox;
+        u32                             consmbox ____cacheline_aligned;
         u32                             rx_rcb_ptr;
         u16                             *rx_rcb_prod_idx;
-        struct tg3_rx_prodring_set      *prodring;
-
+        struct tg3_rx_prodring_set      prodring;
         struct tg3_rx_buffer_desc       *rx_rcb;
+
+        u32                             tx_prod ____cacheline_aligned;
+        u32                             tx_cons;
+        u32                             tx_pending;
+        u32                             prodmbox;
         struct tg3_tx_buffer_desc       *tx_ring;
         struct ring_info                *tx_buffers;
 
@@ -2682,6 +2826,86 @@ struct tg3_napi {
         unsigned int                    irq_vec;
 };
 
+enum TG3_FLAGS {
+        TG3_FLAG_TAGGED_STATUS = 0,
+        TG3_FLAG_TXD_MBOX_HWBUG,
+        TG3_FLAG_USE_LINKCHG_REG,
+        TG3_FLAG_ERROR_PROCESSED,
+        TG3_FLAG_ENABLE_ASF,
+        TG3_FLAG_ASPM_WORKAROUND,
+        TG3_FLAG_POLL_SERDES,
+        TG3_FLAG_MBOX_WRITE_REORDER,
+        TG3_FLAG_PCIX_TARGET_HWBUG,
+        TG3_FLAG_WOL_SPEED_100MB,
+        TG3_FLAG_WOL_ENABLE,
+        TG3_FLAG_EEPROM_WRITE_PROT,
+        TG3_FLAG_NVRAM,
+        TG3_FLAG_NVRAM_BUFFERED,
+        TG3_FLAG_SUPPORT_MSI,
+        TG3_FLAG_SUPPORT_MSIX,
+        TG3_FLAG_PCIX_MODE,
+        TG3_FLAG_PCI_HIGH_SPEED,
+        TG3_FLAG_PCI_32BIT,
+        TG3_FLAG_SRAM_USE_CONFIG,
+        TG3_FLAG_TX_RECOVERY_PENDING,
+        TG3_FLAG_WOL_CAP,
+        TG3_FLAG_JUMBO_RING_ENABLE,
+        TG3_FLAG_PAUSE_AUTONEG,
+        TG3_FLAG_CPMU_PRESENT,
+        TG3_FLAG_40BIT_DMA_BUG,
+        TG3_FLAG_BROKEN_CHECKSUMS,
+        TG3_FLAG_JUMBO_CAPABLE,
+        TG3_FLAG_CHIP_RESETTING,
+        TG3_FLAG_INIT_COMPLETE,
+        TG3_FLAG_RESTART_TIMER,
+        TG3_FLAG_TSO_BUG,
+        TG3_FLAG_IS_5788,
+        TG3_FLAG_MAX_RXPEND_64,
+        TG3_FLAG_TSO_CAPABLE,
+        TG3_FLAG_PCI_EXPRESS,
+        TG3_FLAG_ASF_NEW_HANDSHAKE,
+        TG3_FLAG_HW_AUTONEG,
+        TG3_FLAG_IS_NIC,
+        TG3_FLAG_FLASH,
+        TG3_FLAG_HW_TSO_1,
+        TG3_FLAG_5705_PLUS,
+        TG3_FLAG_5750_PLUS,
+        TG3_FLAG_HW_TSO_3,
+        TG3_FLAG_USING_MSI,
+        TG3_FLAG_USING_MSIX,
+        TG3_FLAG_ICH_WORKAROUND,
+        TG3_FLAG_5780_CLASS,
+        TG3_FLAG_HW_TSO_2,
+        TG3_FLAG_1SHOT_MSI,
+        TG3_FLAG_NO_FWARE_REPORTED,
+        TG3_FLAG_NO_NVRAM_ADDR_TRANS,
+        TG3_FLAG_ENABLE_APE,
+        TG3_FLAG_PROTECTED_NVRAM,
+        TG3_FLAG_5701_DMA_BUG,
+        TG3_FLAG_USE_PHYLIB,
+        TG3_FLAG_MDIOBUS_INITED,
+        TG3_FLAG_LRG_PROD_RING_CAP,
+        TG3_FLAG_RGMII_INBAND_DISABLE,
+        TG3_FLAG_RGMII_EXT_IBND_RX_EN,
+        TG3_FLAG_RGMII_EXT_IBND_TX_EN,
+        TG3_FLAG_CLKREQ_BUG,
+        TG3_FLAG_5755_PLUS,
+        TG3_FLAG_NO_NVRAM,
+        TG3_FLAG_ENABLE_RSS,
+        TG3_FLAG_ENABLE_TSS,
+        TG3_FLAG_4G_DMA_BNDRY_BUG,
+        TG3_FLAG_40BIT_DMA_LIMIT_BUG,
+        TG3_FLAG_SHORT_DMA_BUG,
+        TG3_FLAG_USE_JUMBO_BDFLAG,
+        TG3_FLAG_L1PLLPD_EN,
+        TG3_FLAG_57765_PLUS,
+        TG3_FLAG_APE_HAS_NCSI,
+        TG3_FLAG_5717_PLUS,
+
+        /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
+        TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
+};
+
 struct tg3 {
         /* begin "general, frequently-used members" cacheline section */
 
@@ -2705,7 +2929,7 @@ struct tg3 {
         /* SMP locking strategy:
          *
          * lock: Held during reset, PHY access, timer, and when
-         *       updating tg3_flags and tg3_flags2.
+         *       updating tg3_flags.
          *
          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
          *                netif_tx_lock when it needs to call
@@ -2746,16 +2970,14 @@ struct tg3 {
         void                            (*write32_rx_mbox) (struct tg3 *, u32,
                                                             u32);
         u32                             rx_copy_thresh;
+        u32                             rx_std_ring_mask;
+        u32                             rx_jmb_ring_mask;
+        u32                             rx_ret_ring_mask;
         u32                             rx_pending;
         u32                             rx_jumbo_pending;
         u32                             rx_std_max_post;
         u32                             rx_offset;
         u32                             rx_pkt_map_sz;
-#if TG3_VLAN_TAG_USED
-        struct vlan_group               *vlgrp;
-#endif
-
-        struct tg3_rx_prodring_set      prodring[TG3_IRQ_MAX_VECS];
 
 
         /* begin "everything else" cacheline(s) section */
@@ -2764,93 +2986,13 @@ struct tg3 {
         struct tg3_ethtool_stats        estats;
         struct tg3_ethtool_stats        estats_prev;
 
+        DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
+
         union {
         unsigned long                   phy_crc_errors;
         unsigned long                   last_event_jiffies;
         };
 
-        u32                             tg3_flags;
-#define TG3_FLAG_TAGGED_STATUS          0x00000001
-#define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
-#define TG3_FLAG_RX_CHECKSUMS           0x00000004
-#define TG3_FLAG_USE_LINKCHG_REG        0x00000008
-#define TG3_FLAG_ENABLE_ASF             0x00000020
-#define TG3_FLAG_ASPM_WORKAROUND        0x00000040
-#define TG3_FLAG_POLL_SERDES            0x00000080
-#define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
-#define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
-#define TG3_FLAG_WOL_SPEED_100MB        0x00000400
-#define TG3_FLAG_WOL_ENABLE             0x00000800
-#define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
-#define TG3_FLAG_NVRAM                  0x00002000
-#define TG3_FLAG_NVRAM_BUFFERED         0x00004000
-#define TG3_FLAG_SUPPORT_MSI            0x00008000
-#define TG3_FLAG_SUPPORT_MSIX           0x00010000
-#define TG3_FLAG_SUPPORT_MSI_OR_MSIX    (TG3_FLAG_SUPPORT_MSI | \
-                                         TG3_FLAG_SUPPORT_MSIX)
-#define TG3_FLAG_PCIX_MODE              0x00020000
-#define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
-#define TG3_FLAG_PCI_32BIT              0x00080000
-#define TG3_FLAG_SRAM_USE_CONFIG        0x00100000
-#define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
-#define TG3_FLAG_WOL_CAP                0x00400000
-#define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
-#define TG3_FLAG_PAUSE_AUTONEG          0x02000000
-#define TG3_FLAG_CPMU_PRESENT           0x04000000
-#define TG3_FLAG_40BIT_DMA_BUG          0x08000000
-#define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
-#define TG3_FLAG_JUMBO_CAPABLE          0x20000000
-#define TG3_FLAG_CHIP_RESETTING         0x40000000
-#define TG3_FLAG_INIT_COMPLETE          0x80000000
-        u32                             tg3_flags2;
-#define TG3_FLG2_RESTART_TIMER          0x00000001
-#define TG3_FLG2_TSO_BUG                0x00000002
-#define TG3_FLG2_IS_5788                0x00000008
-#define TG3_FLG2_MAX_RXPEND_64          0x00000010
-#define TG3_FLG2_TSO_CAPABLE            0x00000020
-#define TG3_FLG2_PCI_EXPRESS            0x00000200
-#define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
-#define TG3_FLG2_HW_AUTONEG             0x00000800
-#define TG3_FLG2_IS_NIC                 0x00001000
-#define TG3_FLG2_FLASH                  0x00008000
-#define TG3_FLG2_HW_TSO_1               0x00010000
-#define TG3_FLG2_5705_PLUS              0x00040000
-#define TG3_FLG2_5750_PLUS              0x00080000
-#define TG3_FLG2_HW_TSO_3               0x00100000
-#define TG3_FLG2_USING_MSI              0x00200000
-#define TG3_FLG2_USING_MSIX             0x00400000
-#define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
-                                        TG3_FLG2_USING_MSIX)
-#define TG3_FLG2_ICH_WORKAROUND         0x02000000
-#define TG3_FLG2_5780_CLASS             0x04000000
-#define TG3_FLG2_HW_TSO_2               0x08000000
-#define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | \
-                                         TG3_FLG2_HW_TSO_2 | \
-                                         TG3_FLG2_HW_TSO_3)
-#define TG3_FLG2_1SHOT_MSI              0x10000000
-#define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
-        u32                             tg3_flags3;
-#define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
-#define TG3_FLG3_ENABLE_APE             0x00000002
-#define TG3_FLG3_PROTECTED_NVRAM        0x00000004
-#define TG3_FLG3_5701_DMA_BUG           0x00000008
-#define TG3_FLG3_USE_PHYLIB             0x00000010
-#define TG3_FLG3_MDIOBUS_INITED         0x00000020
-#define TG3_FLG3_RGMII_INBAND_DISABLE   0x00000100
-#define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
-#define TG3_FLG3_RGMII_EXT_IBND_TX_EN   0x00000400
-#define TG3_FLG3_CLKREQ_BUG             0x00000800
-#define TG3_FLG3_5755_PLUS              0x00002000
-#define TG3_FLG3_NO_NVRAM               0x00004000
-#define TG3_FLG3_ENABLE_RSS             0x00020000
-#define TG3_FLG3_ENABLE_TSS             0x00040000
-#define TG3_FLG3_4G_DMA_BNDRY_BUG       0x00080000
-#define TG3_FLG3_40BIT_DMA_LIMIT_BUG    0x00100000
-#define TG3_FLG3_SHORT_DMA_BUG          0x00200000
-#define TG3_FLG3_USE_JUMBO_BDFLAG       0x00400000
-#define TG3_FLG3_L1PLLPD_EN             0x00800000
-#define TG3_FLG3_5717_PLUS              0x01000000
-
         struct timer_list               timer;
         u16                             timer_counter;
         u16                             timer_multiplier;
@@ -2891,6 +3033,7 @@ struct tg3 {
         int                             pcix_cap;
         int                             pcie_cap;
         };
+        int                             pcie_readrq;
 
         struct mii_bus                  *mdio_bus;
         int                             mdio_irq[PHY_MAX_ADDR];
@@ -2920,6 +3063,7 @@ struct tg3 {
 #define TG3_PHY_ID_BCM5718S             0xbc050ff0
 #define TG3_PHY_ID_BCM57765             0x5c0d8a40
 #define TG3_PHY_ID_BCM5719C             0x5c0d8a20
+#define TG3_PHY_ID_BCM5720C             0x5c0d8b60
 #define TG3_PHY_ID_BCM5906              0xdc00ac40
 #define TG3_PHY_ID_BCM8002              0x60010140
 #define TG3_PHY_ID_INVALID              0xffffffff
@@ -2966,9 +3110,11 @@ struct tg3 {
 #define TG3_PHYFLG_BER_BUG              0x00008000
 #define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
 #define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
+#define TG3_PHYFLG_EEE_CAP              0x00040000
 
         u32                             led_ctrl;
         u32                             phy_otp;
+        u32                             setlpicnt;
 
 #define TG3_BPN_SIZE                    24
         char                            board_part_number[TG3_BPN_SIZE];
@@ -2984,6 +3130,7 @@ struct tg3 {
 
         int                             nvram_lock_cnt;
         u32                             nvram_size;
+#define TG3_NVRAM_SIZE_2KB              0x00000800
 #define TG3_NVRAM_SIZE_64KB             0x00010000
 #define TG3_NVRAM_SIZE_128KB            0x00020000
 #define TG3_NVRAM_SIZE_256KB            0x00040000
@@ -2999,6 +3146,9 @@ struct tg3 {
 #define JEDEC_SAIFUN                    0x4f
 #define JEDEC_SST                       0xbf
 
+#define ATMEL_AT24C02_CHIP_SIZE         TG3_NVRAM_SIZE_2KB
+#define ATMEL_AT24C02_PAGE_SIZE         (8)
+
 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
 #define ATMEL_AT24C64_PAGE_SIZE         (32)