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authorGiuseppe CAVALLARO <peppe.cavallaro@st.com>2010-01-06 18:07:18 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-07 20:06:09 -0500
commitaec7ff278145280c2c78377aeb98feed02c8b636 (patch)
treefa03f8eac900b08e278b64ad76d825400907af9c /drivers/net/stmmac
parentdb98a0b001df79ffcdd4f231c3516411786a1113 (diff)
stmmac: move the dma out from the main
This patch moves the dma related functions (interrupt, start, stop etc.) out from the main driver code. This will help to support new DMA engines. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/stmmac')
-rw-r--r--drivers/net/stmmac/Makefile2
-rw-r--r--drivers/net/stmmac/common.h209
-rw-r--r--drivers/net/stmmac/dwmac_dma.h107
-rw-r--r--drivers/net/stmmac/dwmac_lib.c263
-rw-r--r--drivers/net/stmmac/gmac.c9
-rw-r--r--drivers/net/stmmac/mac100.c9
-rw-r--r--drivers/net/stmmac/stmmac_ethtool.c1
-rw-r--r--drivers/net/stmmac/stmmac_main.c268
8 files changed, 481 insertions, 387 deletions
diff --git a/drivers/net/stmmac/Makefile b/drivers/net/stmmac/Makefile
index b2d7a5564dfa..c8f499a71251 100644
--- a/drivers/net/stmmac/Makefile
+++ b/drivers/net/stmmac/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_STMMAC_ETH) += stmmac.o 1obj-$(CONFIG_STMMAC_ETH) += stmmac.o
2stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o 2stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o
3stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o \ 3stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o dwmac_lib.o \
4 mac100.o gmac.o $(stmmac-y) 4 mac100.o gmac.o $(stmmac-y)
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index 95782ccf44b4..6f8fe64dd226 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -25,131 +25,6 @@
25#include "descs.h" 25#include "descs.h"
26#include <linux/io.h> 26#include <linux/io.h>
27 27
28/* *********************************************
29 DMA CRS Control and Status Register Mapping
30 * *********************************************/
31#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
32#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
33#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
34#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
35#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
36#define DMA_STATUS 0x00001014 /* Status Register */
37#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
38#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
39#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
40#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
41#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
42
43/* ********************************
44 DMA Control register defines
45 * ********************************/
46#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
47#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
48
49/* **************************************
50 DMA Interrupt Enable register defines
51 * **************************************/
52/**** NORMAL INTERRUPT ****/
53#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
54#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
55#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
56#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
57#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
58
59#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
60 DMA_INTR_ENA_TIE)
61
62/**** ABNORMAL INTERRUPT ****/
63#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
64#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
65#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
66#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
67#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
68#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
69#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
70#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
71#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
72#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
73
74#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
75 DMA_INTR_ENA_UNE)
76
77/* DMA default interrupt mask */
78#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
79
80/* ****************************
81 * DMA Status register defines
82 * ****************************/
83#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
84#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
85#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int. */
86#define DMA_STATUS_GMI 0x08000000
87#define DMA_STATUS_GLI 0x04000000
88#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
89#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
90#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
91#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
92#define DMA_STATUS_TS_SHIFT 20
93#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
94#define DMA_STATUS_RS_SHIFT 17
95#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
96#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
97#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
98#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
99#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
100#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
101#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
102#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
103#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
104#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
105#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
106#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
107#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
108#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
109#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
110
111/* Other defines */
112#define HASH_TABLE_SIZE 64
113#define PAUSE_TIME 0x200
114
115/* Flow Control defines */
116#define FLOW_OFF 0
117#define FLOW_RX 1
118#define FLOW_TX 2
119#define FLOW_AUTO (FLOW_TX | FLOW_RX)
120
121/* DMA STORE-AND-FORWARD Operation Mode */
122#define SF_DMA_MODE 1
123
124#define HW_CSUM 1
125#define NO_HW_CSUM 0
126
127/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
128#define BUF_SIZE_16KiB 16384
129#define BUF_SIZE_8KiB 8192
130#define BUF_SIZE_4KiB 4096
131#define BUF_SIZE_2KiB 2048
132
133/* Power Down and WOL */
134#define PMT_NOT_SUPPORTED 0
135#define PMT_SUPPORTED 1
136
137/* Common MAC defines */
138#define MAC_CTRL_REG 0x00000000 /* MAC Control */
139#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
140#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
141
142/* MAC Management Counters register */
143#define MMC_CONTROL 0x00000100 /* MMC Control */
144#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
145#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
146#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
147#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
148
149#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
150#define MMC_CONTROL_MAX_FRM_SHIFT 3
151#define MMC_CONTROL_MAX_FRAME 0x7FF
152
153struct stmmac_extra_stats { 28struct stmmac_extra_stats {
154 /* Transmit errors */ 29 /* Transmit errors */
155 unsigned long tx_underflow ____cacheline_aligned; 30 unsigned long tx_underflow ____cacheline_aligned;
@@ -198,46 +73,56 @@ struct stmmac_extra_stats {
198 unsigned long normal_irq_n; 73 unsigned long normal_irq_n;
199}; 74};
200 75
201/* GMAC core can compute the checksums in HW. */ 76#define HASH_TABLE_SIZE 64
202enum rx_frame_status { 77#define PAUSE_TIME 0x200
78
79/* Flow Control defines */
80#define FLOW_OFF 0
81#define FLOW_RX 1
82#define FLOW_TX 2
83#define FLOW_AUTO (FLOW_TX | FLOW_RX)
84
85#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
86
87#define HW_CSUM 1
88#define NO_HW_CSUM 0
89enum rx_frame_status { /* IPC status */
203 good_frame = 0, 90 good_frame = 0,
204 discard_frame = 1, 91 discard_frame = 1,
205 csum_none = 2, 92 csum_none = 2,
206}; 93};
207 94
208static inline void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 95enum tx_dma_irq_status {
209 unsigned int high, unsigned int low) 96 tx_hard_error = 1,
210{ 97 tx_hard_error_bump_tc = 2,
211 unsigned long data; 98 handle_tx_rx = 3,
212 99};
213 data = (addr[5] << 8) | addr[4];
214 writel(data, ioaddr + high);
215 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
216 writel(data, ioaddr + low);
217 100
218 return; 101/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
219} 102#define BUF_SIZE_16KiB 16384
103#define BUF_SIZE_8KiB 8192
104#define BUF_SIZE_4KiB 4096
105#define BUF_SIZE_2KiB 2048
220 106
221static inline void stmmac_get_mac_addr(unsigned long ioaddr, 107/* Power Down and WOL */
222 unsigned char *addr, unsigned int high, 108#define PMT_NOT_SUPPORTED 0
223 unsigned int low) 109#define PMT_SUPPORTED 1
224{
225 unsigned int hi_addr, lo_addr;
226 110
227 /* Read the MAC address from the hardware */ 111/* Common MAC defines */
228 hi_addr = readl(ioaddr + high); 112#define MAC_CTRL_REG 0x00000000 /* MAC Control */
229 lo_addr = readl(ioaddr + low); 113#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
114#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
230 115
231 /* Extract the MAC address from the high and low words */ 116/* MAC Management Counters register */
232 addr[0] = lo_addr & 0xff; 117#define MMC_CONTROL 0x00000100 /* MMC Control */
233 addr[1] = (lo_addr >> 8) & 0xff; 118#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
234 addr[2] = (lo_addr >> 16) & 0xff; 119#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
235 addr[3] = (lo_addr >> 24) & 0xff; 120#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
236 addr[4] = hi_addr & 0xff; 121#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
237 addr[5] = (hi_addr >> 8) & 0xff;
238 122
239 return; 123#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
240} 124#define MMC_CONTROL_MAX_FRM_SHIFT 3
125#define MMC_CONTROL_MAX_FRAME 0x7FF
241 126
242struct stmmac_desc_ops { 127struct stmmac_desc_ops {
243 /* DMA RX descriptor ring initialization */ 128 /* DMA RX descriptor ring initialization */
@@ -287,6 +172,15 @@ struct stmmac_dma_ops {
287 /* To track extra statistic (if supported) */ 172 /* To track extra statistic (if supported) */
288 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, 173 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
289 unsigned long ioaddr); 174 unsigned long ioaddr);
175 void (*enable_dma_transmission) (unsigned long ioaddr);
176 void (*enable_dma_irq) (unsigned long ioaddr);
177 void (*disable_dma_irq) (unsigned long ioaddr);
178 void (*start_tx) (unsigned long ioaddr);
179 void (*stop_tx) (unsigned long ioaddr);
180 void (*start_rx) (unsigned long ioaddr);
181 void (*stop_rx) (unsigned long ioaddr);
182 int (*dma_interrupt) (unsigned long ioaddr,
183 struct stmmac_extra_stats *x);
290}; 184};
291 185
292struct stmmac_ops { 186struct stmmac_ops {
@@ -332,3 +226,8 @@ struct mac_device_info {
332 226
333struct mac_device_info *gmac_setup(unsigned long addr); 227struct mac_device_info *gmac_setup(unsigned long addr);
334struct mac_device_info *mac100_setup(unsigned long addr); 228struct mac_device_info *mac100_setup(unsigned long addr);
229
230extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
231 unsigned int high, unsigned int low);
232extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
233 unsigned int high, unsigned int low);
diff --git a/drivers/net/stmmac/dwmac_dma.h b/drivers/net/stmmac/dwmac_dma.h
new file mode 100644
index 000000000000..de848d9f6060
--- /dev/null
+++ b/drivers/net/stmmac/dwmac_dma.h
@@ -0,0 +1,107 @@
1/*******************************************************************************
2 DWMAC DMA Header file.
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
25/* DMA CRS Control and Status Register Mapping */
26#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
27#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
28#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
29#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
30#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
31#define DMA_STATUS 0x00001014 /* Status Register */
32#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
33#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
34#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
35#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
36#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
37
38/* DMA Control register defines */
39#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
40#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
41
42/* DMA Normal interrupt */
43#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
44#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
45#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
46#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
47#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
48
49#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
50 DMA_INTR_ENA_TIE)
51
52/* DMA Abnormal interrupt */
53#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
54#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
55#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
56#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
57#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
58#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
59#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
60#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
61#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
62#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
63
64#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
65 DMA_INTR_ENA_UNE)
66
67/* DMA default interrupt mask */
68#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
69
70/* DMA Status register defines */
71#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
72#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
73#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
74#define DMA_STATUS_GMI 0x08000000
75#define DMA_STATUS_GLI 0x04000000
76#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
77#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
78#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
79#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
80#define DMA_STATUS_TS_SHIFT 20
81#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
82#define DMA_STATUS_RS_SHIFT 17
83#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
84#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
85#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
86#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
87#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
88#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
89#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
90#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
91#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
92#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
93#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
94#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
95#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
96#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
97#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
98
99extern void dwmac_enable_dma_transmission(unsigned long ioaddr);
100extern void dwmac_enable_dma_irq(unsigned long ioaddr);
101extern void dwmac_disable_dma_irq(unsigned long ioaddr);
102extern void dwmac_dma_start_tx(unsigned long ioaddr);
103extern void dwmac_dma_stop_tx(unsigned long ioaddr);
104extern void dwmac_dma_start_rx(unsigned long ioaddr);
105extern void dwmac_dma_stop_rx(unsigned long ioaddr);
106extern int dwmac_dma_interrupt(unsigned long ioaddr,
107 struct stmmac_extra_stats *x);
diff --git a/drivers/net/stmmac/dwmac_lib.c b/drivers/net/stmmac/dwmac_lib.c
new file mode 100644
index 000000000000..d4adb1eaa447
--- /dev/null
+++ b/drivers/net/stmmac/dwmac_lib.c
@@ -0,0 +1,263 @@
1/*******************************************************************************
2 Copyright (C) 2007-2009 STMicroelectronics Ltd
3
4 This program is free software; you can redistribute it and/or modify it
5 under the terms and conditions of the GNU General Public License,
6 version 2, as published by the Free Software Foundation.
7
8 This program is distributed in the hope it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 more details.
12
13 You should have received a copy of the GNU General Public License along with
14 this program; if not, write to the Free Software Foundation, Inc.,
15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16
17 The full GNU General Public License is included in this distribution in
18 the file called "COPYING".
19
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21*******************************************************************************/
22
23#include <linux/io.h>
24#include "common.h"
25#include "dwmac_dma.h"
26
27#undef DWMAC_DMA_DEBUG
28#ifdef DWMAC_DMA_DEBUG
29#define DBG(fmt, args...) printk(fmt, ## args)
30#else
31#define DBG(fmt, args...) do { } while (0)
32#endif
33
34/* CSR1 enables the transmit DMA to check for new descriptor */
35void dwmac_enable_dma_transmission(unsigned long ioaddr)
36{
37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
38}
39
40void dwmac_enable_dma_irq(unsigned long ioaddr)
41{
42 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
43}
44
45void dwmac_disable_dma_irq(unsigned long ioaddr)
46{
47 writel(0, ioaddr + DMA_INTR_ENA);
48}
49
50void dwmac_dma_start_tx(unsigned long ioaddr)
51{
52 u32 value = readl(ioaddr + DMA_CONTROL);
53 value |= DMA_CONTROL_ST;
54 writel(value, ioaddr + DMA_CONTROL);
55 return;
56}
57
58void dwmac_dma_stop_tx(unsigned long ioaddr)
59{
60 u32 value = readl(ioaddr + DMA_CONTROL);
61 value &= ~DMA_CONTROL_ST;
62 writel(value, ioaddr + DMA_CONTROL);
63 return;
64}
65
66void dwmac_dma_start_rx(unsigned long ioaddr)
67{
68 u32 value = readl(ioaddr + DMA_CONTROL);
69 value |= DMA_CONTROL_SR;
70 writel(value, ioaddr + DMA_CONTROL);
71
72 return;
73}
74
75void dwmac_dma_stop_rx(unsigned long ioaddr)
76{
77 u32 value = readl(ioaddr + DMA_CONTROL);
78 value &= ~DMA_CONTROL_SR;
79 writel(value, ioaddr + DMA_CONTROL);
80
81 return;
82}
83
84#ifdef DWMAC_DMA_DEBUG
85static void show_tx_process_state(unsigned int status)
86{
87 unsigned int state;
88 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
89
90 switch (state) {
91 case 0:
92 pr_info("- TX (Stopped): Reset or Stop command\n");
93 break;
94 case 1:
95 pr_info("- TX (Running):Fetching the Tx desc\n");
96 break;
97 case 2:
98 pr_info("- TX (Running): Waiting for end of tx\n");
99 break;
100 case 3:
101 pr_info("- TX (Running): Reading the data "
102 "and queuing the data into the Tx buf\n");
103 break;
104 case 6:
105 pr_info("- TX (Suspended): Tx Buff Underflow "
106 "or an unavailable Transmit descriptor\n");
107 break;
108 case 7:
109 pr_info("- TX (Running): Closing Tx descriptor\n");
110 break;
111 default:
112 break;
113 }
114 return;
115}
116
117static void show_rx_process_state(unsigned int status)
118{
119 unsigned int state;
120 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
121
122 switch (state) {
123 case 0:
124 pr_info("- RX (Stopped): Reset or Stop command\n");
125 break;
126 case 1:
127 pr_info("- RX (Running): Fetching the Rx desc\n");
128 break;
129 case 2:
130 pr_info("- RX (Running):Checking for end of pkt\n");
131 break;
132 case 3:
133 pr_info("- RX (Running): Waiting for Rx pkt\n");
134 break;
135 case 4:
136 pr_info("- RX (Suspended): Unavailable Rx buf\n");
137 break;
138 case 5:
139 pr_info("- RX (Running): Closing Rx descriptor\n");
140 break;
141 case 6:
142 pr_info("- RX(Running): Flushing the current frame"
143 " from the Rx buf\n");
144 break;
145 case 7:
146 pr_info("- RX (Running): Queuing the Rx frame"
147 " from the Rx buf into memory\n");
148 break;
149 default:
150 break;
151 }
152 return;
153}
154#endif
155
156int dwmac_dma_interrupt(unsigned long ioaddr,
157 struct stmmac_extra_stats *x)
158{
159 int ret = 0;
160 /* read the status register (CSR5) */
161 u32 intr_status = readl(ioaddr + DMA_STATUS);
162
163 DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
164#ifdef DWMAC_DMA_DEBUG
165 /* It displays the DMA process states (CSR5 register) */
166 show_tx_process_state(intr_status);
167 show_rx_process_state(intr_status);
168#endif
169 /* ABNORMAL interrupts */
170 if (unlikely(intr_status & DMA_STATUS_AIS)) {
171 DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
172 if (unlikely(intr_status & DMA_STATUS_UNF)) {
173 DBG(INFO, "transmit underflow\n");
174 ret = tx_hard_error_bump_tc;
175 x->tx_undeflow_irq++;
176 }
177 if (unlikely(intr_status & DMA_STATUS_TJT)) {
178 DBG(INFO, "transmit jabber\n");
179 x->tx_jabber_irq++;
180 }
181 if (unlikely(intr_status & DMA_STATUS_OVF)) {
182 DBG(INFO, "recv overflow\n");
183 x->rx_overflow_irq++;
184 }
185 if (unlikely(intr_status & DMA_STATUS_RU)) {
186 DBG(INFO, "receive buffer unavailable\n");
187 x->rx_buf_unav_irq++;
188 }
189 if (unlikely(intr_status & DMA_STATUS_RPS)) {
190 DBG(INFO, "receive process stopped\n");
191 x->rx_process_stopped_irq++;
192 }
193 if (unlikely(intr_status & DMA_STATUS_RWT)) {
194 DBG(INFO, "receive watchdog\n");
195 x->rx_watchdog_irq++;
196 }
197 if (unlikely(intr_status & DMA_STATUS_ETI)) {
198 DBG(INFO, "transmit early interrupt\n");
199 x->tx_early_irq++;
200 }
201 if (unlikely(intr_status & DMA_STATUS_TPS)) {
202 DBG(INFO, "transmit process stopped\n");
203 x->tx_process_stopped_irq++;
204 ret = tx_hard_error;
205 }
206 if (unlikely(intr_status & DMA_STATUS_FBI)) {
207 DBG(INFO, "fatal bus error\n");
208 x->fatal_bus_error_irq++;
209 ret = tx_hard_error;
210 }
211 }
212 /* TX/RX NORMAL interrupts */
213 if (intr_status & DMA_STATUS_NIS) {
214 x->normal_irq_n++;
215 if (likely((intr_status & DMA_STATUS_RI) ||
216 (intr_status & (DMA_STATUS_TI))))
217 ret = handle_tx_rx;
218 }
219 /* Optional hardware blocks, interrupts should be disabled */
220 if (unlikely(intr_status &
221 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
222 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
223 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
224 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
225
226 DBG(INFO, "\n\n");
227 return ret;
228}
229
230
231void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
232 unsigned int high, unsigned int low)
233{
234 unsigned long data;
235
236 data = (addr[5] << 8) | addr[4];
237 writel(data, ioaddr + high);
238 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
239 writel(data, ioaddr + low);
240
241 return;
242}
243
244void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
245 unsigned int high, unsigned int low)
246{
247 unsigned int hi_addr, lo_addr;
248
249 /* Read the MAC address from the hardware */
250 hi_addr = readl(ioaddr + high);
251 lo_addr = readl(ioaddr + low);
252
253 /* Extract the MAC address from the high and low words */
254 addr[0] = lo_addr & 0xff;
255 addr[1] = (lo_addr >> 8) & 0xff;
256 addr[2] = (lo_addr >> 16) & 0xff;
257 addr[3] = (lo_addr >> 24) & 0xff;
258 addr[4] = hi_addr & 0xff;
259 addr[5] = (hi_addr >> 8) & 0xff;
260
261 return;
262}
263
diff --git a/drivers/net/stmmac/gmac.c b/drivers/net/stmmac/gmac.c
index cf199d969227..07880922ff46 100644
--- a/drivers/net/stmmac/gmac.c
+++ b/drivers/net/stmmac/gmac.c
@@ -31,6 +31,7 @@
31 31
32#include "stmmac.h" 32#include "stmmac.h"
33#include "gmac.h" 33#include "gmac.h"
34#include "dwmac_dma.h"
34 35
35#undef GMAC_DEBUG 36#undef GMAC_DEBUG
36/*#define GMAC_DEBUG*/ 37/*#define GMAC_DEBUG*/
@@ -646,6 +647,14 @@ struct stmmac_dma_ops gmac_dma_ops = {
646 .dump_regs = gmac_dump_dma_regs, 647 .dump_regs = gmac_dump_dma_regs,
647 .dma_mode = gmac_dma_operation_mode, 648 .dma_mode = gmac_dma_operation_mode,
648 .dma_diagnostic_fr = gmac_dma_diagnostic_fr, 649 .dma_diagnostic_fr = gmac_dma_diagnostic_fr,
650 .enable_dma_transmission = dwmac_enable_dma_transmission,
651 .enable_dma_irq = dwmac_enable_dma_irq,
652 .disable_dma_irq = dwmac_disable_dma_irq,
653 .start_tx = dwmac_dma_start_tx,
654 .stop_tx = dwmac_dma_stop_tx,
655 .start_rx = dwmac_dma_start_rx,
656 .stop_rx = dwmac_dma_stop_rx,
657 .dma_interrupt = dwmac_dma_interrupt,
649}; 658};
650 659
651struct stmmac_desc_ops gmac_desc_ops = { 660struct stmmac_desc_ops gmac_desc_ops = {
diff --git a/drivers/net/stmmac/mac100.c b/drivers/net/stmmac/mac100.c
index 45d0457ddb6e..b675f7c67f6e 100644
--- a/drivers/net/stmmac/mac100.c
+++ b/drivers/net/stmmac/mac100.c
@@ -33,6 +33,7 @@
33 33
34#include "common.h" 34#include "common.h"
35#include "mac100.h" 35#include "mac100.h"
36#include "dwmac_dma.h"
36 37
37#undef MAC100_DEBUG 38#undef MAC100_DEBUG
38/*#define MAC100_DEBUG*/ 39/*#define MAC100_DEBUG*/
@@ -483,6 +484,14 @@ struct stmmac_dma_ops mac100_dma_ops = {
483 .dump_regs = mac100_dump_dma_regs, 484 .dump_regs = mac100_dump_dma_regs,
484 .dma_mode = mac100_dma_operation_mode, 485 .dma_mode = mac100_dma_operation_mode,
485 .dma_diagnostic_fr = mac100_dma_diagnostic_fr, 486 .dma_diagnostic_fr = mac100_dma_diagnostic_fr,
487 .enable_dma_transmission = dwmac_enable_dma_transmission,
488 .enable_dma_irq = dwmac_enable_dma_irq,
489 .disable_dma_irq = dwmac_disable_dma_irq,
490 .start_tx = dwmac_dma_start_tx,
491 .stop_tx = dwmac_dma_stop_tx,
492 .start_rx = dwmac_dma_start_rx,
493 .stop_rx = dwmac_dma_stop_rx,
494 .dma_interrupt = dwmac_dma_interrupt,
486}; 495};
487 496
488struct stmmac_desc_ops mac100_desc_ops = { 497struct stmmac_desc_ops mac100_desc_ops = {
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index 9c7ce1ea3aea..0abeff6193a1 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -28,6 +28,7 @@
28#include <linux/phy.h> 28#include <linux/phy.h>
29 29
30#include "stmmac.h" 30#include "stmmac.h"
31#include "dwmac_dma.h"
31 32
32#define REG_SPACE_SIZE 0x1054 33#define REG_SPACE_SIZE 0x1054
33#define MAC100_ETHTOOL_NAME "st_mac100" 34#define MAC100_ETHTOOL_NAME "st_mac100"
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 86e910300969..e6c5a3cf4af2 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -572,50 +572,6 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
572} 572}
573 573
574/** 574/**
575 * stmmac_dma_start_tx
576 * @ioaddr: device I/O address
577 * Description: this function starts the DMA tx process.
578 */
579static void stmmac_dma_start_tx(unsigned long ioaddr)
580{
581 u32 value = readl(ioaddr + DMA_CONTROL);
582 value |= DMA_CONTROL_ST;
583 writel(value, ioaddr + DMA_CONTROL);
584 return;
585}
586
587static void stmmac_dma_stop_tx(unsigned long ioaddr)
588{
589 u32 value = readl(ioaddr + DMA_CONTROL);
590 value &= ~DMA_CONTROL_ST;
591 writel(value, ioaddr + DMA_CONTROL);
592 return;
593}
594
595/**
596 * stmmac_dma_start_rx
597 * @ioaddr: device I/O address
598 * Description: this function starts the DMA rx process.
599 */
600static void stmmac_dma_start_rx(unsigned long ioaddr)
601{
602 u32 value = readl(ioaddr + DMA_CONTROL);
603 value |= DMA_CONTROL_SR;
604 writel(value, ioaddr + DMA_CONTROL);
605
606 return;
607}
608
609static void stmmac_dma_stop_rx(unsigned long ioaddr)
610{
611 u32 value = readl(ioaddr + DMA_CONTROL);
612 value &= ~DMA_CONTROL_SR;
613 writel(value, ioaddr + DMA_CONTROL);
614
615 return;
616}
617
618/**
619 * stmmac_dma_operation_mode - HW DMA operation mode 575 * stmmac_dma_operation_mode - HW DMA operation mode
620 * @priv : pointer to the private device structure. 576 * @priv : pointer to the private device structure.
621 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 577 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
@@ -646,88 +602,6 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
646 return; 602 return;
647} 603}
648 604
649#ifdef STMMAC_DEBUG
650/**
651 * show_tx_process_state
652 * @status: tx descriptor status field
653 * Description: it shows the Transmit Process State for CSR5[22:20]
654 */
655static void show_tx_process_state(unsigned int status)
656{
657 unsigned int state;
658 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
659
660 switch (state) {
661 case 0:
662 pr_info("- TX (Stopped): Reset or Stop command\n");
663 break;
664 case 1:
665 pr_info("- TX (Running):Fetching the Tx desc\n");
666 break;
667 case 2:
668 pr_info("- TX (Running): Waiting for end of tx\n");
669 break;
670 case 3:
671 pr_info("- TX (Running): Reading the data "
672 "and queuing the data into the Tx buf\n");
673 break;
674 case 6:
675 pr_info("- TX (Suspended): Tx Buff Underflow "
676 "or an unavailable Transmit descriptor\n");
677 break;
678 case 7:
679 pr_info("- TX (Running): Closing Tx descriptor\n");
680 break;
681 default:
682 break;
683 }
684 return;
685}
686
687/**
688 * show_rx_process_state
689 * @status: rx descriptor status field
690 * Description: it shows the Receive Process State for CSR5[19:17]
691 */
692static void show_rx_process_state(unsigned int status)
693{
694 unsigned int state;
695 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
696
697 switch (state) {
698 case 0:
699 pr_info("- RX (Stopped): Reset or Stop command\n");
700 break;
701 case 1:
702 pr_info("- RX (Running): Fetching the Rx desc\n");
703 break;
704 case 2:
705 pr_info("- RX (Running):Checking for end of pkt\n");
706 break;
707 case 3:
708 pr_info("- RX (Running): Waiting for Rx pkt\n");
709 break;
710 case 4:
711 pr_info("- RX (Suspended): Unavailable Rx buf\n");
712 break;
713 case 5:
714 pr_info("- RX (Running): Closing Rx descriptor\n");
715 break;
716 case 6:
717 pr_info("- RX(Running): Flushing the current frame"
718 " from the Rx buf\n");
719 break;
720 case 7:
721 pr_info("- RX (Running): Queuing the Rx frame"
722 " from the Rx buf into memory\n");
723 break;
724 default:
725 break;
726 }
727 return;
728}
729#endif
730
731/** 605/**
732 * stmmac_tx: 606 * stmmac_tx:
733 * @priv: private driver structure 607 * @priv: private driver structure
@@ -811,7 +685,7 @@ static inline void stmmac_enable_irq(struct stmmac_priv *priv)
811 priv->tm->timer_start(tmrate); 685 priv->tm->timer_start(tmrate);
812 else 686 else
813#endif 687#endif
814 writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA); 688 priv->hw->dma->enable_dma_irq(priv->dev->base_addr);
815} 689}
816 690
817static inline void stmmac_disable_irq(struct stmmac_priv *priv) 691static inline void stmmac_disable_irq(struct stmmac_priv *priv)
@@ -821,7 +695,7 @@ static inline void stmmac_disable_irq(struct stmmac_priv *priv)
821 priv->tm->timer_stop(); 695 priv->tm->timer_stop();
822 else 696 else
823#endif 697#endif
824 writel(0, priv->dev->base_addr + DMA_INTR_ENA); 698 priv->hw->dma->disable_dma_irq(priv->dev->base_addr);
825} 699}
826 700
827static int stmmac_has_work(struct stmmac_priv *priv) 701static int stmmac_has_work(struct stmmac_priv *priv)
@@ -880,12 +754,12 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
880{ 754{
881 netif_stop_queue(priv->dev); 755 netif_stop_queue(priv->dev);
882 756
883 stmmac_dma_stop_tx(priv->dev->base_addr); 757 priv->hw->dma->stop_tx(priv->dev->base_addr);
884 dma_free_tx_skbufs(priv); 758 dma_free_tx_skbufs(priv);
885 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 759 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
886 priv->dirty_tx = 0; 760 priv->dirty_tx = 0;
887 priv->cur_tx = 0; 761 priv->cur_tx = 0;
888 stmmac_dma_start_tx(priv->dev->base_addr); 762 priv->hw->dma->start_tx(priv->dev->base_addr);
889 763
890 priv->dev->stats.tx_errors++; 764 priv->dev->stats.tx_errors++;
891 netif_wake_queue(priv->dev); 765 netif_wake_queue(priv->dev);
@@ -893,95 +767,27 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
893 return; 767 return;
894} 768}
895 769
896/**
897 * stmmac_dma_interrupt - Interrupt handler for the driver
898 * @dev: net device structure
899 * Description: Interrupt handler for the driver (DMA).
900 */
901static void stmmac_dma_interrupt(struct net_device *dev)
902{
903 unsigned long ioaddr = dev->base_addr;
904 struct stmmac_priv *priv = netdev_priv(dev);
905 /* read the status register (CSR5) */
906 u32 intr_status = readl(ioaddr + DMA_STATUS);
907
908 DBG(intr, INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
909 770
910#ifdef STMMAC_DEBUG 771static void stmmac_dma_interrupt(struct stmmac_priv *priv)
911 /* It displays the DMA transmit process state (CSR5 register) */ 772{
912 if (netif_msg_tx_done(priv)) 773 unsigned long ioaddr = priv->dev->base_addr;
913 show_tx_process_state(intr_status); 774 int status;
914 if (netif_msg_rx_status(priv)) 775
915 show_rx_process_state(intr_status); 776 status = priv->hw->dma->dma_interrupt(priv->dev->base_addr,
916#endif 777 &priv->xstats);
917 /* ABNORMAL interrupts */ 778 if (likely(status == handle_tx_rx))
918 if (unlikely(intr_status & DMA_STATUS_AIS)) { 779 _stmmac_schedule(priv);
919 DBG(intr, INFO, "CSR5[15] DMA ABNORMAL IRQ: "); 780
920 if (unlikely(intr_status & DMA_STATUS_UNF)) { 781 else if (unlikely(status == tx_hard_error_bump_tc)) {
921 DBG(intr, INFO, "transmit underflow\n"); 782 /* Try to bump up the dma threshold on this failure */
922 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 783 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
923 /* Try to bump up the threshold */ 784 tc += 64;
924 tc += 64; 785 priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE);
925 priv->hw->dma->dma_mode(ioaddr, tc, 786 priv->xstats.threshold = tc;
926 SF_DMA_MODE);
927 priv->xstats.threshold = tc;
928 }
929 stmmac_tx_err(priv);
930 priv->xstats.tx_undeflow_irq++;
931 }
932 if (unlikely(intr_status & DMA_STATUS_TJT)) {
933 DBG(intr, INFO, "transmit jabber\n");
934 priv->xstats.tx_jabber_irq++;
935 }
936 if (unlikely(intr_status & DMA_STATUS_OVF)) {
937 DBG(intr, INFO, "recv overflow\n");
938 priv->xstats.rx_overflow_irq++;
939 }
940 if (unlikely(intr_status & DMA_STATUS_RU)) {
941 DBG(intr, INFO, "receive buffer unavailable\n");
942 priv->xstats.rx_buf_unav_irq++;
943 }
944 if (unlikely(intr_status & DMA_STATUS_RPS)) {
945 DBG(intr, INFO, "receive process stopped\n");
946 priv->xstats.rx_process_stopped_irq++;
947 }
948 if (unlikely(intr_status & DMA_STATUS_RWT)) {
949 DBG(intr, INFO, "receive watchdog\n");
950 priv->xstats.rx_watchdog_irq++;
951 }
952 if (unlikely(intr_status & DMA_STATUS_ETI)) {
953 DBG(intr, INFO, "transmit early interrupt\n");
954 priv->xstats.tx_early_irq++;
955 }
956 if (unlikely(intr_status & DMA_STATUS_TPS)) {
957 DBG(intr, INFO, "transmit process stopped\n");
958 priv->xstats.tx_process_stopped_irq++;
959 stmmac_tx_err(priv);
960 }
961 if (unlikely(intr_status & DMA_STATUS_FBI)) {
962 DBG(intr, INFO, "fatal bus error\n");
963 priv->xstats.fatal_bus_error_irq++;
964 stmmac_tx_err(priv);
965 } 787 }
966 } 788 stmmac_tx_err(priv);
967 789 } else if (unlikely(status == tx_hard_error))
968 /* TX/RX NORMAL interrupts */ 790 stmmac_tx_err(priv);
969 if (intr_status & DMA_STATUS_NIS) {
970 priv->xstats.normal_irq_n++;
971 if (likely((intr_status & DMA_STATUS_RI) ||
972 (intr_status & (DMA_STATUS_TI))))
973 _stmmac_schedule(priv);
974 }
975
976 /* Optional hardware blocks, interrupts should be disabled */
977 if (unlikely(intr_status &
978 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
979 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
980
981 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
982 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
983
984 DBG(intr, INFO, "\n\n");
985 791
986 return; 792 return;
987} 793}
@@ -1089,8 +895,8 @@ static int stmmac_open(struct net_device *dev)
1089 895
1090 /* Start the ball rolling... */ 896 /* Start the ball rolling... */
1091 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); 897 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1092 stmmac_dma_start_tx(ioaddr); 898 priv->hw->dma->start_tx(ioaddr);
1093 stmmac_dma_start_rx(ioaddr); 899 priv->hw->dma->start_rx(ioaddr);
1094 900
1095#ifdef CONFIG_STMMAC_TIMER 901#ifdef CONFIG_STMMAC_TIMER
1096 priv->tm->timer_start(tmrate); 902 priv->tm->timer_start(tmrate);
@@ -1142,8 +948,8 @@ static int stmmac_release(struct net_device *dev)
1142 free_irq(dev->irq, dev); 948 free_irq(dev->irq, dev);
1143 949
1144 /* Stop TX/RX DMA and clear the descriptors */ 950 /* Stop TX/RX DMA and clear the descriptors */
1145 stmmac_dma_stop_tx(dev->base_addr); 951 priv->hw->dma->stop_tx(dev->base_addr);
1146 stmmac_dma_stop_rx(dev->base_addr); 952 priv->hw->dma->stop_rx(dev->base_addr);
1147 953
1148 /* Release and free the Rx/Tx resources */ 954 /* Release and free the Rx/Tx resources */
1149 free_dma_desc_resources(priv); 955 free_dma_desc_resources(priv);
@@ -1227,7 +1033,6 @@ static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1227 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size, 1033 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1228 csum_insertion); 1034 csum_insertion);
1229 priv->hw->desc->set_tx_owner(desc); 1035 priv->hw->desc->set_tx_owner(desc);
1230
1231 priv->tx_skbuff[entry] = NULL; 1036 priv->tx_skbuff[entry] = NULL;
1232 } else { 1037 } else {
1233 desc->des2 = dma_map_single(priv->device, skb->data, 1038 desc->des2 = dma_map_single(priv->device, skb->data,
@@ -1353,8 +1158,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1353 1158
1354 dev->stats.tx_bytes += skb->len; 1159 dev->stats.tx_bytes += skb->len;
1355 1160
1356 /* CSR1 enables the transmit DMA to check for new descriptor */ 1161 priv->hw->dma->enable_dma_transmission(dev->base_addr);
1357 writel(1, dev->base_addr + DMA_XMT_POLL_DEMAND);
1358 1162
1359 return NETDEV_TX_OK; 1163 return NETDEV_TX_OK;
1360} 1164}
@@ -1624,7 +1428,8 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1624 /* To handle GMAC own interrupts */ 1428 /* To handle GMAC own interrupts */
1625 priv->hw->mac->host_irq_status(ioaddr); 1429 priv->hw->mac->host_irq_status(ioaddr);
1626 } 1430 }
1627 stmmac_dma_interrupt(dev); 1431
1432 stmmac_dma_interrupt(priv);
1628 1433
1629 return IRQ_HANDLED; 1434 return IRQ_HANDLED;
1630} 1435}
@@ -1988,12 +1793,13 @@ out:
1988static int stmmac_dvr_remove(struct platform_device *pdev) 1793static int stmmac_dvr_remove(struct platform_device *pdev)
1989{ 1794{
1990 struct net_device *ndev = platform_get_drvdata(pdev); 1795 struct net_device *ndev = platform_get_drvdata(pdev);
1796 struct stmmac_priv *priv = netdev_priv(ndev);
1991 struct resource *res; 1797 struct resource *res;
1992 1798
1993 pr_info("%s:\n\tremoving driver", __func__); 1799 pr_info("%s:\n\tremoving driver", __func__);
1994 1800
1995 stmmac_dma_stop_rx(ndev->base_addr); 1801 priv->hw->dma->stop_rx(ndev->base_addr);
1996 stmmac_dma_stop_tx(ndev->base_addr); 1802 priv->hw->dma->stop_tx(ndev->base_addr);
1997 1803
1998 stmmac_mac_disable_rx(ndev->base_addr); 1804 stmmac_mac_disable_rx(ndev->base_addr);
1999 stmmac_mac_disable_tx(ndev->base_addr); 1805 stmmac_mac_disable_tx(ndev->base_addr);
@@ -2040,8 +1846,8 @@ static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
2040 napi_disable(&priv->napi); 1846 napi_disable(&priv->napi);
2041 1847
2042 /* Stop TX/RX DMA */ 1848 /* Stop TX/RX DMA */
2043 stmmac_dma_stop_tx(dev->base_addr); 1849 priv->hw->dma->stop_tx(dev->base_addr);
2044 stmmac_dma_stop_rx(dev->base_addr); 1850 priv->hw->dma->stop_rx(dev->base_addr);
2045 /* Clear the Rx/Tx descriptors */ 1851 /* Clear the Rx/Tx descriptors */
2046 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, 1852 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2047 dis_ic); 1853 dis_ic);
@@ -2101,8 +1907,8 @@ static int stmmac_resume(struct platform_device *pdev)
2101 /* Enable the MAC and DMA */ 1907 /* Enable the MAC and DMA */
2102 stmmac_mac_enable_rx(ioaddr); 1908 stmmac_mac_enable_rx(ioaddr);
2103 stmmac_mac_enable_tx(ioaddr); 1909 stmmac_mac_enable_tx(ioaddr);
2104 stmmac_dma_start_tx(ioaddr); 1910 priv->hw->dma->start_tx(ioaddr);
2105 stmmac_dma_start_rx(ioaddr); 1911 priv->hw->dma->start_rx(ioaddr);
2106 1912
2107#ifdef CONFIG_STMMAC_TIMER 1913#ifdef CONFIG_STMMAC_TIMER
2108 priv->tm->timer_start(tmrate); 1914 priv->tm->timer_start(tmrate);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 09:59:51 -0400