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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/sh_eth.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/sh_eth.h')
-rw-r--r--drivers/net/sh_eth.h655
1 files changed, 371 insertions, 284 deletions
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 8b47763958f2..c3048a6ba676 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -2,7 +2,7 @@
2 * SuperH Ethernet device driver 2 * SuperH Ethernet device driver
3 * 3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp. 5 * Copyright (C) 2008-2011 Renesas Solutions Corp.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License, 8 * under the terms and conditions of the GNU General Public License,
@@ -26,7 +26,6 @@
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29#include <linux/workqueue.h>
30#include <linux/netdevice.h> 29#include <linux/netdevice.h>
31#include <linux/phy.h> 30#include <linux/phy.h>
32 31
@@ -39,278 +38,340 @@
39#define ETHERSMALL 60 38#define ETHERSMALL 60
40#define PKT_BUF_SZ 1538 39#define PKT_BUF_SZ 1538
41 40
42#if defined(CONFIG_CPU_SUBTYPE_SH7763) 41enum {
43/* This CPU register maps is very difference by other SH4 CPU */ 42 /* E-DMAC registers */
44 43 EDSR = 0,
45/* Chip Base Address */ 44 EDMR,
46# define SH_TSU_ADDR 0xFEE01800 45 EDTRR,
47# define ARSTR SH_TSU_ADDR 46 EDRRR,
48 47 EESR,
49/* Chip Registers */ 48 EESIPR,
50/* E-DMAC */ 49 TDLAR,
51# define EDSR 0x000 50 TDFAR,
52# define EDMR 0x400 51 TDFXR,
53# define EDTRR 0x408 52 TDFFR,
54# define EDRRR 0x410 53 RDLAR,
55# define EESR 0x428 54 RDFAR,
56# define EESIPR 0x430 55 RDFXR,
57# define TDLAR 0x010 56 RDFFR,
58# define TDFAR 0x014 57 TRSCER,
59# define TDFXR 0x018 58 RMFCR,
60# define TDFFR 0x01C 59 TFTR,
61# define RDLAR 0x030 60 FDR,
62# define RDFAR 0x034 61 RMCR,
63# define RDFXR 0x038 62 EDOCR,
64# define RDFFR 0x03C 63 TFUCR,
65# define TRSCER 0x438 64 RFOCR,
66# define RMFCR 0x440 65 FCFTR,
67# define TFTR 0x448 66 RPADIR,
68# define FDR 0x450 67 TRIMD,
69# define RMCR 0x458 68 RBWAR,
70# define RPADIR 0x460 69 TBRAR,
71# define FCFTR 0x468 70
72 71 /* Ether registers */
73/* Ether Register */ 72 ECMR,
74# define ECMR 0x500 73 ECSR,
75# define ECSR 0x510 74 ECSIPR,
76# define ECSIPR 0x518 75 PIR,
77# define PIR 0x520 76 PSR,
78# define PSR 0x528 77 RDMLR,
79# define PIPR 0x52C 78 PIPR,
80# define RFLR 0x508 79 RFLR,
81# define APR 0x554 80 IPGR,
82# define MPR 0x558 81 APR,
83# define PFTCR 0x55C 82 MPR,
84# define PFRCR 0x560 83 PFTCR,
85# define TPAUSER 0x564 84 PFRCR,
86# define GECMR 0x5B0 85 RFCR,
87# define BCULR 0x5B4 86 RFCF,
88# define MAHR 0x5C0 87 TPAUSER,
89# define MALR 0x5C8 88 TPAUSECR,
90# define TROCR 0x700 89 BCFR,
91# define CDCR 0x708 90 BCFRR,
92# define LCCR 0x710 91 GECMR,
93# define CEFCR 0x740 92 BCULR,
94# define FRECR 0x748 93 MAHR,
95# define TSFRCR 0x750 94 MALR,
96# define TLFRCR 0x758 95 TROCR,
97# define RFCR 0x760 96 CDCR,
98# define CERCR 0x768 97 LCCR,
99# define CEECR 0x770 98 CNDCR,
100# define MAFCR 0x778 99 CEFCR,
101 100 FRECR,
102/* TSU Absolute Address */ 101 TSFRCR,
103# define TSU_CTRST 0x004 102 TLFRCR,
104# define TSU_FWEN0 0x010 103 CERCR,
105# define TSU_FWEN1 0x014 104 CEECR,
106# define TSU_FCM 0x18 105 MAFCR,
107# define TSU_BSYSL0 0x20 106 RTRATE,
108# define TSU_BSYSL1 0x24 107
109# define TSU_PRISL0 0x28 108 /* TSU Absolute address */
110# define TSU_PRISL1 0x2C 109 ARSTR,
111# define TSU_FWSL0 0x30 110 TSU_CTRST,
112# define TSU_FWSL1 0x34 111 TSU_FWEN0,
113# define TSU_FWSLC 0x38 112 TSU_FWEN1,
114# define TSU_QTAG0 0x40 113 TSU_FCM,
115# define TSU_QTAG1 0x44 114 TSU_BSYSL0,
116# define TSU_FWSR 0x50 115 TSU_BSYSL1,
117# define TSU_FWINMK 0x54 116 TSU_PRISL0,
118# define TSU_ADQT0 0x48 117 TSU_PRISL1,
119# define TSU_ADQT1 0x4C 118 TSU_FWSL0,
120# define TSU_VTAG0 0x58 119 TSU_FWSL1,
121# define TSU_VTAG1 0x5C 120 TSU_FWSLC,
122# define TSU_ADSBSY 0x60 121 TSU_QTAG0,
123# define TSU_TEN 0x64 122 TSU_QTAG1,
124# define TSU_POST1 0x70 123 TSU_QTAGM0,
125# define TSU_POST2 0x74 124 TSU_QTAGM1,
126# define TSU_POST3 0x78 125 TSU_FWSR,
127# define TSU_POST4 0x7C 126 TSU_FWINMK,
128# define TSU_ADRH0 0x100 127 TSU_ADQT0,
129# define TSU_ADRL0 0x104 128 TSU_ADQT1,
130# define TSU_ADRH31 0x1F8 129 TSU_VTAG0,
131# define TSU_ADRL31 0x1FC 130 TSU_VTAG1,
132 131 TSU_ADSBSY,
133# define TXNLCR0 0x80 132 TSU_TEN,
134# define TXALCR0 0x84 133 TSU_POST1,
135# define RXNLCR0 0x88 134 TSU_POST2,
136# define RXALCR0 0x8C 135 TSU_POST3,
137# define FWNLCR0 0x90 136 TSU_POST4,
138# define FWALCR0 0x94 137 TSU_ADRH0,
139# define TXNLCR1 0xA0 138 TSU_ADRL0,
140# define TXALCR1 0xA4 139 TSU_ADRH31,
141# define RXNLCR1 0xA8 140 TSU_ADRL31,
142# define RXALCR1 0xAC 141
143# define FWNLCR1 0xB0 142 TXNLCR0,
144# define FWALCR1 0x40 143 TXALCR0,
145 144 RXNLCR0,
146#elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */ 145 RXALCR0,
147/* EtherC */ 146 FWNLCR0,
148#define ECMR 0x100 147 FWALCR0,
149#define RFLR 0x108 148 TXNLCR1,
150#define ECSR 0x110 149 TXALCR1,
151#define ECSIPR 0x118 150 RXNLCR1,
152#define PIR 0x120 151 RXALCR1,
153#define PSR 0x128 152 FWNLCR1,
154#define RDMLR 0x140 153 FWALCR1,
155#define IPGR 0x150 154
156#define APR 0x154 155 /* This value must be written at last. */
157#define MPR 0x158 156 SH_ETH_MAX_REGISTER_OFFSET,
158#define TPAUSER 0x164 157};
159#define RFCF 0x160 158
160#define TPAUSECR 0x168 159static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
161#define BCFRR 0x16c 160 [EDSR] = 0x0000,
162#define MAHR 0x1c0 161 [EDMR] = 0x0400,
163#define MALR 0x1c8 162 [EDTRR] = 0x0408,
164#define TROCR 0x1d0 163 [EDRRR] = 0x0410,
165#define CDCR 0x1d4 164 [EESR] = 0x0428,
166#define LCCR 0x1d8 165 [EESIPR] = 0x0430,
167#define CNDCR 0x1dc 166 [TDLAR] = 0x0010,
168#define CEFCR 0x1e4 167 [TDFAR] = 0x0014,
169#define FRECR 0x1e8 168 [TDFXR] = 0x0018,
170#define TSFRCR 0x1ec 169 [TDFFR] = 0x001c,
171#define TLFRCR 0x1f0 170 [RDLAR] = 0x0030,
172#define RFCR 0x1f4 171 [RDFAR] = 0x0034,
173#define MAFCR 0x1f8 172 [RDFXR] = 0x0038,
174#define RTRATE 0x1fc 173 [RDFFR] = 0x003c,
175 174 [TRSCER] = 0x0438,
176/* E-DMAC */ 175 [RMFCR] = 0x0440,
177#define EDMR 0x000 176 [TFTR] = 0x0448,
178#define EDTRR 0x008 177 [FDR] = 0x0450,
179#define EDRRR 0x010 178 [RMCR] = 0x0458,
180#define TDLAR 0x018 179 [RPADIR] = 0x0460,
181#define RDLAR 0x020 180 [FCFTR] = 0x0468,
182#define EESR 0x028 181
183#define EESIPR 0x030 182 [ECMR] = 0x0500,
184#define TRSCER 0x038 183 [ECSR] = 0x0510,
185#define RMFCR 0x040 184 [ECSIPR] = 0x0518,
186#define TFTR 0x048 185 [PIR] = 0x0520,
187#define FDR 0x050 186 [PSR] = 0x0528,
188#define RMCR 0x058 187 [PIPR] = 0x052c,
189#define TFUCR 0x064 188 [RFLR] = 0x0508,
190#define RFOCR 0x068 189 [APR] = 0x0554,
191#define FCFTR 0x070 190 [MPR] = 0x0558,
192#define RPADIR 0x078 191 [PFTCR] = 0x055c,
193#define TRIMD 0x07c 192 [PFRCR] = 0x0560,
194#define RBWAR 0x0c8 193 [TPAUSER] = 0x0564,
195#define RDFAR 0x0cc 194 [GECMR] = 0x05b0,
196#define TBRAR 0x0d4 195 [BCULR] = 0x05b4,
197#define TDFAR 0x0d8 196 [MAHR] = 0x05c0,
198#else /* #elif defined(CONFIG_CPU_SH4) */ 197 [MALR] = 0x05c8,
199/* This section is SH3 or SH2 */ 198 [TROCR] = 0x0700,
200#ifndef CONFIG_CPU_SUBTYPE_SH7619 199 [CDCR] = 0x0708,
201/* Chip base address */ 200 [LCCR] = 0x0710,
202# define SH_TSU_ADDR 0xA7000804 201 [CEFCR] = 0x0740,
203# define ARSTR 0xA7000800 202 [FRECR] = 0x0748,
204#endif 203 [TSFRCR] = 0x0750,
205/* Chip Registers */ 204 [TLFRCR] = 0x0758,
206/* E-DMAC */ 205 [RFCR] = 0x0760,
207# define EDMR 0x0000 206 [CERCR] = 0x0768,
208# define EDTRR 0x0004 207 [CEECR] = 0x0770,
209# define EDRRR 0x0008 208 [MAFCR] = 0x0778,
210# define TDLAR 0x000C 209
211# define RDLAR 0x0010 210 [ARSTR] = 0x0000,
212# define EESR 0x0014 211 [TSU_CTRST] = 0x0004,
213# define EESIPR 0x0018 212 [TSU_FWEN0] = 0x0010,
214# define TRSCER 0x001C 213 [TSU_FWEN1] = 0x0014,
215# define RMFCR 0x0020 214 [TSU_FCM] = 0x0018,
216# define TFTR 0x0024 215 [TSU_BSYSL0] = 0x0020,
217# define FDR 0x0028 216 [TSU_BSYSL1] = 0x0024,
218# define RMCR 0x002C 217 [TSU_PRISL0] = 0x0028,
219# define EDOCR 0x0030 218 [TSU_PRISL1] = 0x002c,
220# define FCFTR 0x0034 219 [TSU_FWSL0] = 0x0030,
221# define RPADIR 0x0038 220 [TSU_FWSL1] = 0x0034,
222# define TRIMD 0x003C 221 [TSU_FWSLC] = 0x0038,
223# define RBWAR 0x0040 222 [TSU_QTAG0] = 0x0040,
224# define RDFAR 0x0044 223 [TSU_QTAG1] = 0x0044,
225# define TBRAR 0x004C 224 [TSU_FWSR] = 0x0050,
226# define TDFAR 0x0050 225 [TSU_FWINMK] = 0x0054,
227 226 [TSU_ADQT0] = 0x0048,
228/* Ether Register */ 227 [TSU_ADQT1] = 0x004c,
229# define ECMR 0x0160 228 [TSU_VTAG0] = 0x0058,
230# define ECSR 0x0164 229 [TSU_VTAG1] = 0x005c,
231# define ECSIPR 0x0168 230 [TSU_ADSBSY] = 0x0060,
232# define PIR 0x016C 231 [TSU_TEN] = 0x0064,
233# define MAHR 0x0170 232 [TSU_POST1] = 0x0070,
234# define MALR 0x0174 233 [TSU_POST2] = 0x0074,
235# define RFLR 0x0178 234 [TSU_POST3] = 0x0078,
236# define PSR 0x017C 235 [TSU_POST4] = 0x007c,
237# define TROCR 0x0180 236 [TSU_ADRH0] = 0x0100,
238# define CDCR 0x0184 237 [TSU_ADRL0] = 0x0104,
239# define LCCR 0x0188 238 [TSU_ADRH31] = 0x01f8,
240# define CNDCR 0x018C 239 [TSU_ADRL31] = 0x01fc,
241# define CEFCR 0x0194 240
242# define FRECR 0x0198 241 [TXNLCR0] = 0x0080,
243# define TSFRCR 0x019C 242 [TXALCR0] = 0x0084,
244# define TLFRCR 0x01A0 243 [RXNLCR0] = 0x0088,
245# define RFCR 0x01A4 244 [RXALCR0] = 0x008c,
246# define MAFCR 0x01A8 245 [FWNLCR0] = 0x0090,
247# define IPGR 0x01B4 246 [FWALCR0] = 0x0094,
248# if defined(CONFIG_CPU_SUBTYPE_SH7710) 247 [TXNLCR1] = 0x00a0,
249# define APR 0x01B8 248 [TXALCR1] = 0x00a0,
250# define MPR 0x01BC 249 [RXNLCR1] = 0x00a8,
251# define TPAUSER 0x1C4 250 [RXALCR1] = 0x00ac,
252# define BCFR 0x1CC 251 [FWNLCR1] = 0x00b0,
253# endif /* CONFIG_CPU_SH7710 */ 252 [FWALCR1] = 0x00b4,
254 253};
255/* TSU */ 254
256# define TSU_CTRST 0x004 255static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
257# define TSU_FWEN0 0x010 256 [ECMR] = 0x0100,
258# define TSU_FWEN1 0x014 257 [RFLR] = 0x0108,
259# define TSU_FCM 0x018 258 [ECSR] = 0x0110,
260# define TSU_BSYSL0 0x020 259 [ECSIPR] = 0x0118,
261# define TSU_BSYSL1 0x024 260 [PIR] = 0x0120,
262# define TSU_PRISL0 0x028 261 [PSR] = 0x0128,
263# define TSU_PRISL1 0x02C 262 [RDMLR] = 0x0140,
264# define TSU_FWSL0 0x030 263 [IPGR] = 0x0150,
265# define TSU_FWSL1 0x034 264 [APR] = 0x0154,
266# define TSU_FWSLC 0x038 265 [MPR] = 0x0158,
267# define TSU_QTAGM0 0x040 266 [TPAUSER] = 0x0164,
268# define TSU_QTAGM1 0x044 267 [RFCF] = 0x0160,
269# define TSU_ADQT0 0x048 268 [TPAUSECR] = 0x0168,
270# define TSU_ADQT1 0x04C 269 [BCFRR] = 0x016c,
271# define TSU_FWSR 0x050 270 [MAHR] = 0x01c0,
272# define TSU_FWINMK 0x054 271 [MALR] = 0x01c8,
273# define TSU_ADSBSY 0x060 272 [TROCR] = 0x01d0,
274# define TSU_TEN 0x064 273 [CDCR] = 0x01d4,
275# define TSU_POST1 0x070 274 [LCCR] = 0x01d8,
276# define TSU_POST2 0x074 275 [CNDCR] = 0x01dc,
277# define TSU_POST3 0x078 276 [CEFCR] = 0x01e4,
278# define TSU_POST4 0x07C 277 [FRECR] = 0x01e8,
279# define TXNLCR0 0x080 278 [TSFRCR] = 0x01ec,
280# define TXALCR0 0x084 279 [TLFRCR] = 0x01f0,
281# define RXNLCR0 0x088 280 [RFCR] = 0x01f4,
282# define RXALCR0 0x08C 281 [MAFCR] = 0x01f8,
283# define FWNLCR0 0x090 282 [RTRATE] = 0x01fc,
284# define FWALCR0 0x094 283
285# define TXNLCR1 0x0A0 284 [EDMR] = 0x0000,
286# define TXALCR1 0x0A4 285 [EDTRR] = 0x0008,
287# define RXNLCR1 0x0A8 286 [EDRRR] = 0x0010,
288# define RXALCR1 0x0AC 287 [TDLAR] = 0x0018,
289# define FWNLCR1 0x0B0 288 [RDLAR] = 0x0020,
290# define FWALCR1 0x0B4 289 [EESR] = 0x0028,
291 290 [EESIPR] = 0x0030,
292#define TSU_ADRH0 0x0100 291 [TRSCER] = 0x0038,
293#define TSU_ADRL0 0x0104 292 [RMFCR] = 0x0040,
294#define TSU_ADRL31 0x01FC 293 [TFTR] = 0x0048,
295 294 [FDR] = 0x0050,
296#endif /* CONFIG_CPU_SUBTYPE_SH7763 */ 295 [RMCR] = 0x0058,
297 296 [TFUCR] = 0x0064,
298/* There are avoid compile error... */ 297 [RFOCR] = 0x0068,
299#if !defined(BCULR) 298 [FCFTR] = 0x0070,
300#define BCULR 0x0fc 299 [RPADIR] = 0x0078,
301#endif 300 [TRIMD] = 0x007c,
302#if !defined(TRIMD) 301 [RBWAR] = 0x00c8,
303#define TRIMD 0x0fc 302 [RDFAR] = 0x00cc,
304#endif 303 [TBRAR] = 0x00d4,
305#if !defined(APR) 304 [TDFAR] = 0x00d8,
306#define APR 0x0fc 305};
307#endif 306
308#if !defined(MPR) 307static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
309#define MPR 0x0fc 308 [ECMR] = 0x0160,
310#endif 309 [ECSR] = 0x0164,
311#if !defined(TPAUSER) 310 [ECSIPR] = 0x0168,
312#define TPAUSER 0x0fc 311 [PIR] = 0x016c,
313#endif 312 [MAHR] = 0x0170,
313 [MALR] = 0x0174,
314 [RFLR] = 0x0178,
315 [PSR] = 0x017c,
316 [TROCR] = 0x0180,
317 [CDCR] = 0x0184,
318 [LCCR] = 0x0188,
319 [CNDCR] = 0x018c,
320 [CEFCR] = 0x0194,
321 [FRECR] = 0x0198,
322 [TSFRCR] = 0x019c,
323 [TLFRCR] = 0x01a0,
324 [RFCR] = 0x01a4,
325 [MAFCR] = 0x01a8,
326 [IPGR] = 0x01b4,
327 [APR] = 0x01b8,
328 [MPR] = 0x01bc,
329 [TPAUSER] = 0x01c4,
330 [BCFR] = 0x01cc,
331
332 [ARSTR] = 0x0000,
333 [TSU_CTRST] = 0x0004,
334 [TSU_FWEN0] = 0x0010,
335 [TSU_FWEN1] = 0x0014,
336 [TSU_FCM] = 0x0018,
337 [TSU_BSYSL0] = 0x0020,
338 [TSU_BSYSL1] = 0x0024,
339 [TSU_PRISL0] = 0x0028,
340 [TSU_PRISL1] = 0x002c,
341 [TSU_FWSL0] = 0x0030,
342 [TSU_FWSL1] = 0x0034,
343 [TSU_FWSLC] = 0x0038,
344 [TSU_QTAGM0] = 0x0040,
345 [TSU_QTAGM1] = 0x0044,
346 [TSU_ADQT0] = 0x0048,
347 [TSU_ADQT1] = 0x004c,
348 [TSU_FWSR] = 0x0050,
349 [TSU_FWINMK] = 0x0054,
350 [TSU_ADSBSY] = 0x0060,
351 [TSU_TEN] = 0x0064,
352 [TSU_POST1] = 0x0070,
353 [TSU_POST2] = 0x0074,
354 [TSU_POST3] = 0x0078,
355 [TSU_POST4] = 0x007c,
356
357 [TXNLCR0] = 0x0080,
358 [TXALCR0] = 0x0084,
359 [RXNLCR0] = 0x0088,
360 [RXALCR0] = 0x008c,
361 [FWNLCR0] = 0x0090,
362 [FWALCR0] = 0x0094,
363 [TXNLCR1] = 0x00a0,
364 [TXALCR1] = 0x00a0,
365 [RXNLCR1] = 0x00a8,
366 [RXALCR1] = 0x00ac,
367 [FWNLCR1] = 0x00b0,
368 [FWALCR1] = 0x00b4,
369
370 [TSU_ADRH0] = 0x0100,
371 [TSU_ADRL0] = 0x0104,
372 [TSU_ADRL31] = 0x01fc,
373
374};
314 375
315/* Driver's parameters */ 376/* Driver's parameters */
316#if defined(CONFIG_CPU_SH4) 377#if defined(CONFIG_CPU_SH4)
@@ -339,20 +400,14 @@ enum GECMR_BIT {
339enum DMAC_M_BIT { 400enum DMAC_M_BIT {
340 EDMR_EL = 0x40, /* Litte endian */ 401 EDMR_EL = 0x40, /* Litte endian */
341 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 402 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
342#ifdef CONFIG_CPU_SUBTYPE_SH7763 403 EDMR_SRST_GETHER = 0x03,
343 EDMR_SRST = 0x03, 404 EDMR_SRST_ETHER = 0x01,
344#else /* CONFIG_CPU_SUBTYPE_SH7763 */
345 EDMR_SRST = 0x01,
346#endif
347}; 405};
348 406
349/* EDTRR */ 407/* EDTRR */
350enum DMAC_T_BIT { 408enum DMAC_T_BIT {
351#ifdef CONFIG_CPU_SUBTYPE_SH7763 409 EDTRR_TRNS_GETHER = 0x03,
352 EDTRR_TRNS = 0x03, 410 EDTRR_TRNS_ETHER = 0x01,
353#else
354 EDTRR_TRNS = 0x01,
355#endif
356}; 411};
357 412
358/* EDRRR*/ 413/* EDRRR*/
@@ -696,6 +751,7 @@ struct sh_eth_cpu_data {
696 unsigned mpr:1; /* EtherC have MPR */ 751 unsigned mpr:1; /* EtherC have MPR */
697 unsigned tpauser:1; /* EtherC have TPAUSER */ 752 unsigned tpauser:1; /* EtherC have TPAUSER */
698 unsigned bculr:1; /* EtherC have BCULR */ 753 unsigned bculr:1; /* EtherC have BCULR */
754 unsigned tsu:1; /* EtherC have TSU */
699 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */ 755 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
700 unsigned rpadir:1; /* E-DMAC have RPADIR */ 756 unsigned rpadir:1; /* E-DMAC have RPADIR */
701 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ 757 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
@@ -705,6 +761,8 @@ struct sh_eth_cpu_data {
705struct sh_eth_private { 761struct sh_eth_private {
706 struct platform_device *pdev; 762 struct platform_device *pdev;
707 struct sh_eth_cpu_data *cd; 763 struct sh_eth_cpu_data *cd;
764 const u16 *reg_offset;
765 void __iomem *tsu_addr;
708 dma_addr_t rx_desc_dma; 766 dma_addr_t rx_desc_dma;
709 dma_addr_t tx_desc_dma; 767 dma_addr_t tx_desc_dma;
710 struct sh_eth_rxdesc *rx_ring; 768 struct sh_eth_rxdesc *rx_ring;
@@ -723,6 +781,7 @@ struct sh_eth_private {
723 struct mii_bus *mii_bus; /* MDIO bus control */ 781 struct mii_bus *mii_bus; /* MDIO bus control */
724 struct phy_device *phydev; /* PHY device control */ 782 struct phy_device *phydev; /* PHY device control */
725 enum phy_state link; 783 enum phy_state link;
784 phy_interface_t phy_interface;
726 int msg_enable; 785 int msg_enable;
727 int speed; 786 int speed;
728 int duplex; 787 int duplex;
@@ -747,4 +806,32 @@ static inline void sh_eth_soft_swap(char *src, int len)
747#endif 806#endif
748} 807}
749 808
809static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
810 int enum_index)
811{
812 struct sh_eth_private *mdp = netdev_priv(ndev);
813
814 writel(data, ndev->base_addr + mdp->reg_offset[enum_index]);
815}
816
817static inline unsigned long sh_eth_read(struct net_device *ndev,
818 int enum_index)
819{
820 struct sh_eth_private *mdp = netdev_priv(ndev);
821
822 return readl(ndev->base_addr + mdp->reg_offset[enum_index]);
823}
824
825static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
826 unsigned long data, int enum_index)
827{
828 writel(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
829}
830
831static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
832 int enum_index)
833{
834 return readl(mdp->tsu_addr + mdp->reg_offset[enum_index]);
835}
836
750#endif /* #ifndef __SH_ETH_H__ */ 837#endif /* #ifndef __SH_ETH_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 14:30:39 -0400