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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/net/sfc/falcon.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/net/sfc/falcon.c')
-rw-r--r--drivers/net/sfc/falcon.c2839
1 files changed, 759 insertions, 2080 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index c049364aec46..08278e7302b3 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -1,7 +1,7 @@
1/**************************************************************************** 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards 2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd. 3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc. 4 * Copyright 2006-2009 Solarflare Communications Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published 7 * under the terms of the GNU General Public License version 2 as published
@@ -14,66 +14,21 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/seq_file.h> 15#include <linux/seq_file.h>
16#include <linux/i2c.h> 16#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
18#include <linux/mii.h> 17#include <linux/mii.h>
18#include <linux/slab.h>
19#include "net_driver.h" 19#include "net_driver.h"
20#include "bitfield.h" 20#include "bitfield.h"
21#include "efx.h" 21#include "efx.h"
22#include "mac.h" 22#include "mac.h"
23#include "spi.h" 23#include "spi.h"
24#include "falcon.h" 24#include "nic.h"
25#include "falcon_hwdefs.h" 25#include "regs.h"
26#include "falcon_io.h" 26#include "io.h"
27#include "mdio_10g.h" 27#include "mdio_10g.h"
28#include "phy.h" 28#include "phy.h"
29#include "boards.h"
30#include "workarounds.h" 29#include "workarounds.h"
31 30
32/* Falcon hardware control. 31/* Hardware control for SFC4000 (aka Falcon). */
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37/**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
42 * @int_error_count: Number of internal errors seen recently
43 * @int_error_expire: Time at which error count will be expired
44 */
45struct falcon_nic_data {
46 unsigned next_buffer_table;
47 struct pci_dev *pci_dev2;
48 struct i2c_algo_bit_data i2c_data;
49
50 unsigned int_error_count;
51 unsigned long int_error_expire;
52};
53
54/**************************************************************************
55 *
56 * Configurable values
57 *
58 **************************************************************************
59 */
60
61static int disable_dma_stats;
62
63/* This is set to 16 for a good reason. In summary, if larger than
64 * 16, the descriptor cache holds more than a default socket
65 * buffer's worth of packets (for UDP we can only have at most one
66 * socket buffer's worth outstanding). This combined with the fact
67 * that we only get 1 TX event per descriptor cache means the NIC
68 * goes idle.
69 */
70#define TX_DC_ENTRIES 16
71#define TX_DC_ENTRIES_ORDER 0
72#define TX_DC_BASE 0x130000
73
74#define RX_DC_ENTRIES 64
75#define RX_DC_ENTRIES_ORDER 2
76#define RX_DC_BASE 0x100000
77 32
78static const unsigned int 33static const unsigned int
79/* "Large" EEPROM device: Atmel AT25640 or similar 34/* "Large" EEPROM device: Atmel AT25640 or similar
@@ -89,104 +44,6 @@ default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
89 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) 44 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
90 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); 45 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
91 46
92/* RX FIFO XOFF watermark
93 *
94 * When the amount of the RX FIFO increases used increases past this
95 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
96 * This also has an effect on RX/TX arbitration
97 */
98static int rx_xoff_thresh_bytes = -1;
99module_param(rx_xoff_thresh_bytes, int, 0644);
100MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
101
102/* RX FIFO XON watermark
103 *
104 * When the amount of the RX FIFO used decreases below this
105 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
106 * This also has an effect on RX/TX arbitration
107 */
108static int rx_xon_thresh_bytes = -1;
109module_param(rx_xon_thresh_bytes, int, 0644);
110MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
111
112/* TX descriptor ring size - min 512 max 4k */
113#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
114#define FALCON_TXD_RING_SIZE 1024
115#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
116
117/* RX descriptor ring size - min 512 max 4k */
118#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
119#define FALCON_RXD_RING_SIZE 1024
120#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
121
122/* Event queue size - max 32k */
123#define FALCON_EVQ_ORDER EVQ_SIZE_4K
124#define FALCON_EVQ_SIZE 4096
125#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
126
127/* If FALCON_MAX_INT_ERRORS internal errors occur within
128 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
129 * disable it.
130 */
131#define FALCON_INT_ERROR_EXPIRE 3600
132#define FALCON_MAX_INT_ERRORS 5
133
134/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
135 */
136#define FALCON_FLUSH_INTERVAL 10
137#define FALCON_FLUSH_POLL_COUNT 100
138
139/**************************************************************************
140 *
141 * Falcon constants
142 *
143 **************************************************************************
144 */
145
146/* DMA address mask */
147#define FALCON_DMA_MASK DMA_BIT_MASK(46)
148
149/* TX DMA length mask (13-bit) */
150#define FALCON_TX_DMA_MASK (4096 - 1)
151
152/* Size and alignment of special buffers (4KB) */
153#define FALCON_BUF_SIZE 4096
154
155/* Dummy SRAM size code */
156#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
157
158#define FALCON_IS_DUAL_FUNC(efx) \
159 (falcon_rev(efx) < FALCON_REV_B0)
160
161/**************************************************************************
162 *
163 * Falcon hardware access
164 *
165 **************************************************************************/
166
167/* Read the current event from the event queue */
168static inline efx_qword_t *falcon_event(struct efx_channel *channel,
169 unsigned int index)
170{
171 return (((efx_qword_t *) (channel->eventq.addr)) + index);
172}
173
174/* See if an event is present
175 *
176 * We check both the high and low dword of the event for all ones. We
177 * wrote all ones when we cleared the event, and no valid event can
178 * have all ones in either its high or low dwords. This approach is
179 * robust against reordering.
180 *
181 * Note that using a single 64-bit comparison is incorrect; even
182 * though the CPU read will be atomic, the DMA write may not be.
183 */
184static inline int falcon_event_present(efx_qword_t *event)
185{
186 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
187 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
188}
189
190/************************************************************************** 47/**************************************************************************
191 * 48 *
192 * I2C bus - this is a bit-bashing interface using GPIO pins 49 * I2C bus - this is a bit-bashing interface using GPIO pins
@@ -200,9 +57,9 @@ static void falcon_setsda(void *data, int state)
200 struct efx_nic *efx = (struct efx_nic *)data; 57 struct efx_nic *efx = (struct efx_nic *)data;
201 efx_oword_t reg; 58 efx_oword_t reg;
202 59
203 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 60 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
204 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state); 61 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
205 falcon_write(efx, &reg, GPIO_CTL_REG_KER); 62 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
206} 63}
207 64
208static void falcon_setscl(void *data, int state) 65static void falcon_setscl(void *data, int state)
@@ -210,9 +67,9 @@ static void falcon_setscl(void *data, int state)
210 struct efx_nic *efx = (struct efx_nic *)data; 67 struct efx_nic *efx = (struct efx_nic *)data;
211 efx_oword_t reg; 68 efx_oword_t reg;
212 69
213 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 70 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
214 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state); 71 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
215 falcon_write(efx, &reg, GPIO_CTL_REG_KER); 72 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
216} 73}
217 74
218static int falcon_getsda(void *data) 75static int falcon_getsda(void *data)
@@ -220,8 +77,8 @@ static int falcon_getsda(void *data)
220 struct efx_nic *efx = (struct efx_nic *)data; 77 struct efx_nic *efx = (struct efx_nic *)data;
221 efx_oword_t reg; 78 efx_oword_t reg;
222 79
223 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 80 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
224 return EFX_OWORD_FIELD(reg, GPIO3_IN); 81 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
225} 82}
226 83
227static int falcon_getscl(void *data) 84static int falcon_getscl(void *data)
@@ -229,8 +86,8 @@ static int falcon_getscl(void *data)
229 struct efx_nic *efx = (struct efx_nic *)data; 86 struct efx_nic *efx = (struct efx_nic *)data;
230 efx_oword_t reg; 87 efx_oword_t reg;
231 88
232 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 89 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
233 return EFX_OWORD_FIELD(reg, GPIO0_IN); 90 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
234} 91}
235 92
236static struct i2c_algo_bit_data falcon_i2c_bit_operations = { 93static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
@@ -243,1115 +100,39 @@ static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
243 .timeout = DIV_ROUND_UP(HZ, 20), 100 .timeout = DIV_ROUND_UP(HZ, 20),
244}; 101};
245 102
246/************************************************************************** 103static void falcon_push_irq_moderation(struct efx_channel *channel)
247 *
248 * Falcon special buffer handling
249 * Special buffers are used for event queues and the TX and RX
250 * descriptor rings.
251 *
252 *************************************************************************/
253
254/*
255 * Initialise a Falcon special buffer
256 *
257 * This will define a buffer (previously allocated via
258 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
259 * it to be used for event queues, descriptor rings etc.
260 */
261static void
262falcon_init_special_buffer(struct efx_nic *efx,
263 struct efx_special_buffer *buffer)
264{
265 efx_qword_t buf_desc;
266 int index;
267 dma_addr_t dma_addr;
268 int i;
269
270 EFX_BUG_ON_PARANOID(!buffer->addr);
271
272 /* Write buffer descriptors to NIC */
273 for (i = 0; i < buffer->entries; i++) {
274 index = buffer->index + i;
275 dma_addr = buffer->dma_addr + (i * 4096);
276 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
277 index, (unsigned long long)dma_addr);
278 EFX_POPULATE_QWORD_4(buf_desc,
279 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
280 BUF_ADR_REGION, 0,
281 BUF_ADR_FBUF, (dma_addr >> 12),
282 BUF_OWNER_ID_FBUF, 0);
283 falcon_write_sram(efx, &buf_desc, index);
284 }
285}
286
287/* Unmaps a buffer from Falcon and clears the buffer table entries */
288static void
289falcon_fini_special_buffer(struct efx_nic *efx,
290 struct efx_special_buffer *buffer)
291{
292 efx_oword_t buf_tbl_upd;
293 unsigned int start = buffer->index;
294 unsigned int end = (buffer->index + buffer->entries - 1);
295
296 if (!buffer->entries)
297 return;
298
299 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
300 buffer->index, buffer->index + buffer->entries - 1);
301
302 EFX_POPULATE_OWORD_4(buf_tbl_upd,
303 BUF_UPD_CMD, 0,
304 BUF_CLR_CMD, 1,
305 BUF_CLR_END_ID, end,
306 BUF_CLR_START_ID, start);
307 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
308}
309
310/*
311 * Allocate a new Falcon special buffer
312 *
313 * This allocates memory for a new buffer, clears it and allocates a
314 * new buffer ID range. It does not write into Falcon's buffer table.
315 *
316 * This call will allocate 4KB buffers, since Falcon can't use 8KB
317 * buffers for event queues and descriptor rings.
318 */
319static int falcon_alloc_special_buffer(struct efx_nic *efx,
320 struct efx_special_buffer *buffer,
321 unsigned int len)
322{
323 struct falcon_nic_data *nic_data = efx->nic_data;
324
325 len = ALIGN(len, FALCON_BUF_SIZE);
326
327 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
328 &buffer->dma_addr);
329 if (!buffer->addr)
330 return -ENOMEM;
331 buffer->len = len;
332 buffer->entries = len / FALCON_BUF_SIZE;
333 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
334
335 /* All zeros is a potentially valid event so memset to 0xff */
336 memset(buffer->addr, 0xff, len);
337
338 /* Select new buffer ID */
339 buffer->index = nic_data->next_buffer_table;
340 nic_data->next_buffer_table += buffer->entries;
341
342 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
343 "(virt %p phys %llx)\n", buffer->index,
344 buffer->index + buffer->entries - 1,
345 (u64)buffer->dma_addr, len,
346 buffer->addr, (u64)virt_to_phys(buffer->addr));
347
348 return 0;
349}
350
351static void falcon_free_special_buffer(struct efx_nic *efx,
352 struct efx_special_buffer *buffer)
353{
354 if (!buffer->addr)
355 return;
356
357 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
358 "(virt %p phys %llx)\n", buffer->index,
359 buffer->index + buffer->entries - 1,
360 (u64)buffer->dma_addr, buffer->len,
361 buffer->addr, (u64)virt_to_phys(buffer->addr));
362
363 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
364 buffer->dma_addr);
365 buffer->addr = NULL;
366 buffer->entries = 0;
367}
368
369/**************************************************************************
370 *
371 * Falcon generic buffer handling
372 * These buffers are used for interrupt status and MAC stats
373 *
374 **************************************************************************/
375
376static int falcon_alloc_buffer(struct efx_nic *efx,
377 struct efx_buffer *buffer, unsigned int len)
378{
379 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
380 &buffer->dma_addr);
381 if (!buffer->addr)
382 return -ENOMEM;
383 buffer->len = len;
384 memset(buffer->addr, 0, len);
385 return 0;
386}
387
388static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
389{
390 if (buffer->addr) {
391 pci_free_consistent(efx->pci_dev, buffer->len,
392 buffer->addr, buffer->dma_addr);
393 buffer->addr = NULL;
394 }
395}
396
397/**************************************************************************
398 *
399 * Falcon TX path
400 *
401 **************************************************************************/
402
403/* Returns a pointer to the specified transmit descriptor in the TX
404 * descriptor queue belonging to the specified channel.
405 */
406static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
407 unsigned int index)
408{
409 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
410}
411
412/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
413static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
414{
415 unsigned write_ptr;
416 efx_dword_t reg;
417
418 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
419 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
420 falcon_writel_page(tx_queue->efx, &reg,
421 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
422}
423
424
425/* For each entry inserted into the software descriptor ring, create a
426 * descriptor in the hardware TX descriptor ring (in host memory), and
427 * write a doorbell.
428 */
429void falcon_push_buffers(struct efx_tx_queue *tx_queue)
430{
431
432 struct efx_tx_buffer *buffer;
433 efx_qword_t *txd;
434 unsigned write_ptr;
435
436 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
437
438 do {
439 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
440 buffer = &tx_queue->buffer[write_ptr];
441 txd = falcon_tx_desc(tx_queue, write_ptr);
442 ++tx_queue->write_count;
443
444 /* Create TX descriptor ring entry */
445 EFX_POPULATE_QWORD_5(*txd,
446 TX_KER_PORT, 0,
447 TX_KER_CONT, buffer->continuation,
448 TX_KER_BYTE_CNT, buffer->len,
449 TX_KER_BUF_REGION, 0,
450 TX_KER_BUF_ADR, buffer->dma_addr);
451 } while (tx_queue->write_count != tx_queue->insert_count);
452
453 wmb(); /* Ensure descriptors are written before they are fetched */
454 falcon_notify_tx_desc(tx_queue);
455}
456
457/* Allocate hardware resources for a TX queue */
458int falcon_probe_tx(struct efx_tx_queue *tx_queue)
459{
460 struct efx_nic *efx = tx_queue->efx;
461 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
462 FALCON_TXD_RING_SIZE *
463 sizeof(efx_qword_t));
464}
465
466void falcon_init_tx(struct efx_tx_queue *tx_queue)
467{
468 efx_oword_t tx_desc_ptr;
469 struct efx_nic *efx = tx_queue->efx;
470
471 tx_queue->flushed = false;
472
473 /* Pin TX descriptor ring */
474 falcon_init_special_buffer(efx, &tx_queue->txd);
475
476 /* Push TX descriptor ring to card */
477 EFX_POPULATE_OWORD_10(tx_desc_ptr,
478 TX_DESCQ_EN, 1,
479 TX_ISCSI_DDIG_EN, 0,
480 TX_ISCSI_HDIG_EN, 0,
481 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
482 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
483 TX_DESCQ_OWNER_ID, 0,
484 TX_DESCQ_LABEL, tx_queue->queue,
485 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
486 TX_DESCQ_TYPE, 0,
487 TX_NON_IP_DROP_DIS_B0, 1);
488
489 if (falcon_rev(efx) >= FALCON_REV_B0) {
490 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
491 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
492 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
493 }
494
495 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
496 tx_queue->queue);
497
498 if (falcon_rev(efx) < FALCON_REV_B0) {
499 efx_oword_t reg;
500
501 /* Only 128 bits in this register */
502 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
503
504 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
505 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
506 clear_bit_le(tx_queue->queue, (void *)&reg);
507 else
508 set_bit_le(tx_queue->queue, (void *)&reg);
509 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
510 }
511}
512
513static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
514{
515 struct efx_nic *efx = tx_queue->efx;
516 efx_oword_t tx_flush_descq;
517
518 /* Post a flush command */
519 EFX_POPULATE_OWORD_2(tx_flush_descq,
520 TX_FLUSH_DESCQ_CMD, 1,
521 TX_FLUSH_DESCQ, tx_queue->queue);
522 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
523}
524
525void falcon_fini_tx(struct efx_tx_queue *tx_queue)
526{
527 struct efx_nic *efx = tx_queue->efx;
528 efx_oword_t tx_desc_ptr;
529
530 /* The queue should have been flushed */
531 WARN_ON(!tx_queue->flushed);
532
533 /* Remove TX descriptor ring from card */
534 EFX_ZERO_OWORD(tx_desc_ptr);
535 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
536 tx_queue->queue);
537
538 /* Unpin TX descriptor ring */
539 falcon_fini_special_buffer(efx, &tx_queue->txd);
540}
541
542/* Free buffers backing TX queue */
543void falcon_remove_tx(struct efx_tx_queue *tx_queue)
544{
545 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
546}
547
548/**************************************************************************
549 *
550 * Falcon RX path
551 *
552 **************************************************************************/
553
554/* Returns a pointer to the specified descriptor in the RX descriptor queue */
555static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
556 unsigned int index)
557{
558 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
559}
560
561/* This creates an entry in the RX descriptor queue */
562static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
563 unsigned index)
564{
565 struct efx_rx_buffer *rx_buf;
566 efx_qword_t *rxd;
567
568 rxd = falcon_rx_desc(rx_queue, index);
569 rx_buf = efx_rx_buffer(rx_queue, index);
570 EFX_POPULATE_QWORD_3(*rxd,
571 RX_KER_BUF_SIZE,
572 rx_buf->len -
573 rx_queue->efx->type->rx_buffer_padding,
574 RX_KER_BUF_REGION, 0,
575 RX_KER_BUF_ADR, rx_buf->dma_addr);
576}
577
578/* This writes to the RX_DESC_WPTR register for the specified receive
579 * descriptor ring.
580 */
581void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
582{
583 efx_dword_t reg;
584 unsigned write_ptr;
585
586 while (rx_queue->notified_count != rx_queue->added_count) {
587 falcon_build_rx_desc(rx_queue,
588 rx_queue->notified_count &
589 FALCON_RXD_RING_MASK);
590 ++rx_queue->notified_count;
591 }
592
593 wmb();
594 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
595 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
596 falcon_writel_page(rx_queue->efx, &reg,
597 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
598}
599
600int falcon_probe_rx(struct efx_rx_queue *rx_queue)
601{
602 struct efx_nic *efx = rx_queue->efx;
603 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
604 FALCON_RXD_RING_SIZE *
605 sizeof(efx_qword_t));
606}
607
608void falcon_init_rx(struct efx_rx_queue *rx_queue)
609{
610 efx_oword_t rx_desc_ptr;
611 struct efx_nic *efx = rx_queue->efx;
612 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
613 bool iscsi_digest_en = is_b0;
614
615 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
616 rx_queue->queue, rx_queue->rxd.index,
617 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
618
619 rx_queue->flushed = false;
620
621 /* Pin RX descriptor ring */
622 falcon_init_special_buffer(efx, &rx_queue->rxd);
623
624 /* Push RX descriptor ring to card */
625 EFX_POPULATE_OWORD_10(rx_desc_ptr,
626 RX_ISCSI_DDIG_EN, iscsi_digest_en,
627 RX_ISCSI_HDIG_EN, iscsi_digest_en,
628 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
629 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
630 RX_DESCQ_OWNER_ID, 0,
631 RX_DESCQ_LABEL, rx_queue->queue,
632 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
633 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
634 /* For >=B0 this is scatter so disable */
635 RX_DESCQ_JUMBO, !is_b0,
636 RX_DESCQ_EN, 1);
637 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
638 rx_queue->queue);
639}
640
641static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
642{
643 struct efx_nic *efx = rx_queue->efx;
644 efx_oword_t rx_flush_descq;
645
646 /* Post a flush command */
647 EFX_POPULATE_OWORD_2(rx_flush_descq,
648 RX_FLUSH_DESCQ_CMD, 1,
649 RX_FLUSH_DESCQ, rx_queue->queue);
650 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
651}
652
653void falcon_fini_rx(struct efx_rx_queue *rx_queue)
654{
655 efx_oword_t rx_desc_ptr;
656 struct efx_nic *efx = rx_queue->efx;
657
658 /* The queue should already have been flushed */
659 WARN_ON(!rx_queue->flushed);
660
661 /* Remove RX descriptor ring from card */
662 EFX_ZERO_OWORD(rx_desc_ptr);
663 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
664 rx_queue->queue);
665
666 /* Unpin RX descriptor ring */
667 falcon_fini_special_buffer(efx, &rx_queue->rxd);
668}
669
670/* Free buffers backing RX queue */
671void falcon_remove_rx(struct efx_rx_queue *rx_queue)
672{
673 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
674}
675
676/**************************************************************************
677 *
678 * Falcon event queue processing
679 * Event queues are processed by per-channel tasklets.
680 *
681 **************************************************************************/
682
683/* Update a channel's event queue's read pointer (RPTR) register
684 *
685 * This writes the EVQ_RPTR_REG register for the specified channel's
686 * event queue.
687 *
688 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
689 * whereas channel->eventq_read_ptr contains the index of the "next to
690 * read" event.
691 */
692void falcon_eventq_read_ack(struct efx_channel *channel)
693{
694 efx_dword_t reg;
695 struct efx_nic *efx = channel->efx;
696
697 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
698 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
699 channel->channel);
700}
701
702/* Use HW to insert a SW defined event */
703void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
704{
705 efx_oword_t drv_ev_reg;
706
707 EFX_POPULATE_OWORD_2(drv_ev_reg,
708 DRV_EV_QID, channel->channel,
709 DRV_EV_DATA,
710 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
711 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
712}
713
714/* Handle a transmit completion event
715 *
716 * Falcon batches TX completion events; the message we receive is of
717 * the form "complete all TX events up to this index".
718 */
719static void falcon_handle_tx_event(struct efx_channel *channel,
720 efx_qword_t *event)
721{
722 unsigned int tx_ev_desc_ptr;
723 unsigned int tx_ev_q_label;
724 struct efx_tx_queue *tx_queue;
725 struct efx_nic *efx = channel->efx;
726
727 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
728 /* Transmit completion */
729 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
730 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
731 tx_queue = &efx->tx_queue[tx_ev_q_label];
732 channel->irq_mod_score +=
733 (tx_ev_desc_ptr - tx_queue->read_count) &
734 efx->type->txd_ring_mask;
735 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
736 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
737 /* Rewrite the FIFO write pointer */
738 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
739 tx_queue = &efx->tx_queue[tx_ev_q_label];
740
741 if (efx_dev_registered(efx))
742 netif_tx_lock(efx->net_dev);
743 falcon_notify_tx_desc(tx_queue);
744 if (efx_dev_registered(efx))
745 netif_tx_unlock(efx->net_dev);
746 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
747 EFX_WORKAROUND_10727(efx)) {
748 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
749 } else {
750 EFX_ERR(efx, "channel %d unexpected TX event "
751 EFX_QWORD_FMT"\n", channel->channel,
752 EFX_QWORD_VAL(*event));
753 }
754}
755
756/* Detect errors included in the rx_evt_pkt_ok bit. */
757static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
758 const efx_qword_t *event,
759 bool *rx_ev_pkt_ok,
760 bool *discard)
761{
762 struct efx_nic *efx = rx_queue->efx;
763 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
764 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
765 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
766 bool rx_ev_other_err, rx_ev_pause_frm;
767 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
768 unsigned rx_ev_pkt_type;
769
770 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
771 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
772 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
773 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
774 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
775 RX_EV_BUF_OWNER_ID_ERR);
776 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
777 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
778 RX_EV_IP_HDR_CHKSUM_ERR);
779 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
780 RX_EV_TCP_UDP_CHKSUM_ERR);
781 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
782 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
783 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
784 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
785 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
786
787 /* Every error apart from tobe_disc and pause_frm */
788 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
789 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
790 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
791
792 /* Count errors that are not in MAC stats. Ignore expected
793 * checksum errors during self-test. */
794 if (rx_ev_frm_trunc)
795 ++rx_queue->channel->n_rx_frm_trunc;
796 else if (rx_ev_tobe_disc)
797 ++rx_queue->channel->n_rx_tobe_disc;
798 else if (!efx->loopback_selftest) {
799 if (rx_ev_ip_hdr_chksum_err)
800 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
801 else if (rx_ev_tcp_udp_chksum_err)
802 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
803 }
804 if (rx_ev_ip_frag_err)
805 ++rx_queue->channel->n_rx_ip_frag_err;
806
807 /* The frame must be discarded if any of these are true. */
808 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
809 rx_ev_tobe_disc | rx_ev_pause_frm);
810
811 /* TOBE_DISC is expected on unicast mismatches; don't print out an
812 * error message. FRM_TRUNC indicates RXDP dropped the packet due
813 * to a FIFO overflow.
814 */
815#ifdef EFX_ENABLE_DEBUG
816 if (rx_ev_other_err) {
817 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
818 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
819 rx_queue->queue, EFX_QWORD_VAL(*event),
820 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
821 rx_ev_ip_hdr_chksum_err ?
822 " [IP_HDR_CHKSUM_ERR]" : "",
823 rx_ev_tcp_udp_chksum_err ?
824 " [TCP_UDP_CHKSUM_ERR]" : "",
825 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
826 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
827 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
828 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
829 rx_ev_pause_frm ? " [PAUSE]" : "");
830 }
831#endif
832}
833
834/* Handle receive events that are not in-order. */
835static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
836 unsigned index)
837{
838 struct efx_nic *efx = rx_queue->efx;
839 unsigned expected, dropped;
840
841 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
842 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
843 FALCON_RXD_RING_MASK);
844 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
845 dropped, index, expected);
846
847 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
848 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
849}
850
851/* Handle a packet received event
852 *
853 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
854 * wrong destination address
855 * Also "is multicast" and "matches multicast filter" flags can be used to
856 * discard non-matching multicast packets.
857 */
858static void falcon_handle_rx_event(struct efx_channel *channel,
859 const efx_qword_t *event)
860{
861 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
862 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
863 unsigned expected_ptr;
864 bool rx_ev_pkt_ok, discard = false, checksummed;
865 struct efx_rx_queue *rx_queue;
866 struct efx_nic *efx = channel->efx;
867
868 /* Basic packet information */
869 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
870 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
871 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
872 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
873 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
874 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
875
876 rx_queue = &efx->rx_queue[channel->channel];
877
878 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
879 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
880 if (unlikely(rx_ev_desc_ptr != expected_ptr))
881 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
882
883 if (likely(rx_ev_pkt_ok)) {
884 /* If packet is marked as OK and packet type is TCP/IPv4 or
885 * UDP/IPv4, then we can rely on the hardware checksum.
886 */
887 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
888 } else {
889 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
890 &discard);
891 checksummed = false;
892 }
893
894 /* Detect multicast packets that didn't match the filter */
895 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
896 if (rx_ev_mcast_pkt) {
897 unsigned int rx_ev_mcast_hash_match =
898 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
899
900 if (unlikely(!rx_ev_mcast_hash_match))
901 discard = true;
902 }
903
904 channel->irq_mod_score += 2;
905
906 /* Handle received packet */
907 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
908 checksummed, discard);
909}
910
911/* Global events are basically PHY events */
912static void falcon_handle_global_event(struct efx_channel *channel,
913 efx_qword_t *event)
914{
915 struct efx_nic *efx = channel->efx;
916 bool handled = false;
917
918 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
919 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
920 EFX_QWORD_FIELD(*event, XG_PHY_INTR) ||
921 EFX_QWORD_FIELD(*event, XFP_PHY_INTR)) {
922 efx->phy_op->clear_interrupt(efx);
923 queue_work(efx->workqueue, &efx->phy_work);
924 handled = true;
925 }
926
927 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
928 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0)) {
929 queue_work(efx->workqueue, &efx->mac_work);
930 handled = true;
931 }
932
933 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
934 EFX_ERR(efx, "channel %d seen global RX_RESET "
935 "event. Resetting.\n", channel->channel);
936
937 atomic_inc(&efx->rx_reset);
938 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
939 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
940 handled = true;
941 }
942
943 if (!handled)
944 EFX_ERR(efx, "channel %d unknown global event "
945 EFX_QWORD_FMT "\n", channel->channel,
946 EFX_QWORD_VAL(*event));
947}
948
949static void falcon_handle_driver_event(struct efx_channel *channel,
950 efx_qword_t *event)
951{
952 struct efx_nic *efx = channel->efx;
953 unsigned int ev_sub_code;
954 unsigned int ev_sub_data;
955
956 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
957 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
958
959 switch (ev_sub_code) {
960 case TX_DESCQ_FLS_DONE_EV_DECODE:
961 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
962 channel->channel, ev_sub_data);
963 break;
964 case RX_DESCQ_FLS_DONE_EV_DECODE:
965 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
966 channel->channel, ev_sub_data);
967 break;
968 case EVQ_INIT_DONE_EV_DECODE:
969 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
970 channel->channel, ev_sub_data);
971 break;
972 case SRM_UPD_DONE_EV_DECODE:
973 EFX_TRACE(efx, "channel %d SRAM update done\n",
974 channel->channel);
975 break;
976 case WAKE_UP_EV_DECODE:
977 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
978 channel->channel, ev_sub_data);
979 break;
980 case TIMER_EV_DECODE:
981 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
982 channel->channel, ev_sub_data);
983 break;
984 case RX_RECOVERY_EV_DECODE:
985 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
986 "Resetting.\n", channel->channel);
987 atomic_inc(&efx->rx_reset);
988 efx_schedule_reset(efx,
989 EFX_WORKAROUND_6555(efx) ?
990 RESET_TYPE_RX_RECOVERY :
991 RESET_TYPE_DISABLE);
992 break;
993 case RX_DSC_ERROR_EV_DECODE:
994 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
995 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
996 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
997 break;
998 case TX_DSC_ERROR_EV_DECODE:
999 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1000 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1001 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1002 break;
1003 default:
1004 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1005 "data %04x\n", channel->channel, ev_sub_code,
1006 ev_sub_data);
1007 break;
1008 }
1009}
1010
1011int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1012{
1013 unsigned int read_ptr;
1014 efx_qword_t event, *p_event;
1015 int ev_code;
1016 int rx_packets = 0;
1017
1018 read_ptr = channel->eventq_read_ptr;
1019
1020 do {
1021 p_event = falcon_event(channel, read_ptr);
1022 event = *p_event;
1023
1024 if (!falcon_event_present(&event))
1025 /* End of events */
1026 break;
1027
1028 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1029 channel->channel, EFX_QWORD_VAL(event));
1030
1031 /* Clear this event by marking it all ones */
1032 EFX_SET_QWORD(*p_event);
1033
1034 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1035
1036 switch (ev_code) {
1037 case RX_IP_EV_DECODE:
1038 falcon_handle_rx_event(channel, &event);
1039 ++rx_packets;
1040 break;
1041 case TX_IP_EV_DECODE:
1042 falcon_handle_tx_event(channel, &event);
1043 break;
1044 case DRV_GEN_EV_DECODE:
1045 channel->eventq_magic
1046 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1047 EFX_LOG(channel->efx, "channel %d received generated "
1048 "event "EFX_QWORD_FMT"\n", channel->channel,
1049 EFX_QWORD_VAL(event));
1050 break;
1051 case GLOBAL_EV_DECODE:
1052 falcon_handle_global_event(channel, &event);
1053 break;
1054 case DRIVER_EV_DECODE:
1055 falcon_handle_driver_event(channel, &event);
1056 break;
1057 default:
1058 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1059 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1060 ev_code, EFX_QWORD_VAL(event));
1061 }
1062
1063 /* Increment read pointer */
1064 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1065
1066 } while (rx_packets < rx_quota);
1067
1068 channel->eventq_read_ptr = read_ptr;
1069 return rx_packets;
1070}
1071
1072void falcon_set_int_moderation(struct efx_channel *channel)
1073{ 104{
1074 efx_dword_t timer_cmd; 105 efx_dword_t timer_cmd;
1075 struct efx_nic *efx = channel->efx; 106 struct efx_nic *efx = channel->efx;
1076 107
1077 /* Set timer register */ 108 /* Set timer register */
1078 if (channel->irq_moderation) { 109 if (channel->irq_moderation) {
1079 /* Round to resolution supported by hardware. The value we
1080 * program is based at 0. So actual interrupt moderation
1081 * achieved is ((x + 1) * res).
1082 */
1083 channel->irq_moderation -= (channel->irq_moderation %
1084 FALCON_IRQ_MOD_RESOLUTION);
1085 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1086 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1087 EFX_POPULATE_DWORD_2(timer_cmd, 110 EFX_POPULATE_DWORD_2(timer_cmd,
1088 TIMER_MODE, TIMER_MODE_INT_HLDOFF, 111 FRF_AB_TC_TIMER_MODE,
1089 TIMER_VAL, 112 FFE_BB_TIMER_MODE_INT_HLDOFF,
1090 channel->irq_moderation / 113 FRF_AB_TC_TIMER_VAL,
1091 FALCON_IRQ_MOD_RESOLUTION - 1); 114 channel->irq_moderation - 1);
1092 } else { 115 } else {
1093 EFX_POPULATE_DWORD_2(timer_cmd, 116 EFX_POPULATE_DWORD_2(timer_cmd,
1094 TIMER_MODE, TIMER_MODE_DIS, 117 FRF_AB_TC_TIMER_MODE,
1095 TIMER_VAL, 0); 118 FFE_BB_TIMER_MODE_DIS,
119 FRF_AB_TC_TIMER_VAL, 0);
1096 } 120 }
1097 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER, 121 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1098 channel->channel); 122 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1099 123 channel->channel);
1100} 124}
1101 125
1102/* Allocate buffer table entries for event queue */ 126static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
1103int falcon_probe_eventq(struct efx_channel *channel)
1104{
1105 struct efx_nic *efx = channel->efx;
1106 unsigned int evq_size;
1107 127
1108 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t); 128static void falcon_prepare_flush(struct efx_nic *efx)
1109 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1110}
1111
1112void falcon_init_eventq(struct efx_channel *channel)
1113{ 129{
1114 efx_oword_t evq_ptr; 130 falcon_deconfigure_mac_wrapper(efx);
1115 struct efx_nic *efx = channel->efx;
1116
1117 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1118 channel->channel, channel->eventq.index,
1119 channel->eventq.index + channel->eventq.entries - 1);
1120
1121 /* Pin event queue buffer */
1122 falcon_init_special_buffer(efx, &channel->eventq);
1123
1124 /* Fill event queue with all ones (i.e. empty events) */
1125 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1126 131
1127 /* Push event queue to card */ 132 /* Wait for the tx and rx fifo's to get to the next packet boundary
1128 EFX_POPULATE_OWORD_3(evq_ptr, 133 * (~1ms without back-pressure), then to drain the remainder of the
1129 EVQ_EN, 1, 134 * fifo's at data path speeds (negligible), with a healthy margin. */
1130 EVQ_SIZE, FALCON_EVQ_ORDER, 135 msleep(10);
1131 EVQ_BUF_BASE_ID, channel->eventq.index);
1132 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1133 channel->channel);
1134
1135 falcon_set_int_moderation(channel);
1136}
1137
1138void falcon_fini_eventq(struct efx_channel *channel)
1139{
1140 efx_oword_t eventq_ptr;
1141 struct efx_nic *efx = channel->efx;
1142
1143 /* Remove event queue from card */
1144 EFX_ZERO_OWORD(eventq_ptr);
1145 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1146 channel->channel);
1147
1148 /* Unpin event queue */
1149 falcon_fini_special_buffer(efx, &channel->eventq);
1150}
1151
1152/* Free buffers backing event queue */
1153void falcon_remove_eventq(struct efx_channel *channel)
1154{
1155 falcon_free_special_buffer(channel->efx, &channel->eventq);
1156}
1157
1158
1159/* Generates a test event on the event queue. A subsequent call to
1160 * process_eventq() should pick up the event and place the value of
1161 * "magic" into channel->eventq_magic;
1162 */
1163void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1164{
1165 efx_qword_t test_event;
1166
1167 EFX_POPULATE_QWORD_2(test_event,
1168 EV_CODE, DRV_GEN_EV_DECODE,
1169 EVQ_MAGIC, magic);
1170 falcon_generate_event(channel, &test_event);
1171}
1172
1173void falcon_sim_phy_event(struct efx_nic *efx)
1174{
1175 efx_qword_t phy_event;
1176
1177 EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE);
1178 if (EFX_IS10G(efx))
1179 EFX_SET_QWORD_FIELD(phy_event, XG_PHY_INTR, 1);
1180 else
1181 EFX_SET_QWORD_FIELD(phy_event, G_PHY0_INTR, 1);
1182
1183 falcon_generate_event(&efx->channel[0], &phy_event);
1184}
1185
1186/**************************************************************************
1187 *
1188 * Flush handling
1189 *
1190 **************************************************************************/
1191
1192
1193static void falcon_poll_flush_events(struct efx_nic *efx)
1194{
1195 struct efx_channel *channel = &efx->channel[0];
1196 struct efx_tx_queue *tx_queue;
1197 struct efx_rx_queue *rx_queue;
1198 unsigned int read_ptr = channel->eventq_read_ptr;
1199 unsigned int end_ptr = (read_ptr - 1) & FALCON_EVQ_MASK;
1200
1201 do {
1202 efx_qword_t *event = falcon_event(channel, read_ptr);
1203 int ev_code, ev_sub_code, ev_queue;
1204 bool ev_failed;
1205
1206 if (!falcon_event_present(event))
1207 break;
1208
1209 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1210 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1211 if (ev_code == DRIVER_EV_DECODE &&
1212 ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) {
1213 ev_queue = EFX_QWORD_FIELD(*event,
1214 DRIVER_EV_TX_DESCQ_ID);
1215 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1216 tx_queue = efx->tx_queue + ev_queue;
1217 tx_queue->flushed = true;
1218 }
1219 } else if (ev_code == DRIVER_EV_DECODE &&
1220 ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) {
1221 ev_queue = EFX_QWORD_FIELD(*event,
1222 DRIVER_EV_RX_DESCQ_ID);
1223 ev_failed = EFX_QWORD_FIELD(*event,
1224 DRIVER_EV_RX_FLUSH_FAIL);
1225 if (ev_queue < efx->n_rx_queues) {
1226 rx_queue = efx->rx_queue + ev_queue;
1227
1228 /* retry the rx flush */
1229 if (ev_failed)
1230 falcon_flush_rx_queue(rx_queue);
1231 else
1232 rx_queue->flushed = true;
1233 }
1234 }
1235
1236 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1237 } while (read_ptr != end_ptr);
1238}
1239
1240/* Handle tx and rx flushes at the same time, since they run in
1241 * parallel in the hardware and there's no reason for us to
1242 * serialise them */
1243int falcon_flush_queues(struct efx_nic *efx)
1244{
1245 struct efx_rx_queue *rx_queue;
1246 struct efx_tx_queue *tx_queue;
1247 int i;
1248 bool outstanding;
1249
1250 /* Issue flush requests */
1251 efx_for_each_tx_queue(tx_queue, efx) {
1252 tx_queue->flushed = false;
1253 falcon_flush_tx_queue(tx_queue);
1254 }
1255 efx_for_each_rx_queue(rx_queue, efx) {
1256 rx_queue->flushed = false;
1257 falcon_flush_rx_queue(rx_queue);
1258 }
1259
1260 /* Poll the evq looking for flush completions. Since we're not pushing
1261 * any more rx or tx descriptors at this point, we're in no danger of
1262 * overflowing the evq whilst we wait */
1263 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1264 msleep(FALCON_FLUSH_INTERVAL);
1265 falcon_poll_flush_events(efx);
1266
1267 /* Check if every queue has been succesfully flushed */
1268 outstanding = false;
1269 efx_for_each_tx_queue(tx_queue, efx)
1270 outstanding |= !tx_queue->flushed;
1271 efx_for_each_rx_queue(rx_queue, efx)
1272 outstanding |= !rx_queue->flushed;
1273 if (!outstanding)
1274 return 0;
1275 }
1276
1277 /* Mark the queues as all flushed. We're going to return failure
1278 * leading to a reset, or fake up success anyway. "flushed" now
1279 * indicates that we tried to flush. */
1280 efx_for_each_tx_queue(tx_queue, efx) {
1281 if (!tx_queue->flushed)
1282 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1283 tx_queue->queue);
1284 tx_queue->flushed = true;
1285 }
1286 efx_for_each_rx_queue(rx_queue, efx) {
1287 if (!rx_queue->flushed)
1288 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1289 rx_queue->queue);
1290 rx_queue->flushed = true;
1291 }
1292
1293 if (EFX_WORKAROUND_7803(efx))
1294 return 0;
1295
1296 return -ETIMEDOUT;
1297}
1298
1299/**************************************************************************
1300 *
1301 * Falcon hardware interrupts
1302 * The hardware interrupt handler does very little work; all the event
1303 * queue processing is carried out by per-channel tasklets.
1304 *
1305 **************************************************************************/
1306
1307/* Enable/disable/generate Falcon interrupts */
1308static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1309 int force)
1310{
1311 efx_oword_t int_en_reg_ker;
1312
1313 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1314 KER_INT_KER, force,
1315 DRV_INT_EN_KER, enabled);
1316 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1317}
1318
1319void falcon_enable_interrupts(struct efx_nic *efx)
1320{
1321 efx_oword_t int_adr_reg_ker;
1322 struct efx_channel *channel;
1323
1324 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1325 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1326
1327 /* Program address */
1328 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1329 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1330 INT_ADR_KER, efx->irq_status.dma_addr);
1331 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1332
1333 /* Enable interrupts */
1334 falcon_interrupts(efx, 1, 0);
1335
1336 /* Force processing of all the channels to get the EVQ RPTRs up to
1337 date */
1338 efx_for_each_channel(channel, efx)
1339 efx_schedule_channel(channel);
1340}
1341
1342void falcon_disable_interrupts(struct efx_nic *efx)
1343{
1344 /* Disable interrupts */
1345 falcon_interrupts(efx, 0, 0);
1346}
1347
1348/* Generate a Falcon test interrupt
1349 * Interrupt must already have been enabled, otherwise nasty things
1350 * may happen.
1351 */
1352void falcon_generate_interrupt(struct efx_nic *efx)
1353{
1354 falcon_interrupts(efx, 1, 1);
1355} 136}
1356 137
1357/* Acknowledge a legacy interrupt from Falcon 138/* Acknowledge a legacy interrupt from Falcon
@@ -1364,113 +145,17 @@ void falcon_generate_interrupt(struct efx_nic *efx)
1364 * 145 *
1365 * NB most hardware supports MSI interrupts 146 * NB most hardware supports MSI interrupts
1366 */ 147 */
1367static inline void falcon_irq_ack_a1(struct efx_nic *efx) 148inline void falcon_irq_ack_a1(struct efx_nic *efx)
1368{ 149{
1369 efx_dword_t reg; 150 efx_dword_t reg;
1370 151
1371 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e); 152 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1372 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1); 153 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1373 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1); 154 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1374} 155}
1375 156
1376/* Process a fatal interrupt
1377 * Disable bus mastering ASAP and schedule a reset
1378 */
1379static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1380{
1381 struct falcon_nic_data *nic_data = efx->nic_data;
1382 efx_oword_t *int_ker = efx->irq_status.addr;
1383 efx_oword_t fatal_intr;
1384 int error, mem_perr;
1385
1386 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1387 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1388
1389 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1390 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1391 EFX_OWORD_VAL(fatal_intr),
1392 error ? "disabling bus mastering" : "no recognised error");
1393 if (error == 0)
1394 goto out;
1395
1396 /* If this is a memory parity error dump which blocks are offending */
1397 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1398 if (mem_perr) {
1399 efx_oword_t reg;
1400 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1401 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1402 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1403 }
1404
1405 /* Disable both devices */
1406 pci_clear_master(efx->pci_dev);
1407 if (FALCON_IS_DUAL_FUNC(efx))
1408 pci_clear_master(nic_data->pci_dev2);
1409 falcon_disable_interrupts(efx);
1410
1411 /* Count errors and reset or disable the NIC accordingly */
1412 if (nic_data->int_error_count == 0 ||
1413 time_after(jiffies, nic_data->int_error_expire)) {
1414 nic_data->int_error_count = 0;
1415 nic_data->int_error_expire =
1416 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1417 }
1418 if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1419 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1420 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1421 } else {
1422 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1423 "NIC will be disabled\n");
1424 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1425 }
1426out:
1427 return IRQ_HANDLED;
1428}
1429 157
1430/* Handle a legacy interrupt from Falcon 158irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1431 * Acknowledges the interrupt and schedule event queue processing.
1432 */
1433static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1434{
1435 struct efx_nic *efx = dev_id;
1436 efx_oword_t *int_ker = efx->irq_status.addr;
1437 irqreturn_t result = IRQ_NONE;
1438 struct efx_channel *channel;
1439 efx_dword_t reg;
1440 u32 queues;
1441 int syserr;
1442
1443 /* Read the ISR which also ACKs the interrupts */
1444 falcon_readl(efx, &reg, INT_ISR0_B0);
1445 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1446
1447 /* Check to see if we have a serious error condition */
1448 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1449 if (unlikely(syserr))
1450 return falcon_fatal_interrupt(efx);
1451
1452 /* Schedule processing of any interrupting queues */
1453 efx_for_each_channel(channel, efx) {
1454 if ((queues & 1) ||
1455 falcon_event_present(
1456 falcon_event(channel, channel->eventq_read_ptr))) {
1457 efx_schedule_channel(channel);
1458 result = IRQ_HANDLED;
1459 }
1460 queues >>= 1;
1461 }
1462
1463 if (result == IRQ_HANDLED) {
1464 efx->last_irq_cpu = raw_smp_processor_id();
1465 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1466 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1467 }
1468
1469 return result;
1470}
1471
1472
1473static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1474{ 159{
1475 struct efx_nic *efx = dev_id; 160 struct efx_nic *efx = dev_id;
1476 efx_oword_t *int_ker = efx->irq_status.addr; 161 efx_oword_t *int_ker = efx->irq_status.addr;
@@ -1491,15 +176,15 @@ static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1491 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 176 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1492 177
1493 /* Check to see if we have a serious error condition */ 178 /* Check to see if we have a serious error condition */
1494 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); 179 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1495 if (unlikely(syserr)) 180 if (unlikely(syserr))
1496 return falcon_fatal_interrupt(efx); 181 return efx_nic_fatal_interrupt(efx);
1497 182
1498 /* Determine interrupting queues, clear interrupt status 183 /* Determine interrupting queues, clear interrupt status
1499 * register and acknowledge the device interrupt. 184 * register and acknowledge the device interrupt.
1500 */ 185 */
1501 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS); 186 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
1502 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS); 187 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
1503 EFX_ZERO_OWORD(*int_ker); 188 EFX_ZERO_OWORD(*int_ker);
1504 wmb(); /* Ensure the vector is cleared before interrupt ack */ 189 wmb(); /* Ensure the vector is cleared before interrupt ack */
1505 falcon_irq_ack_a1(efx); 190 falcon_irq_ack_a1(efx);
@@ -1515,126 +200,6 @@ static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1515 200
1516 return IRQ_HANDLED; 201 return IRQ_HANDLED;
1517} 202}
1518
1519/* Handle an MSI interrupt from Falcon
1520 *
1521 * Handle an MSI hardware interrupt. This routine schedules event
1522 * queue processing. No interrupt acknowledgement cycle is necessary.
1523 * Also, we never need to check that the interrupt is for us, since
1524 * MSI interrupts cannot be shared.
1525 */
1526static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1527{
1528 struct efx_channel *channel = dev_id;
1529 struct efx_nic *efx = channel->efx;
1530 efx_oword_t *int_ker = efx->irq_status.addr;
1531 int syserr;
1532
1533 efx->last_irq_cpu = raw_smp_processor_id();
1534 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1535 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1536
1537 /* Check to see if we have a serious error condition */
1538 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1539 if (unlikely(syserr))
1540 return falcon_fatal_interrupt(efx);
1541
1542 /* Schedule processing of the channel */
1543 efx_schedule_channel(channel);
1544
1545 return IRQ_HANDLED;
1546}
1547
1548
1549/* Setup RSS indirection table.
1550 * This maps from the hash value of the packet to RXQ
1551 */
1552static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1553{
1554 int i = 0;
1555 unsigned long offset;
1556 efx_dword_t dword;
1557
1558 if (falcon_rev(efx) < FALCON_REV_B0)
1559 return;
1560
1561 for (offset = RX_RSS_INDIR_TBL_B0;
1562 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1563 offset += 0x10) {
1564 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1565 i % efx->n_rx_queues);
1566 falcon_writel(efx, &dword, offset);
1567 i++;
1568 }
1569}
1570
1571/* Hook interrupt handler(s)
1572 * Try MSI and then legacy interrupts.
1573 */
1574int falcon_init_interrupt(struct efx_nic *efx)
1575{
1576 struct efx_channel *channel;
1577 int rc;
1578
1579 if (!EFX_INT_MODE_USE_MSI(efx)) {
1580 irq_handler_t handler;
1581 if (falcon_rev(efx) >= FALCON_REV_B0)
1582 handler = falcon_legacy_interrupt_b0;
1583 else
1584 handler = falcon_legacy_interrupt_a1;
1585
1586 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1587 efx->name, efx);
1588 if (rc) {
1589 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1590 efx->pci_dev->irq);
1591 goto fail1;
1592 }
1593 return 0;
1594 }
1595
1596 /* Hook MSI or MSI-X interrupt */
1597 efx_for_each_channel(channel, efx) {
1598 rc = request_irq(channel->irq, falcon_msi_interrupt,
1599 IRQF_PROBE_SHARED, /* Not shared */
1600 channel->name, channel);
1601 if (rc) {
1602 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1603 goto fail2;
1604 }
1605 }
1606
1607 return 0;
1608
1609 fail2:
1610 efx_for_each_channel(channel, efx)
1611 free_irq(channel->irq, channel);
1612 fail1:
1613 return rc;
1614}
1615
1616void falcon_fini_interrupt(struct efx_nic *efx)
1617{
1618 struct efx_channel *channel;
1619 efx_oword_t reg;
1620
1621 /* Disable MSI/MSI-X interrupts */
1622 efx_for_each_channel(channel, efx) {
1623 if (channel->irq)
1624 free_irq(channel->irq, channel);
1625 }
1626
1627 /* ACK legacy interrupt */
1628 if (falcon_rev(efx) >= FALCON_REV_B0)
1629 falcon_read(efx, &reg, INT_ISR0_B0);
1630 else
1631 falcon_irq_ack_a1(efx);
1632
1633 /* Disable legacy interrupt */
1634 if (efx->legacy_irq)
1635 free_irq(efx->legacy_irq, efx);
1636}
1637
1638/************************************************************************** 203/**************************************************************************
1639 * 204 *
1640 * EEPROM/flash 205 * EEPROM/flash
@@ -1647,8 +212,8 @@ void falcon_fini_interrupt(struct efx_nic *efx)
1647static int falcon_spi_poll(struct efx_nic *efx) 212static int falcon_spi_poll(struct efx_nic *efx)
1648{ 213{
1649 efx_oword_t reg; 214 efx_oword_t reg;
1650 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER); 215 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1651 return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; 216 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1652} 217}
1653 218
1654/* Wait for SPI command completion */ 219/* Wait for SPI command completion */
@@ -1678,11 +243,10 @@ static int falcon_spi_wait(struct efx_nic *efx)
1678 } 243 }
1679} 244}
1680 245
1681int falcon_spi_cmd(const struct efx_spi_device *spi, 246int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
1682 unsigned int command, int address, 247 unsigned int command, int address,
1683 const void *in, void *out, size_t len) 248 const void *in, void *out, size_t len)
1684{ 249{
1685 struct efx_nic *efx = spi->efx;
1686 bool addressed = (address >= 0); 250 bool addressed = (address >= 0);
1687 bool reading = (out != NULL); 251 bool reading = (out != NULL);
1688 efx_oword_t reg; 252 efx_oword_t reg;
@@ -1700,27 +264,27 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1700 264
1701 /* Program address register, if we have an address */ 265 /* Program address register, if we have an address */
1702 if (addressed) { 266 if (addressed) {
1703 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address); 267 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1704 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER); 268 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1705 } 269 }
1706 270
1707 /* Program data register, if we have data */ 271 /* Program data register, if we have data */
1708 if (in != NULL) { 272 if (in != NULL) {
1709 memcpy(&reg, in, len); 273 memcpy(&reg, in, len);
1710 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER); 274 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1711 } 275 }
1712 276
1713 /* Issue read/write command */ 277 /* Issue read/write command */
1714 EFX_POPULATE_OWORD_7(reg, 278 EFX_POPULATE_OWORD_7(reg,
1715 EE_SPI_HCMD_CMD_EN, 1, 279 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1716 EE_SPI_HCMD_SF_SEL, spi->device_id, 280 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1717 EE_SPI_HCMD_DABCNT, len, 281 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1718 EE_SPI_HCMD_READ, reading, 282 FRF_AB_EE_SPI_HCMD_READ, reading,
1719 EE_SPI_HCMD_DUBCNT, 0, 283 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1720 EE_SPI_HCMD_ADBCNT, 284 FRF_AB_EE_SPI_HCMD_ADBCNT,
1721 (addressed ? spi->addr_len : 0), 285 (addressed ? spi->addr_len : 0),
1722 EE_SPI_HCMD_ENC, command); 286 FRF_AB_EE_SPI_HCMD_ENC, command);
1723 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER); 287 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1724 288
1725 /* Wait for read/write to complete */ 289 /* Wait for read/write to complete */
1726 rc = falcon_spi_wait(efx); 290 rc = falcon_spi_wait(efx);
@@ -1729,7 +293,7 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1729 293
1730 /* Read data */ 294 /* Read data */
1731 if (out != NULL) { 295 if (out != NULL) {
1732 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER); 296 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1733 memcpy(out, &reg, len); 297 memcpy(out, &reg, len);
1734 } 298 }
1735 299
@@ -1751,15 +315,15 @@ efx_spi_munge_command(const struct efx_spi_device *spi,
1751} 315}
1752 316
1753/* Wait up to 10 ms for buffered write completion */ 317/* Wait up to 10 ms for buffered write completion */
1754int falcon_spi_wait_write(const struct efx_spi_device *spi) 318int
319falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
1755{ 320{
1756 struct efx_nic *efx = spi->efx;
1757 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); 321 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1758 u8 status; 322 u8 status;
1759 int rc; 323 int rc;
1760 324
1761 for (;;) { 325 for (;;) {
1762 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL, 326 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
1763 &status, sizeof(status)); 327 &status, sizeof(status));
1764 if (rc) 328 if (rc)
1765 return rc; 329 return rc;
@@ -1775,8 +339,8 @@ int falcon_spi_wait_write(const struct efx_spi_device *spi)
1775 } 339 }
1776} 340}
1777 341
1778int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, 342int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
1779 size_t len, size_t *retlen, u8 *buffer) 343 loff_t start, size_t len, size_t *retlen, u8 *buffer)
1780{ 344{
1781 size_t block_len, pos = 0; 345 size_t block_len, pos = 0;
1782 unsigned int command; 346 unsigned int command;
@@ -1786,7 +350,7 @@ int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1786 block_len = min(len - pos, FALCON_SPI_MAX_LEN); 350 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1787 351
1788 command = efx_spi_munge_command(spi, SPI_READ, start + pos); 352 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1789 rc = falcon_spi_cmd(spi, command, start + pos, NULL, 353 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
1790 buffer + pos, block_len); 354 buffer + pos, block_len);
1791 if (rc) 355 if (rc)
1792 break; 356 break;
@@ -1805,8 +369,9 @@ int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1805 return rc; 369 return rc;
1806} 370}
1807 371
1808int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, 372int
1809 size_t len, size_t *retlen, const u8 *buffer) 373falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
374 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
1810{ 375{
1811 u8 verify_buffer[FALCON_SPI_MAX_LEN]; 376 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1812 size_t block_len, pos = 0; 377 size_t block_len, pos = 0;
@@ -1814,24 +379,24 @@ int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1814 int rc = 0; 379 int rc = 0;
1815 380
1816 while (pos < len) { 381 while (pos < len) {
1817 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0); 382 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
1818 if (rc) 383 if (rc)
1819 break; 384 break;
1820 385
1821 block_len = min(len - pos, 386 block_len = min(len - pos,
1822 falcon_spi_write_limit(spi, start + pos)); 387 falcon_spi_write_limit(spi, start + pos));
1823 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); 388 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1824 rc = falcon_spi_cmd(spi, command, start + pos, 389 rc = falcon_spi_cmd(efx, spi, command, start + pos,
1825 buffer + pos, NULL, block_len); 390 buffer + pos, NULL, block_len);
1826 if (rc) 391 if (rc)
1827 break; 392 break;
1828 393
1829 rc = falcon_spi_wait_write(spi); 394 rc = falcon_spi_wait_write(efx, spi);
1830 if (rc) 395 if (rc)
1831 break; 396 break;
1832 397
1833 command = efx_spi_munge_command(spi, SPI_READ, start + pos); 398 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1834 rc = falcon_spi_cmd(spi, command, start + pos, 399 rc = falcon_spi_cmd(efx, spi, command, start + pos,
1835 NULL, verify_buffer, block_len); 400 NULL, verify_buffer, block_len);
1836 if (memcmp(verify_buffer, buffer + pos, block_len)) { 401 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1837 rc = -EIO; 402 rc = -EIO;
@@ -1860,60 +425,70 @@ int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1860 ************************************************************************** 425 **************************************************************************
1861 */ 426 */
1862 427
1863static int falcon_reset_macs(struct efx_nic *efx) 428static void falcon_push_multicast_hash(struct efx_nic *efx)
1864{ 429{
1865 efx_oword_t reg; 430 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
431
432 WARN_ON(!mutex_is_locked(&efx->mac_lock));
433
434 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
435 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
436}
437
438static void falcon_reset_macs(struct efx_nic *efx)
439{
440 struct falcon_nic_data *nic_data = efx->nic_data;
441 efx_oword_t reg, mac_ctrl;
1866 int count; 442 int count;
1867 443
1868 if (falcon_rev(efx) < FALCON_REV_B0) { 444 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1869 /* It's not safe to use GLB_CTL_REG to reset the 445 /* It's not safe to use GLB_CTL_REG to reset the
1870 * macs, so instead use the internal MAC resets 446 * macs, so instead use the internal MAC resets
1871 */ 447 */
1872 if (!EFX_IS10G(efx)) { 448 if (!EFX_IS10G(efx)) {
1873 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1); 449 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1874 falcon_write(efx, &reg, GM_CFG1_REG); 450 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1875 udelay(1000); 451 udelay(1000);
1876 452
1877 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0); 453 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1878 falcon_write(efx, &reg, GM_CFG1_REG); 454 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1879 udelay(1000); 455 udelay(1000);
1880 return 0; 456 return;
1881 } else { 457 } else {
1882 EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1); 458 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1883 falcon_write(efx, &reg, XM_GLB_CFG_REG); 459 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1884 460
1885 for (count = 0; count < 10000; count++) { 461 for (count = 0; count < 10000; count++) {
1886 falcon_read(efx, &reg, XM_GLB_CFG_REG); 462 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1887 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0) 463 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1888 return 0; 464 0)
465 return;
1889 udelay(10); 466 udelay(10);
1890 } 467 }
1891 468
1892 EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); 469 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1893 return -ETIMEDOUT;
1894 } 470 }
1895 } 471 }
1896 472
1897 /* MAC stats will fail whilst the TX fifo is draining. Serialise 473 /* Mac stats will fail whist the TX fifo is draining */
1898 * the drain sequence with the statistics fetch */ 474 WARN_ON(nic_data->stats_disable_count == 0);
1899 efx_stats_disable(efx);
1900 475
1901 falcon_read(efx, &reg, MAC0_CTRL_REG_KER); 476 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1902 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1); 477 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1903 falcon_write(efx, &reg, MAC0_CTRL_REG_KER); 478 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1904 479
1905 falcon_read(efx, &reg, GLB_CTL_REG_KER); 480 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1906 EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1); 481 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1907 EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1); 482 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1908 EFX_SET_OWORD_FIELD(reg, RST_EM, 1); 483 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1909 falcon_write(efx, &reg, GLB_CTL_REG_KER); 484 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1910 485
1911 count = 0; 486 count = 0;
1912 while (1) { 487 while (1) {
1913 falcon_read(efx, &reg, GLB_CTL_REG_KER); 488 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1914 if (!EFX_OWORD_FIELD(reg, RST_XGTX) && 489 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1915 !EFX_OWORD_FIELD(reg, RST_XGRX) && 490 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1916 !EFX_OWORD_FIELD(reg, RST_EM)) { 491 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1917 EFX_LOG(efx, "Completed MAC reset after %d loops\n", 492 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1918 count); 493 count);
1919 break; 494 break;
@@ -1926,55 +501,50 @@ static int falcon_reset_macs(struct efx_nic *efx)
1926 udelay(10); 501 udelay(10);
1927 } 502 }
1928 503
1929 efx_stats_enable(efx); 504 /* Ensure the correct MAC is selected before statistics
1930 505 * are re-enabled by the caller */
1931 /* If we've reset the EM block and the link is up, then 506 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1932 * we'll have to kick the XAUI link so the PHY can recover */
1933 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1934 falcon_reset_xaui(efx);
1935
1936 return 0;
1937} 507}
1938 508
1939void falcon_drain_tx_fifo(struct efx_nic *efx) 509void falcon_drain_tx_fifo(struct efx_nic *efx)
1940{ 510{
1941 efx_oword_t reg; 511 efx_oword_t reg;
1942 512
1943 if ((falcon_rev(efx) < FALCON_REV_B0) || 513 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1944 (efx->loopback_mode != LOOPBACK_NONE)) 514 (efx->loopback_mode != LOOPBACK_NONE))
1945 return; 515 return;
1946 516
1947 falcon_read(efx, &reg, MAC0_CTRL_REG_KER); 517 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1948 /* There is no point in draining more than once */ 518 /* There is no point in draining more than once */
1949 if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0)) 519 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1950 return; 520 return;
1951 521
1952 falcon_reset_macs(efx); 522 falcon_reset_macs(efx);
1953} 523}
1954 524
1955void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) 525static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1956{ 526{
1957 efx_oword_t reg; 527 efx_oword_t reg;
1958 528
1959 if (falcon_rev(efx) < FALCON_REV_B0) 529 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1960 return; 530 return;
1961 531
1962 /* Isolate the MAC -> RX */ 532 /* Isolate the MAC -> RX */
1963 falcon_read(efx, &reg, RX_CFG_REG_KER); 533 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1964 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0); 534 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1965 falcon_write(efx, &reg, RX_CFG_REG_KER); 535 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1966 536
1967 if (!efx->link_up) 537 /* Isolate TX -> MAC */
1968 falcon_drain_tx_fifo(efx); 538 falcon_drain_tx_fifo(efx);
1969} 539}
1970 540
1971void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) 541void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1972{ 542{
543 struct efx_link_state *link_state = &efx->link_state;
1973 efx_oword_t reg; 544 efx_oword_t reg;
1974 int link_speed; 545 int link_speed;
1975 bool tx_fc;
1976 546
1977 switch (efx->link_speed) { 547 switch (link_state->speed) {
1978 case 10000: link_speed = 3; break; 548 case 10000: link_speed = 3; break;
1979 case 1000: link_speed = 2; break; 549 case 1000: link_speed = 2; break;
1980 case 100: link_speed = 1; break; 550 case 100: link_speed = 1; break;
@@ -1985,75 +555,139 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1985 * indefinitely held and TX queue can be flushed at any point 555 * indefinitely held and TX queue can be flushed at any point
1986 * while the link is down. */ 556 * while the link is down. */
1987 EFX_POPULATE_OWORD_5(reg, 557 EFX_POPULATE_OWORD_5(reg,
1988 MAC_XOFF_VAL, 0xffff /* max pause time */, 558 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1989 MAC_BCAD_ACPT, 1, 559 FRF_AB_MAC_BCAD_ACPT, 1,
1990 MAC_UC_PROM, efx->promiscuous, 560 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1991 MAC_LINK_STATUS, 1, /* always set */ 561 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1992 MAC_SPEED, link_speed); 562 FRF_AB_MAC_SPEED, link_speed);
1993 /* On B0, MAC backpressure can be disabled and packets get 563 /* On B0, MAC backpressure can be disabled and packets get
1994 * discarded. */ 564 * discarded. */
1995 if (falcon_rev(efx) >= FALCON_REV_B0) { 565 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1996 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 566 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1997 !efx->link_up); 567 !link_state->up);
1998 } 568 }
1999 569
2000 falcon_write(efx, &reg, MAC0_CTRL_REG_KER); 570 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
2001 571
2002 /* Restore the multicast hash registers. */ 572 /* Restore the multicast hash registers. */
2003 falcon_set_multicast_hash(efx); 573 falcon_push_multicast_hash(efx);
2004
2005 /* Transmission of pause frames when RX crosses the threshold is
2006 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2007 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2008 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2009 falcon_read(efx, &reg, RX_CFG_REG_KER);
2010 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
2011 574
575 efx_reado(efx, &reg, FR_AZ_RX_CFG);
576 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
577 * initialisation but it may read back as 0) */
578 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2012 /* Unisolate the MAC -> RX */ 579 /* Unisolate the MAC -> RX */
2013 if (falcon_rev(efx) >= FALCON_REV_B0) 580 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
2014 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1); 581 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2015 falcon_write(efx, &reg, RX_CFG_REG_KER); 582 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2016} 583}
2017 584
2018int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) 585static void falcon_stats_request(struct efx_nic *efx)
2019{ 586{
587 struct falcon_nic_data *nic_data = efx->nic_data;
2020 efx_oword_t reg; 588 efx_oword_t reg;
2021 u32 *dma_done;
2022 int i;
2023 589
2024 if (disable_dma_stats) 590 WARN_ON(nic_data->stats_pending);
2025 return 0; 591 WARN_ON(nic_data->stats_disable_count);
2026 592
2027 /* Statistics fetch will fail if the MAC is in TX drain */ 593 if (nic_data->stats_dma_done == NULL)
2028 if (falcon_rev(efx) >= FALCON_REV_B0) { 594 return; /* no mac selected */
2029 efx_oword_t temp;
2030 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
2031 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
2032 return 0;
2033 }
2034 595
2035 dma_done = (efx->stats_buffer.addr + done_offset); 596 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
2036 *dma_done = FALCON_STATS_NOT_DONE; 597 nic_data->stats_pending = true;
2037 wmb(); /* ensure done flag is clear */ 598 wmb(); /* ensure done flag is clear */
2038 599
2039 /* Initiate DMA transfer of stats */ 600 /* Initiate DMA transfer of stats */
2040 EFX_POPULATE_OWORD_2(reg, 601 EFX_POPULATE_OWORD_2(reg,
2041 MAC_STAT_DMA_CMD, 1, 602 FRF_AB_MAC_STAT_DMA_CMD, 1,
2042 MAC_STAT_DMA_ADR, 603 FRF_AB_MAC_STAT_DMA_ADR,
2043 efx->stats_buffer.dma_addr); 604 efx->stats_buffer.dma_addr);
2044 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER); 605 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2045 606
2046 /* Wait for transfer to complete */ 607 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
2047 for (i = 0; i < 400; i++) { 608}
2048 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) { 609
2049 rmb(); /* Ensure the stats are valid. */ 610static void falcon_stats_complete(struct efx_nic *efx)
2050 return 0; 611{
2051 } 612 struct falcon_nic_data *nic_data = efx->nic_data;
2052 udelay(10); 613
614 if (!nic_data->stats_pending)
615 return;
616
617 nic_data->stats_pending = 0;
618 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
619 rmb(); /* read the done flag before the stats */
620 efx->mac_op->update_stats(efx);
621 } else {
622 EFX_ERR(efx, "timed out waiting for statistics\n");
2053 } 623 }
624}
2054 625
2055 EFX_ERR(efx, "timed out waiting for statistics\n"); 626static void falcon_stats_timer_func(unsigned long context)
2056 return -ETIMEDOUT; 627{
628 struct efx_nic *efx = (struct efx_nic *)context;
629 struct falcon_nic_data *nic_data = efx->nic_data;
630
631 spin_lock(&efx->stats_lock);
632
633 falcon_stats_complete(efx);
634 if (nic_data->stats_disable_count == 0)
635 falcon_stats_request(efx);
636
637 spin_unlock(&efx->stats_lock);
638}
639
640static void falcon_switch_mac(struct efx_nic *efx);
641
642static bool falcon_loopback_link_poll(struct efx_nic *efx)
643{
644 struct efx_link_state old_state = efx->link_state;
645
646 WARN_ON(!mutex_is_locked(&efx->mac_lock));
647 WARN_ON(!LOOPBACK_INTERNAL(efx));
648
649 efx->link_state.fd = true;
650 efx->link_state.fc = efx->wanted_fc;
651 efx->link_state.up = true;
652
653 if (efx->loopback_mode == LOOPBACK_GMAC)
654 efx->link_state.speed = 1000;
655 else
656 efx->link_state.speed = 10000;
657
658 return !efx_link_state_equal(&efx->link_state, &old_state);
659}
660
661static int falcon_reconfigure_port(struct efx_nic *efx)
662{
663 int rc;
664
665 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
666
667 /* Poll the PHY link state *before* reconfiguring it. This means we
668 * will pick up the correct speed (in loopback) to select the correct
669 * MAC.
670 */
671 if (LOOPBACK_INTERNAL(efx))
672 falcon_loopback_link_poll(efx);
673 else
674 efx->phy_op->poll(efx);
675
676 falcon_stop_nic_stats(efx);
677 falcon_deconfigure_mac_wrapper(efx);
678
679 falcon_switch_mac(efx);
680
681 efx->phy_op->reconfigure(efx);
682 rc = efx->mac_op->reconfigure(efx);
683 BUG_ON(rc);
684
685 falcon_start_nic_stats(efx);
686
687 /* Synchronise efx->link_state with the kernel */
688 efx_link_status_changed(efx);
689
690 return 0;
2057} 691}
2058 692
2059/************************************************************************** 693/**************************************************************************
@@ -2066,18 +700,18 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2066/* Wait for GMII access to complete */ 700/* Wait for GMII access to complete */
2067static int falcon_gmii_wait(struct efx_nic *efx) 701static int falcon_gmii_wait(struct efx_nic *efx)
2068{ 702{
2069 efx_dword_t md_stat; 703 efx_oword_t md_stat;
2070 int count; 704 int count;
2071 705
2072 /* wait upto 50ms - taken max from datasheet */ 706 /* wait upto 50ms - taken max from datasheet */
2073 for (count = 0; count < 5000; count++) { 707 for (count = 0; count < 5000; count++) {
2074 falcon_readl(efx, &md_stat, MD_STAT_REG_KER); 708 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
2075 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) { 709 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2076 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 || 710 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2077 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) { 711 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2078 EFX_ERR(efx, "error from GMII access " 712 EFX_ERR(efx, "error from GMII access "
2079 EFX_DWORD_FMT"\n", 713 EFX_OWORD_FMT"\n",
2080 EFX_DWORD_VAL(md_stat)); 714 EFX_OWORD_VAL(md_stat));
2081 return -EIO; 715 return -EIO;
2082 } 716 }
2083 return 0; 717 return 0;
@@ -2099,7 +733,7 @@ static int falcon_mdio_write(struct net_device *net_dev,
2099 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n", 733 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2100 prtad, devad, addr, value); 734 prtad, devad, addr, value);
2101 735
2102 spin_lock_bh(&efx->phy_lock); 736 mutex_lock(&efx->mdio_lock);
2103 737
2104 /* Check MDIO not currently being accessed */ 738 /* Check MDIO not currently being accessed */
2105 rc = falcon_gmii_wait(efx); 739 rc = falcon_gmii_wait(efx);
@@ -2107,34 +741,35 @@ static int falcon_mdio_write(struct net_device *net_dev,
2107 goto out; 741 goto out;
2108 742
2109 /* Write the address/ID register */ 743 /* Write the address/ID register */
2110 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); 744 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2111 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER); 745 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2112 746
2113 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad); 747 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2114 falcon_write(efx, &reg, MD_ID_REG_KER); 748 FRF_AB_MD_DEV_ADR, devad);
749 efx_writeo(efx, &reg, FR_AB_MD_ID);
2115 750
2116 /* Write data */ 751 /* Write data */
2117 EFX_POPULATE_OWORD_1(reg, MD_TXD, value); 752 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2118 falcon_write(efx, &reg, MD_TXD_REG_KER); 753 efx_writeo(efx, &reg, FR_AB_MD_TXD);
2119 754
2120 EFX_POPULATE_OWORD_2(reg, 755 EFX_POPULATE_OWORD_2(reg,
2121 MD_WRC, 1, 756 FRF_AB_MD_WRC, 1,
2122 MD_GC, 0); 757 FRF_AB_MD_GC, 0);
2123 falcon_write(efx, &reg, MD_CS_REG_KER); 758 efx_writeo(efx, &reg, FR_AB_MD_CS);
2124 759
2125 /* Wait for data to be written */ 760 /* Wait for data to be written */
2126 rc = falcon_gmii_wait(efx); 761 rc = falcon_gmii_wait(efx);
2127 if (rc) { 762 if (rc) {
2128 /* Abort the write operation */ 763 /* Abort the write operation */
2129 EFX_POPULATE_OWORD_2(reg, 764 EFX_POPULATE_OWORD_2(reg,
2130 MD_WRC, 0, 765 FRF_AB_MD_WRC, 0,
2131 MD_GC, 1); 766 FRF_AB_MD_GC, 1);
2132 falcon_write(efx, &reg, MD_CS_REG_KER); 767 efx_writeo(efx, &reg, FR_AB_MD_CS);
2133 udelay(10); 768 udelay(10);
2134 } 769 }
2135 770
2136 out: 771out:
2137 spin_unlock_bh(&efx->phy_lock); 772 mutex_unlock(&efx->mdio_lock);
2138 return rc; 773 return rc;
2139} 774}
2140 775
@@ -2146,152 +781,141 @@ static int falcon_mdio_read(struct net_device *net_dev,
2146 efx_oword_t reg; 781 efx_oword_t reg;
2147 int rc; 782 int rc;
2148 783
2149 spin_lock_bh(&efx->phy_lock); 784 mutex_lock(&efx->mdio_lock);
2150 785
2151 /* Check MDIO not currently being accessed */ 786 /* Check MDIO not currently being accessed */
2152 rc = falcon_gmii_wait(efx); 787 rc = falcon_gmii_wait(efx);
2153 if (rc) 788 if (rc)
2154 goto out; 789 goto out;
2155 790
2156 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); 791 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2157 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER); 792 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2158 793
2159 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad); 794 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2160 falcon_write(efx, &reg, MD_ID_REG_KER); 795 FRF_AB_MD_DEV_ADR, devad);
796 efx_writeo(efx, &reg, FR_AB_MD_ID);
2161 797
2162 /* Request data to be read */ 798 /* Request data to be read */
2163 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0); 799 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2164 falcon_write(efx, &reg, MD_CS_REG_KER); 800 efx_writeo(efx, &reg, FR_AB_MD_CS);
2165 801
2166 /* Wait for data to become available */ 802 /* Wait for data to become available */
2167 rc = falcon_gmii_wait(efx); 803 rc = falcon_gmii_wait(efx);
2168 if (rc == 0) { 804 if (rc == 0) {
2169 falcon_read(efx, &reg, MD_RXD_REG_KER); 805 efx_reado(efx, &reg, FR_AB_MD_RXD);
2170 rc = EFX_OWORD_FIELD(reg, MD_RXD); 806 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2171 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", 807 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2172 prtad, devad, addr, rc); 808 prtad, devad, addr, rc);
2173 } else { 809 } else {
2174 /* Abort the read operation */ 810 /* Abort the read operation */
2175 EFX_POPULATE_OWORD_2(reg, 811 EFX_POPULATE_OWORD_2(reg,
2176 MD_RIC, 0, 812 FRF_AB_MD_RIC, 0,
2177 MD_GC, 1); 813 FRF_AB_MD_GC, 1);
2178 falcon_write(efx, &reg, MD_CS_REG_KER); 814 efx_writeo(efx, &reg, FR_AB_MD_CS);
2179 815
2180 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", 816 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2181 prtad, devad, addr, rc); 817 prtad, devad, addr, rc);
2182 } 818 }
2183 819
2184 out: 820out:
2185 spin_unlock_bh(&efx->phy_lock); 821 mutex_unlock(&efx->mdio_lock);
2186 return rc; 822 return rc;
2187} 823}
2188 824
2189static int falcon_probe_phy(struct efx_nic *efx) 825static void falcon_clock_mac(struct efx_nic *efx)
2190{ 826{
2191 switch (efx->phy_type) { 827 unsigned strap_val;
2192 case PHY_TYPE_SFX7101: 828 efx_oword_t nic_stat;
2193 efx->phy_op = &falcon_sfx7101_phy_ops;
2194 break;
2195 case PHY_TYPE_SFT9001A:
2196 case PHY_TYPE_SFT9001B:
2197 efx->phy_op = &falcon_sft9001_phy_ops;
2198 break;
2199 case PHY_TYPE_QT2022C2:
2200 case PHY_TYPE_QT2025C:
2201 efx->phy_op = &falcon_xfp_phy_ops;
2202 break;
2203 default:
2204 EFX_ERR(efx, "Unknown PHY type %d\n",
2205 efx->phy_type);
2206 return -1;
2207 }
2208
2209 if (efx->phy_op->macs & EFX_XMAC)
2210 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2211 (1 << LOOPBACK_XGXS) |
2212 (1 << LOOPBACK_XAUI));
2213 if (efx->phy_op->macs & EFX_GMAC)
2214 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2215 efx->loopback_modes |= efx->phy_op->loopbacks;
2216 829
2217 return 0; 830 /* Configure the NIC generated MAC clock correctly */
831 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
832 strap_val = EFX_IS10G(efx) ? 5 : 3;
833 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
834 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
835 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
836 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
837 } else {
838 /* Falcon A1 does not support 1G/10G speed switching
839 * and must not be used with a PHY that does. */
840 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
841 strap_val);
842 }
2218} 843}
2219 844
2220int falcon_switch_mac(struct efx_nic *efx) 845static void falcon_switch_mac(struct efx_nic *efx)
2221{ 846{
2222 struct efx_mac_operations *old_mac_op = efx->mac_op; 847 struct efx_mac_operations *old_mac_op = efx->mac_op;
2223 efx_oword_t nic_stat; 848 struct falcon_nic_data *nic_data = efx->nic_data;
2224 unsigned strap_val; 849 unsigned int stats_done_offset;
2225 int rc = 0;
2226
2227 /* Don't try to fetch MAC stats while we're switching MACs */
2228 efx_stats_disable(efx);
2229
2230 /* Internal loopbacks override the phy speed setting */
2231 if (efx->loopback_mode == LOOPBACK_GMAC) {
2232 efx->link_speed = 1000;
2233 efx->link_fd = true;
2234 } else if (LOOPBACK_INTERNAL(efx)) {
2235 efx->link_speed = 10000;
2236 efx->link_fd = true;
2237 }
2238 850
2239 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 851 WARN_ON(!mutex_is_locked(&efx->mac_lock));
852 WARN_ON(nic_data->stats_disable_count == 0);
853
2240 efx->mac_op = (EFX_IS10G(efx) ? 854 efx->mac_op = (EFX_IS10G(efx) ?
2241 &falcon_xmac_operations : &falcon_gmac_operations); 855 &falcon_xmac_operations : &falcon_gmac_operations);
2242 856
2243 /* Always push the NIC_STAT_REG setting even if the mac hasn't 857 if (EFX_IS10G(efx))
2244 * changed, because this function is run post online reset */ 858 stats_done_offset = XgDmaDone_offset;
2245 falcon_read(efx, &nic_stat, NIC_STAT_REG); 859 else
2246 strap_val = EFX_IS10G(efx) ? 5 : 3; 860 stats_done_offset = GDmaDone_offset;
2247 if (falcon_rev(efx) >= FALCON_REV_B0) { 861 nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
2248 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1);
2249 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val);
2250 falcon_write(efx, &nic_stat, NIC_STAT_REG);
2251 } else {
2252 /* Falcon A1 does not support 1G/10G speed switching
2253 * and must not be used with a PHY that does. */
2254 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);
2255 }
2256 862
2257 if (old_mac_op == efx->mac_op) 863 if (old_mac_op == efx->mac_op)
2258 goto out; 864 return;
865
866 falcon_clock_mac(efx);
2259 867
2260 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G'); 868 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2261 /* Not all macs support a mac-level link state */ 869 /* Not all macs support a mac-level link state */
2262 efx->mac_up = true; 870 efx->xmac_poll_required = false;
2263 871 falcon_reset_macs(efx);
2264 rc = falcon_reset_macs(efx);
2265out:
2266 efx_stats_enable(efx);
2267 return rc;
2268} 872}
2269 873
2270/* This call is responsible for hooking in the MAC and PHY operations */ 874/* This call is responsible for hooking in the MAC and PHY operations */
2271int falcon_probe_port(struct efx_nic *efx) 875static int falcon_probe_port(struct efx_nic *efx)
2272{ 876{
2273 int rc; 877 int rc;
2274 878
2275 /* Hook in PHY operations table */ 879 switch (efx->phy_type) {
2276 rc = falcon_probe_phy(efx); 880 case PHY_TYPE_SFX7101:
2277 if (rc) 881 efx->phy_op = &falcon_sfx7101_phy_ops;
2278 return rc; 882 break;
883 case PHY_TYPE_SFT9001A:
884 case PHY_TYPE_SFT9001B:
885 efx->phy_op = &falcon_sft9001_phy_ops;
886 break;
887 case PHY_TYPE_QT2022C2:
888 case PHY_TYPE_QT2025C:
889 efx->phy_op = &falcon_qt202x_phy_ops;
890 break;
891 default:
892 EFX_ERR(efx, "Unknown PHY type %d\n",
893 efx->phy_type);
894 return -ENODEV;
895 }
2279 896
2280 /* Set up MDIO structure for PHY */ 897 /* Fill out MDIO structure and loopback modes */
2281 efx->mdio.mmds = efx->phy_op->mmds;
2282 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2283 efx->mdio.mdio_read = falcon_mdio_read; 898 efx->mdio.mdio_read = falcon_mdio_read;
2284 efx->mdio.mdio_write = falcon_mdio_write; 899 efx->mdio.mdio_write = falcon_mdio_write;
900 rc = efx->phy_op->probe(efx);
901 if (rc != 0)
902 return rc;
903
904 /* Initial assumption */
905 efx->link_state.speed = 10000;
906 efx->link_state.fd = true;
2285 907
2286 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ 908 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2287 if (falcon_rev(efx) >= FALCON_REV_B0) 909 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
2288 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; 910 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2289 else 911 else
2290 efx->wanted_fc = EFX_FC_RX; 912 efx->wanted_fc = EFX_FC_RX;
913 if (efx->mdio.mmds & MDIO_DEVS_AN)
914 efx->wanted_fc |= EFX_FC_AUTO;
2291 915
2292 /* Allocate buffer for stats */ 916 /* Allocate buffer for stats */
2293 rc = falcon_alloc_buffer(efx, &efx->stats_buffer, 917 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
2294 FALCON_MAC_STATS_SIZE); 918 FALCON_MAC_STATS_SIZE);
2295 if (rc) 919 if (rc)
2296 return rc; 920 return rc;
2297 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", 921 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
@@ -2302,40 +926,20 @@ int falcon_probe_port(struct efx_nic *efx)
2302 return 0; 926 return 0;
2303} 927}
2304 928
2305void falcon_remove_port(struct efx_nic *efx) 929static void falcon_remove_port(struct efx_nic *efx)
2306{ 930{
2307 falcon_free_buffer(efx, &efx->stats_buffer); 931 efx->phy_op->remove(efx);
932 efx_nic_free_buffer(efx, &efx->stats_buffer);
2308} 933}
2309 934
2310/************************************************************************** 935/**************************************************************************
2311 * 936 *
2312 * Multicast filtering
2313 *
2314 **************************************************************************
2315 */
2316
2317void falcon_set_multicast_hash(struct efx_nic *efx)
2318{
2319 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2320
2321 /* Broadcast packets go through the multicast hash filter.
2322 * ether_crc_le() of the broadcast address is 0xbe2612ff
2323 * so we always add bit 0xff to the mask.
2324 */
2325 set_bit_le(0xff, mc_hash->byte);
2326
2327 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2328 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2329}
2330
2331
2332/**************************************************************************
2333 *
2334 * Falcon test code 937 * Falcon test code
2335 * 938 *
2336 **************************************************************************/ 939 **************************************************************************/
2337 940
2338int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) 941static int
942falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2339{ 943{
2340 struct falcon_nvconfig *nvconfig; 944 struct falcon_nvconfig *nvconfig;
2341 struct efx_spi_device *spi; 945 struct efx_spi_device *spi;
@@ -2351,10 +955,10 @@ int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2351 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); 955 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2352 if (!region) 956 if (!region)
2353 return -ENOMEM; 957 return -ENOMEM;
2354 nvconfig = region + NVCONFIG_OFFSET; 958 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2355 959
2356 mutex_lock(&efx->spi_lock); 960 mutex_lock(&efx->spi_lock);
2357 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); 961 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
2358 mutex_unlock(&efx->spi_lock); 962 mutex_unlock(&efx->spi_lock);
2359 if (rc) { 963 if (rc) {
2360 EFX_ERR(efx, "Failed to read %s\n", 964 EFX_ERR(efx, "Failed to read %s\n",
@@ -2367,7 +971,7 @@ int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2367 struct_ver = le16_to_cpu(nvconfig->board_struct_ver); 971 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2368 972
2369 rc = -EINVAL; 973 rc = -EINVAL;
2370 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) { 974 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2371 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); 975 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2372 goto out; 976 goto out;
2373 } 977 }
@@ -2398,107 +1002,54 @@ int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2398 return rc; 1002 return rc;
2399} 1003}
2400 1004
2401/* Registers tested in the falcon register test */ 1005static int falcon_test_nvram(struct efx_nic *efx)
2402static struct { 1006{
2403 unsigned address; 1007 return falcon_read_nvram(efx, NULL);
2404 efx_oword_t mask; 1008}
2405} efx_test_registers[] = { 1009
2406 { ADR_REGION_REG_KER, 1010static const struct efx_nic_register_test falcon_b0_register_tests[] = {
2407 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, 1011 { FR_AZ_ADR_REGION,
2408 { RX_CFG_REG_KER, 1012 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1013 { FR_AZ_RX_CFG,
2409 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, 1014 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2410 { TX_CFG_REG_KER, 1015 { FR_AZ_TX_CFG,
2411 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, 1016 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2412 { TX_CFG2_REG_KER, 1017 { FR_AZ_TX_RESERVED,
2413 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, 1018 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2414 { MAC0_CTRL_REG_KER, 1019 { FR_AB_MAC_CTRL,
2415 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, 1020 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2416 { SRM_TX_DC_CFG_REG_KER, 1021 { FR_AZ_SRM_TX_DC_CFG,
2417 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, 1022 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2418 { RX_DC_CFG_REG_KER, 1023 { FR_AZ_RX_DC_CFG,
2419 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, 1024 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2420 { RX_DC_PF_WM_REG_KER, 1025 { FR_AZ_RX_DC_PF_WM,
2421 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, 1026 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2422 { DP_CTRL_REG, 1027 { FR_BZ_DP_CTRL,
2423 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, 1028 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2424 { GM_CFG2_REG, 1029 { FR_AB_GM_CFG2,
2425 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, 1030 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2426 { GMF_CFG0_REG, 1031 { FR_AB_GMF_CFG0,
2427 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, 1032 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2428 { XM_GLB_CFG_REG, 1033 { FR_AB_XM_GLB_CFG,
2429 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, 1034 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2430 { XM_TX_CFG_REG, 1035 { FR_AB_XM_TX_CFG,
2431 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, 1036 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2432 { XM_RX_CFG_REG, 1037 { FR_AB_XM_RX_CFG,
2433 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, 1038 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2434 { XM_RX_PARAM_REG, 1039 { FR_AB_XM_RX_PARAM,
2435 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, 1040 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2436 { XM_FC_REG, 1041 { FR_AB_XM_FC,
2437 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, 1042 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2438 { XM_ADR_LO_REG, 1043 { FR_AB_XM_ADR_LO,
2439 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, 1044 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2440 { XX_SD_CTL_REG, 1045 { FR_AB_XX_SD_CTL,
2441 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, 1046 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2442}; 1047};
2443 1048
2444static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, 1049static int falcon_b0_test_registers(struct efx_nic *efx)
2445 const efx_oword_t *mask)
2446{
2447 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2448 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2449}
2450
2451int falcon_test_registers(struct efx_nic *efx)
2452{ 1050{
2453 unsigned address = 0, i, j; 1051 return efx_nic_test_registers(efx, falcon_b0_register_tests,
2454 efx_oword_t mask, imask, original, reg, buf; 1052 ARRAY_SIZE(falcon_b0_register_tests));
2455
2456 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2457 WARN_ON(!LOOPBACK_INTERNAL(efx));
2458
2459 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2460 address = efx_test_registers[i].address;
2461 mask = imask = efx_test_registers[i].mask;
2462 EFX_INVERT_OWORD(imask);
2463
2464 falcon_read(efx, &original, address);
2465
2466 /* bit sweep on and off */
2467 for (j = 0; j < 128; j++) {
2468 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2469 continue;
2470
2471 /* Test this testable bit can be set in isolation */
2472 EFX_AND_OWORD(reg, original, mask);
2473 EFX_SET_OWORD32(reg, j, j, 1);
2474
2475 falcon_write(efx, &reg, address);
2476 falcon_read(efx, &buf, address);
2477
2478 if (efx_masked_compare_oword(&reg, &buf, &mask))
2479 goto fail;
2480
2481 /* Test this testable bit can be cleared in isolation */
2482 EFX_OR_OWORD(reg, original, mask);
2483 EFX_SET_OWORD32(reg, j, j, 0);
2484
2485 falcon_write(efx, &reg, address);
2486 falcon_read(efx, &buf, address);
2487
2488 if (efx_masked_compare_oword(&reg, &buf, &mask))
2489 goto fail;
2490 }
2491
2492 falcon_write(efx, &original, address);
2493 }
2494
2495 return 0;
2496
2497fail:
2498 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2499 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2500 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2501 return -EIO;
2502} 1053}
2503 1054
2504/************************************************************************** 1055/**************************************************************************
@@ -2510,13 +1061,13 @@ fail:
2510 1061
2511/* Resets NIC to known state. This routine must be called in process 1062/* Resets NIC to known state. This routine must be called in process
2512 * context and is allowed to sleep. */ 1063 * context and is allowed to sleep. */
2513int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) 1064static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2514{ 1065{
2515 struct falcon_nic_data *nic_data = efx->nic_data; 1066 struct falcon_nic_data *nic_data = efx->nic_data;
2516 efx_oword_t glb_ctl_reg_ker; 1067 efx_oword_t glb_ctl_reg_ker;
2517 int rc; 1068 int rc;
2518 1069
2519 EFX_LOG(efx, "performing hardware reset (%d)\n", method); 1070 EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
2520 1071
2521 /* Initiate device reset */ 1072 /* Initiate device reset */
2522 if (method == RESET_TYPE_WORLD) { 1073 if (method == RESET_TYPE_WORLD) {
@@ -2526,7 +1077,7 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2526 "function prior to hardware reset\n"); 1077 "function prior to hardware reset\n");
2527 goto fail1; 1078 goto fail1;
2528 } 1079 }
2529 if (FALCON_IS_DUAL_FUNC(efx)) { 1080 if (efx_nic_is_dual_func(efx)) {
2530 rc = pci_save_state(nic_data->pci_dev2); 1081 rc = pci_save_state(nic_data->pci_dev2);
2531 if (rc) { 1082 if (rc) {
2532 EFX_ERR(efx, "failed to backup PCI state of " 1083 EFX_ERR(efx, "failed to backup PCI state of "
@@ -2537,29 +1088,31 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2537 } 1088 }
2538 1089
2539 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, 1090 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2540 EXT_PHY_RST_DUR, 0x7, 1091 FRF_AB_EXT_PHY_RST_DUR,
2541 SWRST, 1); 1092 FFE_AB_EXT_PHY_RST_DUR_10240US,
1093 FRF_AB_SWRST, 1);
2542 } else { 1094 } else {
2543 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2544 EXCLUDE_FROM_RESET : 0);
2545
2546 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, 1095 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2547 EXT_PHY_RST_CTL, reset_phy, 1096 /* exclude PHY from "invisible" reset */
2548 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET, 1097 FRF_AB_EXT_PHY_RST_CTL,
2549 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET, 1098 method == RESET_TYPE_INVISIBLE,
2550 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET, 1099 /* exclude EEPROM/flash and PCIe */
2551 EE_RST_CTL, EXCLUDE_FROM_RESET, 1100 FRF_AB_PCIE_CORE_RST_CTL, 1,
2552 EXT_PHY_RST_DUR, 0x7 /* 10ms */, 1101 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2553 SWRST, 1); 1102 FRF_AB_PCIE_SD_RST_CTL, 1,
2554 } 1103 FRF_AB_EE_RST_CTL, 1,
2555 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER); 1104 FRF_AB_EXT_PHY_RST_DUR,
1105 FFE_AB_EXT_PHY_RST_DUR_10240US,
1106 FRF_AB_SWRST, 1);
1107 }
1108 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2556 1109
2557 EFX_LOG(efx, "waiting for hardware reset\n"); 1110 EFX_LOG(efx, "waiting for hardware reset\n");
2558 schedule_timeout_uninterruptible(HZ / 20); 1111 schedule_timeout_uninterruptible(HZ / 20);
2559 1112
2560 /* Restore PCI configuration if needed */ 1113 /* Restore PCI configuration if needed */
2561 if (method == RESET_TYPE_WORLD) { 1114 if (method == RESET_TYPE_WORLD) {
2562 if (FALCON_IS_DUAL_FUNC(efx)) { 1115 if (efx_nic_is_dual_func(efx)) {
2563 rc = pci_restore_state(nic_data->pci_dev2); 1116 rc = pci_restore_state(nic_data->pci_dev2);
2564 if (rc) { 1117 if (rc) {
2565 EFX_ERR(efx, "failed to restore PCI config for " 1118 EFX_ERR(efx, "failed to restore PCI config for "
@@ -2577,8 +1130,8 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2577 } 1130 }
2578 1131
2579 /* Assert that reset complete */ 1132 /* Assert that reset complete */
2580 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER); 1133 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2581 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) { 1134 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2582 rc = -ETIMEDOUT; 1135 rc = -ETIMEDOUT;
2583 EFX_ERR(efx, "timed out waiting for hardware reset\n"); 1136 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2584 goto fail5; 1137 goto fail5;
@@ -2597,6 +1150,44 @@ fail5:
2597 return rc; 1150 return rc;
2598} 1151}
2599 1152
1153static void falcon_monitor(struct efx_nic *efx)
1154{
1155 bool link_changed;
1156 int rc;
1157
1158 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1159
1160 rc = falcon_board(efx)->type->monitor(efx);
1161 if (rc) {
1162 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
1163 (rc == -ERANGE) ? "reported fault" : "failed");
1164 efx->phy_mode |= PHY_MODE_LOW_POWER;
1165 rc = __efx_reconfigure_port(efx);
1166 WARN_ON(rc);
1167 }
1168
1169 if (LOOPBACK_INTERNAL(efx))
1170 link_changed = falcon_loopback_link_poll(efx);
1171 else
1172 link_changed = efx->phy_op->poll(efx);
1173
1174 if (link_changed) {
1175 falcon_stop_nic_stats(efx);
1176 falcon_deconfigure_mac_wrapper(efx);
1177
1178 falcon_switch_mac(efx);
1179 rc = efx->mac_op->reconfigure(efx);
1180 BUG_ON(rc);
1181
1182 falcon_start_nic_stats(efx);
1183
1184 efx_link_status_changed(efx);
1185 }
1186
1187 if (EFX_IS10G(efx))
1188 falcon_poll_xmac(efx);
1189}
1190
2600/* Zeroes out the SRAM contents. This routine must be called in 1191/* Zeroes out the SRAM contents. This routine must be called in
2601 * process context and is allowed to sleep. 1192 * process context and is allowed to sleep.
2602 */ 1193 */
@@ -2606,16 +1197,16 @@ static int falcon_reset_sram(struct efx_nic *efx)
2606 int count; 1197 int count;
2607 1198
2608 /* Set the SRAM wake/sleep GPIO appropriately. */ 1199 /* Set the SRAM wake/sleep GPIO appropriately. */
2609 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); 1200 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2610 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1); 1201 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2611 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1); 1202 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2612 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); 1203 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2613 1204
2614 /* Initiate SRAM reset */ 1205 /* Initiate SRAM reset */
2615 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, 1206 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2616 SRAM_OOB_BT_INIT_EN, 1, 1207 FRF_AZ_SRM_INIT_EN, 1,
2617 SRM_NUM_BANKS_AND_BANK_SIZE, 0); 1208 FRF_AZ_SRM_NB_SZ, 0);
2618 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); 1209 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2619 1210
2620 /* Wait for SRAM reset to complete */ 1211 /* Wait for SRAM reset to complete */
2621 count = 0; 1212 count = 0;
@@ -2626,8 +1217,8 @@ static int falcon_reset_sram(struct efx_nic *efx)
2626 schedule_timeout_uninterruptible(HZ / 50); 1217 schedule_timeout_uninterruptible(HZ / 50);
2627 1218
2628 /* Check for reset complete */ 1219 /* Check for reset complete */
2629 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); 1220 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2630 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) { 1221 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2631 EFX_LOG(efx, "SRAM reset complete\n"); 1222 EFX_LOG(efx, "SRAM reset complete\n");
2632 1223
2633 return 0; 1224 return 0;
@@ -2663,8 +1254,6 @@ static int falcon_spi_device_init(struct efx_nic *efx,
2663 spi_device->block_size = 1254 spi_device->block_size =
2664 1 << SPI_DEV_TYPE_FIELD(device_type, 1255 1 << SPI_DEV_TYPE_FIELD(device_type,
2665 SPI_DEV_TYPE_BLOCK_SIZE); 1256 SPI_DEV_TYPE_BLOCK_SIZE);
2666
2667 spi_device->efx = efx;
2668 } else { 1257 } else {
2669 spi_device = NULL; 1258 spi_device = NULL;
2670 } 1259 }
@@ -2674,7 +1263,6 @@ static int falcon_spi_device_init(struct efx_nic *efx,
2674 return 0; 1263 return 0;
2675} 1264}
2676 1265
2677
2678static void falcon_remove_spi_devices(struct efx_nic *efx) 1266static void falcon_remove_spi_devices(struct efx_nic *efx)
2679{ 1267{
2680 kfree(efx->spi_eeprom); 1268 kfree(efx->spi_eeprom);
@@ -2712,16 +1300,16 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2712 board_rev = le16_to_cpu(v2->board_revision); 1300 board_rev = le16_to_cpu(v2->board_revision);
2713 1301
2714 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { 1302 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2715 __le32 fl = v3->spi_device_type[EE_SPI_FLASH]; 1303 rc = falcon_spi_device_init(
2716 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM]; 1304 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2717 rc = falcon_spi_device_init(efx, &efx->spi_flash, 1305 le32_to_cpu(v3->spi_device_type
2718 EE_SPI_FLASH, 1306 [FFE_AB_SPI_DEVICE_FLASH]));
2719 le32_to_cpu(fl));
2720 if (rc) 1307 if (rc)
2721 goto fail2; 1308 goto fail2;
2722 rc = falcon_spi_device_init(efx, &efx->spi_eeprom, 1309 rc = falcon_spi_device_init(
2723 EE_SPI_EEPROM, 1310 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2724 le32_to_cpu(ee)); 1311 le32_to_cpu(v3->spi_device_type
1312 [FFE_AB_SPI_DEVICE_EEPROM]));
2725 if (rc) 1313 if (rc)
2726 goto fail2; 1314 goto fail2;
2727 } 1315 }
@@ -2732,7 +1320,9 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2732 1320
2733 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad); 1321 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2734 1322
2735 efx_set_board_info(efx, board_rev); 1323 rc = falcon_probe_board(efx, board_rev);
1324 if (rc)
1325 goto fail2;
2736 1326
2737 kfree(nvconfig); 1327 kfree(nvconfig);
2738 return 0; 1328 return 0;
@@ -2744,89 +1334,49 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2744 return rc; 1334 return rc;
2745} 1335}
2746 1336
2747/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2748 * count, port speed). Set workaround and feature flags accordingly.
2749 */
2750static int falcon_probe_nic_variant(struct efx_nic *efx)
2751{
2752 efx_oword_t altera_build;
2753 efx_oword_t nic_stat;
2754
2755 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2756 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2757 EFX_ERR(efx, "Falcon FPGA not supported\n");
2758 return -ENODEV;
2759 }
2760
2761 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2762
2763 switch (falcon_rev(efx)) {
2764 case FALCON_REV_A0:
2765 case 0xff:
2766 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2767 return -ENODEV;
2768
2769 case FALCON_REV_A1:
2770 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2771 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2772 return -ENODEV;
2773 }
2774 break;
2775
2776 case FALCON_REV_B0:
2777 break;
2778
2779 default:
2780 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2781 return -ENODEV;
2782 }
2783
2784 /* Initial assumed speed */
2785 efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000;
2786
2787 return 0;
2788}
2789
2790/* Probe all SPI devices on the NIC */ 1337/* Probe all SPI devices on the NIC */
2791static void falcon_probe_spi_devices(struct efx_nic *efx) 1338static void falcon_probe_spi_devices(struct efx_nic *efx)
2792{ 1339{
2793 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; 1340 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2794 int boot_dev; 1341 int boot_dev;
2795 1342
2796 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER); 1343 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2797 falcon_read(efx, &nic_stat, NIC_STAT_REG); 1344 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2798 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER); 1345 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2799 1346
2800 if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) { 1347 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2801 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ? 1348 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2802 EE_SPI_FLASH : EE_SPI_EEPROM); 1349 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2803 EFX_LOG(efx, "Booted from %s\n", 1350 EFX_LOG(efx, "Booted from %s\n",
2804 boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM"); 1351 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2805 } else { 1352 } else {
2806 /* Disable VPD and set clock dividers to safe 1353 /* Disable VPD and set clock dividers to safe
2807 * values for initial programming. */ 1354 * values for initial programming. */
2808 boot_dev = -1; 1355 boot_dev = -1;
2809 EFX_LOG(efx, "Booted from internal ASIC settings;" 1356 EFX_LOG(efx, "Booted from internal ASIC settings;"
2810 " setting SPI config\n"); 1357 " setting SPI config\n");
2811 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0, 1358 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2812 /* 125 MHz / 7 ~= 20 MHz */ 1359 /* 125 MHz / 7 ~= 20 MHz */
2813 EE_SF_CLOCK_DIV, 7, 1360 FRF_AB_EE_SF_CLOCK_DIV, 7,
2814 /* 125 MHz / 63 ~= 2 MHz */ 1361 /* 125 MHz / 63 ~= 2 MHz */
2815 EE_EE_CLOCK_DIV, 63); 1362 FRF_AB_EE_EE_CLOCK_DIV, 63);
2816 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER); 1363 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2817 } 1364 }
2818 1365
2819 if (boot_dev == EE_SPI_FLASH) 1366 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2820 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH, 1367 falcon_spi_device_init(efx, &efx->spi_flash,
1368 FFE_AB_SPI_DEVICE_FLASH,
2821 default_flash_type); 1369 default_flash_type);
2822 if (boot_dev == EE_SPI_EEPROM) 1370 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2823 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM, 1371 falcon_spi_device_init(efx, &efx->spi_eeprom,
1372 FFE_AB_SPI_DEVICE_EEPROM,
2824 large_eeprom_type); 1373 large_eeprom_type);
2825} 1374}
2826 1375
2827int falcon_probe_nic(struct efx_nic *efx) 1376static int falcon_probe_nic(struct efx_nic *efx)
2828{ 1377{
2829 struct falcon_nic_data *nic_data; 1378 struct falcon_nic_data *nic_data;
1379 struct falcon_board *board;
2830 int rc; 1380 int rc;
2831 1381
2832 /* Allocate storage for hardware specific data */ 1382 /* Allocate storage for hardware specific data */
@@ -2835,15 +1385,33 @@ int falcon_probe_nic(struct efx_nic *efx)
2835 return -ENOMEM; 1385 return -ENOMEM;
2836 efx->nic_data = nic_data; 1386 efx->nic_data = nic_data;
2837 1387
2838 /* Determine number of ports etc. */ 1388 rc = -ENODEV;
2839 rc = falcon_probe_nic_variant(efx); 1389
2840 if (rc) 1390 if (efx_nic_fpga_ver(efx) != 0) {
1391 EFX_ERR(efx, "Falcon FPGA not supported\n");
2841 goto fail1; 1392 goto fail1;
1393 }
2842 1394
2843 /* Probe secondary function if expected */ 1395 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2844 if (FALCON_IS_DUAL_FUNC(efx)) { 1396 efx_oword_t nic_stat;
2845 struct pci_dev *dev = pci_dev_get(efx->pci_dev); 1397 struct pci_dev *dev;
1398 u8 pci_rev = efx->pci_dev->revision;
1399
1400 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1401 EFX_ERR(efx, "Falcon rev A0 not supported\n");
1402 goto fail1;
1403 }
1404 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1405 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1406 EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
1407 goto fail1;
1408 }
1409 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1410 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
1411 goto fail1;
1412 }
2846 1413
1414 dev = pci_dev_get(efx->pci_dev);
2847 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, 1415 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2848 dev))) { 1416 dev))) {
2849 if (dev->bus == efx->pci_dev->bus && 1417 if (dev->bus == efx->pci_dev->bus &&
@@ -2867,7 +1435,7 @@ int falcon_probe_nic(struct efx_nic *efx)
2867 } 1435 }
2868 1436
2869 /* Allocate memory for INT_KER */ 1437 /* Allocate memory for INT_KER */
2870 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); 1438 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2871 if (rc) 1439 if (rc)
2872 goto fail4; 1440 goto fail4;
2873 BUG_ON(efx->irq_status.dma_addr & 0x0f); 1441 BUG_ON(efx->irq_status.dma_addr & 0x0f);
@@ -2884,21 +1452,36 @@ int falcon_probe_nic(struct efx_nic *efx)
2884 goto fail5; 1452 goto fail5;
2885 1453
2886 /* Initialise I2C adapter */ 1454 /* Initialise I2C adapter */
2887 efx->i2c_adap.owner = THIS_MODULE; 1455 board = falcon_board(efx);
2888 nic_data->i2c_data = falcon_i2c_bit_operations; 1456 board->i2c_adap.owner = THIS_MODULE;
2889 nic_data->i2c_data.data = efx; 1457 board->i2c_data = falcon_i2c_bit_operations;
2890 efx->i2c_adap.algo_data = &nic_data->i2c_data; 1458 board->i2c_data.data = efx;
2891 efx->i2c_adap.dev.parent = &efx->pci_dev->dev; 1459 board->i2c_adap.algo_data = &board->i2c_data;
2892 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name)); 1460 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2893 rc = i2c_bit_add_bus(&efx->i2c_adap); 1461 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1462 sizeof(board->i2c_adap.name));
1463 rc = i2c_bit_add_bus(&board->i2c_adap);
2894 if (rc) 1464 if (rc)
2895 goto fail5; 1465 goto fail5;
2896 1466
1467 rc = falcon_board(efx)->type->init(efx);
1468 if (rc) {
1469 EFX_ERR(efx, "failed to initialise board\n");
1470 goto fail6;
1471 }
1472
1473 nic_data->stats_disable_count = 1;
1474 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1475 (unsigned long)efx);
1476
2897 return 0; 1477 return 0;
2898 1478
1479 fail6:
1480 BUG_ON(i2c_del_adapter(&board->i2c_adap));
1481 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2899 fail5: 1482 fail5:
2900 falcon_remove_spi_devices(efx); 1483 falcon_remove_spi_devices(efx);
2901 falcon_free_buffer(efx, &efx->irq_status); 1484 efx_nic_free_buffer(efx, &efx->irq_status);
2902 fail4: 1485 fail4:
2903 fail3: 1486 fail3:
2904 if (nic_data->pci_dev2) { 1487 if (nic_data->pci_dev2) {
@@ -2911,166 +1494,147 @@ int falcon_probe_nic(struct efx_nic *efx)
2911 return rc; 1494 return rc;
2912} 1495}
2913 1496
1497static void falcon_init_rx_cfg(struct efx_nic *efx)
1498{
1499 /* Prior to Siena the RX DMA engine will split each frame at
1500 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1501 * be so large that that never happens. */
1502 const unsigned huge_buf_size = (3 * 4096) >> 5;
1503 /* RX control FIFO thresholds (32 entries) */
1504 const unsigned ctrl_xon_thr = 20;
1505 const unsigned ctrl_xoff_thr = 25;
1506 /* RX data FIFO thresholds (256-byte units; size varies) */
1507 int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1508 int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1509 efx_oword_t reg;
1510
1511 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1512 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1513 /* Data FIFO size is 5.5K */
1514 if (data_xon_thr < 0)
1515 data_xon_thr = 512 >> 8;
1516 if (data_xoff_thr < 0)
1517 data_xoff_thr = 2048 >> 8;
1518 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1519 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1520 huge_buf_size);
1521 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1522 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1523 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1524 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1525 } else {
1526 /* Data FIFO size is 80K; register fields moved */
1527 if (data_xon_thr < 0)
1528 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1529 if (data_xoff_thr < 0)
1530 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1531 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1532 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1533 huge_buf_size);
1534 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1535 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1536 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1537 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1538 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1539 }
1540 /* Always enable XOFF signal from RX FIFO. We enable
1541 * or disable transmission of pause frames at the MAC. */
1542 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1543 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1544}
1545
2914/* This call performs hardware-specific global initialisation, such as 1546/* This call performs hardware-specific global initialisation, such as
2915 * defining the descriptor cache sizes and number of RSS channels. 1547 * defining the descriptor cache sizes and number of RSS channels.
2916 * It does not set up any buffers, descriptor rings or event queues. 1548 * It does not set up any buffers, descriptor rings or event queues.
2917 */ 1549 */
2918int falcon_init_nic(struct efx_nic *efx) 1550static int falcon_init_nic(struct efx_nic *efx)
2919{ 1551{
2920 efx_oword_t temp; 1552 efx_oword_t temp;
2921 unsigned thresh;
2922 int rc; 1553 int rc;
2923 1554
2924 /* Use on-chip SRAM */ 1555 /* Use on-chip SRAM */
2925 falcon_read(efx, &temp, NIC_STAT_REG); 1556 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2926 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1); 1557 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2927 falcon_write(efx, &temp, NIC_STAT_REG); 1558 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2928 1559
2929 /* Set the source of the GMAC clock */ 1560 /* Set the source of the GMAC clock */
2930 if (falcon_rev(efx) == FALCON_REV_B0) { 1561 if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
2931 falcon_read(efx, &temp, GPIO_CTL_REG_KER); 1562 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2932 EFX_SET_OWORD_FIELD(temp, GPIO_USE_NIC_CLK, true); 1563 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2933 falcon_write(efx, &temp, GPIO_CTL_REG_KER); 1564 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2934 } 1565 }
2935 1566
2936 /* Set buffer table mode */ 1567 /* Select the correct MAC */
2937 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL); 1568 falcon_clock_mac(efx);
2938 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2939 1569
2940 rc = falcon_reset_sram(efx); 1570 rc = falcon_reset_sram(efx);
2941 if (rc) 1571 if (rc)
2942 return rc; 1572 return rc;
2943 1573
2944 /* Set positions of descriptor caches in SRAM. */
2945 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2946 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2947 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2948 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2949
2950 /* Set TX descriptor cache size. */
2951 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2952 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2953 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2954
2955 /* Set RX descriptor cache size. Set low watermark to size-8, as
2956 * this allows most efficient prefetching.
2957 */
2958 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2959 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2960 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2961 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2962 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2963
2964 /* Clear the parity enables on the TX data fifos as 1574 /* Clear the parity enables on the TX data fifos as
2965 * they produce false parity errors because of timing issues 1575 * they produce false parity errors because of timing issues
2966 */ 1576 */
2967 if (EFX_WORKAROUND_5129(efx)) { 1577 if (EFX_WORKAROUND_5129(efx)) {
2968 falcon_read(efx, &temp, SPARE_REG_KER); 1578 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2969 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0); 1579 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2970 falcon_write(efx, &temp, SPARE_REG_KER); 1580 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2971 } 1581 }
2972 1582
2973 /* Enable all the genuinely fatal interrupts. (They are still
2974 * masked by the overall interrupt mask, controlled by
2975 * falcon_interrupts()).
2976 *
2977 * Note: All other fatal interrupts are enabled
2978 */
2979 EFX_POPULATE_OWORD_3(temp,
2980 ILL_ADR_INT_KER_EN, 1,
2981 RBUF_OWN_INT_KER_EN, 1,
2982 TBUF_OWN_INT_KER_EN, 1);
2983 EFX_INVERT_OWORD(temp);
2984 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2985
2986 if (EFX_WORKAROUND_7244(efx)) { 1583 if (EFX_WORKAROUND_7244(efx)) {
2987 falcon_read(efx, &temp, RX_FILTER_CTL_REG); 1584 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2988 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8); 1585 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
2989 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8); 1586 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
2990 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8); 1587 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
2991 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8); 1588 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
2992 falcon_write(efx, &temp, RX_FILTER_CTL_REG); 1589 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2993 } 1590 }
2994 1591
2995 falcon_setup_rss_indir_table(efx); 1592 /* XXX This is documented only for Falcon A0/A1 */
2996
2997 /* Setup RX. Wait for descriptor is broken and must 1593 /* Setup RX. Wait for descriptor is broken and must
2998 * be disabled. RXDP recovery shouldn't be needed, but is. 1594 * be disabled. RXDP recovery shouldn't be needed, but is.
2999 */ 1595 */
3000 falcon_read(efx, &temp, RX_SELF_RST_REG_KER); 1596 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3001 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1); 1597 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3002 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1); 1598 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3003 if (EFX_WORKAROUND_5583(efx)) 1599 if (EFX_WORKAROUND_5583(efx))
3004 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1); 1600 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3005 falcon_write(efx, &temp, RX_SELF_RST_REG_KER); 1601 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3006
3007 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3008 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3009 */
3010 falcon_read(efx, &temp, TX_CFG2_REG_KER);
3011 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
3012 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
3013 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
3014 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
3015 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
3016 /* Enable SW_EV to inherit in char driver - assume harmless here */
3017 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
3018 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3019 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
3020 /* Squash TX of packets of 16 bytes or less */
3021 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3022 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
3023 falcon_write(efx, &temp, TX_CFG2_REG_KER);
3024 1602
3025 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 1603 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3026 * descriptors (which is bad). 1604 * descriptors (which is bad).
3027 */ 1605 */
3028 falcon_read(efx, &temp, TX_CFG_REG_KER); 1606 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3029 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0); 1607 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3030 falcon_write(efx, &temp, TX_CFG_REG_KER); 1608 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3031 1609
3032 /* RX config */ 1610 falcon_init_rx_cfg(efx);
3033 falcon_read(efx, &temp, RX_CFG_REG_KER);
3034 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
3035 if (EFX_WORKAROUND_7575(efx))
3036 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
3037 (3 * 4096) / 32);
3038 if (falcon_rev(efx) >= FALCON_REV_B0)
3039 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
3040
3041 /* RX FIFO flow control thresholds */
3042 thresh = ((rx_xon_thresh_bytes >= 0) ?
3043 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
3044 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
3045 thresh = ((rx_xoff_thresh_bytes >= 0) ?
3046 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
3047 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
3048 /* RX control FIFO thresholds [32 entries] */
3049 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3050 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
3051 falcon_write(efx, &temp, RX_CFG_REG_KER);
3052 1611
3053 /* Set destination of both TX and RX Flush events */ 1612 /* Set destination of both TX and RX Flush events */
3054 if (falcon_rev(efx) >= FALCON_REV_B0) { 1613 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
3055 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0); 1614 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3056 falcon_write(efx, &temp, DP_CTRL_REG); 1615 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3057 } 1616 }
3058 1617
1618 efx_nic_init_common(efx);
1619
3059 return 0; 1620 return 0;
3060} 1621}
3061 1622
3062void falcon_remove_nic(struct efx_nic *efx) 1623static void falcon_remove_nic(struct efx_nic *efx)
3063{ 1624{
3064 struct falcon_nic_data *nic_data = efx->nic_data; 1625 struct falcon_nic_data *nic_data = efx->nic_data;
1626 struct falcon_board *board = falcon_board(efx);
3065 int rc; 1627 int rc;
3066 1628
1629 board->type->fini(efx);
1630
3067 /* Remove I2C adapter and clear it in preparation for a retry */ 1631 /* Remove I2C adapter and clear it in preparation for a retry */
3068 rc = i2c_del_adapter(&efx->i2c_adap); 1632 rc = i2c_del_adapter(&board->i2c_adap);
3069 BUG_ON(rc); 1633 BUG_ON(rc);
3070 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap)); 1634 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
3071 1635
3072 falcon_remove_spi_devices(efx); 1636 falcon_remove_spi_devices(efx);
3073 falcon_free_buffer(efx, &efx->irq_status); 1637 efx_nic_free_buffer(efx, &efx->irq_status);
3074 1638
3075 falcon_reset_hw(efx, RESET_TYPE_ALL); 1639 falcon_reset_hw(efx, RESET_TYPE_ALL);
3076 1640
@@ -3085,65 +1649,180 @@ void falcon_remove_nic(struct efx_nic *efx)
3085 efx->nic_data = NULL; 1649 efx->nic_data = NULL;
3086} 1650}
3087 1651
3088void falcon_update_nic_stats(struct efx_nic *efx) 1652static void falcon_update_nic_stats(struct efx_nic *efx)
3089{ 1653{
1654 struct falcon_nic_data *nic_data = efx->nic_data;
3090 efx_oword_t cnt; 1655 efx_oword_t cnt;
3091 1656
3092 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER); 1657 if (nic_data->stats_disable_count)
3093 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT); 1658 return;
1659
1660 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1661 efx->n_rx_nodesc_drop_cnt +=
1662 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1663
1664 if (nic_data->stats_pending &&
1665 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1666 nic_data->stats_pending = false;
1667 rmb(); /* read the done flag before the stats */
1668 efx->mac_op->update_stats(efx);
1669 }
1670}
1671
1672void falcon_start_nic_stats(struct efx_nic *efx)
1673{
1674 struct falcon_nic_data *nic_data = efx->nic_data;
1675
1676 spin_lock_bh(&efx->stats_lock);
1677 if (--nic_data->stats_disable_count == 0)
1678 falcon_stats_request(efx);
1679 spin_unlock_bh(&efx->stats_lock);
1680}
1681
1682void falcon_stop_nic_stats(struct efx_nic *efx)
1683{
1684 struct falcon_nic_data *nic_data = efx->nic_data;
1685 int i;
1686
1687 might_sleep();
1688
1689 spin_lock_bh(&efx->stats_lock);
1690 ++nic_data->stats_disable_count;
1691 spin_unlock_bh(&efx->stats_lock);
1692
1693 del_timer_sync(&nic_data->stats_timer);
1694
1695 /* Wait enough time for the most recent transfer to
1696 * complete. */
1697 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1698 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1699 break;
1700 msleep(1);
1701 }
1702
1703 spin_lock_bh(&efx->stats_lock);
1704 falcon_stats_complete(efx);
1705 spin_unlock_bh(&efx->stats_lock);
1706}
1707
1708static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1709{
1710 falcon_board(efx)->type->set_id_led(efx, mode);
1711}
1712
1713/**************************************************************************
1714 *
1715 * Wake on LAN
1716 *
1717 **************************************************************************
1718 */
1719
1720static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1721{
1722 wol->supported = 0;
1723 wol->wolopts = 0;
1724 memset(&wol->sopass, 0, sizeof(wol->sopass));
1725}
1726
1727static int falcon_set_wol(struct efx_nic *efx, u32 type)
1728{
1729 if (type != 0)
1730 return -EINVAL;
1731 return 0;
3094} 1732}
3095 1733
3096/************************************************************************** 1734/**************************************************************************
3097 * 1735 *
3098 * Revision-dependent attributes used by efx.c 1736 * Revision-dependent attributes used by efx.c and nic.c
3099 * 1737 *
3100 ************************************************************************** 1738 **************************************************************************
3101 */ 1739 */
3102 1740
3103struct efx_nic_type falcon_a_nic_type = { 1741struct efx_nic_type falcon_a1_nic_type = {
3104 .mem_bar = 2, 1742 .probe = falcon_probe_nic,
1743 .remove = falcon_remove_nic,
1744 .init = falcon_init_nic,
1745 .fini = efx_port_dummy_op_void,
1746 .monitor = falcon_monitor,
1747 .reset = falcon_reset_hw,
1748 .probe_port = falcon_probe_port,
1749 .remove_port = falcon_remove_port,
1750 .prepare_flush = falcon_prepare_flush,
1751 .update_stats = falcon_update_nic_stats,
1752 .start_stats = falcon_start_nic_stats,
1753 .stop_stats = falcon_stop_nic_stats,
1754 .set_id_led = falcon_set_id_led,
1755 .push_irq_moderation = falcon_push_irq_moderation,
1756 .push_multicast_hash = falcon_push_multicast_hash,
1757 .reconfigure_port = falcon_reconfigure_port,
1758 .get_wol = falcon_get_wol,
1759 .set_wol = falcon_set_wol,
1760 .resume_wol = efx_port_dummy_op_void,
1761 .test_nvram = falcon_test_nvram,
1762 .default_mac_ops = &falcon_xmac_operations,
1763
1764 .revision = EFX_REV_FALCON_A1,
3105 .mem_map_size = 0x20000, 1765 .mem_map_size = 0x20000,
3106 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1, 1766 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3107 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1, 1767 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3108 .buf_tbl_base = BUF_TBL_KER_A1, 1768 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3109 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1, 1769 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3110 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1, 1770 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3111 .txd_ring_mask = FALCON_TXD_RING_MASK, 1771 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3112 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3113 .evq_size = FALCON_EVQ_SIZE,
3114 .max_dma_mask = FALCON_DMA_MASK,
3115 .tx_dma_mask = FALCON_TX_DMA_MASK,
3116 .bug5391_mask = 0xf,
3117 .rx_xoff_thresh = 2048,
3118 .rx_xon_thresh = 512,
3119 .rx_buffer_padding = 0x24, 1772 .rx_buffer_padding = 0x24,
3120 .max_interrupt_mode = EFX_INT_MODE_MSI, 1773 .max_interrupt_mode = EFX_INT_MODE_MSI,
3121 .phys_addr_channels = 4, 1774 .phys_addr_channels = 4,
1775 .tx_dc_base = 0x130000,
1776 .rx_dc_base = 0x100000,
1777 .offload_features = NETIF_F_IP_CSUM,
1778 .reset_world_flags = ETH_RESET_IRQ,
3122}; 1779};
3123 1780
3124struct efx_nic_type falcon_b_nic_type = { 1781struct efx_nic_type falcon_b0_nic_type = {
3125 .mem_bar = 2, 1782 .probe = falcon_probe_nic,
1783 .remove = falcon_remove_nic,
1784 .init = falcon_init_nic,
1785 .fini = efx_port_dummy_op_void,
1786 .monitor = falcon_monitor,
1787 .reset = falcon_reset_hw,
1788 .probe_port = falcon_probe_port,
1789 .remove_port = falcon_remove_port,
1790 .prepare_flush = falcon_prepare_flush,
1791 .update_stats = falcon_update_nic_stats,
1792 .start_stats = falcon_start_nic_stats,
1793 .stop_stats = falcon_stop_nic_stats,
1794 .set_id_led = falcon_set_id_led,
1795 .push_irq_moderation = falcon_push_irq_moderation,
1796 .push_multicast_hash = falcon_push_multicast_hash,
1797 .reconfigure_port = falcon_reconfigure_port,
1798 .get_wol = falcon_get_wol,
1799 .set_wol = falcon_set_wol,
1800 .resume_wol = efx_port_dummy_op_void,
1801 .test_registers = falcon_b0_test_registers,
1802 .test_nvram = falcon_test_nvram,
1803 .default_mac_ops = &falcon_xmac_operations,
1804
1805 .revision = EFX_REV_FALCON_B0,
3126 /* Map everything up to and including the RSS indirection 1806 /* Map everything up to and including the RSS indirection
3127 * table. Don't map MSI-X table, MSI-X PBA since Linux 1807 * table. Don't map MSI-X table, MSI-X PBA since Linux
3128 * requires that they not be mapped. */ 1808 * requires that they not be mapped. */
3129 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800, 1809 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3130 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0, 1810 FR_BZ_RX_INDIRECTION_TBL_STEP *
3131 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0, 1811 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3132 .buf_tbl_base = BUF_TBL_KER_B0, 1812 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3133 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0, 1813 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3134 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0, 1814 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3135 .txd_ring_mask = FALCON_TXD_RING_MASK, 1815 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3136 .rxd_ring_mask = FALCON_RXD_RING_MASK, 1816 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3137 .evq_size = FALCON_EVQ_SIZE, 1817 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3138 .max_dma_mask = FALCON_DMA_MASK,
3139 .tx_dma_mask = FALCON_TX_DMA_MASK,
3140 .bug5391_mask = 0,
3141 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3142 .rx_xon_thresh = 27648, /* ~3*max MTU */
3143 .rx_buffer_padding = 0, 1818 .rx_buffer_padding = 0,
3144 .max_interrupt_mode = EFX_INT_MODE_MSIX, 1819 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3145 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy 1820 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3146 * interrupt handler only supports 32 1821 * interrupt handler only supports 32
3147 * channels */ 1822 * channels */
1823 .tx_dc_base = 0x130000,
1824 .rx_dc_base = 0x100000,
1825 .offload_features = NETIF_F_IP_CSUM,
1826 .reset_world_flags = ETH_RESET_IRQ,
3148}; 1827};
3149 1828
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-29 07:56:29 -0400