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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/s2io.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/s2io.h')
-rw-r--r--drivers/net/s2io.h33
1 files changed, 9 insertions, 24 deletions
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 0af033533905..800b3a44e653 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -355,13 +355,12 @@ struct stat_block {
355#define FIFO_OTHER_MAX_NUM 1 355#define FIFO_OTHER_MAX_NUM 1
356 356
357 357
358#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 ) 358#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128)
359#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) 359#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86)
360#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
361#define MAX_TX_DESC (MAX_AVAILABLE_TXDS) 360#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
362 361
363/* FIFO mappings for all possible number of fifos configured */ 362/* FIFO mappings for all possible number of fifos configured */
364static int fifo_map[][MAX_TX_FIFOS] = { 363static const int fifo_map[][MAX_TX_FIFOS] = {
365 {0, 0, 0, 0, 0, 0, 0, 0}, 364 {0, 0, 0, 0, 0, 0, 0, 0},
366 {0, 0, 0, 0, 1, 1, 1, 1}, 365 {0, 0, 0, 0, 1, 1, 1, 1},
367 {0, 0, 0, 1, 1, 1, 2, 2}, 366 {0, 0, 0, 1, 1, 1, 2, 2},
@@ -372,12 +371,12 @@ static int fifo_map[][MAX_TX_FIFOS] = {
372 {0, 1, 2, 3, 4, 5, 6, 7}, 371 {0, 1, 2, 3, 4, 5, 6, 7},
373}; 372};
374 373
375static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7}; 374static const u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
376 375
377/* Maintains Per FIFO related information. */ 376/* Maintains Per FIFO related information. */
378struct tx_fifo_config { 377struct tx_fifo_config {
379#define MAX_AVAILABLE_TXDS 8192 378#define MAX_AVAILABLE_TXDS 8192
380 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ 379 u32 fifo_len; /* specifies len of FIFO up to 8192, ie no of TxDLs */
381/* Priority definition */ 380/* Priority definition */
382#define TX_FIFO_PRI_0 0 /*Highest */ 381#define TX_FIFO_PRI_0 0 /*Highest */
383#define TX_FIFO_PRI_1 1 382#define TX_FIFO_PRI_1 1
@@ -816,12 +815,6 @@ struct mac_info {
816 struct stat_block *stats_info; /* Logical address of the stat block */ 815 struct stat_block *stats_info; /* Logical address of the stat block */
817}; 816};
818 817
819/* structure representing the user defined MAC addresses */
820struct usr_addr {
821 char addr[ETH_ALEN];
822 int usage_cnt;
823};
824
825/* Default Tunable parameters of the NIC. */ 818/* Default Tunable parameters of the NIC. */
826#define DEFAULT_FIFO_0_LEN 4096 819#define DEFAULT_FIFO_0_LEN 4096
827#define DEFAULT_FIFO_1_7_LEN 512 820#define DEFAULT_FIFO_1_7_LEN 512
@@ -894,17 +887,12 @@ struct s2io_nic {
894#define ALL_MULTI 2 887#define ALL_MULTI 2
895 888
896#define MAX_ADDRS_SUPPORTED 64 889#define MAX_ADDRS_SUPPORTED 64
897 u16 usr_addr_count;
898 u16 mc_addr_count; 890 u16 mc_addr_count;
899 struct usr_addr usr_addrs[256];
900 891
901 u16 m_cast_flg; 892 u16 m_cast_flg;
902 u16 all_multi_pos; 893 u16 all_multi_pos;
903 u16 promisc_flg; 894 u16 promisc_flg;
904 895
905 /* Id timer, used to blink NIC to physically identify NIC. */
906 struct timer_list id_timer;
907
908 /* Restart timer, used to restart NIC if the device is stuck and 896 /* Restart timer, used to restart NIC if the device is stuck and
909 * a schedule task that will set the correct Link state once the 897 * a schedule task that will set the correct Link state once the
910 * NIC's PHY has stabilized after a state change. 898 * NIC's PHY has stabilized after a state change.
@@ -971,7 +959,6 @@ struct s2io_nic {
971 959
972 unsigned long clubbed_frms_cnt; 960 unsigned long clubbed_frms_cnt;
973 unsigned long sending_both; 961 unsigned long sending_both;
974 u8 lro;
975 u16 lro_max_aggr_per_sess; 962 u16 lro_max_aggr_per_sess;
976 volatile unsigned long state; 963 volatile unsigned long state;
977 u64 general_int_mask; 964 u64 general_int_mask;
@@ -1015,18 +1002,16 @@ static inline void writeq(u64 val, void __iomem *addr)
1015#define LF 2 1002#define LF 2
1016static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) 1003static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
1017{ 1004{
1018 u32 ret;
1019
1020 if (order == LF) { 1005 if (order == LF) {
1021 writel((u32) (val), addr); 1006 writel((u32) (val), addr);
1022 ret = readl(addr); 1007 (void) readl(addr);
1023 writel((u32) (val >> 32), (addr + 4)); 1008 writel((u32) (val >> 32), (addr + 4));
1024 ret = readl(addr + 4); 1009 (void) readl(addr + 4);
1025 } else { 1010 } else {
1026 writel((u32) (val >> 32), (addr + 4)); 1011 writel((u32) (val >> 32), (addr + 4));
1027 ret = readl(addr + 4); 1012 (void) readl(addr + 4);
1028 writel((u32) (val), addr); 1013 writel((u32) (val), addr);
1029 ret = readl(addr); 1014 (void) readl(addr);
1030 } 1015 }
1031} 1016}
1032 1017