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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/r8169.c
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c3325
1 files changed, 1863 insertions, 1462 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 992db2fa136e..5990621fb5cd 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -24,6 +24,9 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
26#include <linux/pm_runtime.h> 26#include <linux/pm_runtime.h>
27#include <linux/firmware.h>
28#include <linux/pci-aspm.h>
29#include <linux/prefetch.h>
27 30
28#include <asm/system.h> 31#include <asm/system.h>
29#include <asm/io.h> 32#include <asm/io.h>
@@ -33,6 +36,12 @@
33#define MODULENAME "r8169" 36#define MODULENAME "r8169"
34#define PFX MODULENAME ": " 37#define PFX MODULENAME ": "
35 38
39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
44
36#ifdef RTL8169_DEBUG 45#ifdef RTL8169_DEBUG
37#define assert(expr) \ 46#define assert(expr) \
38 if (!(expr)) { \ 47 if (!(expr)) { \
@@ -63,7 +72,6 @@ static const int multicast_filter_limit = 32;
63#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 72#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 73#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 77
@@ -91,71 +99,123 @@ static const int multicast_filter_limit = 32;
91#define RTL_R32(reg) readl (ioaddr + (reg)) 99#define RTL_R32(reg) readl (ioaddr + (reg))
92 100
93enum mac_version { 101enum mac_version {
94 RTL_GIGA_MAC_NONE = 0x00, 102 RTL_GIGA_MAC_VER_01 = 0,
95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 103 RTL_GIGA_MAC_VER_02,
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S 104 RTL_GIGA_MAC_VER_03,
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S 105 RTL_GIGA_MAC_VER_04,
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB 106 RTL_GIGA_MAC_VER_05,
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd 107 RTL_GIGA_MAC_VER_06,
100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe 108 RTL_GIGA_MAC_VER_07,
101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e 109 RTL_GIGA_MAC_VER_08,
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e 110 RTL_GIGA_MAC_VER_09,
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e 111 RTL_GIGA_MAC_VER_10,
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e 112 RTL_GIGA_MAC_VER_11,
105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb 113 RTL_GIGA_MAC_VER_12,
106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 114 RTL_GIGA_MAC_VER_13,
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 115 RTL_GIGA_MAC_VER_14,
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? 116 RTL_GIGA_MAC_VER_15,
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? 117 RTL_GIGA_MAC_VER_16,
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec 118 RTL_GIGA_MAC_VER_17,
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf 119 RTL_GIGA_MAC_VER_18,
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP 120 RTL_GIGA_MAC_VER_19,
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C 121 RTL_GIGA_MAC_VER_20,
114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C 122 RTL_GIGA_MAC_VER_21,
115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C 123 RTL_GIGA_MAC_VER_22,
116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C 124 RTL_GIGA_MAC_VER_23,
117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP 125 RTL_GIGA_MAC_VER_24,
118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP 126 RTL_GIGA_MAC_VER_25,
119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D 127 RTL_GIGA_MAC_VER_26,
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D 128 RTL_GIGA_MAC_VER_27,
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP 129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
135 RTL_GIGA_MAC_NONE = 0xff,
136};
137
138enum rtl_tx_desc_version {
139 RTL_TD_0 = 0,
140 RTL_TD_1 = 1,
122}; 141};
123 142
124#define _R(NAME,MAC,MASK) \ 143#define _R(NAME,TD,FW) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } 144 { .name = NAME, .txd_version = TD, .fw_name = FW }
126 145
127static const struct { 146static const struct {
128 const char *name; 147 const char *name;
129 u8 mac_version; 148 enum rtl_tx_desc_version txd_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */ 149 const char *fw_name;
131} rtl_chip_info[] = { 150} rtl_chip_infos[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 151 /* PCI devices. */
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S 152 [RTL_GIGA_MAC_VER_01] =
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S 153 _R("RTL8169", RTL_TD_0, NULL),
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB 154 [RTL_GIGA_MAC_VER_02] =
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd 155 _R("RTL8169s", RTL_TD_0, NULL),
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe 156 [RTL_GIGA_MAC_VER_03] =
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E 157 _R("RTL8110s", RTL_TD_0, NULL),
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E 158 [RTL_GIGA_MAC_VER_04] =
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E 159 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E 160 [RTL_GIGA_MAC_VER_05] =
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E 161 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E 162 [RTL_GIGA_MAC_VER_06] =
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 163 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 164 /* PCI-E devices. */
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 165 [RTL_GIGA_MAC_VER_07] =
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E 166 _R("RTL8102e", RTL_TD_1, NULL),
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E 167 [RTL_GIGA_MAC_VER_08] =
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E 168 _R("RTL8102e", RTL_TD_1, NULL),
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E 169 [RTL_GIGA_MAC_VER_09] =
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E 170 _R("RTL8102e", RTL_TD_1, NULL),
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E 171 [RTL_GIGA_MAC_VER_10] =
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E 172 _R("RTL8101e", RTL_TD_0, NULL),
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E 173 [RTL_GIGA_MAC_VER_11] =
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E 174 _R("RTL8168b/8111b", RTL_TD_0, NULL),
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E 175 [RTL_GIGA_MAC_VER_12] =
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E 176 _R("RTL8168b/8111b", RTL_TD_0, NULL),
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E 177 [RTL_GIGA_MAC_VER_13] =
178 _R("RTL8101e", RTL_TD_0, NULL),
179 [RTL_GIGA_MAC_VER_14] =
180 _R("RTL8100e", RTL_TD_0, NULL),
181 [RTL_GIGA_MAC_VER_15] =
182 _R("RTL8100e", RTL_TD_0, NULL),
183 [RTL_GIGA_MAC_VER_16] =
184 _R("RTL8101e", RTL_TD_0, NULL),
185 [RTL_GIGA_MAC_VER_17] =
186 _R("RTL8168b/8111b", RTL_TD_0, NULL),
187 [RTL_GIGA_MAC_VER_18] =
188 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
189 [RTL_GIGA_MAC_VER_19] =
190 _R("RTL8168c/8111c", RTL_TD_1, NULL),
191 [RTL_GIGA_MAC_VER_20] =
192 _R("RTL8168c/8111c", RTL_TD_1, NULL),
193 [RTL_GIGA_MAC_VER_21] =
194 _R("RTL8168c/8111c", RTL_TD_1, NULL),
195 [RTL_GIGA_MAC_VER_22] =
196 _R("RTL8168c/8111c", RTL_TD_1, NULL),
197 [RTL_GIGA_MAC_VER_23] =
198 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
199 [RTL_GIGA_MAC_VER_24] =
200 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
201 [RTL_GIGA_MAC_VER_25] =
202 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
203 [RTL_GIGA_MAC_VER_26] =
204 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
205 [RTL_GIGA_MAC_VER_27] =
206 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
207 [RTL_GIGA_MAC_VER_28] =
208 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
209 [RTL_GIGA_MAC_VER_29] =
210 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
211 [RTL_GIGA_MAC_VER_30] =
212 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
213 [RTL_GIGA_MAC_VER_31] =
214 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
215 [RTL_GIGA_MAC_VER_32] =
216 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
217 [RTL_GIGA_MAC_VER_33] =
218 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
159}; 219};
160#undef _R 220#undef _R
161 221
@@ -187,12 +247,7 @@ static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
187 247
188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 248MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189 249
190/* 250static int rx_buf_sz = 16383;
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
193 * rtl8169_open()
194 */
195static int rx_copybreak = 16383;
196static int use_dac; 251static int use_dac;
197static struct { 252static struct {
198 u32 msg_enable; 253 u32 msg_enable;
@@ -216,6 +271,9 @@ enum rtl_registers {
216 IntrStatus = 0x3e, 271 IntrStatus = 0x3e,
217 TxConfig = 0x40, 272 TxConfig = 0x40,
218 RxConfig = 0x44, 273 RxConfig = 0x44,
274
275#define RTL_RX_CONFIG_MASK 0xff7e1880u
276
219 RxMissed = 0x4c, 277 RxMissed = 0x4c,
220 Cfg9346 = 0x50, 278 Cfg9346 = 0x50,
221 Config0 = 0x51, 279 Config0 = 0x51,
@@ -232,7 +290,14 @@ enum rtl_registers {
232 IntrMitigate = 0xe2, 290 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4, 291 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8, 292 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec, 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295#define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299#define TxPacketMax (8064 >> 7)
300
236 FuncEvent = 0xf0, 301 FuncEvent = 0xf0,
237 FuncEventMask = 0xf4, 302 FuncEventMask = 0xf4,
238 FuncPresetState = 0xf8, 303 FuncPresetState = 0xf8,
@@ -253,16 +318,22 @@ enum rtl8168_8101_registers {
253#define CSIAR_BYTE_ENABLE 0x0f 318#define CSIAR_BYTE_ENABLE 0x0f
254#define CSIAR_BYTE_ENABLE_SHIFT 12 319#define CSIAR_BYTE_ENABLE_SHIFT 12
255#define CSIAR_ADDR_MASK 0x0fff 320#define CSIAR_ADDR_MASK 0x0fff
256 321 PMCH = 0x6f,
257 EPHYAR = 0x80, 322 EPHYAR = 0x80,
258#define EPHYAR_FLAG 0x80000000 323#define EPHYAR_FLAG 0x80000000
259#define EPHYAR_WRITE_CMD 0x80000000 324#define EPHYAR_WRITE_CMD 0x80000000
260#define EPHYAR_REG_MASK 0x1f 325#define EPHYAR_REG_MASK 0x1f
261#define EPHYAR_REG_SHIFT 16 326#define EPHYAR_REG_SHIFT 16
262#define EPHYAR_DATA_MASK 0xffff 327#define EPHYAR_DATA_MASK 0xffff
328 DLLPR = 0xd0,
329#define PM_SWITCH (1 << 6)
263 DBG_REG = 0xd1, 330 DBG_REG = 0xd1,
264#define FIX_NAK_1 (1 << 4) 331#define FIX_NAK_1 (1 << 4)
265#define FIX_NAK_2 (1 << 3) 332#define FIX_NAK_2 (1 << 3)
333 TWSI = 0xd2,
334 MCU = 0xd3,
335#define EN_NDP (1 << 3)
336#define EN_OOB_RESET (1 << 2)
266 EFUSEAR = 0xdc, 337 EFUSEAR = 0xdc,
267#define EFUSEAR_FLAG 0x80000000 338#define EFUSEAR_FLAG 0x80000000
268#define EFUSEAR_WRITE_CMD 0x80000000 339#define EFUSEAR_WRITE_CMD 0x80000000
@@ -272,6 +343,35 @@ enum rtl8168_8101_registers {
272#define EFUSEAR_DATA_MASK 0xff 343#define EFUSEAR_DATA_MASK 0xff
273}; 344};
274 345
346enum rtl8168_registers {
347 ERIDR = 0x70,
348 ERIAR = 0x74,
349#define ERIAR_FLAG 0x80000000
350#define ERIAR_WRITE_CMD 0x80000000
351#define ERIAR_READ_CMD 0x00000000
352#define ERIAR_ADDR_BYTE_ALIGN 4
353#define ERIAR_EXGMAC 0
354#define ERIAR_MSIX 1
355#define ERIAR_ASF 2
356#define ERIAR_TYPE_SHIFT 16
357#define ERIAR_BYTEEN 0x0f
358#define ERIAR_BYTEEN_SHIFT 12
359 EPHY_RXER_NUM = 0x7c,
360 OCPDR = 0xb0, /* OCP GPHY access */
361#define OCPDR_WRITE_CMD 0x80000000
362#define OCPDR_READ_CMD 0x00000000
363#define OCPDR_REG_MASK 0x7f
364#define OCPDR_GPHY_REG_SHIFT 16
365#define OCPDR_DATA_MASK 0xffff
366 OCPAR = 0xb4,
367#define OCPAR_FLAG 0x80000000
368#define OCPAR_GPHY_WRITE_CMD 0x8000f060
369#define OCPAR_GPHY_READ_CMD 0x0000f060
370 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
371 MISC = 0xf0, /* 8168e only. */
372#define TXPLA_RST (1 << 29)
373};
374
275enum rtl_register_content { 375enum rtl_register_content {
276 /* InterruptStatusBits */ 376 /* InterruptStatusBits */
277 SYSErr = 0x8000, 377 SYSErr = 0x8000,
@@ -347,6 +447,7 @@ enum rtl_register_content {
347 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 447 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 448 MWF = (1 << 5), /* Accept Multicast wakeup frame */
349 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 449 UWF = (1 << 4), /* Accept Unicast wakeup frame */
450 Spi_en = (1 << 3),
350 LanWake = (1 << 1), /* LanWake enable/disable */ 451 LanWake = (1 << 1), /* LanWake enable/disable */
351 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 452 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
352 453
@@ -395,21 +496,69 @@ enum rtl_register_content {
395 CounterDump = 0x8, 496 CounterDump = 0x8,
396}; 497};
397 498
398enum desc_status_bit { 499enum rtl_desc_bit {
500 /* First doubleword. */
399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 501 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */ 502 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */ 503 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */ 504 LastFrag = (1 << 28), /* Final segment of a packet */
505};
506
507/* Generic case. */
508enum rtl_tx_desc_bit {
509 /* First doubleword. */
510 TD_LSO = (1 << 27), /* Large Send Offload */
511#define TD_MSS_MAX 0x07ffu /* MSS value */
512
513 /* Second doubleword. */
514 TxVlanTag = (1 << 17), /* Add VLAN tag */
515};
516
517/* 8169, 8168b and 810x except 8102e. */
518enum rtl_tx_desc_bit_0 {
519 /* First doubleword. */
520#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
521 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
522 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
523 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
524};
525
526/* 8102e, 8168c and beyond. */
527enum rtl_tx_desc_bit_1 {
528 /* Second doubleword. */
529#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
530 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
531 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
532 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
533};
403 534
404 /* Tx private */ 535static const struct rtl_tx_desc_info {
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ 536 struct {
406 MSSShift = 16, /* MSS value position */ 537 u32 udp;
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ 538 u32 tcp;
408 IPCS = (1 << 18), /* Calculate IP checksum */ 539 } checksum;
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ 540 u16 mss_shift;
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ 541 u16 opts_offset;
411 TxVlanTag = (1 << 17), /* Add VLAN tag */ 542} tx_desc_info [] = {
543 [RTL_TD_0] = {
544 .checksum = {
545 .udp = TD0_IP_CS | TD0_UDP_CS,
546 .tcp = TD0_IP_CS | TD0_TCP_CS
547 },
548 .mss_shift = TD0_MSS_SHIFT,
549 .opts_offset = 0
550 },
551 [RTL_TD_1] = {
552 .checksum = {
553 .udp = TD1_IP_CS | TD1_UDP_CS,
554 .tcp = TD1_IP_CS | TD1_TCP_CS
555 },
556 .mss_shift = TD1_MSS_SHIFT,
557 .opts_offset = 1
558 }
559};
412 560
561enum rtl_rx_desc_bit {
413 /* Rx private */ 562 /* Rx private */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 563 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ 564 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
@@ -469,13 +618,13 @@ struct rtl8169_counters {
469 618
470struct rtl8169_private { 619struct rtl8169_private {
471 void __iomem *mmio_addr; /* memory map physical address */ 620 void __iomem *mmio_addr; /* memory map physical address */
472 struct pci_dev *pci_dev; /* Index of PCI device */ 621 struct pci_dev *pci_dev;
473 struct net_device *dev; 622 struct net_device *dev;
474 struct napi_struct napi; 623 struct napi_struct napi;
475 spinlock_t lock; /* spin lock flag */ 624 spinlock_t lock;
476 u32 msg_enable; 625 u32 msg_enable;
477 int chipset; 626 u16 txd_version;
478 int mac_version; 627 u16 mac_version;
479 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 628 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 629 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
481 u32 dirty_rx; 630 u32 dirty_rx;
@@ -484,24 +633,29 @@ struct rtl8169_private {
484 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 633 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr; 634 dma_addr_t TxPhyAddr;
486 dma_addr_t RxPhyAddr; 635 dma_addr_t RxPhyAddr;
487 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ 636 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
488 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 637 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
489 unsigned align;
490 unsigned rx_buf_sz;
491 struct timer_list timer; 638 struct timer_list timer;
492 u16 cp_cmd; 639 u16 cp_cmd;
493 u16 intr_event; 640 u16 intr_event;
494 u16 napi_event; 641 u16 napi_event;
495 u16 intr_mask; 642 u16 intr_mask;
496 int phy_1000_ctrl_reg; 643
497#ifdef CONFIG_R8169_VLAN 644 struct mdio_ops {
498 struct vlan_group *vlgrp; 645 void (*write)(void __iomem *, int, int);
499#endif 646 int (*read)(void __iomem *, int);
500 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); 647 } mdio_ops;
648
649 struct pll_power_ops {
650 void (*down)(struct rtl8169_private *);
651 void (*up)(struct rtl8169_private *);
652 } pll_power_ops;
653
654 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
501 int (*get_settings)(struct net_device *, struct ethtool_cmd *); 655 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
502 void (*phy_reset_enable)(void __iomem *); 656 void (*phy_reset_enable)(struct rtl8169_private *tp);
503 void (*hw_start)(struct net_device *); 657 void (*hw_start)(struct net_device *);
504 unsigned int (*phy_reset_pending)(void __iomem *); 658 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
505 unsigned int (*link_ok)(void __iomem *); 659 unsigned int (*link_ok)(void __iomem *);
506 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); 660 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
507 int pcie_cap; 661 int pcie_cap;
@@ -511,18 +665,24 @@ struct rtl8169_private {
511 struct mii_if_info mii; 665 struct mii_if_info mii;
512 struct rtl8169_counters counters; 666 struct rtl8169_counters counters;
513 u32 saved_wolopts; 667 u32 saved_wolopts;
668
669 const struct firmware *fw;
670#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
514}; 671};
515 672
516MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 673MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
517MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 674MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
518module_param(rx_copybreak, int, 0);
519MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
520module_param(use_dac, int, 0); 675module_param(use_dac, int, 0);
521MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); 676MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
522module_param_named(debug, debug.msg_enable, int, 0); 677module_param_named(debug, debug.msg_enable, int, 0);
523MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 678MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
524MODULE_LICENSE("GPL"); 679MODULE_LICENSE("GPL");
525MODULE_VERSION(RTL8169_VERSION); 680MODULE_VERSION(RTL8169_VERSION);
681MODULE_FIRMWARE(FIRMWARE_8168D_1);
682MODULE_FIRMWARE(FIRMWARE_8168D_2);
683MODULE_FIRMWARE(FIRMWARE_8168E_1);
684MODULE_FIRMWARE(FIRMWARE_8168E_2);
685MODULE_FIRMWARE(FIRMWARE_8105E_1);
526 686
527static int rtl8169_open(struct net_device *dev); 687static int rtl8169_open(struct net_device *dev);
528static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 688static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
@@ -544,7 +704,100 @@ static int rtl8169_poll(struct napi_struct *napi, int budget);
544static const unsigned int rtl8169_rx_config = 704static const unsigned int rtl8169_rx_config =
545 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 705 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
546 706
547static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) 707static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
708{
709 void __iomem *ioaddr = tp->mmio_addr;
710 int i;
711
712 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
713 for (i = 0; i < 20; i++) {
714 udelay(100);
715 if (RTL_R32(OCPAR) & OCPAR_FLAG)
716 break;
717 }
718 return RTL_R32(OCPDR);
719}
720
721static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
722{
723 void __iomem *ioaddr = tp->mmio_addr;
724 int i;
725
726 RTL_W32(OCPDR, data);
727 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
728 for (i = 0; i < 20; i++) {
729 udelay(100);
730 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
731 break;
732 }
733}
734
735static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
736{
737 void __iomem *ioaddr = tp->mmio_addr;
738 int i;
739
740 RTL_W8(ERIDR, cmd);
741 RTL_W32(ERIAR, 0x800010e8);
742 msleep(2);
743 for (i = 0; i < 5; i++) {
744 udelay(100);
745 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
746 break;
747 }
748
749 ocp_write(tp, 0x1, 0x30, 0x00000001);
750}
751
752#define OOB_CMD_RESET 0x00
753#define OOB_CMD_DRIVER_START 0x05
754#define OOB_CMD_DRIVER_STOP 0x06
755
756static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
757{
758 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
759}
760
761static void rtl8168_driver_start(struct rtl8169_private *tp)
762{
763 u16 reg;
764 int i;
765
766 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
767
768 reg = rtl8168_get_ocp_reg(tp);
769
770 for (i = 0; i < 10; i++) {
771 msleep(10);
772 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
773 break;
774 }
775}
776
777static void rtl8168_driver_stop(struct rtl8169_private *tp)
778{
779 u16 reg;
780 int i;
781
782 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
783
784 reg = rtl8168_get_ocp_reg(tp);
785
786 for (i = 0; i < 10; i++) {
787 msleep(10);
788 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
789 break;
790 }
791}
792
793static int r8168dp_check_dash(struct rtl8169_private *tp)
794{
795 u16 reg = rtl8168_get_ocp_reg(tp);
796
797 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
798}
799
800static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
548{ 801{
549 int i; 802 int i;
550 803
@@ -566,7 +819,7 @@ static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
566 udelay(20); 819 udelay(20);
567} 820}
568 821
569static int mdio_read(void __iomem *ioaddr, int reg_addr) 822static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
570{ 823{
571 int i, value = -1; 824 int i, value = -1;
572 825
@@ -592,34 +845,117 @@ static int mdio_read(void __iomem *ioaddr, int reg_addr)
592 return value; 845 return value;
593} 846}
594 847
595static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) 848static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
849{
850 int i;
851
852 RTL_W32(OCPDR, data |
853 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
854 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
855 RTL_W32(EPHY_RXER_NUM, 0);
856
857 for (i = 0; i < 100; i++) {
858 mdelay(1);
859 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
860 break;
861 }
862}
863
864static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
596{ 865{
597 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); 866 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
867 (value & OCPDR_DATA_MASK));
598} 868}
599 869
600static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m) 870static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
871{
872 int i;
873
874 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
875
876 mdelay(1);
877 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
878 RTL_W32(EPHY_RXER_NUM, 0);
879
880 for (i = 0; i < 100; i++) {
881 mdelay(1);
882 if (RTL_R32(OCPAR) & OCPAR_FLAG)
883 break;
884 }
885
886 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
887}
888
889#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
890
891static void r8168dp_2_mdio_start(void __iomem *ioaddr)
892{
893 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
894}
895
896static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
897{
898 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
899}
900
901static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
902{
903 r8168dp_2_mdio_start(ioaddr);
904
905 r8169_mdio_write(ioaddr, reg_addr, value);
906
907 r8168dp_2_mdio_stop(ioaddr);
908}
909
910static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
911{
912 int value;
913
914 r8168dp_2_mdio_start(ioaddr);
915
916 value = r8169_mdio_read(ioaddr, reg_addr);
917
918 r8168dp_2_mdio_stop(ioaddr);
919
920 return value;
921}
922
923static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
924{
925 tp->mdio_ops.write(tp->mmio_addr, location, val);
926}
927
928static int rtl_readphy(struct rtl8169_private *tp, int location)
929{
930 return tp->mdio_ops.read(tp->mmio_addr, location);
931}
932
933static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
934{
935 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
936}
937
938static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
601{ 939{
602 int val; 940 int val;
603 941
604 val = mdio_read(ioaddr, reg_addr); 942 val = rtl_readphy(tp, reg_addr);
605 mdio_write(ioaddr, reg_addr, (val | p) & ~m); 943 rtl_writephy(tp, reg_addr, (val | p) & ~m);
606} 944}
607 945
608static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, 946static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
609 int val) 947 int val)
610{ 948{
611 struct rtl8169_private *tp = netdev_priv(dev); 949 struct rtl8169_private *tp = netdev_priv(dev);
612 void __iomem *ioaddr = tp->mmio_addr;
613 950
614 mdio_write(ioaddr, location, val); 951 rtl_writephy(tp, location, val);
615} 952}
616 953
617static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) 954static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
618{ 955{
619 struct rtl8169_private *tp = netdev_priv(dev); 956 struct rtl8169_private *tp = netdev_priv(dev);
620 void __iomem *ioaddr = tp->mmio_addr;
621 957
622 return mdio_read(ioaddr, location); 958 return rtl_readphy(tp, location);
623} 959}
624 960
625static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) 961static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
@@ -720,14 +1056,16 @@ static void rtl8169_asic_down(void __iomem *ioaddr)
720 RTL_R16(CPlusCmd); 1056 RTL_R16(CPlusCmd);
721} 1057}
722 1058
723static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) 1059static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
724{ 1060{
1061 void __iomem *ioaddr = tp->mmio_addr;
1062
725 return RTL_R32(TBICSR) & TBIReset; 1063 return RTL_R32(TBICSR) & TBIReset;
726} 1064}
727 1065
728static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) 1066static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
729{ 1067{
730 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; 1068 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
731} 1069}
732 1070
733static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) 1071static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
@@ -740,39 +1078,51 @@ static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
740 return RTL_R8(PHYstatus) & LinkStatus; 1078 return RTL_R8(PHYstatus) & LinkStatus;
741} 1079}
742 1080
743static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) 1081static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
744{ 1082{
1083 void __iomem *ioaddr = tp->mmio_addr;
1084
745 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); 1085 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
746} 1086}
747 1087
748static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) 1088static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
749{ 1089{
750 unsigned int val; 1090 unsigned int val;
751 1091
752 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; 1092 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
753 mdio_write(ioaddr, MII_BMCR, val & 0xffff); 1093 rtl_writephy(tp, MII_BMCR, val & 0xffff);
754} 1094}
755 1095
756static void rtl8169_check_link_status(struct net_device *dev, 1096static void __rtl8169_check_link_status(struct net_device *dev,
757 struct rtl8169_private *tp, 1097 struct rtl8169_private *tp,
758 void __iomem *ioaddr) 1098 void __iomem *ioaddr, bool pm)
759{ 1099{
760 unsigned long flags; 1100 unsigned long flags;
761 1101
762 spin_lock_irqsave(&tp->lock, flags); 1102 spin_lock_irqsave(&tp->lock, flags);
763 if (tp->link_ok(ioaddr)) { 1103 if (tp->link_ok(ioaddr)) {
764 /* This is to cancel a scheduled suspend if there's one. */ 1104 /* This is to cancel a scheduled suspend if there's one. */
765 pm_request_resume(&tp->pci_dev->dev); 1105 if (pm)
1106 pm_request_resume(&tp->pci_dev->dev);
766 netif_carrier_on(dev); 1107 netif_carrier_on(dev);
767 netif_info(tp, ifup, dev, "link up\n"); 1108 if (net_ratelimit())
1109 netif_info(tp, ifup, dev, "link up\n");
768 } else { 1110 } else {
769 netif_carrier_off(dev); 1111 netif_carrier_off(dev);
770 netif_info(tp, ifdown, dev, "link down\n"); 1112 netif_info(tp, ifdown, dev, "link down\n");
771 pm_schedule_suspend(&tp->pci_dev->dev, 100); 1113 if (pm)
1114 pm_schedule_suspend(&tp->pci_dev->dev, 100);
772 } 1115 }
773 spin_unlock_irqrestore(&tp->lock, flags); 1116 spin_unlock_irqrestore(&tp->lock, flags);
774} 1117}
775 1118
1119static void rtl8169_check_link_status(struct net_device *dev,
1120 struct rtl8169_private *tp,
1121 void __iomem *ioaddr)
1122{
1123 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1124}
1125
776#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1126#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
777 1127
778static u32 __rtl8169_get_wol(struct rtl8169_private *tp) 1128static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
@@ -855,13 +1205,18 @@ static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
855 else 1205 else
856 tp->features &= ~RTL_FEATURE_WOL; 1206 tp->features &= ~RTL_FEATURE_WOL;
857 __rtl8169_set_wol(tp, wol->wolopts); 1207 __rtl8169_set_wol(tp, wol->wolopts);
858 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
859
860 spin_unlock_irq(&tp->lock); 1208 spin_unlock_irq(&tp->lock);
861 1209
1210 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1211
862 return 0; 1212 return 0;
863} 1213}
864 1214
1215static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1216{
1217 return rtl_chip_infos[tp->mac_version].fw_name;
1218}
1219
865static void rtl8169_get_drvinfo(struct net_device *dev, 1220static void rtl8169_get_drvinfo(struct net_device *dev,
866 struct ethtool_drvinfo *info) 1221 struct ethtool_drvinfo *info)
867{ 1222{
@@ -870,6 +1225,8 @@ static void rtl8169_get_drvinfo(struct net_device *dev,
870 strcpy(info->driver, MODULENAME); 1225 strcpy(info->driver, MODULENAME);
871 strcpy(info->version, RTL8169_VERSION); 1226 strcpy(info->version, RTL8169_VERSION);
872 strcpy(info->bus_info, pci_name(tp->pci_dev)); 1227 strcpy(info->bus_info, pci_name(tp->pci_dev));
1228 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1229 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
873} 1230}
874 1231
875static int rtl8169_get_regs_len(struct net_device *dev) 1232static int rtl8169_get_regs_len(struct net_device *dev)
@@ -878,7 +1235,7 @@ static int rtl8169_get_regs_len(struct net_device *dev)
878} 1235}
879 1236
880static int rtl8169_set_speed_tbi(struct net_device *dev, 1237static int rtl8169_set_speed_tbi(struct net_device *dev,
881 u8 autoneg, u16 speed, u8 duplex) 1238 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
882{ 1239{
883 struct rtl8169_private *tp = netdev_priv(dev); 1240 struct rtl8169_private *tp = netdev_priv(dev);
884 void __iomem *ioaddr = tp->mmio_addr; 1241 void __iomem *ioaddr = tp->mmio_addr;
@@ -901,54 +1258,52 @@ static int rtl8169_set_speed_tbi(struct net_device *dev,
901} 1258}
902 1259
903static int rtl8169_set_speed_xmii(struct net_device *dev, 1260static int rtl8169_set_speed_xmii(struct net_device *dev,
904 u8 autoneg, u16 speed, u8 duplex) 1261 u8 autoneg, u16 speed, u8 duplex, u32 adv)
905{ 1262{
906 struct rtl8169_private *tp = netdev_priv(dev); 1263 struct rtl8169_private *tp = netdev_priv(dev);
907 void __iomem *ioaddr = tp->mmio_addr;
908 int giga_ctrl, bmcr; 1264 int giga_ctrl, bmcr;
1265 int rc = -EINVAL;
1266
1267 rtl_writephy(tp, 0x1f, 0x0000);
909 1268
910 if (autoneg == AUTONEG_ENABLE) { 1269 if (autoneg == AUTONEG_ENABLE) {
911 int auto_nego; 1270 int auto_nego;
912 1271
913 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); 1272 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
914 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | 1273 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
915 ADVERTISE_100HALF | ADVERTISE_100FULL); 1274 ADVERTISE_100HALF | ADVERTISE_100FULL);
1275
1276 if (adv & ADVERTISED_10baseT_Half)
1277 auto_nego |= ADVERTISE_10HALF;
1278 if (adv & ADVERTISED_10baseT_Full)
1279 auto_nego |= ADVERTISE_10FULL;
1280 if (adv & ADVERTISED_100baseT_Half)
1281 auto_nego |= ADVERTISE_100HALF;
1282 if (adv & ADVERTISED_100baseT_Full)
1283 auto_nego |= ADVERTISE_100FULL;
1284
916 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1285 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
917 1286
918 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); 1287 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
919 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 1288 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
920 1289
921 /* The 8100e/8101e/8102e do Fast Ethernet only. */ 1290 /* The 8100e/8101e/8102e do Fast Ethernet only. */
922 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && 1291 if (tp->mii.supports_gmii) {
923 (tp->mac_version != RTL_GIGA_MAC_VER_08) && 1292 if (adv & ADVERTISED_1000baseT_Half)
924 (tp->mac_version != RTL_GIGA_MAC_VER_09) && 1293 giga_ctrl |= ADVERTISE_1000HALF;
925 (tp->mac_version != RTL_GIGA_MAC_VER_10) && 1294 if (adv & ADVERTISED_1000baseT_Full)
926 (tp->mac_version != RTL_GIGA_MAC_VER_13) && 1295 giga_ctrl |= ADVERTISE_1000FULL;
927 (tp->mac_version != RTL_GIGA_MAC_VER_14) && 1296 } else if (adv & (ADVERTISED_1000baseT_Half |
928 (tp->mac_version != RTL_GIGA_MAC_VER_15) && 1297 ADVERTISED_1000baseT_Full)) {
929 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
930 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
931 } else {
932 netif_info(tp, link, dev, 1298 netif_info(tp, link, dev,
933 "PHY does not support 1000Mbps\n"); 1299 "PHY does not support 1000Mbps\n");
1300 goto out;
934 } 1301 }
935 1302
936 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 1303 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
937 1304
938 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || 1305 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
939 (tp->mac_version == RTL_GIGA_MAC_VER_12) || 1306 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
940 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
941 /*
942 * Wake up the PHY.
943 * Vendor specific (0x1f) and reserved (0x0e) MII
944 * registers.
945 */
946 mdio_write(ioaddr, 0x1f, 0x0000);
947 mdio_write(ioaddr, 0x0e, 0x0000);
948 }
949
950 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
951 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
952 } else { 1307 } else {
953 giga_ctrl = 0; 1308 giga_ctrl = 0;
954 1309
@@ -957,43 +1312,45 @@ static int rtl8169_set_speed_xmii(struct net_device *dev,
957 else if (speed == SPEED_100) 1312 else if (speed == SPEED_100)
958 bmcr = BMCR_SPEED100; 1313 bmcr = BMCR_SPEED100;
959 else 1314 else
960 return -EINVAL; 1315 goto out;
961 1316
962 if (duplex == DUPLEX_FULL) 1317 if (duplex == DUPLEX_FULL)
963 bmcr |= BMCR_FULLDPLX; 1318 bmcr |= BMCR_FULLDPLX;
964
965 mdio_write(ioaddr, 0x1f, 0x0000);
966 } 1319 }
967 1320
968 tp->phy_1000_ctrl_reg = giga_ctrl; 1321 rtl_writephy(tp, MII_BMCR, bmcr);
969
970 mdio_write(ioaddr, MII_BMCR, bmcr);
971 1322
972 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || 1323 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
973 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { 1324 tp->mac_version == RTL_GIGA_MAC_VER_03) {
974 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { 1325 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
975 mdio_write(ioaddr, 0x17, 0x2138); 1326 rtl_writephy(tp, 0x17, 0x2138);
976 mdio_write(ioaddr, 0x0e, 0x0260); 1327 rtl_writephy(tp, 0x0e, 0x0260);
977 } else { 1328 } else {
978 mdio_write(ioaddr, 0x17, 0x2108); 1329 rtl_writephy(tp, 0x17, 0x2108);
979 mdio_write(ioaddr, 0x0e, 0x0000); 1330 rtl_writephy(tp, 0x0e, 0x0000);
980 } 1331 }
981 } 1332 }
982 1333
983 return 0; 1334 rc = 0;
1335out:
1336 return rc;
984} 1337}
985 1338
986static int rtl8169_set_speed(struct net_device *dev, 1339static int rtl8169_set_speed(struct net_device *dev,
987 u8 autoneg, u16 speed, u8 duplex) 1340 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
988{ 1341{
989 struct rtl8169_private *tp = netdev_priv(dev); 1342 struct rtl8169_private *tp = netdev_priv(dev);
990 int ret; 1343 int ret;
991 1344
992 ret = tp->set_speed(dev, autoneg, speed, duplex); 1345 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1346 if (ret < 0)
1347 goto out;
993 1348
994 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) 1349 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1350 (advertising & ADVERTISED_1000baseT_Full)) {
995 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); 1351 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
996 1352 }
1353out:
997 return ret; 1354 return ret;
998} 1355}
999 1356
@@ -1003,21 +1360,25 @@ static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1003 unsigned long flags; 1360 unsigned long flags;
1004 int ret; 1361 int ret;
1005 1362
1363 del_timer_sync(&tp->timer);
1364
1006 spin_lock_irqsave(&tp->lock, flags); 1365 spin_lock_irqsave(&tp->lock, flags);
1007 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); 1366 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1367 cmd->duplex, cmd->advertising);
1008 spin_unlock_irqrestore(&tp->lock, flags); 1368 spin_unlock_irqrestore(&tp->lock, flags);
1009 1369
1010 return ret; 1370 return ret;
1011} 1371}
1012 1372
1013static u32 rtl8169_get_rx_csum(struct net_device *dev) 1373static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1014{ 1374{
1015 struct rtl8169_private *tp = netdev_priv(dev); 1375 if (dev->mtu > TD_MSS_MAX)
1376 features &= ~NETIF_F_ALL_TSO;
1016 1377
1017 return tp->cp_cmd & RxChkSum; 1378 return features;
1018} 1379}
1019 1380
1020static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) 1381static int rtl8169_set_features(struct net_device *dev, u32 features)
1021{ 1382{
1022 struct rtl8169_private *tp = netdev_priv(dev); 1383 struct rtl8169_private *tp = netdev_priv(dev);
1023 void __iomem *ioaddr = tp->mmio_addr; 1384 void __iomem *ioaddr = tp->mmio_addr;
@@ -1025,11 +1386,16 @@ static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1025 1386
1026 spin_lock_irqsave(&tp->lock, flags); 1387 spin_lock_irqsave(&tp->lock, flags);
1027 1388
1028 if (data) 1389 if (features & NETIF_F_RXCSUM)
1029 tp->cp_cmd |= RxChkSum; 1390 tp->cp_cmd |= RxChkSum;
1030 else 1391 else
1031 tp->cp_cmd &= ~RxChkSum; 1392 tp->cp_cmd &= ~RxChkSum;
1032 1393
1394 if (dev->features & NETIF_F_HW_VLAN_RX)
1395 tp->cp_cmd |= RxVlan;
1396 else
1397 tp->cp_cmd &= ~RxVlan;
1398
1033 RTL_W16(CPlusCmd, tp->cp_cmd); 1399 RTL_W16(CPlusCmd, tp->cp_cmd);
1034 RTL_R16(CPlusCmd); 1400 RTL_R16(CPlusCmd);
1035 1401
@@ -1038,68 +1404,23 @@ static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1038 return 0; 1404 return 0;
1039} 1405}
1040 1406
1041#ifdef CONFIG_R8169_VLAN
1042
1043static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, 1407static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1044 struct sk_buff *skb) 1408 struct sk_buff *skb)
1045{ 1409{
1046 return (tp->vlgrp && vlan_tx_tag_present(skb)) ? 1410 return (vlan_tx_tag_present(skb)) ?
1047 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; 1411 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1048} 1412}
1049 1413
1050static void rtl8169_vlan_rx_register(struct net_device *dev, 1414static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1051 struct vlan_group *grp)
1052{
1053 struct rtl8169_private *tp = netdev_priv(dev);
1054 void __iomem *ioaddr = tp->mmio_addr;
1055 unsigned long flags;
1056
1057 spin_lock_irqsave(&tp->lock, flags);
1058 tp->vlgrp = grp;
1059 /*
1060 * Do not disable RxVlan on 8110SCd.
1061 */
1062 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1063 tp->cp_cmd |= RxVlan;
1064 else
1065 tp->cp_cmd &= ~RxVlan;
1066 RTL_W16(CPlusCmd, tp->cp_cmd);
1067 RTL_R16(CPlusCmd);
1068 spin_unlock_irqrestore(&tp->lock, flags);
1069}
1070
1071static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1072 struct sk_buff *skb, int polling)
1073{ 1415{
1074 u32 opts2 = le32_to_cpu(desc->opts2); 1416 u32 opts2 = le32_to_cpu(desc->opts2);
1075 struct vlan_group *vlgrp = tp->vlgrp;
1076 int ret;
1077 1417
1078 if (vlgrp && (opts2 & RxVlanTag)) { 1418 if (opts2 & RxVlanTag)
1079 __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling); 1419 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1080 ret = 0;
1081 } else
1082 ret = -1;
1083 desc->opts2 = 0;
1084 return ret;
1085}
1086 1420
1087#else /* !CONFIG_R8169_VLAN */ 1421 desc->opts2 = 0;
1088
1089static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1090 struct sk_buff *skb)
1091{
1092 return 0;
1093}
1094
1095static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1096 struct sk_buff *skb, int polling)
1097{
1098 return -1;
1099} 1422}
1100 1423
1101#endif
1102
1103static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) 1424static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1104{ 1425{
1105 struct rtl8169_private *tp = netdev_priv(dev); 1426 struct rtl8169_private *tp = netdev_priv(dev);
@@ -1115,7 +1436,7 @@ static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1115 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; 1436 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1116 cmd->autoneg = !!(status & TBINwEnable); 1437 cmd->autoneg = !!(status & TBINwEnable);
1117 1438
1118 cmd->speed = SPEED_1000; 1439 ethtool_cmd_speed_set(cmd, SPEED_1000);
1119 cmd->duplex = DUPLEX_FULL; /* Always set */ 1440 cmd->duplex = DUPLEX_FULL; /* Always set */
1120 1441
1121 return 0; 1442 return 0;
@@ -1200,6 +1521,7 @@ static void rtl8169_update_counters(struct net_device *dev)
1200{ 1521{
1201 struct rtl8169_private *tp = netdev_priv(dev); 1522 struct rtl8169_private *tp = netdev_priv(dev);
1202 void __iomem *ioaddr = tp->mmio_addr; 1523 void __iomem *ioaddr = tp->mmio_addr;
1524 struct device *d = &tp->pci_dev->dev;
1203 struct rtl8169_counters *counters; 1525 struct rtl8169_counters *counters;
1204 dma_addr_t paddr; 1526 dma_addr_t paddr;
1205 u32 cmd; 1527 u32 cmd;
@@ -1212,8 +1534,7 @@ static void rtl8169_update_counters(struct net_device *dev)
1212 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) 1534 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1213 return; 1535 return;
1214 1536
1215 counters = dma_alloc_coherent(&tp->pci_dev->dev, sizeof(*counters), 1537 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1216 &paddr, GFP_KERNEL);
1217 if (!counters) 1538 if (!counters)
1218 return; 1539 return;
1219 1540
@@ -1224,7 +1545,6 @@ static void rtl8169_update_counters(struct net_device *dev)
1224 1545
1225 while (wait--) { 1546 while (wait--) {
1226 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { 1547 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1227 /* copy updated counters */
1228 memcpy(&tp->counters, counters, sizeof(*counters)); 1548 memcpy(&tp->counters, counters, sizeof(*counters));
1229 break; 1549 break;
1230 } 1550 }
@@ -1234,8 +1554,7 @@ static void rtl8169_update_counters(struct net_device *dev)
1234 RTL_W32(CounterAddrLow, 0); 1554 RTL_W32(CounterAddrLow, 0);
1235 RTL_W32(CounterAddrHigh, 0); 1555 RTL_W32(CounterAddrHigh, 0);
1236 1556
1237 dma_free_coherent(&tp->pci_dev->dev, sizeof(*counters), counters, 1557 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1238 paddr);
1239} 1558}
1240 1559
1241static void rtl8169_get_ethtool_stats(struct net_device *dev, 1560static void rtl8169_get_ethtool_stats(struct net_device *dev,
@@ -1279,11 +1598,6 @@ static const struct ethtool_ops rtl8169_ethtool_ops = {
1279 .set_settings = rtl8169_set_settings, 1598 .set_settings = rtl8169_set_settings,
1280 .get_msglevel = rtl8169_get_msglevel, 1599 .get_msglevel = rtl8169_get_msglevel,
1281 .set_msglevel = rtl8169_set_msglevel, 1600 .set_msglevel = rtl8169_set_msglevel,
1282 .get_rx_csum = rtl8169_get_rx_csum,
1283 .set_rx_csum = rtl8169_set_rx_csum,
1284 .set_tx_csum = ethtool_op_set_tx_csum,
1285 .set_sg = ethtool_op_set_sg,
1286 .set_tso = ethtool_op_set_tso,
1287 .get_regs = rtl8169_get_regs, 1601 .get_regs = rtl8169_get_regs,
1288 .get_wol = rtl8169_get_wol, 1602 .get_wol = rtl8169_get_wol,
1289 .set_wol = rtl8169_set_wol, 1603 .set_wol = rtl8169_set_wol,
@@ -1293,8 +1607,9 @@ static const struct ethtool_ops rtl8169_ethtool_ops = {
1293}; 1607};
1294 1608
1295static void rtl8169_get_mac_version(struct rtl8169_private *tp, 1609static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1296 void __iomem *ioaddr) 1610 struct net_device *dev, u8 default_version)
1297{ 1611{
1612 void __iomem *ioaddr = tp->mmio_addr;
1298 /* 1613 /*
1299 * The driver currently handles the 8168Bf and the 8168Be identically 1614 * The driver currently handles the 8168Bf and the 8168Be identically
1300 * but they can be identified more specifically through the test below 1615 * but they can be identified more specifically through the test below
@@ -1306,17 +1621,26 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1306 * 1621 *
1307 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1622 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1308 */ 1623 */
1309 static const struct { 1624 static const struct rtl_mac_info {
1310 u32 mask; 1625 u32 mask;
1311 u32 val; 1626 u32 val;
1312 int mac_version; 1627 int mac_version;
1313 } mac_info[] = { 1628 } mac_info[] = {
1629 /* 8168E family. */
1630 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1631 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1632 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1633
1314 /* 8168D family. */ 1634 /* 8168D family. */
1315 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, 1635 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1316 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, 1636 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1317 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1318 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, 1637 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1319 1638
1639 /* 8168DP family. */
1640 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1641 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1642 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1643
1320 /* 8168C family. */ 1644 /* 8168C family. */
1321 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, 1645 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1322 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, 1646 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
@@ -1335,6 +1659,10 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1335 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, 1659 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1336 1660
1337 /* 8101 family. */ 1661 /* 8101 family. */
1662 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1663 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1664 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1665 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1338 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, 1666 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1339 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, 1667 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1340 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, 1668 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
@@ -1361,13 +1689,20 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1361 1689
1362 /* Catch-all */ 1690 /* Catch-all */
1363 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } 1691 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1364 }, *p = mac_info; 1692 };
1693 const struct rtl_mac_info *p = mac_info;
1365 u32 reg; 1694 u32 reg;
1366 1695
1367 reg = RTL_R32(TxConfig); 1696 reg = RTL_R32(TxConfig);
1368 while ((reg & p->mask) != p->val) 1697 while ((reg & p->mask) != p->val)
1369 p++; 1698 p++;
1370 tp->mac_version = p->mac_version; 1699 tp->mac_version = p->mac_version;
1700
1701 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1702 netif_notice(tp, probe, dev,
1703 "unknown MAC, using family default\n");
1704 tp->mac_version = default_version;
1705 }
1371} 1706}
1372 1707
1373static void rtl8169_print_mac_version(struct rtl8169_private *tp) 1708static void rtl8169_print_mac_version(struct rtl8169_private *tp)
@@ -1380,15 +1715,193 @@ struct phy_reg {
1380 u16 val; 1715 u16 val;
1381}; 1716};
1382 1717
1383static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len) 1718static void rtl_writephy_batch(struct rtl8169_private *tp,
1719 const struct phy_reg *regs, int len)
1384{ 1720{
1385 while (len-- > 0) { 1721 while (len-- > 0) {
1386 mdio_write(ioaddr, regs->reg, regs->val); 1722 rtl_writephy(tp, regs->reg, regs->val);
1387 regs++; 1723 regs++;
1388 } 1724 }
1389} 1725}
1390 1726
1391static void rtl8169s_hw_phy_config(void __iomem *ioaddr) 1727#define PHY_READ 0x00000000
1728#define PHY_DATA_OR 0x10000000
1729#define PHY_DATA_AND 0x20000000
1730#define PHY_BJMPN 0x30000000
1731#define PHY_READ_EFUSE 0x40000000
1732#define PHY_READ_MAC_BYTE 0x50000000
1733#define PHY_WRITE_MAC_BYTE 0x60000000
1734#define PHY_CLEAR_READCOUNT 0x70000000
1735#define PHY_WRITE 0x80000000
1736#define PHY_READCOUNT_EQ_SKIP 0x90000000
1737#define PHY_COMP_EQ_SKIPN 0xa0000000
1738#define PHY_COMP_NEQ_SKIPN 0xb0000000
1739#define PHY_WRITE_PREVIOUS 0xc0000000
1740#define PHY_SKIPN 0xd0000000
1741#define PHY_DELAY_MS 0xe0000000
1742#define PHY_WRITE_ERI_WORD 0xf0000000
1743
1744static void
1745rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1746{
1747 __le32 *phytable = (__le32 *)fw->data;
1748 struct net_device *dev = tp->dev;
1749 size_t index, fw_size = fw->size / sizeof(*phytable);
1750 u32 predata, count;
1751
1752 if (fw->size % sizeof(*phytable)) {
1753 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1754 return;
1755 }
1756
1757 for (index = 0; index < fw_size; index++) {
1758 u32 action = le32_to_cpu(phytable[index]);
1759 u32 regno = (action & 0x0fff0000) >> 16;
1760
1761 switch(action & 0xf0000000) {
1762 case PHY_READ:
1763 case PHY_DATA_OR:
1764 case PHY_DATA_AND:
1765 case PHY_READ_EFUSE:
1766 case PHY_CLEAR_READCOUNT:
1767 case PHY_WRITE:
1768 case PHY_WRITE_PREVIOUS:
1769 case PHY_DELAY_MS:
1770 break;
1771
1772 case PHY_BJMPN:
1773 if (regno > index) {
1774 netif_err(tp, probe, tp->dev,
1775 "Out of range of firmware\n");
1776 return;
1777 }
1778 break;
1779 case PHY_READCOUNT_EQ_SKIP:
1780 if (index + 2 >= fw_size) {
1781 netif_err(tp, probe, tp->dev,
1782 "Out of range of firmware\n");
1783 return;
1784 }
1785 break;
1786 case PHY_COMP_EQ_SKIPN:
1787 case PHY_COMP_NEQ_SKIPN:
1788 case PHY_SKIPN:
1789 if (index + 1 + regno >= fw_size) {
1790 netif_err(tp, probe, tp->dev,
1791 "Out of range of firmware\n");
1792 return;
1793 }
1794 break;
1795
1796 case PHY_READ_MAC_BYTE:
1797 case PHY_WRITE_MAC_BYTE:
1798 case PHY_WRITE_ERI_WORD:
1799 default:
1800 netif_err(tp, probe, tp->dev,
1801 "Invalid action 0x%08x\n", action);
1802 return;
1803 }
1804 }
1805
1806 predata = 0;
1807 count = 0;
1808
1809 for (index = 0; index < fw_size; ) {
1810 u32 action = le32_to_cpu(phytable[index]);
1811 u32 data = action & 0x0000ffff;
1812 u32 regno = (action & 0x0fff0000) >> 16;
1813
1814 if (!action)
1815 break;
1816
1817 switch(action & 0xf0000000) {
1818 case PHY_READ:
1819 predata = rtl_readphy(tp, regno);
1820 count++;
1821 index++;
1822 break;
1823 case PHY_DATA_OR:
1824 predata |= data;
1825 index++;
1826 break;
1827 case PHY_DATA_AND:
1828 predata &= data;
1829 index++;
1830 break;
1831 case PHY_BJMPN:
1832 index -= regno;
1833 break;
1834 case PHY_READ_EFUSE:
1835 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1836 index++;
1837 break;
1838 case PHY_CLEAR_READCOUNT:
1839 count = 0;
1840 index++;
1841 break;
1842 case PHY_WRITE:
1843 rtl_writephy(tp, regno, data);
1844 index++;
1845 break;
1846 case PHY_READCOUNT_EQ_SKIP:
1847 index += (count == data) ? 2 : 1;
1848 break;
1849 case PHY_COMP_EQ_SKIPN:
1850 if (predata == data)
1851 index += regno;
1852 index++;
1853 break;
1854 case PHY_COMP_NEQ_SKIPN:
1855 if (predata != data)
1856 index += regno;
1857 index++;
1858 break;
1859 case PHY_WRITE_PREVIOUS:
1860 rtl_writephy(tp, regno, predata);
1861 index++;
1862 break;
1863 case PHY_SKIPN:
1864 index += regno + 1;
1865 break;
1866 case PHY_DELAY_MS:
1867 mdelay(data);
1868 index++;
1869 break;
1870
1871 case PHY_READ_MAC_BYTE:
1872 case PHY_WRITE_MAC_BYTE:
1873 case PHY_WRITE_ERI_WORD:
1874 default:
1875 BUG();
1876 }
1877 }
1878}
1879
1880static void rtl_release_firmware(struct rtl8169_private *tp)
1881{
1882 if (!IS_ERR_OR_NULL(tp->fw))
1883 release_firmware(tp->fw);
1884 tp->fw = RTL_FIRMWARE_UNKNOWN;
1885}
1886
1887static void rtl_apply_firmware(struct rtl8169_private *tp)
1888{
1889 const struct firmware *fw = tp->fw;
1890
1891 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1892 if (!IS_ERR_OR_NULL(fw))
1893 rtl_phy_write_fw(tp, fw);
1894}
1895
1896static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1897{
1898 if (rtl_readphy(tp, reg) != val)
1899 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1900 else
1901 rtl_apply_firmware(tp);
1902}
1903
1904static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1392{ 1905{
1393 static const struct phy_reg phy_reg_init[] = { 1906 static const struct phy_reg phy_reg_init[] = {
1394 { 0x1f, 0x0001 }, 1907 { 0x1f, 0x0001 },
@@ -1452,10 +1965,10 @@ static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1452 { 0x00, 0x9200 } 1965 { 0x00, 0x9200 }
1453 }; 1966 };
1454 1967
1455 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 1968 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1456} 1969}
1457 1970
1458static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) 1971static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1459{ 1972{
1460 static const struct phy_reg phy_reg_init[] = { 1973 static const struct phy_reg phy_reg_init[] = {
1461 { 0x1f, 0x0002 }, 1974 { 0x1f, 0x0002 },
@@ -1463,11 +1976,10 @@ static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1463 { 0x1f, 0x0000 } 1976 { 0x1f, 0x0000 }
1464 }; 1977 };
1465 1978
1466 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 1979 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1467} 1980}
1468 1981
1469static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, 1982static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1470 void __iomem *ioaddr)
1471{ 1983{
1472 struct pci_dev *pdev = tp->pci_dev; 1984 struct pci_dev *pdev = tp->pci_dev;
1473 u16 vendor_id, device_id; 1985 u16 vendor_id, device_id;
@@ -1478,13 +1990,12 @@ static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1478 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) 1990 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1479 return; 1991 return;
1480 1992
1481 mdio_write(ioaddr, 0x1f, 0x0001); 1993 rtl_writephy(tp, 0x1f, 0x0001);
1482 mdio_write(ioaddr, 0x10, 0xf01b); 1994 rtl_writephy(tp, 0x10, 0xf01b);
1483 mdio_write(ioaddr, 0x1f, 0x0000); 1995 rtl_writephy(tp, 0x1f, 0x0000);
1484} 1996}
1485 1997
1486static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 1998static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1487 void __iomem *ioaddr)
1488{ 1999{
1489 static const struct phy_reg phy_reg_init[] = { 2000 static const struct phy_reg phy_reg_init[] = {
1490 { 0x1f, 0x0001 }, 2001 { 0x1f, 0x0001 },
@@ -1526,12 +2037,12 @@ static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1526 { 0x1f, 0x0000 } 2037 { 0x1f, 0x0000 }
1527 }; 2038 };
1528 2039
1529 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1530 2041
1531 rtl8169scd_hw_phy_config_quirk(tp, ioaddr); 2042 rtl8169scd_hw_phy_config_quirk(tp);
1532} 2043}
1533 2044
1534static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) 2045static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1535{ 2046{
1536 static const struct phy_reg phy_reg_init[] = { 2047 static const struct phy_reg phy_reg_init[] = {
1537 { 0x1f, 0x0001 }, 2048 { 0x1f, 0x0001 },
@@ -1581,23 +2092,23 @@ static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1581 { 0x1f, 0x0000 } 2092 { 0x1f, 0x0000 }
1582 }; 2093 };
1583 2094
1584 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2095 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1585} 2096}
1586 2097
1587static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) 2098static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1588{ 2099{
1589 static const struct phy_reg phy_reg_init[] = { 2100 static const struct phy_reg phy_reg_init[] = {
1590 { 0x10, 0xf41b }, 2101 { 0x10, 0xf41b },
1591 { 0x1f, 0x0000 } 2102 { 0x1f, 0x0000 }
1592 }; 2103 };
1593 2104
1594 mdio_write(ioaddr, 0x1f, 0x0001); 2105 rtl_writephy(tp, 0x1f, 0x0001);
1595 mdio_patch(ioaddr, 0x16, 1 << 0); 2106 rtl_patchphy(tp, 0x16, 1 << 0);
1596 2107
1597 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1598} 2109}
1599 2110
1600static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) 2111static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
1601{ 2112{
1602 static const struct phy_reg phy_reg_init[] = { 2113 static const struct phy_reg phy_reg_init[] = {
1603 { 0x1f, 0x0001 }, 2114 { 0x1f, 0x0001 },
@@ -1605,10 +2116,10 @@ static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1605 { 0x1f, 0x0000 } 2116 { 0x1f, 0x0000 }
1606 }; 2117 };
1607 2118
1608 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2119 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1609} 2120}
1610 2121
1611static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) 2122static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
1612{ 2123{
1613 static const struct phy_reg phy_reg_init[] = { 2124 static const struct phy_reg phy_reg_init[] = {
1614 { 0x1f, 0x0000 }, 2125 { 0x1f, 0x0000 },
@@ -1618,10 +2129,10 @@ static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1618 { 0x1f, 0x0000 } 2129 { 0x1f, 0x0000 }
1619 }; 2130 };
1620 2131
1621 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2132 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1622} 2133}
1623 2134
1624static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) 2135static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
1625{ 2136{
1626 static const struct phy_reg phy_reg_init[] = { 2137 static const struct phy_reg phy_reg_init[] = {
1627 { 0x1f, 0x0001 }, 2138 { 0x1f, 0x0001 },
@@ -1629,14 +2140,14 @@ static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1629 { 0x1f, 0x0000 } 2140 { 0x1f, 0x0000 }
1630 }; 2141 };
1631 2142
1632 mdio_write(ioaddr, 0x1f, 0x0000); 2143 rtl_writephy(tp, 0x1f, 0x0000);
1633 mdio_patch(ioaddr, 0x14, 1 << 5); 2144 rtl_patchphy(tp, 0x14, 1 << 5);
1634 mdio_patch(ioaddr, 0x0d, 1 << 5); 2145 rtl_patchphy(tp, 0x0d, 1 << 5);
1635 2146
1636 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2147 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1637} 2148}
1638 2149
1639static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) 2150static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
1640{ 2151{
1641 static const struct phy_reg phy_reg_init[] = { 2152 static const struct phy_reg phy_reg_init[] = {
1642 { 0x1f, 0x0001 }, 2153 { 0x1f, 0x0001 },
@@ -1658,14 +2169,14 @@ static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1658 { 0x09, 0x0000 } 2169 { 0x09, 0x0000 }
1659 }; 2170 };
1660 2171
1661 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2172 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1662 2173
1663 mdio_patch(ioaddr, 0x14, 1 << 5); 2174 rtl_patchphy(tp, 0x14, 1 << 5);
1664 mdio_patch(ioaddr, 0x0d, 1 << 5); 2175 rtl_patchphy(tp, 0x0d, 1 << 5);
1665 mdio_write(ioaddr, 0x1f, 0x0000); 2176 rtl_writephy(tp, 0x1f, 0x0000);
1666} 2177}
1667 2178
1668static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) 2179static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
1669{ 2180{
1670 static const struct phy_reg phy_reg_init[] = { 2181 static const struct phy_reg phy_reg_init[] = {
1671 { 0x1f, 0x0001 }, 2182 { 0x1f, 0x0001 },
@@ -1685,15 +2196,15 @@ static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1685 { 0x1f, 0x0000 } 2196 { 0x1f, 0x0000 }
1686 }; 2197 };
1687 2198
1688 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2199 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1689 2200
1690 mdio_patch(ioaddr, 0x16, 1 << 0); 2201 rtl_patchphy(tp, 0x16, 1 << 0);
1691 mdio_patch(ioaddr, 0x14, 1 << 5); 2202 rtl_patchphy(tp, 0x14, 1 << 5);
1692 mdio_patch(ioaddr, 0x0d, 1 << 5); 2203 rtl_patchphy(tp, 0x0d, 1 << 5);
1693 mdio_write(ioaddr, 0x1f, 0x0000); 2204 rtl_writephy(tp, 0x1f, 0x0000);
1694} 2205}
1695 2206
1696static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) 2207static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
1697{ 2208{
1698 static const struct phy_reg phy_reg_init[] = { 2209 static const struct phy_reg phy_reg_init[] = {
1699 { 0x1f, 0x0001 }, 2210 { 0x1f, 0x0001 },
@@ -1707,22 +2218,23 @@ static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1707 { 0x1f, 0x0000 } 2218 { 0x1f, 0x0000 }
1708 }; 2219 };
1709 2220
1710 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2221 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1711 2222
1712 mdio_patch(ioaddr, 0x16, 1 << 0); 2223 rtl_patchphy(tp, 0x16, 1 << 0);
1713 mdio_patch(ioaddr, 0x14, 1 << 5); 2224 rtl_patchphy(tp, 0x14, 1 << 5);
1714 mdio_patch(ioaddr, 0x0d, 1 << 5); 2225 rtl_patchphy(tp, 0x0d, 1 << 5);
1715 mdio_write(ioaddr, 0x1f, 0x0000); 2226 rtl_writephy(tp, 0x1f, 0x0000);
1716} 2227}
1717 2228
1718static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) 2229static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
1719{ 2230{
1720 rtl8168c_3_hw_phy_config(ioaddr); 2231 rtl8168c_3_hw_phy_config(tp);
1721} 2232}
1722 2233
1723static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) 2234static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
1724{ 2235{
1725 static const struct phy_reg phy_reg_init_0[] = { 2236 static const struct phy_reg phy_reg_init_0[] = {
2237 /* Channel Estimation */
1726 { 0x1f, 0x0001 }, 2238 { 0x1f, 0x0001 },
1727 { 0x06, 0x4064 }, 2239 { 0x06, 0x4064 },
1728 { 0x07, 0x2863 }, 2240 { 0x07, 0x2863 },
@@ -1739,378 +2251,39 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1739 { 0x12, 0xf49f }, 2251 { 0x12, 0xf49f },
1740 { 0x13, 0x070b }, 2252 { 0x13, 0x070b },
1741 { 0x1a, 0x05ad }, 2253 { 0x1a, 0x05ad },
1742 { 0x14, 0x94c0 } 2254 { 0x14, 0x94c0 },
1743 }; 2255
1744 static const struct phy_reg phy_reg_init_1[] = { 2256 /*
2257 * Tx Error Issue
2258 * Enhance line driver power
2259 */
1745 { 0x1f, 0x0002 }, 2260 { 0x1f, 0x0002 },
1746 { 0x06, 0x5561 }, 2261 { 0x06, 0x5561 },
1747 { 0x1f, 0x0005 }, 2262 { 0x1f, 0x0005 },
1748 { 0x05, 0x8332 }, 2263 { 0x05, 0x8332 },
1749 { 0x06, 0x5561 } 2264 { 0x06, 0x5561 },
1750 }; 2265
1751 static const struct phy_reg phy_reg_init_2[] = { 2266 /*
1752 { 0x1f, 0x0005 }, 2267 * Can not link to 1Gbps with bad cable
1753 { 0x05, 0xffc2 }, 2268 * Decrease SNR threshold form 21.07dB to 19.04dB
1754 { 0x1f, 0x0005 }, 2269 */
1755 { 0x05, 0x8000 }, 2270 { 0x1f, 0x0001 },
1756 { 0x06, 0xf8f9 }, 2271 { 0x17, 0x0cc0 },
1757 { 0x06, 0xfaef },
1758 { 0x06, 0x59ee },
1759 { 0x06, 0xf8ea },
1760 { 0x06, 0x00ee },
1761 { 0x06, 0xf8eb },
1762 { 0x06, 0x00e0 },
1763 { 0x06, 0xf87c },
1764 { 0x06, 0xe1f8 },
1765 { 0x06, 0x7d59 },
1766 { 0x06, 0x0fef },
1767 { 0x06, 0x0139 },
1768 { 0x06, 0x029e },
1769 { 0x06, 0x06ef },
1770 { 0x06, 0x1039 },
1771 { 0x06, 0x089f },
1772 { 0x06, 0x2aee },
1773 { 0x06, 0xf8ea },
1774 { 0x06, 0x00ee },
1775 { 0x06, 0xf8eb },
1776 { 0x06, 0x01e0 },
1777 { 0x06, 0xf87c },
1778 { 0x06, 0xe1f8 },
1779 { 0x06, 0x7d58 },
1780 { 0x06, 0x409e },
1781 { 0x06, 0x0f39 },
1782 { 0x06, 0x46aa },
1783 { 0x06, 0x0bbf },
1784 { 0x06, 0x8290 },
1785 { 0x06, 0xd682 },
1786 { 0x06, 0x9802 },
1787 { 0x06, 0x014f },
1788 { 0x06, 0xae09 },
1789 { 0x06, 0xbf82 },
1790 { 0x06, 0x98d6 },
1791 { 0x06, 0x82a0 },
1792 { 0x06, 0x0201 },
1793 { 0x06, 0x4fef },
1794 { 0x06, 0x95fe },
1795 { 0x06, 0xfdfc },
1796 { 0x06, 0x05f8 },
1797 { 0x06, 0xf9fa },
1798 { 0x06, 0xeef8 },
1799 { 0x06, 0xea00 },
1800 { 0x06, 0xeef8 },
1801 { 0x06, 0xeb00 },
1802 { 0x06, 0xe2f8 },
1803 { 0x06, 0x7ce3 },
1804 { 0x06, 0xf87d },
1805 { 0x06, 0xa511 },
1806 { 0x06, 0x1112 },
1807 { 0x06, 0xd240 },
1808 { 0x06, 0xd644 },
1809 { 0x06, 0x4402 },
1810 { 0x06, 0x8217 },
1811 { 0x06, 0xd2a0 },
1812 { 0x06, 0xd6aa },
1813 { 0x06, 0xaa02 },
1814 { 0x06, 0x8217 },
1815 { 0x06, 0xae0f },
1816 { 0x06, 0xa544 },
1817 { 0x06, 0x4402 },
1818 { 0x06, 0xae4d },
1819 { 0x06, 0xa5aa },
1820 { 0x06, 0xaa02 },
1821 { 0x06, 0xae47 },
1822 { 0x06, 0xaf82 },
1823 { 0x06, 0x13ee },
1824 { 0x06, 0x834e },
1825 { 0x06, 0x00ee },
1826 { 0x06, 0x834d },
1827 { 0x06, 0x0fee },
1828 { 0x06, 0x834c },
1829 { 0x06, 0x0fee },
1830 { 0x06, 0x834f },
1831 { 0x06, 0x00ee },
1832 { 0x06, 0x8351 },
1833 { 0x06, 0x00ee },
1834 { 0x06, 0x834a },
1835 { 0x06, 0xffee },
1836 { 0x06, 0x834b },
1837 { 0x06, 0xffe0 },
1838 { 0x06, 0x8330 },
1839 { 0x06, 0xe183 },
1840 { 0x06, 0x3158 },
1841 { 0x06, 0xfee4 },
1842 { 0x06, 0xf88a },
1843 { 0x06, 0xe5f8 },
1844 { 0x06, 0x8be0 },
1845 { 0x06, 0x8332 },
1846 { 0x06, 0xe183 },
1847 { 0x06, 0x3359 },
1848 { 0x06, 0x0fe2 },
1849 { 0x06, 0x834d },
1850 { 0x06, 0x0c24 },
1851 { 0x06, 0x5af0 },
1852 { 0x06, 0x1e12 },
1853 { 0x06, 0xe4f8 },
1854 { 0x06, 0x8ce5 },
1855 { 0x06, 0xf88d },
1856 { 0x06, 0xaf82 },
1857 { 0x06, 0x13e0 },
1858 { 0x06, 0x834f },
1859 { 0x06, 0x10e4 },
1860 { 0x06, 0x834f },
1861 { 0x06, 0xe083 },
1862 { 0x06, 0x4e78 },
1863 { 0x06, 0x009f },
1864 { 0x06, 0x0ae0 },
1865 { 0x06, 0x834f },
1866 { 0x06, 0xa010 },
1867 { 0x06, 0xa5ee },
1868 { 0x06, 0x834e },
1869 { 0x06, 0x01e0 },
1870 { 0x06, 0x834e },
1871 { 0x06, 0x7805 },
1872 { 0x06, 0x9e9a },
1873 { 0x06, 0xe083 },
1874 { 0x06, 0x4e78 },
1875 { 0x06, 0x049e },
1876 { 0x06, 0x10e0 },
1877 { 0x06, 0x834e },
1878 { 0x06, 0x7803 },
1879 { 0x06, 0x9e0f },
1880 { 0x06, 0xe083 },
1881 { 0x06, 0x4e78 },
1882 { 0x06, 0x019e },
1883 { 0x06, 0x05ae },
1884 { 0x06, 0x0caf },
1885 { 0x06, 0x81f8 },
1886 { 0x06, 0xaf81 },
1887 { 0x06, 0xa3af },
1888 { 0x06, 0x81dc },
1889 { 0x06, 0xaf82 },
1890 { 0x06, 0x13ee },
1891 { 0x06, 0x8348 },
1892 { 0x06, 0x00ee },
1893 { 0x06, 0x8349 },
1894 { 0x06, 0x00e0 },
1895 { 0x06, 0x8351 },
1896 { 0x06, 0x10e4 },
1897 { 0x06, 0x8351 },
1898 { 0x06, 0x5801 },
1899 { 0x06, 0x9fea },
1900 { 0x06, 0xd000 },
1901 { 0x06, 0xd180 },
1902 { 0x06, 0x1f66 },
1903 { 0x06, 0xe2f8 },
1904 { 0x06, 0xeae3 },
1905 { 0x06, 0xf8eb },
1906 { 0x06, 0x5af8 },
1907 { 0x06, 0x1e20 },
1908 { 0x06, 0xe6f8 },
1909 { 0x06, 0xeae5 },
1910 { 0x06, 0xf8eb },
1911 { 0x06, 0xd302 },
1912 { 0x06, 0xb3fe },
1913 { 0x06, 0xe2f8 },
1914 { 0x06, 0x7cef },
1915 { 0x06, 0x325b },
1916 { 0x06, 0x80e3 },
1917 { 0x06, 0xf87d },
1918 { 0x06, 0x9e03 },
1919 { 0x06, 0x7dff },
1920 { 0x06, 0xff0d },
1921 { 0x06, 0x581c },
1922 { 0x06, 0x551a },
1923 { 0x06, 0x6511 },
1924 { 0x06, 0xa190 },
1925 { 0x06, 0xd3e2 },
1926 { 0x06, 0x8348 },
1927 { 0x06, 0xe383 },
1928 { 0x06, 0x491b },
1929 { 0x06, 0x56ab },
1930 { 0x06, 0x08ef },
1931 { 0x06, 0x56e6 },
1932 { 0x06, 0x8348 },
1933 { 0x06, 0xe783 },
1934 { 0x06, 0x4910 },
1935 { 0x06, 0xd180 },
1936 { 0x06, 0x1f66 },
1937 { 0x06, 0xa004 },
1938 { 0x06, 0xb9e2 },
1939 { 0x06, 0x8348 },
1940 { 0x06, 0xe383 },
1941 { 0x06, 0x49ef },
1942 { 0x06, 0x65e2 },
1943 { 0x06, 0x834a },
1944 { 0x06, 0xe383 },
1945 { 0x06, 0x4b1b },
1946 { 0x06, 0x56aa },
1947 { 0x06, 0x0eef },
1948 { 0x06, 0x56e6 },
1949 { 0x06, 0x834a },
1950 { 0x06, 0xe783 },
1951 { 0x06, 0x4be2 },
1952 { 0x06, 0x834d },
1953 { 0x06, 0xe683 },
1954 { 0x06, 0x4ce0 },
1955 { 0x06, 0x834d },
1956 { 0x06, 0xa000 },
1957 { 0x06, 0x0caf },
1958 { 0x06, 0x81dc },
1959 { 0x06, 0xe083 },
1960 { 0x06, 0x4d10 },
1961 { 0x06, 0xe483 },
1962 { 0x06, 0x4dae },
1963 { 0x06, 0x0480 },
1964 { 0x06, 0xe483 },
1965 { 0x06, 0x4de0 },
1966 { 0x06, 0x834e },
1967 { 0x06, 0x7803 },
1968 { 0x06, 0x9e0b },
1969 { 0x06, 0xe083 },
1970 { 0x06, 0x4e78 },
1971 { 0x06, 0x049e },
1972 { 0x06, 0x04ee },
1973 { 0x06, 0x834e },
1974 { 0x06, 0x02e0 },
1975 { 0x06, 0x8332 },
1976 { 0x06, 0xe183 },
1977 { 0x06, 0x3359 },
1978 { 0x06, 0x0fe2 },
1979 { 0x06, 0x834d },
1980 { 0x06, 0x0c24 },
1981 { 0x06, 0x5af0 },
1982 { 0x06, 0x1e12 },
1983 { 0x06, 0xe4f8 },
1984 { 0x06, 0x8ce5 },
1985 { 0x06, 0xf88d },
1986 { 0x06, 0xe083 },
1987 { 0x06, 0x30e1 },
1988 { 0x06, 0x8331 },
1989 { 0x06, 0x6801 },
1990 { 0x06, 0xe4f8 },
1991 { 0x06, 0x8ae5 },
1992 { 0x06, 0xf88b },
1993 { 0x06, 0xae37 },
1994 { 0x06, 0xee83 },
1995 { 0x06, 0x4e03 },
1996 { 0x06, 0xe083 },
1997 { 0x06, 0x4ce1 },
1998 { 0x06, 0x834d },
1999 { 0x06, 0x1b01 },
2000 { 0x06, 0x9e04 },
2001 { 0x06, 0xaaa1 },
2002 { 0x06, 0xaea8 },
2003 { 0x06, 0xee83 },
2004 { 0x06, 0x4e04 },
2005 { 0x06, 0xee83 },
2006 { 0x06, 0x4f00 },
2007 { 0x06, 0xaeab },
2008 { 0x06, 0xe083 },
2009 { 0x06, 0x4f78 },
2010 { 0x06, 0x039f },
2011 { 0x06, 0x14ee },
2012 { 0x06, 0x834e },
2013 { 0x06, 0x05d2 },
2014 { 0x06, 0x40d6 },
2015 { 0x06, 0x5554 },
2016 { 0x06, 0x0282 },
2017 { 0x06, 0x17d2 },
2018 { 0x06, 0xa0d6 },
2019 { 0x06, 0xba00 },
2020 { 0x06, 0x0282 },
2021 { 0x06, 0x17fe },
2022 { 0x06, 0xfdfc },
2023 { 0x06, 0x05f8 },
2024 { 0x06, 0xe0f8 },
2025 { 0x06, 0x60e1 },
2026 { 0x06, 0xf861 },
2027 { 0x06, 0x6802 },
2028 { 0x06, 0xe4f8 },
2029 { 0x06, 0x60e5 },
2030 { 0x06, 0xf861 },
2031 { 0x06, 0xe0f8 },
2032 { 0x06, 0x48e1 },
2033 { 0x06, 0xf849 },
2034 { 0x06, 0x580f },
2035 { 0x06, 0x1e02 },
2036 { 0x06, 0xe4f8 },
2037 { 0x06, 0x48e5 },
2038 { 0x06, 0xf849 },
2039 { 0x06, 0xd000 },
2040 { 0x06, 0x0282 },
2041 { 0x06, 0x5bbf },
2042 { 0x06, 0x8350 },
2043 { 0x06, 0xef46 },
2044 { 0x06, 0xdc19 },
2045 { 0x06, 0xddd0 },
2046 { 0x06, 0x0102 },
2047 { 0x06, 0x825b },
2048 { 0x06, 0x0282 },
2049 { 0x06, 0x77e0 },
2050 { 0x06, 0xf860 },
2051 { 0x06, 0xe1f8 },
2052 { 0x06, 0x6158 },
2053 { 0x06, 0xfde4 },
2054 { 0x06, 0xf860 },
2055 { 0x06, 0xe5f8 },
2056 { 0x06, 0x61fc },
2057 { 0x06, 0x04f9 },
2058 { 0x06, 0xfafb },
2059 { 0x06, 0xc6bf },
2060 { 0x06, 0xf840 },
2061 { 0x06, 0xbe83 },
2062 { 0x06, 0x50a0 },
2063 { 0x06, 0x0101 },
2064 { 0x06, 0x071b },
2065 { 0x06, 0x89cf },
2066 { 0x06, 0xd208 },
2067 { 0x06, 0xebdb },
2068 { 0x06, 0x19b2 },
2069 { 0x06, 0xfbff },
2070 { 0x06, 0xfefd },
2071 { 0x06, 0x04f8 },
2072 { 0x06, 0xe0f8 },
2073 { 0x06, 0x48e1 },
2074 { 0x06, 0xf849 },
2075 { 0x06, 0x6808 },
2076 { 0x06, 0xe4f8 },
2077 { 0x06, 0x48e5 },
2078 { 0x06, 0xf849 },
2079 { 0x06, 0x58f7 },
2080 { 0x06, 0xe4f8 },
2081 { 0x06, 0x48e5 },
2082 { 0x06, 0xf849 },
2083 { 0x06, 0xfc04 },
2084 { 0x06, 0x4d20 },
2085 { 0x06, 0x0002 },
2086 { 0x06, 0x4e22 },
2087 { 0x06, 0x0002 },
2088 { 0x06, 0x4ddf },
2089 { 0x06, 0xff01 },
2090 { 0x06, 0x4edd },
2091 { 0x06, 0xff01 },
2092 { 0x05, 0x83d4 },
2093 { 0x06, 0x8000 },
2094 { 0x05, 0x83d8 },
2095 { 0x06, 0x8051 },
2096 { 0x02, 0x6010 },
2097 { 0x03, 0xdc00 },
2098 { 0x05, 0xfff6 },
2099 { 0x06, 0x00fc },
2100 { 0x1f, 0x0000 },
2101 2272
2102 { 0x1f, 0x0000 }, 2273 { 0x1f, 0x0000 },
2103 { 0x0d, 0xf880 }, 2274 { 0x0d, 0xf880 }
2104 { 0x1f, 0x0000 }
2105 }; 2275 };
2276 void __iomem *ioaddr = tp->mmio_addr;
2106 2277
2107 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); 2278 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2108
2109 mdio_write(ioaddr, 0x1f, 0x0002);
2110 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2111 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2112 2279
2113 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); 2280 /*
2281 * Rx Error Issue
2282 * Fine Tune Switching regulator parameter
2283 */
2284 rtl_writephy(tp, 0x1f, 0x0002);
2285 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2286 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2114 2287
2115 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { 2288 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2116 static const struct phy_reg phy_reg_init[] = { 2289 static const struct phy_reg phy_reg_init[] = {
@@ -2123,9 +2296,9 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
2123 }; 2296 };
2124 int val; 2297 int val;
2125 2298
2126 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2299 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2127 2300
2128 val = mdio_read(ioaddr, 0x0d); 2301 val = rtl_readphy(tp, 0x0d);
2129 2302
2130 if ((val & 0x00ff) != 0x006c) { 2303 if ((val & 0x00ff) != 0x006c) {
2131 static const u32 set[] = { 2304 static const u32 set[] = {
@@ -2134,11 +2307,11 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
2134 }; 2307 };
2135 int i; 2308 int i;
2136 2309
2137 mdio_write(ioaddr, 0x1f, 0x0002); 2310 rtl_writephy(tp, 0x1f, 0x0002);
2138 2311
2139 val &= 0xff00; 2312 val &= 0xff00;
2140 for (i = 0; i < ARRAY_SIZE(set); i++) 2313 for (i = 0; i < ARRAY_SIZE(set); i++)
2141 mdio_write(ioaddr, 0x0d, val | set[i]); 2314 rtl_writephy(tp, 0x0d, val | set[i]);
2142 } 2315 }
2143 } else { 2316 } else {
2144 static const struct phy_reg phy_reg_init[] = { 2317 static const struct phy_reg phy_reg_init[] = {
@@ -2149,23 +2322,31 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
2149 { 0x06, 0x6662 } 2322 { 0x06, 0x6662 }
2150 }; 2323 };
2151 2324
2152 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2153 } 2326 }
2154 2327
2155 mdio_write(ioaddr, 0x1f, 0x0002); 2328 /* RSET couple improve */
2156 mdio_patch(ioaddr, 0x0d, 0x0300); 2329 rtl_writephy(tp, 0x1f, 0x0002);
2157 mdio_patch(ioaddr, 0x0f, 0x0010); 2330 rtl_patchphy(tp, 0x0d, 0x0300);
2331 rtl_patchphy(tp, 0x0f, 0x0010);
2332
2333 /* Fine tune PLL performance */
2334 rtl_writephy(tp, 0x1f, 0x0002);
2335 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2336 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2158 2337
2159 mdio_write(ioaddr, 0x1f, 0x0002); 2338 rtl_writephy(tp, 0x1f, 0x0005);
2160 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); 2339 rtl_writephy(tp, 0x05, 0x001b);
2161 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2162 2340
2163 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2)); 2341 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2342
2343 rtl_writephy(tp, 0x1f, 0x0000);
2164} 2344}
2165 2345
2166static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) 2346static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2167{ 2347{
2168 static const struct phy_reg phy_reg_init_0[] = { 2348 static const struct phy_reg phy_reg_init_0[] = {
2349 /* Channel Estimation */
2169 { 0x1f, 0x0001 }, 2350 { 0x1f, 0x0001 },
2170 { 0x06, 0x4064 }, 2351 { 0x06, 0x4064 },
2171 { 0x07, 0x2863 }, 2352 { 0x07, 0x2863 },
@@ -2184,326 +2365,29 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2184 { 0x1a, 0x05ad }, 2365 { 0x1a, 0x05ad },
2185 { 0x14, 0x94c0 }, 2366 { 0x14, 0x94c0 },
2186 2367
2368 /*
2369 * Tx Error Issue
2370 * Enhance line driver power
2371 */
2187 { 0x1f, 0x0002 }, 2372 { 0x1f, 0x0002 },
2188 { 0x06, 0x5561 }, 2373 { 0x06, 0x5561 },
2189 { 0x1f, 0x0005 }, 2374 { 0x1f, 0x0005 },
2190 { 0x05, 0x8332 }, 2375 { 0x05, 0x8332 },
2191 { 0x06, 0x5561 } 2376 { 0x06, 0x5561 },
2192 }; 2377
2193 static const struct phy_reg phy_reg_init_1[] = { 2378 /*
2194 { 0x1f, 0x0005 }, 2379 * Can not link to 1Gbps with bad cable
2195 { 0x05, 0xffc2 }, 2380 * Decrease SNR threshold form 21.07dB to 19.04dB
2196 { 0x1f, 0x0005 }, 2381 */
2197 { 0x05, 0x8000 }, 2382 { 0x1f, 0x0001 },
2198 { 0x06, 0xf8f9 }, 2383 { 0x17, 0x0cc0 },
2199 { 0x06, 0xfaee },
2200 { 0x06, 0xf8ea },
2201 { 0x06, 0x00ee },
2202 { 0x06, 0xf8eb },
2203 { 0x06, 0x00e2 },
2204 { 0x06, 0xf87c },
2205 { 0x06, 0xe3f8 },
2206 { 0x06, 0x7da5 },
2207 { 0x06, 0x1111 },
2208 { 0x06, 0x12d2 },
2209 { 0x06, 0x40d6 },
2210 { 0x06, 0x4444 },
2211 { 0x06, 0x0281 },
2212 { 0x06, 0xc6d2 },
2213 { 0x06, 0xa0d6 },
2214 { 0x06, 0xaaaa },
2215 { 0x06, 0x0281 },
2216 { 0x06, 0xc6ae },
2217 { 0x06, 0x0fa5 },
2218 { 0x06, 0x4444 },
2219 { 0x06, 0x02ae },
2220 { 0x06, 0x4da5 },
2221 { 0x06, 0xaaaa },
2222 { 0x06, 0x02ae },
2223 { 0x06, 0x47af },
2224 { 0x06, 0x81c2 },
2225 { 0x06, 0xee83 },
2226 { 0x06, 0x4e00 },
2227 { 0x06, 0xee83 },
2228 { 0x06, 0x4d0f },
2229 { 0x06, 0xee83 },
2230 { 0x06, 0x4c0f },
2231 { 0x06, 0xee83 },
2232 { 0x06, 0x4f00 },
2233 { 0x06, 0xee83 },
2234 { 0x06, 0x5100 },
2235 { 0x06, 0xee83 },
2236 { 0x06, 0x4aff },
2237 { 0x06, 0xee83 },
2238 { 0x06, 0x4bff },
2239 { 0x06, 0xe083 },
2240 { 0x06, 0x30e1 },
2241 { 0x06, 0x8331 },
2242 { 0x06, 0x58fe },
2243 { 0x06, 0xe4f8 },
2244 { 0x06, 0x8ae5 },
2245 { 0x06, 0xf88b },
2246 { 0x06, 0xe083 },
2247 { 0x06, 0x32e1 },
2248 { 0x06, 0x8333 },
2249 { 0x06, 0x590f },
2250 { 0x06, 0xe283 },
2251 { 0x06, 0x4d0c },
2252 { 0x06, 0x245a },
2253 { 0x06, 0xf01e },
2254 { 0x06, 0x12e4 },
2255 { 0x06, 0xf88c },
2256 { 0x06, 0xe5f8 },
2257 { 0x06, 0x8daf },
2258 { 0x06, 0x81c2 },
2259 { 0x06, 0xe083 },
2260 { 0x06, 0x4f10 },
2261 { 0x06, 0xe483 },
2262 { 0x06, 0x4fe0 },
2263 { 0x06, 0x834e },
2264 { 0x06, 0x7800 },
2265 { 0x06, 0x9f0a },
2266 { 0x06, 0xe083 },
2267 { 0x06, 0x4fa0 },
2268 { 0x06, 0x10a5 },
2269 { 0x06, 0xee83 },
2270 { 0x06, 0x4e01 },
2271 { 0x06, 0xe083 },
2272 { 0x06, 0x4e78 },
2273 { 0x06, 0x059e },
2274 { 0x06, 0x9ae0 },
2275 { 0x06, 0x834e },
2276 { 0x06, 0x7804 },
2277 { 0x06, 0x9e10 },
2278 { 0x06, 0xe083 },
2279 { 0x06, 0x4e78 },
2280 { 0x06, 0x039e },
2281 { 0x06, 0x0fe0 },
2282 { 0x06, 0x834e },
2283 { 0x06, 0x7801 },
2284 { 0x06, 0x9e05 },
2285 { 0x06, 0xae0c },
2286 { 0x06, 0xaf81 },
2287 { 0x06, 0xa7af },
2288 { 0x06, 0x8152 },
2289 { 0x06, 0xaf81 },
2290 { 0x06, 0x8baf },
2291 { 0x06, 0x81c2 },
2292 { 0x06, 0xee83 },
2293 { 0x06, 0x4800 },
2294 { 0x06, 0xee83 },
2295 { 0x06, 0x4900 },
2296 { 0x06, 0xe083 },
2297 { 0x06, 0x5110 },
2298 { 0x06, 0xe483 },
2299 { 0x06, 0x5158 },
2300 { 0x06, 0x019f },
2301 { 0x06, 0xead0 },
2302 { 0x06, 0x00d1 },
2303 { 0x06, 0x801f },
2304 { 0x06, 0x66e2 },
2305 { 0x06, 0xf8ea },
2306 { 0x06, 0xe3f8 },
2307 { 0x06, 0xeb5a },
2308 { 0x06, 0xf81e },
2309 { 0x06, 0x20e6 },
2310 { 0x06, 0xf8ea },
2311 { 0x06, 0xe5f8 },
2312 { 0x06, 0xebd3 },
2313 { 0x06, 0x02b3 },
2314 { 0x06, 0xfee2 },
2315 { 0x06, 0xf87c },
2316 { 0x06, 0xef32 },
2317 { 0x06, 0x5b80 },
2318 { 0x06, 0xe3f8 },
2319 { 0x06, 0x7d9e },
2320 { 0x06, 0x037d },
2321 { 0x06, 0xffff },
2322 { 0x06, 0x0d58 },
2323 { 0x06, 0x1c55 },
2324 { 0x06, 0x1a65 },
2325 { 0x06, 0x11a1 },
2326 { 0x06, 0x90d3 },
2327 { 0x06, 0xe283 },
2328 { 0x06, 0x48e3 },
2329 { 0x06, 0x8349 },
2330 { 0x06, 0x1b56 },
2331 { 0x06, 0xab08 },
2332 { 0x06, 0xef56 },
2333 { 0x06, 0xe683 },
2334 { 0x06, 0x48e7 },
2335 { 0x06, 0x8349 },
2336 { 0x06, 0x10d1 },
2337 { 0x06, 0x801f },
2338 { 0x06, 0x66a0 },
2339 { 0x06, 0x04b9 },
2340 { 0x06, 0xe283 },
2341 { 0x06, 0x48e3 },
2342 { 0x06, 0x8349 },
2343 { 0x06, 0xef65 },
2344 { 0x06, 0xe283 },
2345 { 0x06, 0x4ae3 },
2346 { 0x06, 0x834b },
2347 { 0x06, 0x1b56 },
2348 { 0x06, 0xaa0e },
2349 { 0x06, 0xef56 },
2350 { 0x06, 0xe683 },
2351 { 0x06, 0x4ae7 },
2352 { 0x06, 0x834b },
2353 { 0x06, 0xe283 },
2354 { 0x06, 0x4de6 },
2355 { 0x06, 0x834c },
2356 { 0x06, 0xe083 },
2357 { 0x06, 0x4da0 },
2358 { 0x06, 0x000c },
2359 { 0x06, 0xaf81 },
2360 { 0x06, 0x8be0 },
2361 { 0x06, 0x834d },
2362 { 0x06, 0x10e4 },
2363 { 0x06, 0x834d },
2364 { 0x06, 0xae04 },
2365 { 0x06, 0x80e4 },
2366 { 0x06, 0x834d },
2367 { 0x06, 0xe083 },
2368 { 0x06, 0x4e78 },
2369 { 0x06, 0x039e },
2370 { 0x06, 0x0be0 },
2371 { 0x06, 0x834e },
2372 { 0x06, 0x7804 },
2373 { 0x06, 0x9e04 },
2374 { 0x06, 0xee83 },
2375 { 0x06, 0x4e02 },
2376 { 0x06, 0xe083 },
2377 { 0x06, 0x32e1 },
2378 { 0x06, 0x8333 },
2379 { 0x06, 0x590f },
2380 { 0x06, 0xe283 },
2381 { 0x06, 0x4d0c },
2382 { 0x06, 0x245a },
2383 { 0x06, 0xf01e },
2384 { 0x06, 0x12e4 },
2385 { 0x06, 0xf88c },
2386 { 0x06, 0xe5f8 },
2387 { 0x06, 0x8de0 },
2388 { 0x06, 0x8330 },
2389 { 0x06, 0xe183 },
2390 { 0x06, 0x3168 },
2391 { 0x06, 0x01e4 },
2392 { 0x06, 0xf88a },
2393 { 0x06, 0xe5f8 },
2394 { 0x06, 0x8bae },
2395 { 0x06, 0x37ee },
2396 { 0x06, 0x834e },
2397 { 0x06, 0x03e0 },
2398 { 0x06, 0x834c },
2399 { 0x06, 0xe183 },
2400 { 0x06, 0x4d1b },
2401 { 0x06, 0x019e },
2402 { 0x06, 0x04aa },
2403 { 0x06, 0xa1ae },
2404 { 0x06, 0xa8ee },
2405 { 0x06, 0x834e },
2406 { 0x06, 0x04ee },
2407 { 0x06, 0x834f },
2408 { 0x06, 0x00ae },
2409 { 0x06, 0xabe0 },
2410 { 0x06, 0x834f },
2411 { 0x06, 0x7803 },
2412 { 0x06, 0x9f14 },
2413 { 0x06, 0xee83 },
2414 { 0x06, 0x4e05 },
2415 { 0x06, 0xd240 },
2416 { 0x06, 0xd655 },
2417 { 0x06, 0x5402 },
2418 { 0x06, 0x81c6 },
2419 { 0x06, 0xd2a0 },
2420 { 0x06, 0xd6ba },
2421 { 0x06, 0x0002 },
2422 { 0x06, 0x81c6 },
2423 { 0x06, 0xfefd },
2424 { 0x06, 0xfc05 },
2425 { 0x06, 0xf8e0 },
2426 { 0x06, 0xf860 },
2427 { 0x06, 0xe1f8 },
2428 { 0x06, 0x6168 },
2429 { 0x06, 0x02e4 },
2430 { 0x06, 0xf860 },
2431 { 0x06, 0xe5f8 },
2432 { 0x06, 0x61e0 },
2433 { 0x06, 0xf848 },
2434 { 0x06, 0xe1f8 },
2435 { 0x06, 0x4958 },
2436 { 0x06, 0x0f1e },
2437 { 0x06, 0x02e4 },
2438 { 0x06, 0xf848 },
2439 { 0x06, 0xe5f8 },
2440 { 0x06, 0x49d0 },
2441 { 0x06, 0x0002 },
2442 { 0x06, 0x820a },
2443 { 0x06, 0xbf83 },
2444 { 0x06, 0x50ef },
2445 { 0x06, 0x46dc },
2446 { 0x06, 0x19dd },
2447 { 0x06, 0xd001 },
2448 { 0x06, 0x0282 },
2449 { 0x06, 0x0a02 },
2450 { 0x06, 0x8226 },
2451 { 0x06, 0xe0f8 },
2452 { 0x06, 0x60e1 },
2453 { 0x06, 0xf861 },
2454 { 0x06, 0x58fd },
2455 { 0x06, 0xe4f8 },
2456 { 0x06, 0x60e5 },
2457 { 0x06, 0xf861 },
2458 { 0x06, 0xfc04 },
2459 { 0x06, 0xf9fa },
2460 { 0x06, 0xfbc6 },
2461 { 0x06, 0xbff8 },
2462 { 0x06, 0x40be },
2463 { 0x06, 0x8350 },
2464 { 0x06, 0xa001 },
2465 { 0x06, 0x0107 },
2466 { 0x06, 0x1b89 },
2467 { 0x06, 0xcfd2 },
2468 { 0x06, 0x08eb },
2469 { 0x06, 0xdb19 },
2470 { 0x06, 0xb2fb },
2471 { 0x06, 0xfffe },
2472 { 0x06, 0xfd04 },
2473 { 0x06, 0xf8e0 },
2474 { 0x06, 0xf848 },
2475 { 0x06, 0xe1f8 },
2476 { 0x06, 0x4968 },
2477 { 0x06, 0x08e4 },
2478 { 0x06, 0xf848 },
2479 { 0x06, 0xe5f8 },
2480 { 0x06, 0x4958 },
2481 { 0x06, 0xf7e4 },
2482 { 0x06, 0xf848 },
2483 { 0x06, 0xe5f8 },
2484 { 0x06, 0x49fc },
2485 { 0x06, 0x044d },
2486 { 0x06, 0x2000 },
2487 { 0x06, 0x024e },
2488 { 0x06, 0x2200 },
2489 { 0x06, 0x024d },
2490 { 0x06, 0xdfff },
2491 { 0x06, 0x014e },
2492 { 0x06, 0xddff },
2493 { 0x06, 0x0100 },
2494 { 0x05, 0x83d8 },
2495 { 0x06, 0x8000 },
2496 { 0x03, 0xdc00 },
2497 { 0x05, 0xfff6 },
2498 { 0x06, 0x00fc },
2499 { 0x1f, 0x0000 },
2500 2384
2501 { 0x1f, 0x0000 }, 2385 { 0x1f, 0x0000 },
2502 { 0x0d, 0xf880 }, 2386 { 0x0d, 0xf880 }
2503 { 0x1f, 0x0000 }
2504 }; 2387 };
2388 void __iomem *ioaddr = tp->mmio_addr;
2505 2389
2506 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); 2390 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2507 2391
2508 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { 2392 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2509 static const struct phy_reg phy_reg_init[] = { 2393 static const struct phy_reg phy_reg_init[] = {
@@ -2517,21 +2401,21 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2517 }; 2401 };
2518 int val; 2402 int val;
2519 2403
2520 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2404 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2521 2405
2522 val = mdio_read(ioaddr, 0x0d); 2406 val = rtl_readphy(tp, 0x0d);
2523 if ((val & 0x00ff) != 0x006c) { 2407 if ((val & 0x00ff) != 0x006c) {
2524 u32 set[] = { 2408 static const u32 set[] = {
2525 0x0065, 0x0066, 0x0067, 0x0068, 2409 0x0065, 0x0066, 0x0067, 0x0068,
2526 0x0069, 0x006a, 0x006b, 0x006c 2410 0x0069, 0x006a, 0x006b, 0x006c
2527 }; 2411 };
2528 int i; 2412 int i;
2529 2413
2530 mdio_write(ioaddr, 0x1f, 0x0002); 2414 rtl_writephy(tp, 0x1f, 0x0002);
2531 2415
2532 val &= 0xff00; 2416 val &= 0xff00;
2533 for (i = 0; i < ARRAY_SIZE(set); i++) 2417 for (i = 0; i < ARRAY_SIZE(set); i++)
2534 mdio_write(ioaddr, 0x0d, val | set[i]); 2418 rtl_writephy(tp, 0x0d, val | set[i]);
2535 } 2419 }
2536 } else { 2420 } else {
2537 static const struct phy_reg phy_reg_init[] = { 2421 static const struct phy_reg phy_reg_init[] = {
@@ -2542,23 +2426,27 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2542 { 0x06, 0x2642 } 2426 { 0x06, 0x2642 }
2543 }; 2427 };
2544 2428
2545 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2429 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2546 } 2430 }
2547 2431
2548 mdio_write(ioaddr, 0x1f, 0x0002); 2432 /* Fine tune PLL performance */
2549 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); 2433 rtl_writephy(tp, 0x1f, 0x0002);
2550 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); 2434 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2435 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2436
2437 /* Switching regulator Slew rate */
2438 rtl_writephy(tp, 0x1f, 0x0002);
2439 rtl_patchphy(tp, 0x0f, 0x0017);
2551 2440
2552 mdio_write(ioaddr, 0x1f, 0x0001); 2441 rtl_writephy(tp, 0x1f, 0x0005);
2553 mdio_write(ioaddr, 0x17, 0x0cc0); 2442 rtl_writephy(tp, 0x05, 0x001b);
2554 2443
2555 mdio_write(ioaddr, 0x1f, 0x0002); 2444 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2556 mdio_patch(ioaddr, 0x0f, 0x0017);
2557 2445
2558 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); 2446 rtl_writephy(tp, 0x1f, 0x0000);
2559} 2447}
2560 2448
2561static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr) 2449static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2562{ 2450{
2563 static const struct phy_reg phy_reg_init[] = { 2451 static const struct phy_reg phy_reg_init[] = {
2564 { 0x1f, 0x0002 }, 2452 { 0x1f, 0x0002 },
@@ -2616,10 +2504,99 @@ static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2616 { 0x1f, 0x0000 } 2504 { 0x1f, 0x0000 }
2617 }; 2505 };
2618 2506
2619 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2507 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2508}
2509
2510static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2511{
2512 static const struct phy_reg phy_reg_init[] = {
2513 { 0x1f, 0x0001 },
2514 { 0x17, 0x0cc0 },
2515
2516 { 0x1f, 0x0007 },
2517 { 0x1e, 0x002d },
2518 { 0x18, 0x0040 },
2519 { 0x1f, 0x0000 }
2520 };
2521
2522 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2523 rtl_patchphy(tp, 0x0d, 1 << 5);
2620} 2524}
2621 2525
2622static void rtl8102e_hw_phy_config(void __iomem *ioaddr) 2526static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2527{
2528 static const struct phy_reg phy_reg_init[] = {
2529 /* Enable Delay cap */
2530 { 0x1f, 0x0005 },
2531 { 0x05, 0x8b80 },
2532 { 0x06, 0xc896 },
2533 { 0x1f, 0x0000 },
2534
2535 /* Channel estimation fine tune */
2536 { 0x1f, 0x0001 },
2537 { 0x0b, 0x6c20 },
2538 { 0x07, 0x2872 },
2539 { 0x1c, 0xefff },
2540 { 0x1f, 0x0003 },
2541 { 0x14, 0x6420 },
2542 { 0x1f, 0x0000 },
2543
2544 /* Update PFM & 10M TX idle timer */
2545 { 0x1f, 0x0007 },
2546 { 0x1e, 0x002f },
2547 { 0x15, 0x1919 },
2548 { 0x1f, 0x0000 },
2549
2550 { 0x1f, 0x0007 },
2551 { 0x1e, 0x00ac },
2552 { 0x18, 0x0006 },
2553 { 0x1f, 0x0000 }
2554 };
2555
2556 rtl_apply_firmware(tp);
2557
2558 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559
2560 /* DCO enable for 10M IDLE Power */
2561 rtl_writephy(tp, 0x1f, 0x0007);
2562 rtl_writephy(tp, 0x1e, 0x0023);
2563 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2564 rtl_writephy(tp, 0x1f, 0x0000);
2565
2566 /* For impedance matching */
2567 rtl_writephy(tp, 0x1f, 0x0002);
2568 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2569 rtl_writephy(tp, 0x1f, 0x0000);
2570
2571 /* PHY auto speed down */
2572 rtl_writephy(tp, 0x1f, 0x0007);
2573 rtl_writephy(tp, 0x1e, 0x002d);
2574 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2575 rtl_writephy(tp, 0x1f, 0x0000);
2576 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2577
2578 rtl_writephy(tp, 0x1f, 0x0005);
2579 rtl_writephy(tp, 0x05, 0x8b86);
2580 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2581 rtl_writephy(tp, 0x1f, 0x0000);
2582
2583 rtl_writephy(tp, 0x1f, 0x0005);
2584 rtl_writephy(tp, 0x05, 0x8b85);
2585 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2586 rtl_writephy(tp, 0x1f, 0x0007);
2587 rtl_writephy(tp, 0x1e, 0x0020);
2588 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2589 rtl_writephy(tp, 0x1f, 0x0006);
2590 rtl_writephy(tp, 0x00, 0x5a00);
2591 rtl_writephy(tp, 0x1f, 0x0000);
2592 rtl_writephy(tp, 0x0d, 0x0007);
2593 rtl_writephy(tp, 0x0e, 0x003c);
2594 rtl_writephy(tp, 0x0d, 0x4007);
2595 rtl_writephy(tp, 0x0e, 0x0000);
2596 rtl_writephy(tp, 0x0d, 0x0000);
2597}
2598
2599static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2623{ 2600{
2624 static const struct phy_reg phy_reg_init[] = { 2601 static const struct phy_reg phy_reg_init[] = {
2625 { 0x1f, 0x0003 }, 2602 { 0x1f, 0x0003 },
@@ -2628,18 +2605,43 @@ static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2628 { 0x1f, 0x0000 } 2605 { 0x1f, 0x0000 }
2629 }; 2606 };
2630 2607
2631 mdio_write(ioaddr, 0x1f, 0x0000); 2608 rtl_writephy(tp, 0x1f, 0x0000);
2632 mdio_patch(ioaddr, 0x11, 1 << 12); 2609 rtl_patchphy(tp, 0x11, 1 << 12);
2633 mdio_patch(ioaddr, 0x19, 1 << 13); 2610 rtl_patchphy(tp, 0x19, 1 << 13);
2634 mdio_patch(ioaddr, 0x10, 1 << 15); 2611 rtl_patchphy(tp, 0x10, 1 << 15);
2612
2613 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2614}
2615
2616static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2617{
2618 static const struct phy_reg phy_reg_init[] = {
2619 { 0x1f, 0x0005 },
2620 { 0x1a, 0x0000 },
2621 { 0x1f, 0x0000 },
2622
2623 { 0x1f, 0x0004 },
2624 { 0x1c, 0x0000 },
2625 { 0x1f, 0x0000 },
2626
2627 { 0x1f, 0x0001 },
2628 { 0x15, 0x7701 },
2629 { 0x1f, 0x0000 }
2630 };
2631
2632 /* Disable ALDPS before ram code */
2633 rtl_writephy(tp, 0x1f, 0x0000);
2634 rtl_writephy(tp, 0x18, 0x0310);
2635 msleep(100);
2636
2637 rtl_apply_firmware(tp);
2635 2638
2636 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2639 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637} 2640}
2638 2641
2639static void rtl_hw_phy_config(struct net_device *dev) 2642static void rtl_hw_phy_config(struct net_device *dev)
2640{ 2643{
2641 struct rtl8169_private *tp = netdev_priv(dev); 2644 struct rtl8169_private *tp = netdev_priv(dev);
2642 void __iomem *ioaddr = tp->mmio_addr;
2643 2645
2644 rtl8169_print_mac_version(tp); 2646 rtl8169_print_mac_version(tp);
2645 2647
@@ -2648,58 +2650,72 @@ static void rtl_hw_phy_config(struct net_device *dev)
2648 break; 2650 break;
2649 case RTL_GIGA_MAC_VER_02: 2651 case RTL_GIGA_MAC_VER_02:
2650 case RTL_GIGA_MAC_VER_03: 2652 case RTL_GIGA_MAC_VER_03:
2651 rtl8169s_hw_phy_config(ioaddr); 2653 rtl8169s_hw_phy_config(tp);
2652 break; 2654 break;
2653 case RTL_GIGA_MAC_VER_04: 2655 case RTL_GIGA_MAC_VER_04:
2654 rtl8169sb_hw_phy_config(ioaddr); 2656 rtl8169sb_hw_phy_config(tp);
2655 break; 2657 break;
2656 case RTL_GIGA_MAC_VER_05: 2658 case RTL_GIGA_MAC_VER_05:
2657 rtl8169scd_hw_phy_config(tp, ioaddr); 2659 rtl8169scd_hw_phy_config(tp);
2658 break; 2660 break;
2659 case RTL_GIGA_MAC_VER_06: 2661 case RTL_GIGA_MAC_VER_06:
2660 rtl8169sce_hw_phy_config(ioaddr); 2662 rtl8169sce_hw_phy_config(tp);
2661 break; 2663 break;
2662 case RTL_GIGA_MAC_VER_07: 2664 case RTL_GIGA_MAC_VER_07:
2663 case RTL_GIGA_MAC_VER_08: 2665 case RTL_GIGA_MAC_VER_08:
2664 case RTL_GIGA_MAC_VER_09: 2666 case RTL_GIGA_MAC_VER_09:
2665 rtl8102e_hw_phy_config(ioaddr); 2667 rtl8102e_hw_phy_config(tp);
2666 break; 2668 break;
2667 case RTL_GIGA_MAC_VER_11: 2669 case RTL_GIGA_MAC_VER_11:
2668 rtl8168bb_hw_phy_config(ioaddr); 2670 rtl8168bb_hw_phy_config(tp);
2669 break; 2671 break;
2670 case RTL_GIGA_MAC_VER_12: 2672 case RTL_GIGA_MAC_VER_12:
2671 rtl8168bef_hw_phy_config(ioaddr); 2673 rtl8168bef_hw_phy_config(tp);
2672 break; 2674 break;
2673 case RTL_GIGA_MAC_VER_17: 2675 case RTL_GIGA_MAC_VER_17:
2674 rtl8168bef_hw_phy_config(ioaddr); 2676 rtl8168bef_hw_phy_config(tp);
2675 break; 2677 break;
2676 case RTL_GIGA_MAC_VER_18: 2678 case RTL_GIGA_MAC_VER_18:
2677 rtl8168cp_1_hw_phy_config(ioaddr); 2679 rtl8168cp_1_hw_phy_config(tp);
2678 break; 2680 break;
2679 case RTL_GIGA_MAC_VER_19: 2681 case RTL_GIGA_MAC_VER_19:
2680 rtl8168c_1_hw_phy_config(ioaddr); 2682 rtl8168c_1_hw_phy_config(tp);
2681 break; 2683 break;
2682 case RTL_GIGA_MAC_VER_20: 2684 case RTL_GIGA_MAC_VER_20:
2683 rtl8168c_2_hw_phy_config(ioaddr); 2685 rtl8168c_2_hw_phy_config(tp);
2684 break; 2686 break;
2685 case RTL_GIGA_MAC_VER_21: 2687 case RTL_GIGA_MAC_VER_21:
2686 rtl8168c_3_hw_phy_config(ioaddr); 2688 rtl8168c_3_hw_phy_config(tp);
2687 break; 2689 break;
2688 case RTL_GIGA_MAC_VER_22: 2690 case RTL_GIGA_MAC_VER_22:
2689 rtl8168c_4_hw_phy_config(ioaddr); 2691 rtl8168c_4_hw_phy_config(tp);
2690 break; 2692 break;
2691 case RTL_GIGA_MAC_VER_23: 2693 case RTL_GIGA_MAC_VER_23:
2692 case RTL_GIGA_MAC_VER_24: 2694 case RTL_GIGA_MAC_VER_24:
2693 rtl8168cp_2_hw_phy_config(ioaddr); 2695 rtl8168cp_2_hw_phy_config(tp);
2694 break; 2696 break;
2695 case RTL_GIGA_MAC_VER_25: 2697 case RTL_GIGA_MAC_VER_25:
2696 rtl8168d_1_hw_phy_config(ioaddr); 2698 rtl8168d_1_hw_phy_config(tp);
2697 break; 2699 break;
2698 case RTL_GIGA_MAC_VER_26: 2700 case RTL_GIGA_MAC_VER_26:
2699 rtl8168d_2_hw_phy_config(ioaddr); 2701 rtl8168d_2_hw_phy_config(tp);
2700 break; 2702 break;
2701 case RTL_GIGA_MAC_VER_27: 2703 case RTL_GIGA_MAC_VER_27:
2702 rtl8168d_3_hw_phy_config(ioaddr); 2704 rtl8168d_3_hw_phy_config(tp);
2705 break;
2706 case RTL_GIGA_MAC_VER_28:
2707 rtl8168d_4_hw_phy_config(tp);
2708 break;
2709 case RTL_GIGA_MAC_VER_29:
2710 case RTL_GIGA_MAC_VER_30:
2711 rtl8105e_hw_phy_config(tp);
2712 break;
2713 case RTL_GIGA_MAC_VER_31:
2714 /* None. */
2715 break;
2716 case RTL_GIGA_MAC_VER_32:
2717 case RTL_GIGA_MAC_VER_33:
2718 rtl8168e_hw_phy_config(tp);
2703 break; 2719 break;
2704 2720
2705 default: 2721 default:
@@ -2717,12 +2733,9 @@ static void rtl8169_phy_timer(unsigned long __opaque)
2717 2733
2718 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); 2734 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2719 2735
2720 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2721 return;
2722
2723 spin_lock_irq(&tp->lock); 2736 spin_lock_irq(&tp->lock);
2724 2737
2725 if (tp->phy_reset_pending(ioaddr)) { 2738 if (tp->phy_reset_pending(tp)) {
2726 /* 2739 /*
2727 * A busy loop could burn quite a few cycles on nowadays CPU. 2740 * A busy loop could burn quite a few cycles on nowadays CPU.
2728 * Let's delay the execution of the timer for a few ticks. 2741 * Let's delay the execution of the timer for a few ticks.
@@ -2736,7 +2749,7 @@ static void rtl8169_phy_timer(unsigned long __opaque)
2736 2749
2737 netif_warn(tp, link, dev, "PHY reset until link up\n"); 2750 netif_warn(tp, link, dev, "PHY reset until link up\n");
2738 2751
2739 tp->phy_reset_enable(ioaddr); 2752 tp->phy_reset_enable(tp);
2740 2753
2741out_mod_timer: 2754out_mod_timer:
2742 mod_timer(timer, jiffies + timeout); 2755 mod_timer(timer, jiffies + timeout);
@@ -2744,28 +2757,6 @@ out_unlock:
2744 spin_unlock_irq(&tp->lock); 2757 spin_unlock_irq(&tp->lock);
2745} 2758}
2746 2759
2747static inline void rtl8169_delete_timer(struct net_device *dev)
2748{
2749 struct rtl8169_private *tp = netdev_priv(dev);
2750 struct timer_list *timer = &tp->timer;
2751
2752 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2753 return;
2754
2755 del_timer_sync(timer);
2756}
2757
2758static inline void rtl8169_request_timer(struct net_device *dev)
2759{
2760 struct rtl8169_private *tp = netdev_priv(dev);
2761 struct timer_list *timer = &tp->timer;
2762
2763 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2764 return;
2765
2766 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2767}
2768
2769#ifdef CONFIG_NET_POLL_CONTROLLER 2760#ifdef CONFIG_NET_POLL_CONTROLLER
2770/* 2761/*
2771 * Polling 'interrupt' - used by things like netconsole to send skbs 2762 * Polling 'interrupt' - used by things like netconsole to send skbs
@@ -2796,12 +2787,11 @@ static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2796static void rtl8169_phy_reset(struct net_device *dev, 2787static void rtl8169_phy_reset(struct net_device *dev,
2797 struct rtl8169_private *tp) 2788 struct rtl8169_private *tp)
2798{ 2789{
2799 void __iomem *ioaddr = tp->mmio_addr;
2800 unsigned int i; 2790 unsigned int i;
2801 2791
2802 tp->phy_reset_enable(ioaddr); 2792 tp->phy_reset_enable(tp);
2803 for (i = 0; i < 100; i++) { 2793 for (i = 0; i < 100; i++) {
2804 if (!tp->phy_reset_pending(ioaddr)) 2794 if (!tp->phy_reset_pending(tp))
2805 return; 2795 return;
2806 msleep(1); 2796 msleep(1);
2807 } 2797 }
@@ -2828,16 +2818,17 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2828 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 2818 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2829 RTL_W8(0x82, 0x01); 2819 RTL_W8(0x82, 0x01);
2830 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); 2820 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2831 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 2821 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2832 } 2822 }
2833 2823
2834 rtl8169_phy_reset(dev, tp); 2824 rtl8169_phy_reset(dev, tp);
2835 2825
2836 /* 2826 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2837 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet 2827 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2838 * only 8101. Don't panic. 2828 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2839 */ 2829 (tp->mii.supports_gmii ?
2840 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); 2830 ADVERTISED_1000baseT_Half |
2831 ADVERTISED_1000baseT_Full : 0));
2841 2832
2842 if (RTL_R8(PHYstatus) & TBI_Enable) 2833 if (RTL_R8(PHYstatus) & TBI_Enable)
2843 netif_info(tp, link, dev, "TBI auto-negotiating\n"); 2834 netif_info(tp, link, dev, "TBI auto-negotiating\n");
@@ -2890,7 +2881,8 @@ static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2890 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; 2881 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2891} 2882}
2892 2883
2893static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) 2884static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2885 struct mii_ioctl_data *data, int cmd)
2894{ 2886{
2895 switch (cmd) { 2887 switch (cmd) {
2896 case SIOCGMIIPHY: 2888 case SIOCGMIIPHY:
@@ -2898,11 +2890,11 @@ static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *dat
2898 return 0; 2890 return 0;
2899 2891
2900 case SIOCGMIIREG: 2892 case SIOCGMIIREG:
2901 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); 2893 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2902 return 0; 2894 return 0;
2903 2895
2904 case SIOCSMIIREG: 2896 case SIOCSMIIREG:
2905 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); 2897 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2906 return 0; 2898 return 0;
2907 } 2899 }
2908 return -EOPNOTSUPP; 2900 return -EOPNOTSUPP;
@@ -2936,7 +2928,7 @@ static const struct rtl_cfg_info {
2936 .hw_start = rtl_hw_start_8168, 2928 .hw_start = rtl_hw_start_8168,
2937 .region = 2, 2929 .region = 2,
2938 .align = 8, 2930 .align = 8,
2939 .intr_event = SYSErr | RxFIFOOver | LinkChg | RxOverflow | 2931 .intr_event = SYSErr | LinkChg | RxOverflow |
2940 TxErr | TxOK | RxOK | RxErr, 2932 TxErr | TxOK | RxOK | RxErr,
2941 .napi_event = TxErr | TxOK | RxOK | RxOverflow, 2933 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2942 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, 2934 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
@@ -2990,18 +2982,272 @@ static const struct net_device_ops rtl8169_netdev_ops = {
2990 .ndo_tx_timeout = rtl8169_tx_timeout, 2982 .ndo_tx_timeout = rtl8169_tx_timeout,
2991 .ndo_validate_addr = eth_validate_addr, 2983 .ndo_validate_addr = eth_validate_addr,
2992 .ndo_change_mtu = rtl8169_change_mtu, 2984 .ndo_change_mtu = rtl8169_change_mtu,
2985 .ndo_fix_features = rtl8169_fix_features,
2986 .ndo_set_features = rtl8169_set_features,
2993 .ndo_set_mac_address = rtl_set_mac_address, 2987 .ndo_set_mac_address = rtl_set_mac_address,
2994 .ndo_do_ioctl = rtl8169_ioctl, 2988 .ndo_do_ioctl = rtl8169_ioctl,
2995 .ndo_set_multicast_list = rtl_set_rx_mode, 2989 .ndo_set_multicast_list = rtl_set_rx_mode,
2996#ifdef CONFIG_R8169_VLAN
2997 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2998#endif
2999#ifdef CONFIG_NET_POLL_CONTROLLER 2990#ifdef CONFIG_NET_POLL_CONTROLLER
3000 .ndo_poll_controller = rtl8169_netpoll, 2991 .ndo_poll_controller = rtl8169_netpoll,
3001#endif 2992#endif
3002 2993
3003}; 2994};
3004 2995
2996static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2997{
2998 struct mdio_ops *ops = &tp->mdio_ops;
2999
3000 switch (tp->mac_version) {
3001 case RTL_GIGA_MAC_VER_27:
3002 ops->write = r8168dp_1_mdio_write;
3003 ops->read = r8168dp_1_mdio_read;
3004 break;
3005 case RTL_GIGA_MAC_VER_28:
3006 case RTL_GIGA_MAC_VER_31:
3007 ops->write = r8168dp_2_mdio_write;
3008 ops->read = r8168dp_2_mdio_read;
3009 break;
3010 default:
3011 ops->write = r8169_mdio_write;
3012 ops->read = r8169_mdio_read;
3013 break;
3014 }
3015}
3016
3017static void r810x_phy_power_down(struct rtl8169_private *tp)
3018{
3019 rtl_writephy(tp, 0x1f, 0x0000);
3020 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3021}
3022
3023static void r810x_phy_power_up(struct rtl8169_private *tp)
3024{
3025 rtl_writephy(tp, 0x1f, 0x0000);
3026 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3027}
3028
3029static void r810x_pll_power_down(struct rtl8169_private *tp)
3030{
3031 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3032 rtl_writephy(tp, 0x1f, 0x0000);
3033 rtl_writephy(tp, MII_BMCR, 0x0000);
3034 return;
3035 }
3036
3037 r810x_phy_power_down(tp);
3038}
3039
3040static void r810x_pll_power_up(struct rtl8169_private *tp)
3041{
3042 r810x_phy_power_up(tp);
3043}
3044
3045static void r8168_phy_power_up(struct rtl8169_private *tp)
3046{
3047 rtl_writephy(tp, 0x1f, 0x0000);
3048 switch (tp->mac_version) {
3049 case RTL_GIGA_MAC_VER_11:
3050 case RTL_GIGA_MAC_VER_12:
3051 case RTL_GIGA_MAC_VER_17:
3052 case RTL_GIGA_MAC_VER_18:
3053 case RTL_GIGA_MAC_VER_19:
3054 case RTL_GIGA_MAC_VER_20:
3055 case RTL_GIGA_MAC_VER_21:
3056 case RTL_GIGA_MAC_VER_22:
3057 case RTL_GIGA_MAC_VER_23:
3058 case RTL_GIGA_MAC_VER_24:
3059 case RTL_GIGA_MAC_VER_25:
3060 case RTL_GIGA_MAC_VER_26:
3061 case RTL_GIGA_MAC_VER_27:
3062 case RTL_GIGA_MAC_VER_28:
3063 case RTL_GIGA_MAC_VER_31:
3064 rtl_writephy(tp, 0x0e, 0x0000);
3065 break;
3066 default:
3067 break;
3068 }
3069 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3070}
3071
3072static void r8168_phy_power_down(struct rtl8169_private *tp)
3073{
3074 rtl_writephy(tp, 0x1f, 0x0000);
3075 switch (tp->mac_version) {
3076 case RTL_GIGA_MAC_VER_32:
3077 case RTL_GIGA_MAC_VER_33:
3078 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3079 break;
3080
3081 case RTL_GIGA_MAC_VER_11:
3082 case RTL_GIGA_MAC_VER_12:
3083 case RTL_GIGA_MAC_VER_17:
3084 case RTL_GIGA_MAC_VER_18:
3085 case RTL_GIGA_MAC_VER_19:
3086 case RTL_GIGA_MAC_VER_20:
3087 case RTL_GIGA_MAC_VER_21:
3088 case RTL_GIGA_MAC_VER_22:
3089 case RTL_GIGA_MAC_VER_23:
3090 case RTL_GIGA_MAC_VER_24:
3091 case RTL_GIGA_MAC_VER_25:
3092 case RTL_GIGA_MAC_VER_26:
3093 case RTL_GIGA_MAC_VER_27:
3094 case RTL_GIGA_MAC_VER_28:
3095 case RTL_GIGA_MAC_VER_31:
3096 rtl_writephy(tp, 0x0e, 0x0200);
3097 default:
3098 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3099 break;
3100 }
3101}
3102
3103static void r8168_pll_power_down(struct rtl8169_private *tp)
3104{
3105 void __iomem *ioaddr = tp->mmio_addr;
3106
3107 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3108 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3109 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3110 r8168dp_check_dash(tp)) {
3111 return;
3112 }
3113
3114 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3115 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3116 (RTL_R16(CPlusCmd) & ASF)) {
3117 return;
3118 }
3119
3120 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3121 tp->mac_version == RTL_GIGA_MAC_VER_33)
3122 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3123
3124 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3125 rtl_writephy(tp, 0x1f, 0x0000);
3126 rtl_writephy(tp, MII_BMCR, 0x0000);
3127
3128 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3129 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3130 return;
3131 }
3132
3133 r8168_phy_power_down(tp);
3134
3135 switch (tp->mac_version) {
3136 case RTL_GIGA_MAC_VER_25:
3137 case RTL_GIGA_MAC_VER_26:
3138 case RTL_GIGA_MAC_VER_27:
3139 case RTL_GIGA_MAC_VER_28:
3140 case RTL_GIGA_MAC_VER_31:
3141 case RTL_GIGA_MAC_VER_32:
3142 case RTL_GIGA_MAC_VER_33:
3143 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3144 break;
3145 }
3146}
3147
3148static void r8168_pll_power_up(struct rtl8169_private *tp)
3149{
3150 void __iomem *ioaddr = tp->mmio_addr;
3151
3152 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3153 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3154 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3155 r8168dp_check_dash(tp)) {
3156 return;
3157 }
3158
3159 switch (tp->mac_version) {
3160 case RTL_GIGA_MAC_VER_25:
3161 case RTL_GIGA_MAC_VER_26:
3162 case RTL_GIGA_MAC_VER_27:
3163 case RTL_GIGA_MAC_VER_28:
3164 case RTL_GIGA_MAC_VER_31:
3165 case RTL_GIGA_MAC_VER_32:
3166 case RTL_GIGA_MAC_VER_33:
3167 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3168 break;
3169 }
3170
3171 r8168_phy_power_up(tp);
3172}
3173
3174static void rtl_pll_power_op(struct rtl8169_private *tp,
3175 void (*op)(struct rtl8169_private *))
3176{
3177 if (op)
3178 op(tp);
3179}
3180
3181static void rtl_pll_power_down(struct rtl8169_private *tp)
3182{
3183 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3184}
3185
3186static void rtl_pll_power_up(struct rtl8169_private *tp)
3187{
3188 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3189}
3190
3191static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3192{
3193 struct pll_power_ops *ops = &tp->pll_power_ops;
3194
3195 switch (tp->mac_version) {
3196 case RTL_GIGA_MAC_VER_07:
3197 case RTL_GIGA_MAC_VER_08:
3198 case RTL_GIGA_MAC_VER_09:
3199 case RTL_GIGA_MAC_VER_10:
3200 case RTL_GIGA_MAC_VER_16:
3201 case RTL_GIGA_MAC_VER_29:
3202 case RTL_GIGA_MAC_VER_30:
3203 ops->down = r810x_pll_power_down;
3204 ops->up = r810x_pll_power_up;
3205 break;
3206
3207 case RTL_GIGA_MAC_VER_11:
3208 case RTL_GIGA_MAC_VER_12:
3209 case RTL_GIGA_MAC_VER_17:
3210 case RTL_GIGA_MAC_VER_18:
3211 case RTL_GIGA_MAC_VER_19:
3212 case RTL_GIGA_MAC_VER_20:
3213 case RTL_GIGA_MAC_VER_21:
3214 case RTL_GIGA_MAC_VER_22:
3215 case RTL_GIGA_MAC_VER_23:
3216 case RTL_GIGA_MAC_VER_24:
3217 case RTL_GIGA_MAC_VER_25:
3218 case RTL_GIGA_MAC_VER_26:
3219 case RTL_GIGA_MAC_VER_27:
3220 case RTL_GIGA_MAC_VER_28:
3221 case RTL_GIGA_MAC_VER_31:
3222 case RTL_GIGA_MAC_VER_32:
3223 case RTL_GIGA_MAC_VER_33:
3224 ops->down = r8168_pll_power_down;
3225 ops->up = r8168_pll_power_up;
3226 break;
3227
3228 default:
3229 ops->down = NULL;
3230 ops->up = NULL;
3231 break;
3232 }
3233}
3234
3235static void rtl_hw_reset(struct rtl8169_private *tp)
3236{
3237 void __iomem *ioaddr = tp->mmio_addr;
3238 int i;
3239
3240 /* Soft reset the chip. */
3241 RTL_W8(ChipCmd, CmdReset);
3242
3243 /* Check that the chip has finished the reset. */
3244 for (i = 0; i < 100; i++) {
3245 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3246 break;
3247 msleep_interruptible(1);
3248 }
3249}
3250
3005static int __devinit 3251static int __devinit
3006rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 3252rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3007{ 3253{
@@ -3011,7 +3257,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3011 struct mii_if_info *mii; 3257 struct mii_if_info *mii;
3012 struct net_device *dev; 3258 struct net_device *dev;
3013 void __iomem *ioaddr; 3259 void __iomem *ioaddr;
3014 unsigned int i; 3260 int chipset, i;
3015 int rc; 3261 int rc;
3016 3262
3017 if (netif_msg_drv(&debug)) { 3263 if (netif_msg_drv(&debug)) {
@@ -3042,6 +3288,11 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3042 mii->reg_num_mask = 0x1f; 3288 mii->reg_num_mask = 0x1f;
3043 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); 3289 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3044 3290
3291 /* disable ASPM completely as that cause random device stop working
3292 * problems as well as full system hangs for some PCIe devices users */
3293 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3294 PCIE_LINK_STATE_CLKPM);
3295
3045 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 3296 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3046 rc = pci_enable_device(pdev); 3297 rc = pci_enable_device(pdev);
3047 if (rc < 0) { 3298 if (rc < 0) {
@@ -3075,7 +3326,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3075 goto err_out_mwi_2; 3326 goto err_out_mwi_2;
3076 } 3327 }
3077 3328
3078 tp->cp_cmd = PCIMulRW | RxChkSum; 3329 tp->cp_cmd = RxChkSum;
3079 3330
3080 if ((sizeof(dma_addr_t) > 4) && 3331 if ((sizeof(dma_addr_t) > 4) &&
3081 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { 3332 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
@@ -3096,6 +3347,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3096 rc = -EIO; 3347 rc = -EIO;
3097 goto err_out_free_res_3; 3348 goto err_out_free_res_3;
3098 } 3349 }
3350 tp->mmio_addr = ioaddr;
3099 3351
3100 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); 3352 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3101 if (!tp->pcie_cap) 3353 if (!tp->pcie_cap)
@@ -3103,42 +3355,29 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3103 3355
3104 RTL_W16(IntrMask, 0x0000); 3356 RTL_W16(IntrMask, 0x0000);
3105 3357
3106 /* Soft reset the chip. */ 3358 rtl_hw_reset(tp);
3107 RTL_W8(ChipCmd, CmdReset);
3108
3109 /* Check that the chip has finished the reset. */
3110 for (i = 0; i < 100; i++) {
3111 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3112 break;
3113 msleep_interruptible(1);
3114 }
3115 3359
3116 RTL_W16(IntrStatus, 0xffff); 3360 RTL_W16(IntrStatus, 0xffff);
3117 3361
3118 pci_set_master(pdev); 3362 pci_set_master(pdev);
3119 3363
3120 /* Identify chip attached to board */ 3364 /* Identify chip attached to board */
3121 rtl8169_get_mac_version(tp, ioaddr); 3365 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3122 3366
3123 /* Use appropriate default if unknown */ 3367 /*
3124 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 3368 * Pretend we are using VLANs; This bypasses a nasty bug where
3125 netif_notice(tp, probe, dev, 3369 * Interrupts stop flowing on high load on 8110SCd controllers.
3126 "unknown MAC, using family default\n"); 3370 */
3127 tp->mac_version = cfg->default_ver; 3371 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3128 } 3372 tp->cp_cmd |= RxVlan;
3373
3374 rtl_init_mdio_ops(tp);
3375 rtl_init_pll_power_ops(tp);
3129 3376
3130 rtl8169_print_mac_version(tp); 3377 rtl8169_print_mac_version(tp);
3131 3378
3132 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { 3379 chipset = tp->mac_version;
3133 if (tp->mac_version == rtl_chip_info[i].mac_version) 3380 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3134 break;
3135 }
3136 if (i == ARRAY_SIZE(rtl_chip_info)) {
3137 dev_err(&pdev->dev,
3138 "driver bug, MAC version not found in rtl_chip_info\n");
3139 goto err_out_msi_4;
3140 }
3141 tp->chipset = i;
3142 3381
3143 RTL_W8(Cfg9346, Cfg9346_Unlock); 3382 RTL_W8(Cfg9346, Cfg9346_Unlock);
3144 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); 3383 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
@@ -3158,8 +3397,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3158 tp->phy_reset_pending = rtl8169_tbi_reset_pending; 3397 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3159 tp->link_ok = rtl8169_tbi_link_ok; 3398 tp->link_ok = rtl8169_tbi_link_ok;
3160 tp->do_ioctl = rtl_tbi_ioctl; 3399 tp->do_ioctl = rtl_tbi_ioctl;
3161
3162 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3163 } else { 3400 } else {
3164 tp->set_speed = rtl8169_set_speed_xmii; 3401 tp->set_speed = rtl8169_set_speed_xmii;
3165 tp->get_settings = rtl8169_gset_xmii; 3402 tp->get_settings = rtl8169_gset_xmii;
@@ -3171,8 +3408,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3171 3408
3172 spin_lock_init(&tp->lock); 3409 spin_lock_init(&tp->lock);
3173 3410
3174 tp->mmio_addr = ioaddr;
3175
3176 /* Get MAC address */ 3411 /* Get MAC address */
3177 for (i = 0; i < MAC_ADDR_LEN; i++) 3412 for (i = 0; i < MAC_ADDR_LEN; i++)
3178 dev->dev_addr[i] = RTL_R8(MAC0 + i); 3413 dev->dev_addr[i] = RTL_R8(MAC0 + i);
@@ -3185,12 +3420,21 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3185 3420
3186 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); 3421 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3187 3422
3188#ifdef CONFIG_R8169_VLAN 3423 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3189 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 3424 * properly for all devices */
3190#endif 3425 dev->features |= NETIF_F_RXCSUM |
3426 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3427
3428 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3429 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3430 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3431 NETIF_F_HIGHDMA;
3432
3433 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3434 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3435 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3191 3436
3192 tp->intr_mask = 0xffff; 3437 tp->intr_mask = 0xffff;
3193 tp->align = cfg->align;
3194 tp->hw_start = cfg->hw_start; 3438 tp->hw_start = cfg->hw_start;
3195 tp->intr_event = cfg->intr_event; 3439 tp->intr_event = cfg->intr_event;
3196 tp->napi_event = cfg->napi_event; 3440 tp->napi_event = cfg->napi_event;
@@ -3199,6 +3443,8 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3199 tp->timer.data = (unsigned long) dev; 3443 tp->timer.data = (unsigned long) dev;
3200 tp->timer.function = rtl8169_phy_timer; 3444 tp->timer.function = rtl8169_phy_timer;
3201 3445
3446 tp->fw = RTL_FIRMWARE_UNKNOWN;
3447
3202 rc = register_netdev(dev); 3448 rc = register_netdev(dev);
3203 if (rc < 0) 3449 if (rc < 0)
3204 goto err_out_msi_4; 3450 goto err_out_msi_4;
@@ -3206,24 +3452,22 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3206 pci_set_drvdata(pdev, dev); 3452 pci_set_drvdata(pdev, dev);
3207 3453
3208 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", 3454 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3209 rtl_chip_info[tp->chipset].name, 3455 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3210 dev->base_addr, dev->dev_addr,
3211 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); 3456 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3212 3457
3213 rtl8169_init_phy(dev, tp); 3458 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3214 3459 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3215 /* 3460 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3216 * Pretend we are using VLANs; This bypasses a nasty bug where 3461 rtl8168_driver_start(tp);
3217 * Interrupts stop flowing on high load on 8110SCd controllers. 3462 }
3218 */
3219 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3220 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3221 3463
3222 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); 3464 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3223 3465
3224 if (pci_dev_run_wake(pdev)) 3466 if (pci_dev_run_wake(pdev))
3225 pm_runtime_put_noidle(&pdev->dev); 3467 pm_runtime_put_noidle(&pdev->dev);
3226 3468
3469 netif_carrier_off(dev);
3470
3227out: 3471out:
3228 return rc; 3472 return rc;
3229 3473
@@ -3245,10 +3489,18 @@ static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3245 struct net_device *dev = pci_get_drvdata(pdev); 3489 struct net_device *dev = pci_get_drvdata(pdev);
3246 struct rtl8169_private *tp = netdev_priv(dev); 3490 struct rtl8169_private *tp = netdev_priv(dev);
3247 3491
3248 flush_scheduled_work(); 3492 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3493 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3494 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3495 rtl8168_driver_stop(tp);
3496 }
3497
3498 cancel_delayed_work_sync(&tp->task);
3249 3499
3250 unregister_netdev(dev); 3500 unregister_netdev(dev);
3251 3501
3502 rtl_release_firmware(tp);
3503
3252 if (pci_dev_run_wake(pdev)) 3504 if (pci_dev_run_wake(pdev))
3253 pm_runtime_get_noresume(&pdev->dev); 3505 pm_runtime_get_noresume(&pdev->dev);
3254 3506
@@ -3260,39 +3512,37 @@ static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3260 pci_set_drvdata(pdev, NULL); 3512 pci_set_drvdata(pdev, NULL);
3261} 3513}
3262 3514
3263static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, 3515static void rtl_request_firmware(struct rtl8169_private *tp)
3264 unsigned int mtu)
3265{ 3516{
3266 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3517 /* Return early if the firmware is already loaded / cached. */
3518 if (IS_ERR(tp->fw)) {
3519 const char *name;
3520
3521 name = rtl_lookup_firmware_name(tp);
3522 if (name) {
3523 int rc;
3267 3524
3268 if (max_frame != 16383) 3525 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3269 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this " 3526 if (rc >= 0)
3270 "NIC may lead to frame reception errors!\n"); 3527 return;
3271 3528
3272 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE; 3529 netif_warn(tp, ifup, tp->dev, "unable to load "
3530 "firmware patch %s (%d)\n", name, rc);
3531 }
3532 tp->fw = NULL;
3533 }
3273} 3534}
3274 3535
3275static int rtl8169_open(struct net_device *dev) 3536static int rtl8169_open(struct net_device *dev)
3276{ 3537{
3277 struct rtl8169_private *tp = netdev_priv(dev); 3538 struct rtl8169_private *tp = netdev_priv(dev);
3539 void __iomem *ioaddr = tp->mmio_addr;
3278 struct pci_dev *pdev = tp->pci_dev; 3540 struct pci_dev *pdev = tp->pci_dev;
3279 int retval = -ENOMEM; 3541 int retval = -ENOMEM;
3280 3542
3281 pm_runtime_get_sync(&pdev->dev); 3543 pm_runtime_get_sync(&pdev->dev);
3282 3544
3283 /* 3545 /*
3284 * Note that we use a magic value here, its wierd I know
3285 * its done because, some subset of rtl8169 hardware suffers from
3286 * a problem in which frames received that are longer than
3287 * the size set in RxMaxSize register return garbage sizes
3288 * when received. To avoid this we need to turn off filtering,
3289 * which is done by setting a value of 16383 in the RxMaxSize register
3290 * and allocating 16k frames to handle the largest possible rx value
3291 * thats what the magic math below does.
3292 */
3293 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3294
3295 /*
3296 * Rx and Tx desscriptors needs 256 bytes alignment. 3546 * Rx and Tx desscriptors needs 256 bytes alignment.
3297 * dma_alloc_coherent provides more. 3547 * dma_alloc_coherent provides more.
3298 */ 3548 */
@@ -3314,26 +3564,33 @@ static int rtl8169_open(struct net_device *dev)
3314 3564
3315 smp_mb(); 3565 smp_mb();
3316 3566
3567 rtl_request_firmware(tp);
3568
3317 retval = request_irq(dev->irq, rtl8169_interrupt, 3569 retval = request_irq(dev->irq, rtl8169_interrupt,
3318 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, 3570 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3319 dev->name, dev); 3571 dev->name, dev);
3320 if (retval < 0) 3572 if (retval < 0)
3321 goto err_release_ring_2; 3573 goto err_release_fw_2;
3322 3574
3323 napi_enable(&tp->napi); 3575 napi_enable(&tp->napi);
3324 3576
3325 rtl_hw_start(dev); 3577 rtl8169_init_phy(dev, tp);
3578
3579 rtl8169_set_features(dev, dev->features);
3326 3580
3327 rtl8169_request_timer(dev); 3581 rtl_pll_power_up(tp);
3582
3583 rtl_hw_start(dev);
3328 3584
3329 tp->saved_wolopts = 0; 3585 tp->saved_wolopts = 0;
3330 pm_runtime_put_noidle(&pdev->dev); 3586 pm_runtime_put_noidle(&pdev->dev);
3331 3587
3332 rtl8169_check_link_status(dev, tp, tp->mmio_addr); 3588 rtl8169_check_link_status(dev, tp, ioaddr);
3333out: 3589out:
3334 return retval; 3590 return retval;
3335 3591
3336err_release_ring_2: 3592err_release_fw_2:
3593 rtl_release_firmware(tp);
3337 rtl8169_rx_clear(tp); 3594 rtl8169_rx_clear(tp);
3338err_free_rx_1: 3595err_free_rx_1:
3339 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 3596 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
@@ -3348,11 +3605,21 @@ err_pm_runtime_put:
3348 goto out; 3605 goto out;
3349} 3606}
3350 3607
3351static void rtl8169_hw_reset(void __iomem *ioaddr) 3608static void rtl8169_hw_reset(struct rtl8169_private *tp)
3352{ 3609{
3610 void __iomem *ioaddr = tp->mmio_addr;
3611
3353 /* Disable interrupts */ 3612 /* Disable interrupts */
3354 rtl8169_irq_mask_and_ack(ioaddr); 3613 rtl8169_irq_mask_and_ack(ioaddr);
3355 3614
3615 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3616 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3617 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3618 while (RTL_R8(TxPoll) & NPQ)
3619 udelay(20);
3620
3621 }
3622
3356 /* Reset the chipset */ 3623 /* Reset the chipset */
3357 RTL_W8(ChipCmd, CmdReset); 3624 RTL_W8(ChipCmd, CmdReset);
3358 3625
@@ -3365,7 +3632,7 @@ static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3365 void __iomem *ioaddr = tp->mmio_addr; 3632 void __iomem *ioaddr = tp->mmio_addr;
3366 u32 cfg = rtl8169_rx_config; 3633 u32 cfg = rtl8169_rx_config;
3367 3634
3368 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 3635 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3369 RTL_W32(RxConfig, cfg); 3636 RTL_W32(RxConfig, cfg);
3370 3637
3371 /* Set DMA burst size and Interframe Gap Time */ 3638 /* Set DMA burst size and Interframe Gap Time */
@@ -3376,25 +3643,14 @@ static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3376static void rtl_hw_start(struct net_device *dev) 3643static void rtl_hw_start(struct net_device *dev)
3377{ 3644{
3378 struct rtl8169_private *tp = netdev_priv(dev); 3645 struct rtl8169_private *tp = netdev_priv(dev);
3379 void __iomem *ioaddr = tp->mmio_addr;
3380 unsigned int i;
3381 3646
3382 /* Soft reset the chip. */ 3647 rtl_hw_reset(tp);
3383 RTL_W8(ChipCmd, CmdReset);
3384
3385 /* Check that the chip has finished the reset. */
3386 for (i = 0; i < 100; i++) {
3387 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3388 break;
3389 msleep_interruptible(1);
3390 }
3391 3648
3392 tp->hw_start(dev); 3649 tp->hw_start(dev);
3393 3650
3394 netif_start_queue(dev); 3651 netif_start_queue(dev);
3395} 3652}
3396 3653
3397
3398static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, 3654static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3399 void __iomem *ioaddr) 3655 void __iomem *ioaddr)
3400{ 3656{
@@ -3426,7 +3682,7 @@ static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3426 3682
3427static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) 3683static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3428{ 3684{
3429 static const struct { 3685 static const struct rtl_cfg2_info {
3430 u32 mac_version; 3686 u32 mac_version;
3431 u32 clk; 3687 u32 clk;
3432 u32 val; 3688 u32 val;
@@ -3435,7 +3691,8 @@ static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3435 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, 3691 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3436 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe 3692 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3437 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } 3693 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3438 }, *p = cfg2_info; 3694 };
3695 const struct rtl_cfg2_info *p = cfg2_info;
3439 unsigned int i; 3696 unsigned int i;
3440 u32 clk; 3697 u32 clk;
3441 3698
@@ -3460,26 +3717,26 @@ static void rtl_hw_start_8169(struct net_device *dev)
3460 } 3717 }
3461 3718
3462 RTL_W8(Cfg9346, Cfg9346_Unlock); 3719 RTL_W8(Cfg9346, Cfg9346_Unlock);
3463 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || 3720 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3464 (tp->mac_version == RTL_GIGA_MAC_VER_02) || 3721 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3465 (tp->mac_version == RTL_GIGA_MAC_VER_03) || 3722 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3466 (tp->mac_version == RTL_GIGA_MAC_VER_04)) 3723 tp->mac_version == RTL_GIGA_MAC_VER_04)
3467 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 3724 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3468 3725
3469 RTL_W8(EarlyTxThres, EarlyTxThld); 3726 RTL_W8(EarlyTxThres, NoEarlyTx);
3470 3727
3471 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); 3728 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3472 3729
3473 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || 3730 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3474 (tp->mac_version == RTL_GIGA_MAC_VER_02) || 3731 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3475 (tp->mac_version == RTL_GIGA_MAC_VER_03) || 3732 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3476 (tp->mac_version == RTL_GIGA_MAC_VER_04)) 3733 tp->mac_version == RTL_GIGA_MAC_VER_04)
3477 rtl_set_rx_tx_config_registers(tp); 3734 rtl_set_rx_tx_config_registers(tp);
3478 3735
3479 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; 3736 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3480 3737
3481 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || 3738 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3482 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { 3739 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3483 dprintk("Set MAC Reg C+CR Offset 0xE0. " 3740 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3484 "Bit-3 and bit-14 MUST be 1\n"); 3741 "Bit-3 and bit-14 MUST be 1\n");
3485 tp->cp_cmd |= (1 << 14); 3742 tp->cp_cmd |= (1 << 14);
@@ -3497,10 +3754,10 @@ static void rtl_hw_start_8169(struct net_device *dev)
3497 3754
3498 rtl_set_rx_tx_desc_registers(tp, ioaddr); 3755 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3499 3756
3500 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && 3757 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3501 (tp->mac_version != RTL_GIGA_MAC_VER_02) && 3758 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3502 (tp->mac_version != RTL_GIGA_MAC_VER_03) && 3759 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3503 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { 3760 tp->mac_version != RTL_GIGA_MAC_VER_04) {
3504 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 3761 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3505 rtl_set_rx_tx_config_registers(tp); 3762 rtl_set_rx_tx_config_registers(tp);
3506 } 3763 }
@@ -3536,12 +3793,22 @@ static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3536 } 3793 }
3537} 3794}
3538 3795
3539static void rtl_csi_access_enable(void __iomem *ioaddr) 3796static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3540{ 3797{
3541 u32 csi; 3798 u32 csi;
3542 3799
3543 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; 3800 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3544 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); 3801 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3802}
3803
3804static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3805{
3806 rtl_csi_access_enable(ioaddr, 0x17000000);
3807}
3808
3809static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3810{
3811 rtl_csi_access_enable(ioaddr, 0x27000000);
3545} 3812}
3546 3813
3547struct ephy_info { 3814struct ephy_info {
@@ -3576,6 +3843,21 @@ static void rtl_disable_clock_request(struct pci_dev *pdev)
3576 } 3843 }
3577} 3844}
3578 3845
3846static void rtl_enable_clock_request(struct pci_dev *pdev)
3847{
3848 struct net_device *dev = pci_get_drvdata(pdev);
3849 struct rtl8169_private *tp = netdev_priv(dev);
3850 int cap = tp->pcie_cap;
3851
3852 if (cap) {
3853 u16 ctl;
3854
3855 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3856 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3857 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3858 }
3859}
3860
3579#define R8168_CPCMD_QUIRK_MASK (\ 3861#define R8168_CPCMD_QUIRK_MASK (\
3580 EnableBist | \ 3862 EnableBist | \
3581 Mac_dbgo_oe | \ 3863 Mac_dbgo_oe | \
@@ -3601,7 +3883,7 @@ static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3601{ 3883{
3602 rtl_hw_start_8168bb(ioaddr, pdev); 3884 rtl_hw_start_8168bb(ioaddr, pdev);
3603 3885
3604 RTL_W8(EarlyTxThres, EarlyTxThld); 3886 RTL_W8(MaxTxPacketSize, TxPacketMax);
3605 3887
3606 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); 3888 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3607} 3889}
@@ -3629,7 +3911,7 @@ static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3629 { 0x07, 0, 0x2000 } 3911 { 0x07, 0, 0x2000 }
3630 }; 3912 };
3631 3913
3632 rtl_csi_access_enable(ioaddr); 3914 rtl_csi_access_enable_2(ioaddr);
3633 3915
3634 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); 3916 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3635 3917
@@ -3638,7 +3920,7 @@ static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3638 3920
3639static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) 3921static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3640{ 3922{
3641 rtl_csi_access_enable(ioaddr); 3923 rtl_csi_access_enable_2(ioaddr);
3642 3924
3643 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 3925 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3644 3926
@@ -3649,14 +3931,14 @@ static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3649 3931
3650static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) 3932static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3651{ 3933{
3652 rtl_csi_access_enable(ioaddr); 3934 rtl_csi_access_enable_2(ioaddr);
3653 3935
3654 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 3936 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3655 3937
3656 /* Magic. */ 3938 /* Magic. */
3657 RTL_W8(DBG_REG, 0x20); 3939 RTL_W8(DBG_REG, 0x20);
3658 3940
3659 RTL_W8(EarlyTxThres, EarlyTxThld); 3941 RTL_W8(MaxTxPacketSize, TxPacketMax);
3660 3942
3661 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 3943 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3662 3944
@@ -3671,7 +3953,7 @@ static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3671 { 0x06, 0x0080, 0x0000 } 3953 { 0x06, 0x0080, 0x0000 }
3672 }; 3954 };
3673 3955
3674 rtl_csi_access_enable(ioaddr); 3956 rtl_csi_access_enable_2(ioaddr);
3675 3957
3676 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3958 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3677 3959
@@ -3687,7 +3969,7 @@ static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3687 { 0x03, 0x0400, 0x0220 } 3969 { 0x03, 0x0400, 0x0220 }
3688 }; 3970 };
3689 3971
3690 rtl_csi_access_enable(ioaddr); 3972 rtl_csi_access_enable_2(ioaddr);
3691 3973
3692 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); 3974 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3693 3975
@@ -3701,24 +3983,96 @@ static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3701 3983
3702static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) 3984static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3703{ 3985{
3704 rtl_csi_access_enable(ioaddr); 3986 rtl_csi_access_enable_2(ioaddr);
3705 3987
3706 __rtl_hw_start_8168cp(ioaddr, pdev); 3988 __rtl_hw_start_8168cp(ioaddr, pdev);
3707} 3989}
3708 3990
3709static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) 3991static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3710{ 3992{
3711 rtl_csi_access_enable(ioaddr); 3993 rtl_csi_access_enable_2(ioaddr);
3712 3994
3713 rtl_disable_clock_request(pdev); 3995 rtl_disable_clock_request(pdev);
3714 3996
3715 RTL_W8(EarlyTxThres, EarlyTxThld); 3997 RTL_W8(MaxTxPacketSize, TxPacketMax);
3716 3998
3717 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 3999 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3718 4000
3719 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 4001 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3720} 4002}
3721 4003
4004static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4005{
4006 rtl_csi_access_enable_1(ioaddr);
4007
4008 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4009
4010 RTL_W8(MaxTxPacketSize, TxPacketMax);
4011
4012 rtl_disable_clock_request(pdev);
4013}
4014
4015static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4016{
4017 static const struct ephy_info e_info_8168d_4[] = {
4018 { 0x0b, ~0, 0x48 },
4019 { 0x19, 0x20, 0x50 },
4020 { 0x0c, ~0, 0x20 }
4021 };
4022 int i;
4023
4024 rtl_csi_access_enable_1(ioaddr);
4025
4026 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4027
4028 RTL_W8(MaxTxPacketSize, TxPacketMax);
4029
4030 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4031 const struct ephy_info *e = e_info_8168d_4 + i;
4032 u16 w;
4033
4034 w = rtl_ephy_read(ioaddr, e->offset);
4035 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4036 }
4037
4038 rtl_enable_clock_request(pdev);
4039}
4040
4041static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4042{
4043 static const struct ephy_info e_info_8168e[] = {
4044 { 0x00, 0x0200, 0x0100 },
4045 { 0x00, 0x0000, 0x0004 },
4046 { 0x06, 0x0002, 0x0001 },
4047 { 0x06, 0x0000, 0x0030 },
4048 { 0x07, 0x0000, 0x2000 },
4049 { 0x00, 0x0000, 0x0020 },
4050 { 0x03, 0x5800, 0x2000 },
4051 { 0x03, 0x0000, 0x0001 },
4052 { 0x01, 0x0800, 0x1000 },
4053 { 0x07, 0x0000, 0x4000 },
4054 { 0x1e, 0x0000, 0x2000 },
4055 { 0x19, 0xffff, 0xfe6c },
4056 { 0x0a, 0x0000, 0x0040 }
4057 };
4058
4059 rtl_csi_access_enable_2(ioaddr);
4060
4061 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4062
4063 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4064
4065 RTL_W8(MaxTxPacketSize, TxPacketMax);
4066
4067 rtl_disable_clock_request(pdev);
4068
4069 /* Reset tx FIFO pointer */
4070 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4071 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4072
4073 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4074}
4075
3722static void rtl_hw_start_8168(struct net_device *dev) 4076static void rtl_hw_start_8168(struct net_device *dev)
3723{ 4077{
3724 struct rtl8169_private *tp = netdev_priv(dev); 4078 struct rtl8169_private *tp = netdev_priv(dev);
@@ -3727,9 +4081,9 @@ static void rtl_hw_start_8168(struct net_device *dev)
3727 4081
3728 RTL_W8(Cfg9346, Cfg9346_Unlock); 4082 RTL_W8(Cfg9346, Cfg9346_Unlock);
3729 4083
3730 RTL_W8(EarlyTxThres, EarlyTxThld); 4084 RTL_W8(MaxTxPacketSize, TxPacketMax);
3731 4085
3732 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); 4086 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3733 4087
3734 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; 4088 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3735 4089
@@ -3738,7 +4092,8 @@ static void rtl_hw_start_8168(struct net_device *dev)
3738 RTL_W16(IntrMitigate, 0x5151); 4092 RTL_W16(IntrMitigate, 0x5151);
3739 4093
3740 /* Work around for RxFIFO overflow. */ 4094 /* Work around for RxFIFO overflow. */
3741 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { 4095 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4096 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3742 tp->intr_event |= RxFIFOOver | PCSTimeout; 4097 tp->intr_event |= RxFIFOOver | PCSTimeout;
3743 tp->intr_event &= ~RxOverflow; 4098 tp->intr_event &= ~RxOverflow;
3744 } 4099 }
@@ -3755,51 +4110,64 @@ static void rtl_hw_start_8168(struct net_device *dev)
3755 switch (tp->mac_version) { 4110 switch (tp->mac_version) {
3756 case RTL_GIGA_MAC_VER_11: 4111 case RTL_GIGA_MAC_VER_11:
3757 rtl_hw_start_8168bb(ioaddr, pdev); 4112 rtl_hw_start_8168bb(ioaddr, pdev);
3758 break; 4113 break;
3759 4114
3760 case RTL_GIGA_MAC_VER_12: 4115 case RTL_GIGA_MAC_VER_12:
3761 case RTL_GIGA_MAC_VER_17: 4116 case RTL_GIGA_MAC_VER_17:
3762 rtl_hw_start_8168bef(ioaddr, pdev); 4117 rtl_hw_start_8168bef(ioaddr, pdev);
3763 break; 4118 break;
3764 4119
3765 case RTL_GIGA_MAC_VER_18: 4120 case RTL_GIGA_MAC_VER_18:
3766 rtl_hw_start_8168cp_1(ioaddr, pdev); 4121 rtl_hw_start_8168cp_1(ioaddr, pdev);
3767 break; 4122 break;
3768 4123
3769 case RTL_GIGA_MAC_VER_19: 4124 case RTL_GIGA_MAC_VER_19:
3770 rtl_hw_start_8168c_1(ioaddr, pdev); 4125 rtl_hw_start_8168c_1(ioaddr, pdev);
3771 break; 4126 break;
3772 4127
3773 case RTL_GIGA_MAC_VER_20: 4128 case RTL_GIGA_MAC_VER_20:
3774 rtl_hw_start_8168c_2(ioaddr, pdev); 4129 rtl_hw_start_8168c_2(ioaddr, pdev);
3775 break; 4130 break;
3776 4131
3777 case RTL_GIGA_MAC_VER_21: 4132 case RTL_GIGA_MAC_VER_21:
3778 rtl_hw_start_8168c_3(ioaddr, pdev); 4133 rtl_hw_start_8168c_3(ioaddr, pdev);
3779 break; 4134 break;
3780 4135
3781 case RTL_GIGA_MAC_VER_22: 4136 case RTL_GIGA_MAC_VER_22:
3782 rtl_hw_start_8168c_4(ioaddr, pdev); 4137 rtl_hw_start_8168c_4(ioaddr, pdev);
3783 break; 4138 break;
3784 4139
3785 case RTL_GIGA_MAC_VER_23: 4140 case RTL_GIGA_MAC_VER_23:
3786 rtl_hw_start_8168cp_2(ioaddr, pdev); 4141 rtl_hw_start_8168cp_2(ioaddr, pdev);
3787 break; 4142 break;
3788 4143
3789 case RTL_GIGA_MAC_VER_24: 4144 case RTL_GIGA_MAC_VER_24:
3790 rtl_hw_start_8168cp_3(ioaddr, pdev); 4145 rtl_hw_start_8168cp_3(ioaddr, pdev);
3791 break; 4146 break;
3792 4147
3793 case RTL_GIGA_MAC_VER_25: 4148 case RTL_GIGA_MAC_VER_25:
3794 case RTL_GIGA_MAC_VER_26: 4149 case RTL_GIGA_MAC_VER_26:
3795 case RTL_GIGA_MAC_VER_27: 4150 case RTL_GIGA_MAC_VER_27:
3796 rtl_hw_start_8168d(ioaddr, pdev); 4151 rtl_hw_start_8168d(ioaddr, pdev);
3797 break; 4152 break;
4153
4154 case RTL_GIGA_MAC_VER_28:
4155 rtl_hw_start_8168d_4(ioaddr, pdev);
4156 break;
4157
4158 case RTL_GIGA_MAC_VER_31:
4159 rtl_hw_start_8168dp(ioaddr, pdev);
4160 break;
4161
4162 case RTL_GIGA_MAC_VER_32:
4163 case RTL_GIGA_MAC_VER_33:
4164 rtl_hw_start_8168e(ioaddr, pdev);
4165 break;
3798 4166
3799 default: 4167 default:
3800 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", 4168 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3801 dev->name, tp->mac_version); 4169 dev->name, tp->mac_version);
3802 break; 4170 break;
3803 } 4171 }
3804 4172
3805 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 4173 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
@@ -3820,8 +4188,7 @@ static void rtl_hw_start_8168(struct net_device *dev)
3820 Cxpl_dbg_sel | \ 4188 Cxpl_dbg_sel | \
3821 ASF | \ 4189 ASF | \
3822 PktCntrDisable | \ 4190 PktCntrDisable | \
3823 PCIDAC | \ 4191 Mac_dbgo_sel)
3824 PCIMulRW)
3825 4192
3826static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) 4193static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3827{ 4194{
@@ -3837,7 +4204,7 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3837 }; 4204 };
3838 u8 cfg1; 4205 u8 cfg1;
3839 4206
3840 rtl_csi_access_enable(ioaddr); 4207 rtl_csi_access_enable_2(ioaddr);
3841 4208
3842 RTL_W8(DBG_REG, FIX_NAK_1); 4209 RTL_W8(DBG_REG, FIX_NAK_1);
3843 4210
@@ -3851,21 +4218,17 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3851 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 4218 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3852 RTL_W8(Config1, cfg1 & ~LEDS0); 4219 RTL_W8(Config1, cfg1 & ~LEDS0);
3853 4220
3854 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3855
3856 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); 4221 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3857} 4222}
3858 4223
3859static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) 4224static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3860{ 4225{
3861 rtl_csi_access_enable(ioaddr); 4226 rtl_csi_access_enable_2(ioaddr);
3862 4227
3863 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 4228 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3864 4229
3865 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); 4230 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3866 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 4231 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3867
3868 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3869} 4232}
3870 4233
3871static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) 4234static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
@@ -3875,14 +4238,45 @@ static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3875 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); 4238 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3876} 4239}
3877 4240
4241static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4242{
4243 static const struct ephy_info e_info_8105e_1[] = {
4244 { 0x07, 0, 0x4000 },
4245 { 0x19, 0, 0x0200 },
4246 { 0x19, 0, 0x0020 },
4247 { 0x1e, 0, 0x2000 },
4248 { 0x03, 0, 0x0001 },
4249 { 0x19, 0, 0x0100 },
4250 { 0x19, 0, 0x0004 },
4251 { 0x0a, 0, 0x0020 }
4252 };
4253
4254 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4255 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4256
4257 /* Disable Early Tally Counter */
4258 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4259
4260 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4261 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4262
4263 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4264}
4265
4266static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4267{
4268 rtl_hw_start_8105e_1(ioaddr, pdev);
4269 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4270}
4271
3878static void rtl_hw_start_8101(struct net_device *dev) 4272static void rtl_hw_start_8101(struct net_device *dev)
3879{ 4273{
3880 struct rtl8169_private *tp = netdev_priv(dev); 4274 struct rtl8169_private *tp = netdev_priv(dev);
3881 void __iomem *ioaddr = tp->mmio_addr; 4275 void __iomem *ioaddr = tp->mmio_addr;
3882 struct pci_dev *pdev = tp->pci_dev; 4276 struct pci_dev *pdev = tp->pci_dev;
3883 4277
3884 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || 4278 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
3885 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { 4279 tp->mac_version == RTL_GIGA_MAC_VER_16) {
3886 int cap = tp->pcie_cap; 4280 int cap = tp->pcie_cap;
3887 4281
3888 if (cap) { 4282 if (cap) {
@@ -3891,6 +4285,8 @@ static void rtl_hw_start_8101(struct net_device *dev)
3891 } 4285 }
3892 } 4286 }
3893 4287
4288 RTL_W8(Cfg9346, Cfg9346_Unlock);
4289
3894 switch (tp->mac_version) { 4290 switch (tp->mac_version) {
3895 case RTL_GIGA_MAC_VER_07: 4291 case RTL_GIGA_MAC_VER_07:
3896 rtl_hw_start_8102e_1(ioaddr, pdev); 4292 rtl_hw_start_8102e_1(ioaddr, pdev);
@@ -3903,16 +4299,22 @@ static void rtl_hw_start_8101(struct net_device *dev)
3903 case RTL_GIGA_MAC_VER_09: 4299 case RTL_GIGA_MAC_VER_09:
3904 rtl_hw_start_8102e_2(ioaddr, pdev); 4300 rtl_hw_start_8102e_2(ioaddr, pdev);
3905 break; 4301 break;
3906 }
3907 4302
3908 RTL_W8(Cfg9346, Cfg9346_Unlock); 4303 case RTL_GIGA_MAC_VER_29:
4304 rtl_hw_start_8105e_1(ioaddr, pdev);
4305 break;
4306 case RTL_GIGA_MAC_VER_30:
4307 rtl_hw_start_8105e_2(ioaddr, pdev);
4308 break;
4309 }
3909 4310
3910 RTL_W8(EarlyTxThres, EarlyTxThld); 4311 RTL_W8(Cfg9346, Cfg9346_Lock);
3911 4312
3912 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); 4313 RTL_W8(MaxTxPacketSize, TxPacketMax);
3913 4314
3914 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; 4315 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3915 4316
4317 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
3916 RTL_W16(CPlusCmd, tp->cp_cmd); 4318 RTL_W16(CPlusCmd, tp->cp_cmd);
3917 4319
3918 RTL_W16(IntrMitigate, 0x0000); 4320 RTL_W16(IntrMitigate, 0x0000);
@@ -3922,14 +4324,10 @@ static void rtl_hw_start_8101(struct net_device *dev)
3922 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 4324 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3923 rtl_set_rx_tx_config_registers(tp); 4325 rtl_set_rx_tx_config_registers(tp);
3924 4326
3925 RTL_W8(Cfg9346, Cfg9346_Lock);
3926
3927 RTL_R8(IntrMask); 4327 RTL_R8(IntrMask);
3928 4328
3929 rtl_set_rx_mode(dev); 4329 rtl_set_rx_mode(dev);
3930 4330
3931 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3932
3933 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); 4331 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3934 4332
3935 RTL_W16(IntrMask, tp->intr_event); 4333 RTL_W16(IntrMask, tp->intr_event);
@@ -3937,33 +4335,13 @@ static void rtl_hw_start_8101(struct net_device *dev)
3937 4335
3938static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 4336static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3939{ 4337{
3940 struct rtl8169_private *tp = netdev_priv(dev);
3941 int ret = 0;
3942
3943 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) 4338 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3944 return -EINVAL; 4339 return -EINVAL;
3945 4340
3946 dev->mtu = new_mtu; 4341 dev->mtu = new_mtu;
4342 netdev_update_features(dev);
3947 4343
3948 if (!netif_running(dev)) 4344 return 0;
3949 goto out;
3950
3951 rtl8169_down(dev);
3952
3953 rtl8169_set_rxbufsize(tp, dev->mtu);
3954
3955 ret = rtl8169_init_ring(dev);
3956 if (ret < 0)
3957 goto out;
3958
3959 napi_enable(&tp->napi);
3960
3961 rtl_hw_start(dev);
3962
3963 rtl8169_request_timer(dev);
3964
3965out:
3966 return ret;
3967} 4345}
3968 4346
3969static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 4347static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
@@ -3972,15 +4350,14 @@ static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3972 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 4350 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3973} 4351}
3974 4352
3975static void rtl8169_free_rx_skb(struct rtl8169_private *tp, 4353static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3976 struct sk_buff **sk_buff, struct RxDesc *desc) 4354 void **data_buff, struct RxDesc *desc)
3977{ 4355{
3978 struct pci_dev *pdev = tp->pci_dev; 4356 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4357 DMA_FROM_DEVICE);
3979 4358
3980 dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), tp->rx_buf_sz, 4359 kfree(*data_buff);
3981 PCI_DMA_FROMDEVICE); 4360 *data_buff = NULL;
3982 dev_kfree_skb(*sk_buff);
3983 *sk_buff = NULL;
3984 rtl8169_make_unusable_by_asic(desc); 4361 rtl8169_make_unusable_by_asic(desc);
3985} 4362}
3986 4363
@@ -3999,33 +4376,45 @@ static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3999 rtl8169_mark_to_asic(desc, rx_buf_sz); 4376 rtl8169_mark_to_asic(desc, rx_buf_sz);
4000} 4377}
4001 4378
4002static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, 4379static inline void *rtl8169_align(void *data)
4003 struct net_device *dev,
4004 struct RxDesc *desc, int rx_buf_sz,
4005 unsigned int align, gfp_t gfp)
4006{ 4380{
4007 struct sk_buff *skb; 4381 return (void *)ALIGN((long)data, 16);
4008 dma_addr_t mapping; 4382}
4009 unsigned int pad;
4010 4383
4011 pad = align ? align : NET_IP_ALIGN; 4384static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4385 struct RxDesc *desc)
4386{
4387 void *data;
4388 dma_addr_t mapping;
4389 struct device *d = &tp->pci_dev->dev;
4390 struct net_device *dev = tp->dev;
4391 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4012 4392
4013 skb = __netdev_alloc_skb(dev, rx_buf_sz + pad, gfp); 4393 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4014 if (!skb) 4394 if (!data)
4015 goto err_out; 4395 return NULL;
4016 4396
4017 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); 4397 if (rtl8169_align(data) != data) {
4398 kfree(data);
4399 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4400 if (!data)
4401 return NULL;
4402 }
4018 4403
4019 mapping = dma_map_single(&pdev->dev, skb->data, rx_buf_sz, 4404 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4020 PCI_DMA_FROMDEVICE); 4405 DMA_FROM_DEVICE);
4406 if (unlikely(dma_mapping_error(d, mapping))) {
4407 if (net_ratelimit())
4408 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4409 goto err_out;
4410 }
4021 4411
4022 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); 4412 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4023out: 4413 return data;
4024 return skb;
4025 4414
4026err_out: 4415err_out:
4027 rtl8169_make_unusable_by_asic(desc); 4416 kfree(data);
4028 goto out; 4417 return NULL;
4029} 4418}
4030 4419
4031static void rtl8169_rx_clear(struct rtl8169_private *tp) 4420static void rtl8169_rx_clear(struct rtl8169_private *tp)
@@ -4033,41 +4422,42 @@ static void rtl8169_rx_clear(struct rtl8169_private *tp)
4033 unsigned int i; 4422 unsigned int i;
4034 4423
4035 for (i = 0; i < NUM_RX_DESC; i++) { 4424 for (i = 0; i < NUM_RX_DESC; i++) {
4036 if (tp->Rx_skbuff[i]) { 4425 if (tp->Rx_databuff[i]) {
4037 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, 4426 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4038 tp->RxDescArray + i); 4427 tp->RxDescArray + i);
4039 } 4428 }
4040 } 4429 }
4041} 4430}
4042 4431
4043static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, 4432static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4044 u32 start, u32 end, gfp_t gfp)
4045{ 4433{
4046 u32 cur; 4434 desc->opts1 |= cpu_to_le32(RingEnd);
4435}
4047 4436
4048 for (cur = start; end - cur != 0; cur++) { 4437static int rtl8169_rx_fill(struct rtl8169_private *tp)
4049 struct sk_buff *skb; 4438{
4050 unsigned int i = cur % NUM_RX_DESC; 4439 unsigned int i;
4051 4440
4052 WARN_ON((s32)(end - cur) < 0); 4441 for (i = 0; i < NUM_RX_DESC; i++) {
4442 void *data;
4053 4443
4054 if (tp->Rx_skbuff[i]) 4444 if (tp->Rx_databuff[i])
4055 continue; 4445 continue;
4056 4446
4057 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, 4447 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4058 tp->RxDescArray + i, 4448 if (!data) {
4059 tp->rx_buf_sz, tp->align, gfp); 4449 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4060 if (!skb) 4450 goto err_out;
4061 break; 4451 }
4062 4452 tp->Rx_databuff[i] = data;
4063 tp->Rx_skbuff[i] = skb;
4064 } 4453 }
4065 return cur - start;
4066}
4067 4454
4068static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 4455 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4069{ 4456 return 0;
4070 desc->opts1 |= cpu_to_le32(RingEnd); 4457
4458err_out:
4459 rtl8169_rx_clear(tp);
4460 return -ENOMEM;
4071} 4461}
4072 4462
4073static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 4463static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
@@ -4082,54 +4472,51 @@ static int rtl8169_init_ring(struct net_device *dev)
4082 rtl8169_init_ring_indexes(tp); 4472 rtl8169_init_ring_indexes(tp);
4083 4473
4084 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); 4474 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4085 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); 4475 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4086
4087 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC, GFP_KERNEL) != NUM_RX_DESC)
4088 goto err_out;
4089 4476
4090 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 4477 return rtl8169_rx_fill(tp);
4091
4092 return 0;
4093
4094err_out:
4095 rtl8169_rx_clear(tp);
4096 return -ENOMEM;
4097} 4478}
4098 4479
4099static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, 4480static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4100 struct TxDesc *desc) 4481 struct TxDesc *desc)
4101{ 4482{
4102 unsigned int len = tx_skb->len; 4483 unsigned int len = tx_skb->len;
4103 4484
4104 dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len, 4485 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4105 PCI_DMA_TODEVICE); 4486
4106 desc->opts1 = 0x00; 4487 desc->opts1 = 0x00;
4107 desc->opts2 = 0x00; 4488 desc->opts2 = 0x00;
4108 desc->addr = 0x00; 4489 desc->addr = 0x00;
4109 tx_skb->len = 0; 4490 tx_skb->len = 0;
4110} 4491}
4111 4492
4112static void rtl8169_tx_clear(struct rtl8169_private *tp) 4493static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4494 unsigned int n)
4113{ 4495{
4114 unsigned int i; 4496 unsigned int i;
4115 4497
4116 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { 4498 for (i = 0; i < n; i++) {
4117 unsigned int entry = i % NUM_TX_DESC; 4499 unsigned int entry = (start + i) % NUM_TX_DESC;
4118 struct ring_info *tx_skb = tp->tx_skb + entry; 4500 struct ring_info *tx_skb = tp->tx_skb + entry;
4119 unsigned int len = tx_skb->len; 4501 unsigned int len = tx_skb->len;
4120 4502
4121 if (len) { 4503 if (len) {
4122 struct sk_buff *skb = tx_skb->skb; 4504 struct sk_buff *skb = tx_skb->skb;
4123 4505
4124 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, 4506 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4125 tp->TxDescArray + entry); 4507 tp->TxDescArray + entry);
4126 if (skb) { 4508 if (skb) {
4509 tp->dev->stats.tx_dropped++;
4127 dev_kfree_skb(skb); 4510 dev_kfree_skb(skb);
4128 tx_skb->skb = NULL; 4511 tx_skb->skb = NULL;
4129 } 4512 }
4130 tp->dev->stats.tx_dropped++;
4131 } 4513 }
4132 } 4514 }
4515}
4516
4517static void rtl8169_tx_clear(struct rtl8169_private *tp)
4518{
4519 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4133 tp->cur_tx = tp->dirty_tx = 0; 4520 tp->cur_tx = tp->dirty_tx = 0;
4134} 4521}
4135 4522
@@ -4191,6 +4578,7 @@ static void rtl8169_reset_task(struct work_struct *work)
4191 struct rtl8169_private *tp = 4578 struct rtl8169_private *tp =
4192 container_of(work, struct rtl8169_private, task.work); 4579 container_of(work, struct rtl8169_private, task.work);
4193 struct net_device *dev = tp->dev; 4580 struct net_device *dev = tp->dev;
4581 int i;
4194 4582
4195 rtnl_lock(); 4583 rtnl_lock();
4196 4584
@@ -4199,19 +4587,15 @@ static void rtl8169_reset_task(struct work_struct *work)
4199 4587
4200 rtl8169_wait_for_quiescence(dev); 4588 rtl8169_wait_for_quiescence(dev);
4201 4589
4202 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); 4590 for (i = 0; i < NUM_RX_DESC; i++)
4591 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4592
4203 rtl8169_tx_clear(tp); 4593 rtl8169_tx_clear(tp);
4204 4594
4205 if (tp->dirty_rx == tp->cur_rx) { 4595 rtl8169_init_ring_indexes(tp);
4206 rtl8169_init_ring_indexes(tp); 4596 rtl_hw_start(dev);
4207 rtl_hw_start(dev); 4597 netif_wake_queue(dev);
4208 netif_wake_queue(dev); 4598 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4209 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4210 } else {
4211 if (net_ratelimit())
4212 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4213 rtl8169_schedule_work(dev, rtl8169_reset_task);
4214 }
4215 4599
4216out_unlock: 4600out_unlock:
4217 rtnl_unlock(); 4601 rtnl_unlock();
@@ -4221,18 +4605,19 @@ static void rtl8169_tx_timeout(struct net_device *dev)
4221{ 4605{
4222 struct rtl8169_private *tp = netdev_priv(dev); 4606 struct rtl8169_private *tp = netdev_priv(dev);
4223 4607
4224 rtl8169_hw_reset(tp->mmio_addr); 4608 rtl8169_hw_reset(tp);
4225 4609
4226 /* Let's wait a bit while any (async) irq lands on */ 4610 /* Let's wait a bit while any (async) irq lands on */
4227 rtl8169_schedule_work(dev, rtl8169_reset_task); 4611 rtl8169_schedule_work(dev, rtl8169_reset_task);
4228} 4612}
4229 4613
4230static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4614static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4231 u32 opts1) 4615 u32 *opts)
4232{ 4616{
4233 struct skb_shared_info *info = skb_shinfo(skb); 4617 struct skb_shared_info *info = skb_shinfo(skb);
4234 unsigned int cur_frag, entry; 4618 unsigned int cur_frag, entry;
4235 struct TxDesc * uninitialized_var(txd); 4619 struct TxDesc * uninitialized_var(txd);
4620 struct device *d = &tp->pci_dev->dev;
4236 4621
4237 entry = tp->cur_tx; 4622 entry = tp->cur_tx;
4238 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4623 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
@@ -4246,13 +4631,20 @@ static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4246 txd = tp->TxDescArray + entry; 4631 txd = tp->TxDescArray + entry;
4247 len = frag->size; 4632 len = frag->size;
4248 addr = ((void *) page_address(frag->page)) + frag->page_offset; 4633 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4249 mapping = dma_map_single(&tp->pci_dev->dev, addr, len, 4634 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4250 PCI_DMA_TODEVICE); 4635 if (unlikely(dma_mapping_error(d, mapping))) {
4636 if (net_ratelimit())
4637 netif_err(tp, drv, tp->dev,
4638 "Failed to map TX fragments DMA!\n");
4639 goto err_out;
4640 }
4251 4641
4252 /* anti gcc 2.95.3 bugware (sic) */ 4642 /* Anti gcc 2.95.3 bugware (sic) */
4253 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); 4643 status = opts[0] | len |
4644 (RingEnd * !((entry + 1) % NUM_TX_DESC));
4254 4645
4255 txd->opts1 = cpu_to_le32(status); 4646 txd->opts1 = cpu_to_le32(status);
4647 txd->opts2 = cpu_to_le32(opts[1]);
4256 txd->addr = cpu_to_le64(mapping); 4648 txd->addr = cpu_to_le64(mapping);
4257 4649
4258 tp->tx_skb[entry].len = len; 4650 tp->tx_skb[entry].len = len;
@@ -4264,77 +4656,94 @@ static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4264 } 4656 }
4265 4657
4266 return cur_frag; 4658 return cur_frag;
4659
4660err_out:
4661 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4662 return -EIO;
4267} 4663}
4268 4664
4269static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) 4665static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4666 struct sk_buff *skb, u32 *opts)
4270{ 4667{
4271 if (dev->features & NETIF_F_TSO) { 4668 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4272 u32 mss = skb_shinfo(skb)->gso_size; 4669 u32 mss = skb_shinfo(skb)->gso_size;
4670 int offset = info->opts_offset;
4273 4671
4274 if (mss) 4672 if (mss) {
4275 return LargeSend | ((mss & MSSMask) << MSSShift); 4673 opts[0] |= TD_LSO;
4276 } 4674 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4277 if (skb->ip_summed == CHECKSUM_PARTIAL) { 4675 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4278 const struct iphdr *ip = ip_hdr(skb); 4676 const struct iphdr *ip = ip_hdr(skb);
4279 4677
4280 if (ip->protocol == IPPROTO_TCP) 4678 if (ip->protocol == IPPROTO_TCP)
4281 return IPCS | TCPCS; 4679 opts[offset] |= info->checksum.tcp;
4282 else if (ip->protocol == IPPROTO_UDP) 4680 else if (ip->protocol == IPPROTO_UDP)
4283 return IPCS | UDPCS; 4681 opts[offset] |= info->checksum.udp;
4284 WARN_ON(1); /* we need a WARN() */ 4682 else
4683 WARN_ON_ONCE(1);
4285 } 4684 }
4286 return 0;
4287} 4685}
4288 4686
4289static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4687static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4290 struct net_device *dev) 4688 struct net_device *dev)
4291{ 4689{
4292 struct rtl8169_private *tp = netdev_priv(dev); 4690 struct rtl8169_private *tp = netdev_priv(dev);
4293 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; 4691 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4294 struct TxDesc *txd = tp->TxDescArray + entry; 4692 struct TxDesc *txd = tp->TxDescArray + entry;
4295 void __iomem *ioaddr = tp->mmio_addr; 4693 void __iomem *ioaddr = tp->mmio_addr;
4694 struct device *d = &tp->pci_dev->dev;
4296 dma_addr_t mapping; 4695 dma_addr_t mapping;
4297 u32 status, len; 4696 u32 status, len;
4298 u32 opts1; 4697 u32 opts[2];
4698 int frags;
4299 4699
4300 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { 4700 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4301 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 4701 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4302 goto err_stop; 4702 goto err_stop_0;
4303 } 4703 }
4304 4704
4305 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 4705 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4306 goto err_stop; 4706 goto err_stop_0;
4307 4707
4308 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); 4708 len = skb_headlen(skb);
4309 4709 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4310 frags = rtl8169_xmit_frags(tp, skb, opts1); 4710 if (unlikely(dma_mapping_error(d, mapping))) {
4311 if (frags) { 4711 if (net_ratelimit())
4312 len = skb_headlen(skb); 4712 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4313 opts1 |= FirstFrag; 4713 goto err_dma_0;
4314 } else {
4315 len = skb->len;
4316 opts1 |= FirstFrag | LastFrag;
4317 tp->tx_skb[entry].skb = skb;
4318 } 4714 }
4319 4715
4320 mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len,
4321 PCI_DMA_TODEVICE);
4322
4323 tp->tx_skb[entry].len = len; 4716 tp->tx_skb[entry].len = len;
4324 txd->addr = cpu_to_le64(mapping); 4717 txd->addr = cpu_to_le64(mapping);
4325 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); 4718
4719 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4720 opts[0] = DescOwn;
4721
4722 rtl8169_tso_csum(tp, skb, opts);
4723
4724 frags = rtl8169_xmit_frags(tp, skb, opts);
4725 if (frags < 0)
4726 goto err_dma_1;
4727 else if (frags)
4728 opts[0] |= FirstFrag;
4729 else {
4730 opts[0] |= FirstFrag | LastFrag;
4731 tp->tx_skb[entry].skb = skb;
4732 }
4733
4734 txd->opts2 = cpu_to_le32(opts[1]);
4326 4735
4327 wmb(); 4736 wmb();
4328 4737
4329 /* anti gcc 2.95.3 bugware (sic) */ 4738 /* Anti gcc 2.95.3 bugware (sic) */
4330 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); 4739 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4331 txd->opts1 = cpu_to_le32(status); 4740 txd->opts1 = cpu_to_le32(status);
4332 4741
4333 tp->cur_tx += frags + 1; 4742 tp->cur_tx += frags + 1;
4334 4743
4335 wmb(); 4744 wmb();
4336 4745
4337 RTL_W8(TxPoll, NPQ); /* set polling bit */ 4746 RTL_W8(TxPoll, NPQ);
4338 4747
4339 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { 4748 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4340 netif_stop_queue(dev); 4749 netif_stop_queue(dev);
@@ -4345,7 +4754,14 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4345 4754
4346 return NETDEV_TX_OK; 4755 return NETDEV_TX_OK;
4347 4756
4348err_stop: 4757err_dma_1:
4758 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4759err_dma_0:
4760 dev_kfree_skb(skb);
4761 dev->stats.tx_dropped++;
4762 return NETDEV_TX_OK;
4763
4764err_stop_0:
4349 netif_stop_queue(dev); 4765 netif_stop_queue(dev);
4350 dev->stats.tx_dropped++; 4766 dev->stats.tx_dropped++;
4351 return NETDEV_TX_BUSY; 4767 return NETDEV_TX_BUSY;
@@ -4355,7 +4771,6 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
4355{ 4771{
4356 struct rtl8169_private *tp = netdev_priv(dev); 4772 struct rtl8169_private *tp = netdev_priv(dev);
4357 struct pci_dev *pdev = tp->pci_dev; 4773 struct pci_dev *pdev = tp->pci_dev;
4358 void __iomem *ioaddr = tp->mmio_addr;
4359 u16 pci_status, pci_cmd; 4774 u16 pci_status, pci_cmd;
4360 4775
4361 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4776 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
@@ -4386,13 +4801,15 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
4386 4801
4387 /* The infamous DAC f*ckup only happens at boot time */ 4802 /* The infamous DAC f*ckup only happens at boot time */
4388 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { 4803 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4804 void __iomem *ioaddr = tp->mmio_addr;
4805
4389 netif_info(tp, intr, dev, "disabling PCI DAC\n"); 4806 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4390 tp->cp_cmd &= ~PCIDAC; 4807 tp->cp_cmd &= ~PCIDAC;
4391 RTL_W16(CPlusCmd, tp->cp_cmd); 4808 RTL_W16(CPlusCmd, tp->cp_cmd);
4392 dev->features &= ~NETIF_F_HIGHDMA; 4809 dev->features &= ~NETIF_F_HIGHDMA;
4393 } 4810 }
4394 4811
4395 rtl8169_hw_reset(ioaddr); 4812 rtl8169_hw_reset(tp);
4396 4813
4397 rtl8169_schedule_work(dev, rtl8169_reinit_task); 4814 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4398} 4815}
@@ -4410,7 +4827,6 @@ static void rtl8169_tx_interrupt(struct net_device *dev,
4410 while (tx_left > 0) { 4827 while (tx_left > 0) {
4411 unsigned int entry = dirty_tx % NUM_TX_DESC; 4828 unsigned int entry = dirty_tx % NUM_TX_DESC;
4412 struct ring_info *tx_skb = tp->tx_skb + entry; 4829 struct ring_info *tx_skb = tp->tx_skb + entry;
4413 u32 len = tx_skb->len;
4414 u32 status; 4830 u32 status;
4415 4831
4416 rmb(); 4832 rmb();
@@ -4418,12 +4834,11 @@ static void rtl8169_tx_interrupt(struct net_device *dev,
4418 if (status & DescOwn) 4834 if (status & DescOwn)
4419 break; 4835 break;
4420 4836
4421 dev->stats.tx_bytes += len; 4837 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4422 dev->stats.tx_packets++; 4838 tp->TxDescArray + entry);
4423
4424 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4425
4426 if (status & LastFrag) { 4839 if (status & LastFrag) {
4840 dev->stats.tx_packets++;
4841 dev->stats.tx_bytes += tx_skb->skb->len;
4427 dev_kfree_skb(tx_skb->skb); 4842 dev_kfree_skb(tx_skb->skb);
4428 tx_skb->skb = NULL; 4843 tx_skb->skb = NULL;
4429 } 4844 }
@@ -4455,56 +4870,42 @@ static inline int rtl8169_fragmented_frame(u32 status)
4455 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4870 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4456} 4871}
4457 4872
4458static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) 4873static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4459{ 4874{
4460 u32 opts1 = le32_to_cpu(desc->opts1);
4461 u32 status = opts1 & RxProtoMask; 4875 u32 status = opts1 & RxProtoMask;
4462 4876
4463 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4877 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4464 ((status == RxProtoUDP) && !(opts1 & UDPFail)) || 4878 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4465 ((status == RxProtoIP) && !(opts1 & IPFail)))
4466 skb->ip_summed = CHECKSUM_UNNECESSARY; 4879 skb->ip_summed = CHECKSUM_UNNECESSARY;
4467 else 4880 else
4468 skb->ip_summed = CHECKSUM_NONE; 4881 skb_checksum_none_assert(skb);
4469} 4882}
4470 4883
4471static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, 4884static struct sk_buff *rtl8169_try_rx_copy(void *data,
4472 struct rtl8169_private *tp, int pkt_size, 4885 struct rtl8169_private *tp,
4473 dma_addr_t addr) 4886 int pkt_size,
4887 dma_addr_t addr)
4474{ 4888{
4475 struct sk_buff *skb; 4889 struct sk_buff *skb;
4476 bool done = false; 4890 struct device *d = &tp->pci_dev->dev;
4477
4478 if (pkt_size >= rx_copybreak)
4479 goto out;
4480 4891
4892 data = rtl8169_align(data);
4893 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4894 prefetch(data);
4481 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); 4895 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4482 if (!skb) 4896 if (skb)
4483 goto out; 4897 memcpy(skb->data, data, pkt_size);
4898 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4484 4899
4485 dma_sync_single_for_cpu(&tp->pci_dev->dev, addr, pkt_size, 4900 return skb;
4486 PCI_DMA_FROMDEVICE);
4487 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4488 *sk_buff = skb;
4489 done = true;
4490out:
4491 return done;
4492} 4901}
4493 4902
4494/*
4495 * Warning : rtl8169_rx_interrupt() might be called :
4496 * 1) from NAPI (softirq) context
4497 * (polling = 1 : we should call netif_receive_skb())
4498 * 2) from process context (rtl8169_reset_task())
4499 * (polling = 0 : we must call netif_rx() instead)
4500 */
4501static int rtl8169_rx_interrupt(struct net_device *dev, 4903static int rtl8169_rx_interrupt(struct net_device *dev,
4502 struct rtl8169_private *tp, 4904 struct rtl8169_private *tp,
4503 void __iomem *ioaddr, u32 budget) 4905 void __iomem *ioaddr, u32 budget)
4504{ 4906{
4505 unsigned int cur_rx, rx_left; 4907 unsigned int cur_rx, rx_left;
4506 unsigned int delta, count; 4908 unsigned int count;
4507 int polling = (budget != ~(u32)0) ? 1 : 0;
4508 4909
4509 cur_rx = tp->cur_rx; 4910 cur_rx = tp->cur_rx;
4510 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; 4911 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
@@ -4532,12 +4933,11 @@ static int rtl8169_rx_interrupt(struct net_device *dev,
4532 rtl8169_schedule_work(dev, rtl8169_reset_task); 4933 rtl8169_schedule_work(dev, rtl8169_reset_task);
4533 dev->stats.rx_fifo_errors++; 4934 dev->stats.rx_fifo_errors++;
4534 } 4935 }
4535 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 4936 rtl8169_mark_to_asic(desc, rx_buf_sz);
4536 } else { 4937 } else {
4537 struct sk_buff *skb = tp->Rx_skbuff[entry]; 4938 struct sk_buff *skb;
4538 dma_addr_t addr = le64_to_cpu(desc->addr); 4939 dma_addr_t addr = le64_to_cpu(desc->addr);
4539 int pkt_size = (status & 0x00001FFF) - 4; 4940 int pkt_size = (status & 0x00001FFF) - 4;
4540 struct pci_dev *pdev = tp->pci_dev;
4541 4941
4542 /* 4942 /*
4543 * The driver does not support incoming fragmented 4943 * The driver does not support incoming fragmented
@@ -4547,31 +4947,25 @@ static int rtl8169_rx_interrupt(struct net_device *dev,
4547 if (unlikely(rtl8169_fragmented_frame(status))) { 4947 if (unlikely(rtl8169_fragmented_frame(status))) {
4548 dev->stats.rx_dropped++; 4948 dev->stats.rx_dropped++;
4549 dev->stats.rx_length_errors++; 4949 dev->stats.rx_length_errors++;
4550 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 4950 rtl8169_mark_to_asic(desc, rx_buf_sz);
4551 continue; 4951 continue;
4552 } 4952 }
4553 4953
4554 rtl8169_rx_csum(skb, desc); 4954 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4555 4955 tp, pkt_size, addr);
4556 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { 4956 rtl8169_mark_to_asic(desc, rx_buf_sz);
4557 dma_sync_single_for_device(&pdev->dev, addr, 4957 if (!skb) {
4558 pkt_size, PCI_DMA_FROMDEVICE); 4958 dev->stats.rx_dropped++;
4559 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 4959 continue;
4560 } else {
4561 dma_unmap_single(&pdev->dev, addr, tp->rx_buf_sz,
4562 PCI_DMA_FROMDEVICE);
4563 tp->Rx_skbuff[entry] = NULL;
4564 } 4960 }
4565 4961
4962 rtl8169_rx_csum(skb, status);
4566 skb_put(skb, pkt_size); 4963 skb_put(skb, pkt_size);
4567 skb->protocol = eth_type_trans(skb, dev); 4964 skb->protocol = eth_type_trans(skb, dev);
4568 4965
4569 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) { 4966 rtl8169_rx_vlan_tag(desc, skb);
4570 if (likely(polling)) 4967
4571 netif_receive_skb(skb); 4968 napi_gro_receive(&tp->napi, skb);
4572 else
4573 netif_rx(skb);
4574 }
4575 4969
4576 dev->stats.rx_bytes += pkt_size; 4970 dev->stats.rx_bytes += pkt_size;
4577 dev->stats.rx_packets++; 4971 dev->stats.rx_packets++;
@@ -4588,20 +4982,7 @@ static int rtl8169_rx_interrupt(struct net_device *dev,
4588 count = cur_rx - tp->cur_rx; 4982 count = cur_rx - tp->cur_rx;
4589 tp->cur_rx = cur_rx; 4983 tp->cur_rx = cur_rx;
4590 4984
4591 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx, GFP_ATOMIC); 4985 tp->dirty_rx += count;
4592 if (!delta && count)
4593 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4594 tp->dirty_rx += delta;
4595
4596 /*
4597 * FIXME: until there is periodic timer to try and refill the ring,
4598 * a temporary shortage may definitely kill the Rx process.
4599 * - disable the asic to try and avoid an overflow and kick it again
4600 * after refill ?
4601 * - how do others driver handle this condition (Uh oh...).
4602 */
4603 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4604 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4605 4986
4606 return count; 4987 return count;
4607} 4988}
@@ -4629,11 +5010,34 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4629 break; 5010 break;
4630 } 5011 }
4631 5012
4632 /* Work around for rx fifo overflow */
4633 if (unlikely(status & RxFIFOOver)) { 5013 if (unlikely(status & RxFIFOOver)) {
4634 netif_stop_queue(dev); 5014 switch (tp->mac_version) {
4635 rtl8169_tx_timeout(dev); 5015 /* Work around for rx fifo overflow */
4636 break; 5016 case RTL_GIGA_MAC_VER_11:
5017 case RTL_GIGA_MAC_VER_22:
5018 case RTL_GIGA_MAC_VER_26:
5019 netif_stop_queue(dev);
5020 rtl8169_tx_timeout(dev);
5021 goto done;
5022 /* Testers needed. */
5023 case RTL_GIGA_MAC_VER_17:
5024 case RTL_GIGA_MAC_VER_19:
5025 case RTL_GIGA_MAC_VER_20:
5026 case RTL_GIGA_MAC_VER_21:
5027 case RTL_GIGA_MAC_VER_23:
5028 case RTL_GIGA_MAC_VER_24:
5029 case RTL_GIGA_MAC_VER_27:
5030 case RTL_GIGA_MAC_VER_28:
5031 case RTL_GIGA_MAC_VER_31:
5032 /* Experimental science. Pktgen proof. */
5033 case RTL_GIGA_MAC_VER_12:
5034 case RTL_GIGA_MAC_VER_25:
5035 if (status == RxFIFOOver)
5036 goto done;
5037 break;
5038 default:
5039 break;
5040 }
4637 } 5041 }
4638 5042
4639 if (unlikely(status & SYSErr)) { 5043 if (unlikely(status & SYSErr)) {
@@ -4642,7 +5046,7 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4642 } 5046 }
4643 5047
4644 if (status & LinkChg) 5048 if (status & LinkChg)
4645 rtl8169_check_link_status(dev, tp, ioaddr); 5049 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4646 5050
4647 /* We need to see the lastest version of tp->intr_mask to 5051 /* We need to see the lastest version of tp->intr_mask to
4648 * avoid ignoring an MSI interrupt and having to wait for 5052 * avoid ignoring an MSI interrupt and having to wait for
@@ -4669,7 +5073,7 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4669 (status & RxFIFOOver) ? (status | RxOverflow) : status); 5073 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4670 status = RTL_R16(IntrStatus); 5074 status = RTL_R16(IntrStatus);
4671 } 5075 }
4672 5076done:
4673 return IRQ_RETVAL(handled); 5077 return IRQ_RETVAL(handled);
4674} 5078}
4675 5079
@@ -4716,19 +5120,21 @@ static void rtl8169_down(struct net_device *dev)
4716{ 5120{
4717 struct rtl8169_private *tp = netdev_priv(dev); 5121 struct rtl8169_private *tp = netdev_priv(dev);
4718 void __iomem *ioaddr = tp->mmio_addr; 5122 void __iomem *ioaddr = tp->mmio_addr;
4719 unsigned int intrmask;
4720 5123
4721 rtl8169_delete_timer(dev); 5124 del_timer_sync(&tp->timer);
4722 5125
4723 netif_stop_queue(dev); 5126 netif_stop_queue(dev);
4724 5127
4725 napi_disable(&tp->napi); 5128 napi_disable(&tp->napi);
4726 5129
4727core_down:
4728 spin_lock_irq(&tp->lock); 5130 spin_lock_irq(&tp->lock);
4729 5131
4730 rtl8169_asic_down(ioaddr); 5132 rtl8169_asic_down(ioaddr);
4731 5133 /*
5134 * At this point device interrupts can not be enabled in any function,
5135 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5136 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5137 */
4732 rtl8169_rx_missed(dev, ioaddr); 5138 rtl8169_rx_missed(dev, ioaddr);
4733 5139
4734 spin_unlock_irq(&tp->lock); 5140 spin_unlock_irq(&tp->lock);
@@ -4738,26 +5144,11 @@ core_down:
4738 /* Give a racing hard_start_xmit a few cycles to complete. */ 5144 /* Give a racing hard_start_xmit a few cycles to complete. */
4739 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ 5145 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4740 5146
4741 /*
4742 * And now for the 50k$ question: are IRQ disabled or not ?
4743 *
4744 * Two paths lead here:
4745 * 1) dev->close
4746 * -> netif_running() is available to sync the current code and the
4747 * IRQ handler. See rtl8169_interrupt for details.
4748 * 2) dev->change_mtu
4749 * -> rtl8169_poll can not be issued again and re-enable the
4750 * interruptions. Let's simply issue the IRQ down sequence again.
4751 *
4752 * No loop if hotpluged or major error (0xffff).
4753 */
4754 intrmask = RTL_R16(IntrMask);
4755 if (intrmask && (intrmask != 0xffff))
4756 goto core_down;
4757
4758 rtl8169_tx_clear(tp); 5147 rtl8169_tx_clear(tp);
4759 5148
4760 rtl8169_rx_clear(tp); 5149 rtl8169_rx_clear(tp);
5150
5151 rtl_pll_power_down(tp);
4761} 5152}
4762 5153
4763static int rtl8169_close(struct net_device *dev) 5154static int rtl8169_close(struct net_device *dev)
@@ -4767,7 +5158,7 @@ static int rtl8169_close(struct net_device *dev)
4767 5158
4768 pm_runtime_get_sync(&pdev->dev); 5159 pm_runtime_get_sync(&pdev->dev);
4769 5160
4770 /* update counters before going down */ 5161 /* Update counters before going down */
4771 rtl8169_update_counters(dev); 5162 rtl8169_update_counters(dev);
4772 5163
4773 rtl8169_down(dev); 5164 rtl8169_down(dev);
@@ -4822,7 +5213,7 @@ static void rtl_set_rx_mode(struct net_device *dev)
4822 spin_lock_irqsave(&tp->lock, flags); 5213 spin_lock_irqsave(&tp->lock, flags);
4823 5214
4824 tmp = rtl8169_rx_config | rx_mode | 5215 tmp = rtl8169_rx_config | rx_mode |
4825 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 5216 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
4826 5217
4827 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 5218 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4828 u32 data = mc_filter[0]; 5219 u32 data = mc_filter[0];
@@ -4862,9 +5253,13 @@ static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4862 5253
4863static void rtl8169_net_suspend(struct net_device *dev) 5254static void rtl8169_net_suspend(struct net_device *dev)
4864{ 5255{
5256 struct rtl8169_private *tp = netdev_priv(dev);
5257
4865 if (!netif_running(dev)) 5258 if (!netif_running(dev))
4866 return; 5259 return;
4867 5260
5261 rtl_pll_power_down(tp);
5262
4868 netif_device_detach(dev); 5263 netif_device_detach(dev);
4869 netif_stop_queue(dev); 5264 netif_stop_queue(dev);
4870} 5265}
@@ -4883,7 +5278,12 @@ static int rtl8169_suspend(struct device *device)
4883 5278
4884static void __rtl8169_resume(struct net_device *dev) 5279static void __rtl8169_resume(struct net_device *dev)
4885{ 5280{
5281 struct rtl8169_private *tp = netdev_priv(dev);
5282
4886 netif_device_attach(dev); 5283 netif_device_attach(dev);
5284
5285 rtl_pll_power_up(tp);
5286
4887 rtl8169_schedule_work(dev, rtl8169_reset_task); 5287 rtl8169_schedule_work(dev, rtl8169_reset_task);
4888} 5288}
4889 5289
@@ -4891,6 +5291,9 @@ static int rtl8169_resume(struct device *device)
4891{ 5291{
4892 struct pci_dev *pdev = to_pci_dev(device); 5292 struct pci_dev *pdev = to_pci_dev(device);
4893 struct net_device *dev = pci_get_drvdata(pdev); 5293 struct net_device *dev = pci_get_drvdata(pdev);
5294 struct rtl8169_private *tp = netdev_priv(dev);
5295
5296 rtl8169_init_phy(dev, tp);
4894 5297
4895 if (netif_running(dev)) 5298 if (netif_running(dev))
4896 __rtl8169_resume(dev); 5299 __rtl8169_resume(dev);
@@ -4931,6 +5334,8 @@ static int rtl8169_runtime_resume(struct device *device)
4931 tp->saved_wolopts = 0; 5334 tp->saved_wolopts = 0;
4932 spin_unlock_irq(&tp->lock); 5335 spin_unlock_irq(&tp->lock);
4933 5336
5337 rtl8169_init_phy(dev, tp);
5338
4934 __rtl8169_resume(dev); 5339 __rtl8169_resume(dev);
4935 5340
4936 return 0; 5341 return 0;
@@ -4942,23 +5347,19 @@ static int rtl8169_runtime_idle(struct device *device)
4942 struct net_device *dev = pci_get_drvdata(pdev); 5347 struct net_device *dev = pci_get_drvdata(pdev);
4943 struct rtl8169_private *tp = netdev_priv(dev); 5348 struct rtl8169_private *tp = netdev_priv(dev);
4944 5349
4945 if (!tp->TxDescArray) 5350 return tp->TxDescArray ? -EBUSY : 0;
4946 return 0;
4947
4948 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4949 return -EBUSY;
4950} 5351}
4951 5352
4952static const struct dev_pm_ops rtl8169_pm_ops = { 5353static const struct dev_pm_ops rtl8169_pm_ops = {
4953 .suspend = rtl8169_suspend, 5354 .suspend = rtl8169_suspend,
4954 .resume = rtl8169_resume, 5355 .resume = rtl8169_resume,
4955 .freeze = rtl8169_suspend, 5356 .freeze = rtl8169_suspend,
4956 .thaw = rtl8169_resume, 5357 .thaw = rtl8169_resume,
4957 .poweroff = rtl8169_suspend, 5358 .poweroff = rtl8169_suspend,
4958 .restore = rtl8169_resume, 5359 .restore = rtl8169_resume,
4959 .runtime_suspend = rtl8169_runtime_suspend, 5360 .runtime_suspend = rtl8169_runtime_suspend,
4960 .runtime_resume = rtl8169_runtime_resume, 5361 .runtime_resume = rtl8169_runtime_resume,
4961 .runtime_idle = rtl8169_runtime_idle, 5362 .runtime_idle = rtl8169_runtime_idle,
4962}; 5363};
4963 5364
4964#define RTL8169_PM_OPS (&rtl8169_pm_ops) 5365#define RTL8169_PM_OPS (&rtl8169_pm_ops)
@@ -4977,7 +5378,7 @@ static void rtl_shutdown(struct pci_dev *pdev)
4977 5378
4978 rtl8169_net_suspend(dev); 5379 rtl8169_net_suspend(dev);
4979 5380
4980 /* restore original MAC address */ 5381 /* Restore original MAC address */
4981 rtl_rar_set(tp, dev->perm_addr); 5382 rtl_rar_set(tp, dev->perm_addr);
4982 5383
4983 spin_lock_irq(&tp->lock); 5384 spin_lock_irq(&tp->lock);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-05 07:21:57 -0400