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authorDavid S. Miller <davem@davemloft.net>2011-07-06 02:23:37 -0400
committerDavid S. Miller <davem@davemloft.net>2011-07-06 02:23:37 -0400
commite12fe68ce34d60c04bb1ddb1d3cc5c3022388fe4 (patch)
tree83c0e192ccaa4752c80b6131a7d0aa8272b5d0d0 /drivers/net/qlge
parent7329f0d58de01878d9ce4f0be7a76e136f223eef (diff)
parent712ae51afd55b20c04c5383d02ba5d10233313b1 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Diffstat (limited to 'drivers/net/qlge')
-rw-r--r--drivers/net/qlge/qlge.h3
-rw-r--r--drivers/net/qlge/qlge_main.c40
2 files changed, 25 insertions, 18 deletions
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h
index 7d8483f9012e..794252c0aedd 100644
--- a/drivers/net/qlge/qlge.h
+++ b/drivers/net/qlge/qlge.h
@@ -17,7 +17,7 @@
17 */ 17 */
18#define DRV_NAME "qlge" 18#define DRV_NAME "qlge"
19#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver " 19#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
20#define DRV_VERSION "v1.00.00.27.00.00-01" 20#define DRV_VERSION "v1.00.00.29.00.00-01"
21 21
22#define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */ 22#define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
23 23
@@ -1997,6 +1997,7 @@ enum {
1997 QL_LB_LINK_UP = 10, 1997 QL_LB_LINK_UP = 10,
1998 QL_FRC_COREDUMP = 11, 1998 QL_FRC_COREDUMP = 11,
1999 QL_EEH_FATAL = 12, 1999 QL_EEH_FATAL = 12,
2000 QL_ASIC_RECOVERY = 14, /* We are in ascic recovery. */
2000}; 2001};
2001 2002
2002/* link_status bit definitions */ 2003/* link_status bit definitions */
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c
index be89610f16a8..68fbfac7a3bf 100644
--- a/drivers/net/qlge/qlge_main.c
+++ b/drivers/net/qlge/qlge_main.c
@@ -2152,6 +2152,10 @@ void ql_queue_asic_error(struct ql_adapter *qdev)
2152 * thread 2152 * thread
2153 */ 2153 */
2154 clear_bit(QL_ADAPTER_UP, &qdev->flags); 2154 clear_bit(QL_ADAPTER_UP, &qdev->flags);
2155 /* Set asic recovery bit to indicate reset process that we are
2156 * in fatal error recovery process rather than normal close
2157 */
2158 set_bit(QL_ASIC_RECOVERY, &qdev->flags);
2155 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0); 2159 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
2156} 2160}
2157 2161
@@ -2166,23 +2170,20 @@ static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
2166 return; 2170 return;
2167 2171
2168 case CAM_LOOKUP_ERR_EVENT: 2172 case CAM_LOOKUP_ERR_EVENT:
2169 netif_err(qdev, link, qdev->ndev, 2173 netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n");
2170 "Multiple CAM hits lookup occurred.\n"); 2174 netdev_err(qdev->ndev, "This event shouldn't occur.\n");
2171 netif_err(qdev, drv, qdev->ndev,
2172 "This event shouldn't occur.\n");
2173 ql_queue_asic_error(qdev); 2175 ql_queue_asic_error(qdev);
2174 return; 2176 return;
2175 2177
2176 case SOFT_ECC_ERROR_EVENT: 2178 case SOFT_ECC_ERROR_EVENT:
2177 netif_err(qdev, rx_err, qdev->ndev, 2179 netdev_err(qdev->ndev, "Soft ECC error detected.\n");
2178 "Soft ECC error detected.\n");
2179 ql_queue_asic_error(qdev); 2180 ql_queue_asic_error(qdev);
2180 break; 2181 break;
2181 2182
2182 case PCI_ERR_ANON_BUF_RD: 2183 case PCI_ERR_ANON_BUF_RD:
2183 netif_err(qdev, rx_err, qdev->ndev, 2184 netdev_err(qdev->ndev, "PCI error occurred when reading "
2184 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n", 2185 "anonymous buffers from rx_ring %d.\n",
2185 ib_ae_rsp->q_id); 2186 ib_ae_rsp->q_id);
2186 ql_queue_asic_error(qdev); 2187 ql_queue_asic_error(qdev);
2187 break; 2188 break;
2188 2189
@@ -2437,11 +2438,10 @@ static irqreturn_t qlge_isr(int irq, void *dev_id)
2437 */ 2438 */
2438 if (var & STS_FE) { 2439 if (var & STS_FE) {
2439 ql_queue_asic_error(qdev); 2440 ql_queue_asic_error(qdev);
2440 netif_err(qdev, intr, qdev->ndev, 2441 netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var);
2441 "Got fatal error, STS = %x.\n", var);
2442 var = ql_read32(qdev, ERR_STS); 2442 var = ql_read32(qdev, ERR_STS);
2443 netif_err(qdev, intr, qdev->ndev, 2443 netdev_err(qdev->ndev, "Resetting chip. "
2444 "Resetting chip. Error Status Register = 0x%x\n", var); 2444 "Error Status Register = 0x%x\n", var);
2445 return IRQ_HANDLED; 2445 return IRQ_HANDLED;
2446 } 2446 }
2447 2447
@@ -3818,11 +3818,17 @@ static int ql_adapter_reset(struct ql_adapter *qdev)
3818 end_jiffies = jiffies + 3818 end_jiffies = jiffies +
3819 max((unsigned long)1, usecs_to_jiffies(30)); 3819 max((unsigned long)1, usecs_to_jiffies(30));
3820 3820
3821 /* Stop management traffic. */ 3821 /* Check if bit is set then skip the mailbox command and
3822 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP); 3822 * clear the bit, else we are in normal reset process.
3823 */
3824 if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) {
3825 /* Stop management traffic. */
3826 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
3823 3827
3824 /* Wait for the NIC and MGMNT FIFOs to empty. */ 3828 /* Wait for the NIC and MGMNT FIFOs to empty. */
3825 ql_wait_fifo_empty(qdev); 3829 ql_wait_fifo_empty(qdev);
3830 } else
3831 clear_bit(QL_ASIC_RECOVERY, &qdev->flags);
3826 3832
3827 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR); 3833 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3828 3834