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authorDhananjay Phadke <dhananjay@netxen.com>2008-07-21 22:44:06 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-22 17:52:04 -0400
commit48bfd1e0fc66b27254ec742b014e689ef218e76c (patch)
treefd380b835dc12a5500ff5972981ee9ae767639b4 /drivers/net/netxen/netxen_nic_hw.c
parenta97342f9790f14ac20bd5f8b16ed661411fa2e3e (diff)
netxen: add netxen_nic_ctx.c
Contains rx and tx ring context management and certain firmware commands for netxen firmware v4.0.0+. This patch gathers all HW context management code into netxen_nic_ctx.c. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hw.c')
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c243
1 files changed, 0 insertions, 243 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index fde8c6f1c9f5..d46b4dff783d 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -280,80 +280,6 @@ static unsigned crb_hub_agt[64] =
280 0, 280 0,
281}; 281};
282 282
283struct netxen_recv_crb recv_crb_registers[] = {
284 /*
285 * Instance 0.
286 */
287 {
288 /* crb_rcv_producer: */
289 {
290 NETXEN_NIC_REG(0x100),
291 /* Jumbo frames */
292 NETXEN_NIC_REG(0x110),
293 /* LRO */
294 NETXEN_NIC_REG(0x120)
295 },
296 /* crb_sts_consumer: */
297 NETXEN_NIC_REG(0x138),
298 },
299 /*
300 * Instance 1,
301 */
302 {
303 /* crb_rcv_producer: */
304 {
305 NETXEN_NIC_REG(0x144),
306 /* Jumbo frames */
307 NETXEN_NIC_REG(0x154),
308 /* LRO */
309 NETXEN_NIC_REG(0x164)
310 },
311 /* crb_sts_consumer: */
312 NETXEN_NIC_REG(0x17c),
313 },
314 /*
315 * Instance 2,
316 */
317 {
318 /* crb_rcv_producer: */
319 {
320 NETXEN_NIC_REG(0x1d8),
321 /* Jumbo frames */
322 NETXEN_NIC_REG(0x1f8),
323 /* LRO */
324 NETXEN_NIC_REG(0x208)
325 },
326 /* crb_sts_consumer: */
327 NETXEN_NIC_REG(0x220),
328 },
329 /*
330 * Instance 3,
331 */
332 {
333 /* crb_rcv_producer: */
334 {
335 NETXEN_NIC_REG(0x22c),
336 /* Jumbo frames */
337 NETXEN_NIC_REG(0x23c),
338 /* LRO */
339 NETXEN_NIC_REG(0x24c)
340 },
341 /* crb_sts_consumer: */
342 NETXEN_NIC_REG(0x264),
343 },
344};
345
346static u64 ctx_addr_sig_regs[][3] = {
347 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
348 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
349 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
350 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
351};
352#define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
353#define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
354#define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
355
356
357/* PCI Windowing for DDR regions. */ 283/* PCI Windowing for DDR regions. */
358 284
359#define ADDR_IN_RANGE(addr, low, high) \ 285#define ADDR_IN_RANGE(addr, low, high) \
@@ -368,10 +294,6 @@ static u64 ctx_addr_sig_regs[][3] = {
368#define NETXEN_NIU_HDRSIZE (0x1 << 6) 294#define NETXEN_NIU_HDRSIZE (0x1 << 6)
369#define NETXEN_NIU_TLRSIZE (0x1 << 5) 295#define NETXEN_NIU_TLRSIZE (0x1 << 5)
370 296
371#define lower32(x) ((u32)((x) & 0xffffffff))
372#define upper32(x) \
373 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
374
375#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL 297#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
376#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL 298#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
377#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL 299#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
@@ -556,171 +478,6 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
556 return 0; 478 return 0;
557} 479}
558 480
559/*
560 * check if the firmware has been downloaded and ready to run and
561 * setup the address for the descriptors in the adapter
562 */
563int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
564{
565 struct netxen_hardware_context *hw = &adapter->ahw;
566 u32 state = 0;
567 void *addr;
568 int err = 0;
569 int ctx, ring;
570 struct netxen_recv_context *recv_ctx;
571 struct netxen_rcv_desc_ctx *rcv_desc;
572 int func_id = adapter->portnum;
573
574 err = netxen_receive_peg_ready(adapter);
575 if (err) {
576 printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n",
577 state);
578 return err;
579 }
580 adapter->intr_scheme = adapter->pci_read_normalize(adapter,
581 CRB_NIC_CAPABILITIES_FW);
582 adapter->msi_mode = adapter->pci_read_normalize(adapter,
583 CRB_NIC_MSI_MODE_FW);
584
585 addr = pci_alloc_consistent(adapter->pdev,
586 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
587 &adapter->ctx_desc_phys_addr);
588
589 if (addr == NULL) {
590 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
591 err = -ENOMEM;
592 return err;
593 }
594 memset(addr, 0, sizeof(struct netxen_ring_ctx));
595 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
596 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
597 adapter->ctx_desc->cmd_consumer_offset =
598 cpu_to_le64(adapter->ctx_desc_phys_addr +
599 sizeof(struct netxen_ring_ctx));
600 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
601 sizeof(struct netxen_ring_ctx));
602
603 addr = pci_alloc_consistent(adapter->pdev,
604 sizeof(struct cmd_desc_type0) *
605 adapter->max_tx_desc_count,
606 &hw->cmd_desc_phys_addr);
607
608 if (addr == NULL) {
609 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
610 netxen_free_hw_resources(adapter);
611 return -ENOMEM;
612 }
613
614 adapter->ctx_desc->cmd_ring_addr =
615 cpu_to_le64(hw->cmd_desc_phys_addr);
616 adapter->ctx_desc->cmd_ring_size =
617 cpu_to_le32(adapter->max_tx_desc_count);
618
619 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
620
621 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
622 recv_ctx = &adapter->recv_ctx[ctx];
623
624 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
625 rcv_desc = &recv_ctx->rcv_desc[ring];
626 addr = pci_alloc_consistent(adapter->pdev,
627 RCV_DESC_RINGSIZE,
628 &rcv_desc->phys_addr);
629 if (addr == NULL) {
630 DPRINTK(ERR, "bad return from "
631 "pci_alloc_consistent\n");
632 netxen_free_hw_resources(adapter);
633 err = -ENOMEM;
634 return err;
635 }
636 rcv_desc->desc_head = (struct rcv_desc *)addr;
637 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
638 cpu_to_le64(rcv_desc->phys_addr);
639 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
640 cpu_to_le32(rcv_desc->max_rx_desc_count);
641 rcv_desc->crb_rcv_producer =
642 recv_crb_registers[adapter->portnum].
643 crb_rcv_producer[ring];
644 }
645
646 addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE,
647 &recv_ctx->rcv_status_desc_phys_addr);
648 if (addr == NULL) {
649 DPRINTK(ERR, "bad return from"
650 " pci_alloc_consistent\n");
651 netxen_free_hw_resources(adapter);
652 err = -ENOMEM;
653 return err;
654 }
655 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
656 adapter->ctx_desc->sts_ring_addr =
657 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
658 adapter->ctx_desc->sts_ring_size =
659 cpu_to_le32(adapter->max_rx_desc_count);
660 recv_ctx->crb_sts_consumer =
661 recv_crb_registers[adapter->portnum].crb_sts_consumer;
662
663 }
664 /* Window = 1 */
665
666 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id),
667 lower32(adapter->ctx_desc_phys_addr));
668 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id),
669 upper32(adapter->ctx_desc_phys_addr));
670 adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id),
671 NETXEN_CTX_SIGNATURE | func_id);
672 return err;
673}
674
675void netxen_free_hw_resources(struct netxen_adapter *adapter)
676{
677 struct netxen_recv_context *recv_ctx;
678 struct netxen_rcv_desc_ctx *rcv_desc;
679 int ctx, ring;
680
681 if (adapter->ctx_desc != NULL) {
682 pci_free_consistent(adapter->pdev,
683 sizeof(struct netxen_ring_ctx) +
684 sizeof(uint32_t),
685 adapter->ctx_desc,
686 adapter->ctx_desc_phys_addr);
687 adapter->ctx_desc = NULL;
688 }
689
690 if (adapter->ahw.cmd_desc_head != NULL) {
691 pci_free_consistent(adapter->pdev,
692 sizeof(struct cmd_desc_type0) *
693 adapter->max_tx_desc_count,
694 adapter->ahw.cmd_desc_head,
695 adapter->ahw.cmd_desc_phys_addr);
696 adapter->ahw.cmd_desc_head = NULL;
697 }
698
699 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
700 recv_ctx = &adapter->recv_ctx[ctx];
701 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
702 rcv_desc = &recv_ctx->rcv_desc[ring];
703
704 if (rcv_desc->desc_head != NULL) {
705 pci_free_consistent(adapter->pdev,
706 RCV_DESC_RINGSIZE,
707 rcv_desc->desc_head,
708 rcv_desc->phys_addr);
709 rcv_desc->desc_head = NULL;
710 }
711 }
712
713 if (recv_ctx->rcv_status_desc_head != NULL) {
714 pci_free_consistent(adapter->pdev,
715 STATUS_DESC_RINGSIZE,
716 recv_ctx->rcv_status_desc_head,
717 recv_ctx->
718 rcv_status_desc_phys_addr);
719 recv_ctx->rcv_status_desc_head = NULL;
720 }
721 }
722}
723
724void netxen_tso_check(struct netxen_adapter *adapter, 481void netxen_tso_check(struct netxen_adapter *adapter,
725 struct cmd_desc_type0 *desc, struct sk_buff *skb) 482 struct cmd_desc_type0 *desc, struct sk_buff *skb)
726{ 483{
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