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authorLennert Buytenhek <buytenh@wantstofly.org>2008-07-14 08:29:40 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-07-24 00:22:59 -0400
commit81600eea98789da09a32de69ca9d3be8b9503c54 (patch)
treeba607eed9bfff70d4f40c3b25baf1bc83ea90024 /drivers/net/mv643xx_eth.c
parent7dde154d3d0d9701ecfb5533017a8f1a20bb4214 (diff)
mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface
The mv643xx_eth hardware has a provision for polling the PHY's MII management registers to obtain the (R)(G)MII interface speed (10/100/1000) and duplex (half/full) and pause (off/symmetric) settings to use to talk to the PHY. The driver currently does not make use of this feature. Instead, whenever there is a link status change event, it reads the current link parameters from the PHY, and programs those parameters into the mv643xx_eth MAC by hand. This patch switches the mv643xx_eth driver to letting the MAC auto-determine the (R)(G)MII link parameters by PHY polling, if there is a PHY present. For PHYless ports (when e.g. the (R)(G)MII interface is connected to a hardware switch), we keep hardcoding the MII interface parameters. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'drivers/net/mv643xx_eth.c')
-rw-r--r--drivers/net/mv643xx_eth.c140
1 files changed, 66 insertions, 74 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 006ad45ddb84..29d4fe37cd50 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -91,6 +91,7 @@ static char mv643xx_eth_driver_version[] = "1.1";
91#define PORT_STATUS(p) (0x0444 + ((p) << 10)) 91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
92#define TX_FIFO_EMPTY 0x00000400 92#define TX_FIFO_EMPTY 0x00000400
93#define TX_IN_PROGRESS 0x00000080 93#define TX_IN_PROGRESS 0x00000080
94#define LINK_UP 0x00000002
94#define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) 95#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
95#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) 96#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
96#define TX_BW_RATE(p) (0x0450 + ((p) << 10)) 97#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
@@ -156,7 +157,6 @@ static char mv643xx_eth_driver_version[] = "1.1";
156#define SET_GMII_SPEED_TO_1000 (1 << 23) 157#define SET_GMII_SPEED_TO_1000 (1 << 23)
157#define SET_FULL_DUPLEX_MODE (1 << 21) 158#define SET_FULL_DUPLEX_MODE (1 << 21)
158#define MAX_RX_PACKET_9700BYTE (5 << 17) 159#define MAX_RX_PACKET_9700BYTE (5 << 17)
159#define MAX_RX_PACKET_MASK (7 << 17)
160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10) 161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9) 162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
@@ -1135,10 +1135,28 @@ static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *
1135 1135
1136static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) 1136static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1137{ 1137{
1138 struct mv643xx_eth_private *mp = netdev_priv(dev);
1139 u32 port_status;
1140
1141 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1142
1138 cmd->supported = SUPPORTED_MII; 1143 cmd->supported = SUPPORTED_MII;
1139 cmd->advertising = ADVERTISED_MII; 1144 cmd->advertising = ADVERTISED_MII;
1140 cmd->speed = SPEED_1000; 1145 switch (port_status & PORT_SPEED_MASK) {
1141 cmd->duplex = DUPLEX_FULL; 1146 case PORT_SPEED_10:
1147 cmd->speed = SPEED_10;
1148 break;
1149 case PORT_SPEED_100:
1150 cmd->speed = SPEED_100;
1151 break;
1152 case PORT_SPEED_1000:
1153 cmd->speed = SPEED_1000;
1154 break;
1155 default:
1156 cmd->speed = -1;
1157 break;
1158 }
1159 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1142 cmd->port = PORT_MII; 1160 cmd->port = PORT_MII;
1143 cmd->phy_address = 0; 1161 cmd->phy_address = 0;
1144 cmd->transceiver = XCVR_INTERNAL; 1162 cmd->transceiver = XCVR_INTERNAL;
@@ -1661,51 +1679,6 @@ static void txq_deinit(struct tx_queue *txq)
1661 1679
1662 1680
1663/* netdev ops and related ***************************************************/ 1681/* netdev ops and related ***************************************************/
1664static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1665{
1666 u32 pscr_o;
1667 u32 pscr_n;
1668
1669 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1670
1671 /* clear speed, duplex and rx buffer size fields */
1672 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1673 SET_GMII_SPEED_TO_1000 |
1674 SET_FULL_DUPLEX_MODE |
1675 MAX_RX_PACKET_MASK);
1676
1677 pscr_n |= MAX_RX_PACKET_9700BYTE;
1678
1679 if (speed == SPEED_1000)
1680 pscr_n |= SET_GMII_SPEED_TO_1000;
1681 else if (speed == SPEED_100)
1682 pscr_n |= SET_MII_SPEED_TO_100;
1683
1684 if (duplex == DUPLEX_FULL)
1685 pscr_n |= SET_FULL_DUPLEX_MODE;
1686
1687 if (pscr_n != pscr_o) {
1688 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1689 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1690 else {
1691 int i;
1692
1693 for (i = 0; i < 8; i++)
1694 if (mp->txq_mask & (1 << i))
1695 txq_disable(mp->txq + i);
1696
1697 pscr_o &= ~SERIAL_PORT_ENABLE;
1698 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1699 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1700 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1701
1702 for (i = 0; i < 8; i++)
1703 if (mp->txq_mask & (1 << i))
1704 txq_enable(mp->txq + i);
1705 }
1706 }
1707}
1708
1709static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 1682static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1710{ 1683{
1711 struct net_device *dev = (struct net_device *)dev_id; 1684 struct net_device *dev = (struct net_device *)dev_id;
@@ -1726,14 +1699,7 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1726 } 1699 }
1727 1700
1728 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) { 1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1729 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) { 1702 if (rdl(mp, PORT_STATUS(mp->port_num)) & LINK_UP) {
1730 if (mp->phy_addr != -1) {
1731 struct ethtool_cmd cmd;
1732
1733 mii_ethtool_gset(&mp->mii, &cmd);
1734 update_pscr(mp, cmd.speed, cmd.duplex);
1735 }
1736
1737 if (!netif_carrier_ok(dev)) { 1703 if (!netif_carrier_ok(dev)) {
1738 netif_carrier_on(dev); 1704 netif_carrier_on(dev);
1739 netif_wake_queue(dev); 1705 netif_wake_queue(dev);
@@ -1847,23 +1813,6 @@ static void port_start(struct mv643xx_eth_private *mp)
1847 int i; 1813 int i;
1848 1814
1849 /* 1815 /*
1850 * Configure basic link parameters.
1851 */
1852 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1853 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1854 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1855 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1856 DISABLE_AUTO_NEG_SPEED_GMII |
1857 DISABLE_AUTO_NEG_FOR_DUPLEX |
1858 DO_NOT_FORCE_LINK_FAIL |
1859 SERIAL_PORT_CONTROL_RESERVED;
1860 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1861 pscr |= SERIAL_PORT_ENABLE;
1862 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1863
1864 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1865
1866 /*
1867 * Perform PHY reset, if there is a PHY. 1816 * Perform PHY reset, if there is a PHY.
1868 */ 1817 */
1869 if (mp->phy_addr != -1) { 1818 if (mp->phy_addr != -1) {
@@ -1875,6 +1824,21 @@ static void port_start(struct mv643xx_eth_private *mp)
1875 } 1824 }
1876 1825
1877 /* 1826 /*
1827 * Configure basic link parameters.
1828 */
1829 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1830
1831 pscr |= SERIAL_PORT_ENABLE;
1832 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1833
1834 pscr |= DO_NOT_FORCE_LINK_FAIL;
1835 if (mp->phy_addr == -1)
1836 pscr |= FORCE_LINK_PASS;
1837 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1838
1839 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1840
1841 /*
1878 * Configure TX path and queues. 1842 * Configure TX path and queues.
1879 */ 1843 */
1880 tx_set_rate(mp, 1000000000, 16777216); 1844 tx_set_rate(mp, 1000000000, 16777216);
@@ -2441,12 +2405,39 @@ static int phy_init(struct mv643xx_eth_private *mp,
2441 cmd.duplex = pd->duplex; 2405 cmd.duplex = pd->duplex;
2442 } 2406 }
2443 2407
2444 update_pscr(mp, cmd.speed, cmd.duplex);
2445 mv643xx_eth_set_settings(mp->dev, &cmd); 2408 mv643xx_eth_set_settings(mp->dev, &cmd);
2446 2409
2447 return 0; 2410 return 0;
2448} 2411}
2449 2412
2413static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2414{
2415 u32 pscr;
2416
2417 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2418 if (pscr & SERIAL_PORT_ENABLE) {
2419 pscr &= ~SERIAL_PORT_ENABLE;
2420 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2421 }
2422
2423 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2424 if (mp->phy_addr == -1) {
2425 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2426 if (speed == SPEED_1000)
2427 pscr |= SET_GMII_SPEED_TO_1000;
2428 else if (speed == SPEED_100)
2429 pscr |= SET_MII_SPEED_TO_100;
2430
2431 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2432
2433 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2434 if (duplex == DUPLEX_FULL)
2435 pscr |= SET_FULL_DUPLEX_MODE;
2436 }
2437
2438 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2439}
2440
2450static int mv643xx_eth_probe(struct platform_device *pdev) 2441static int mv643xx_eth_probe(struct platform_device *pdev)
2451{ 2442{
2452 struct mv643xx_eth_platform_data *pd; 2443 struct mv643xx_eth_platform_data *pd;
@@ -2500,6 +2491,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
2500 } else { 2491 } else {
2501 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless); 2492 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2502 } 2493 }
2494 init_pscr(mp, pd->speed, pd->duplex);
2503 2495
2504 2496
2505 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2497 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);