diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
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committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/meth.h | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/meth.h')
-rw-r--r-- | drivers/net/meth.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/meth.h b/drivers/net/meth.h index a78dc1ca8c29..5b145c6bad60 100644 --- a/drivers/net/meth.h +++ b/drivers/net/meth.h | |||
@@ -144,7 +144,7 @@ typedef struct rx_packet { | |||
144 | /* Bits 22 through 28 are used to determine IPGR2 */ | 144 | /* Bits 22 through 28 are used to determine IPGR2 */ |
145 | 145 | ||
146 | #define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ | 146 | #define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ |
147 | /* 000: Inital revision */ | 147 | /* 000: Initial revision */ |
148 | /* 001: First revision, Improved TX concatenation */ | 148 | /* 001: First revision, Improved TX concatenation */ |
149 | 149 | ||
150 | 150 | ||
@@ -193,7 +193,7 @@ typedef struct rx_packet { | |||
193 | /* 1: A TX message had the INT request bit set, the packet has been sent. */ | 193 | /* 1: A TX message had the INT request bit set, the packet has been sent. */ |
194 | #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ | 194 | #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ |
195 | #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ | 195 | #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ |
196 | /* 1: A memory error occurred durring DMA, DMA stopped, Fatal */ | 196 | /* 1: A memory error occurred during DMA, DMA stopped, Fatal */ |
197 | #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ | 197 | #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ |
198 | #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ | 198 | #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ |
199 | #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ | 199 | #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ |