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authorTristram Ha <Tristram.Ha@micrel.com>2010-02-08 06:36:53 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-12 15:15:21 -0500
commit8ca86fd83eae6c73db5f6b23ee3a63b77d52c8ee (patch)
tree3bbf468bfb1cd02d454c9d53c5787281fddfec20 /drivers/net/ksz884x.c
parent447d8c2603a417cca68240059fbf1babfd27774f (diff)
net: Micrel KSZ8841/2 PCI Ethernet driver
This is a new network driver for Micrel KSZ8841/KSZ8842 PCI Ethernet chips. The same driver can run both chips at the same time. It supports IPv4 TCP hardware checksumming and so can use scatter/gather transmission. The KSZ8842 switch has 2 ports. Some users like to take direct control of those ports. So KSZ8842 has a multiple devices mode in which the driver creates another network device so that users can specify which port to send packets. This mode is enabled by passing the "multi_dev=1" parameter to the driver during loading. The KSZ884X can receive huge frames with size up to 1916 bytes. To use this feature change the network device MTU from 1500 to 1898. The KSZ884X driver has 3 packet receive processing functions for the normal mode, multiple devices mode, and huge frame mode. Those functions are identical except for more checking for the new features. In normal programming point of view the huge frame version is the one to use because it covers all the cases, but this is done for performance consideration because the target clients for the KSZ884X chips are embedded systems, which unlike desktop PC may not have powerful CPU. Signed-off-by: Tristram Ha <Tristram.Ha@micrel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ksz884x.c')
-rw-r--r--drivers/net/ksz884x.c7335
1 files changed, 7335 insertions, 0 deletions
diff --git a/drivers/net/ksz884x.c b/drivers/net/ksz884x.c
new file mode 100644
index 000000000000..6f187c7e61fa
--- /dev/null
+++ b/drivers/net/ksz884x.c
@@ -0,0 +1,7335 @@
1/**
2 * drivers/net/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
3 *
4 * Copyright (c) 2009-2010 Micrel, Inc.
5 * Tristram Ha <Tristram.Ha@micrel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/version.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/proc_fs.h>
24#include <linux/mii.h>
25#include <linux/platform_device.h>
26#include <linux/ethtool.h>
27#include <linux/etherdevice.h>
28#include <linux/in.h>
29#include <linux/ip.h>
30#include <linux/if_vlan.h>
31#include <linux/crc32.h>
32#include <linux/sched.h>
33
34
35/* DMA Registers */
36
37#define KS_DMA_TX_CTRL 0x0000
38#define DMA_TX_ENABLE 0x00000001
39#define DMA_TX_CRC_ENABLE 0x00000002
40#define DMA_TX_PAD_ENABLE 0x00000004
41#define DMA_TX_LOOPBACK 0x00000100
42#define DMA_TX_FLOW_ENABLE 0x00000200
43#define DMA_TX_CSUM_IP 0x00010000
44#define DMA_TX_CSUM_TCP 0x00020000
45#define DMA_TX_CSUM_UDP 0x00040000
46#define DMA_TX_BURST_SIZE 0x3F000000
47
48#define KS_DMA_RX_CTRL 0x0004
49#define DMA_RX_ENABLE 0x00000001
50#define KS884X_DMA_RX_MULTICAST 0x00000002
51#define DMA_RX_PROMISCUOUS 0x00000004
52#define DMA_RX_ERROR 0x00000008
53#define DMA_RX_UNICAST 0x00000010
54#define DMA_RX_ALL_MULTICAST 0x00000020
55#define DMA_RX_BROADCAST 0x00000040
56#define DMA_RX_FLOW_ENABLE 0x00000200
57#define DMA_RX_CSUM_IP 0x00010000
58#define DMA_RX_CSUM_TCP 0x00020000
59#define DMA_RX_CSUM_UDP 0x00040000
60#define DMA_RX_BURST_SIZE 0x3F000000
61
62#define DMA_BURST_SHIFT 24
63#define DMA_BURST_DEFAULT 8
64
65#define KS_DMA_TX_START 0x0008
66#define KS_DMA_RX_START 0x000C
67#define DMA_START 0x00000001
68
69#define KS_DMA_TX_ADDR 0x0010
70#define KS_DMA_RX_ADDR 0x0014
71
72#define DMA_ADDR_LIST_MASK 0xFFFFFFFC
73#define DMA_ADDR_LIST_SHIFT 2
74
75/* MTR0 */
76#define KS884X_MULTICAST_0_OFFSET 0x0020
77#define KS884X_MULTICAST_1_OFFSET 0x0021
78#define KS884X_MULTICAST_2_OFFSET 0x0022
79#define KS884x_MULTICAST_3_OFFSET 0x0023
80/* MTR1 */
81#define KS884X_MULTICAST_4_OFFSET 0x0024
82#define KS884X_MULTICAST_5_OFFSET 0x0025
83#define KS884X_MULTICAST_6_OFFSET 0x0026
84#define KS884X_MULTICAST_7_OFFSET 0x0027
85
86/* Interrupt Registers */
87
88/* INTEN */
89#define KS884X_INTERRUPTS_ENABLE 0x0028
90/* INTST */
91#define KS884X_INTERRUPTS_STATUS 0x002C
92
93#define KS884X_INT_RX_STOPPED 0x02000000
94#define KS884X_INT_TX_STOPPED 0x04000000
95#define KS884X_INT_RX_OVERRUN 0x08000000
96#define KS884X_INT_TX_EMPTY 0x10000000
97#define KS884X_INT_RX 0x20000000
98#define KS884X_INT_TX 0x40000000
99#define KS884X_INT_PHY 0x80000000
100
101#define KS884X_INT_RX_MASK \
102 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
103#define KS884X_INT_TX_MASK \
104 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
105#define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
106
107/* MAC Additional Station Address */
108
109/* MAAL0 */
110#define KS_ADD_ADDR_0_LO 0x0080
111/* MAAH0 */
112#define KS_ADD_ADDR_0_HI 0x0084
113/* MAAL1 */
114#define KS_ADD_ADDR_1_LO 0x0088
115/* MAAH1 */
116#define KS_ADD_ADDR_1_HI 0x008C
117/* MAAL2 */
118#define KS_ADD_ADDR_2_LO 0x0090
119/* MAAH2 */
120#define KS_ADD_ADDR_2_HI 0x0094
121/* MAAL3 */
122#define KS_ADD_ADDR_3_LO 0x0098
123/* MAAH3 */
124#define KS_ADD_ADDR_3_HI 0x009C
125/* MAAL4 */
126#define KS_ADD_ADDR_4_LO 0x00A0
127/* MAAH4 */
128#define KS_ADD_ADDR_4_HI 0x00A4
129/* MAAL5 */
130#define KS_ADD_ADDR_5_LO 0x00A8
131/* MAAH5 */
132#define KS_ADD_ADDR_5_HI 0x00AC
133/* MAAL6 */
134#define KS_ADD_ADDR_6_LO 0x00B0
135/* MAAH6 */
136#define KS_ADD_ADDR_6_HI 0x00B4
137/* MAAL7 */
138#define KS_ADD_ADDR_7_LO 0x00B8
139/* MAAH7 */
140#define KS_ADD_ADDR_7_HI 0x00BC
141/* MAAL8 */
142#define KS_ADD_ADDR_8_LO 0x00C0
143/* MAAH8 */
144#define KS_ADD_ADDR_8_HI 0x00C4
145/* MAAL9 */
146#define KS_ADD_ADDR_9_LO 0x00C8
147/* MAAH9 */
148#define KS_ADD_ADDR_9_HI 0x00CC
149/* MAAL10 */
150#define KS_ADD_ADDR_A_LO 0x00D0
151/* MAAH10 */
152#define KS_ADD_ADDR_A_HI 0x00D4
153/* MAAL11 */
154#define KS_ADD_ADDR_B_LO 0x00D8
155/* MAAH11 */
156#define KS_ADD_ADDR_B_HI 0x00DC
157/* MAAL12 */
158#define KS_ADD_ADDR_C_LO 0x00E0
159/* MAAH12 */
160#define KS_ADD_ADDR_C_HI 0x00E4
161/* MAAL13 */
162#define KS_ADD_ADDR_D_LO 0x00E8
163/* MAAH13 */
164#define KS_ADD_ADDR_D_HI 0x00EC
165/* MAAL14 */
166#define KS_ADD_ADDR_E_LO 0x00F0
167/* MAAH14 */
168#define KS_ADD_ADDR_E_HI 0x00F4
169/* MAAL15 */
170#define KS_ADD_ADDR_F_LO 0x00F8
171/* MAAH15 */
172#define KS_ADD_ADDR_F_HI 0x00FC
173
174#define ADD_ADDR_HI_MASK 0x0000FFFF
175#define ADD_ADDR_ENABLE 0x80000000
176#define ADD_ADDR_INCR 8
177
178/* Miscellaneous Registers */
179
180/* MARL */
181#define KS884X_ADDR_0_OFFSET 0x0200
182#define KS884X_ADDR_1_OFFSET 0x0201
183/* MARM */
184#define KS884X_ADDR_2_OFFSET 0x0202
185#define KS884X_ADDR_3_OFFSET 0x0203
186/* MARH */
187#define KS884X_ADDR_4_OFFSET 0x0204
188#define KS884X_ADDR_5_OFFSET 0x0205
189
190/* OBCR */
191#define KS884X_BUS_CTRL_OFFSET 0x0210
192
193#define BUS_SPEED_125_MHZ 0x0000
194#define BUS_SPEED_62_5_MHZ 0x0001
195#define BUS_SPEED_41_66_MHZ 0x0002
196#define BUS_SPEED_25_MHZ 0x0003
197
198/* EEPCR */
199#define KS884X_EEPROM_CTRL_OFFSET 0x0212
200
201#define EEPROM_CHIP_SELECT 0x0001
202#define EEPROM_SERIAL_CLOCK 0x0002
203#define EEPROM_DATA_OUT 0x0004
204#define EEPROM_DATA_IN 0x0008
205#define EEPROM_ACCESS_ENABLE 0x0010
206
207/* MBIR */
208#define KS884X_MEM_INFO_OFFSET 0x0214
209
210#define RX_MEM_TEST_FAILED 0x0008
211#define RX_MEM_TEST_FINISHED 0x0010
212#define TX_MEM_TEST_FAILED 0x0800
213#define TX_MEM_TEST_FINISHED 0x1000
214
215/* GCR */
216#define KS884X_GLOBAL_CTRL_OFFSET 0x0216
217#define GLOBAL_SOFTWARE_RESET 0x0001
218
219#define KS8841_POWER_MANAGE_OFFSET 0x0218
220
221/* WFCR */
222#define KS8841_WOL_CTRL_OFFSET 0x021A
223#define KS8841_WOL_MAGIC_ENABLE 0x0080
224#define KS8841_WOL_FRAME3_ENABLE 0x0008
225#define KS8841_WOL_FRAME2_ENABLE 0x0004
226#define KS8841_WOL_FRAME1_ENABLE 0x0002
227#define KS8841_WOL_FRAME0_ENABLE 0x0001
228
229/* WF0 */
230#define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
231#define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
232#define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
233
234/* IACR */
235#define KS884X_IACR_P 0x04A0
236#define KS884X_IACR_OFFSET KS884X_IACR_P
237
238/* IADR1 */
239#define KS884X_IADR1_P 0x04A2
240#define KS884X_IADR2_P 0x04A4
241#define KS884X_IADR3_P 0x04A6
242#define KS884X_IADR4_P 0x04A8
243#define KS884X_IADR5_P 0x04AA
244
245#define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
246#define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
247
248#define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
249#define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
250#define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
251#define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
252#define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
253#define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
254#define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
255#define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
256#define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
257
258/* P1MBCR */
259#define KS884X_P1MBCR_P 0x04D0
260#define KS884X_P1MBSR_P 0x04D2
261#define KS884X_PHY1ILR_P 0x04D4
262#define KS884X_PHY1IHR_P 0x04D6
263#define KS884X_P1ANAR_P 0x04D8
264#define KS884X_P1ANLPR_P 0x04DA
265
266/* P2MBCR */
267#define KS884X_P2MBCR_P 0x04E0
268#define KS884X_P2MBSR_P 0x04E2
269#define KS884X_PHY2ILR_P 0x04E4
270#define KS884X_PHY2IHR_P 0x04E6
271#define KS884X_P2ANAR_P 0x04E8
272#define KS884X_P2ANLPR_P 0x04EA
273
274#define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
275#define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
276
277#define KS884X_PHY_CTRL_OFFSET 0x00
278
279/* Mode Control Register */
280#define PHY_REG_CTRL 0
281
282#define PHY_RESET 0x8000
283#define PHY_LOOPBACK 0x4000
284#define PHY_SPEED_100MBIT 0x2000
285#define PHY_AUTO_NEG_ENABLE 0x1000
286#define PHY_POWER_DOWN 0x0800
287#define PHY_MII_DISABLE 0x0400
288#define PHY_AUTO_NEG_RESTART 0x0200
289#define PHY_FULL_DUPLEX 0x0100
290#define PHY_COLLISION_TEST 0x0080
291#define PHY_HP_MDIX 0x0020
292#define PHY_FORCE_MDIX 0x0010
293#define PHY_AUTO_MDIX_DISABLE 0x0008
294#define PHY_REMOTE_FAULT_DISABLE 0x0004
295#define PHY_TRANSMIT_DISABLE 0x0002
296#define PHY_LED_DISABLE 0x0001
297
298#define KS884X_PHY_STATUS_OFFSET 0x02
299
300/* Mode Status Register */
301#define PHY_REG_STATUS 1
302
303#define PHY_100BT4_CAPABLE 0x8000
304#define PHY_100BTX_FD_CAPABLE 0x4000
305#define PHY_100BTX_CAPABLE 0x2000
306#define PHY_10BT_FD_CAPABLE 0x1000
307#define PHY_10BT_CAPABLE 0x0800
308#define PHY_MII_SUPPRESS_CAPABLE 0x0040
309#define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
310#define PHY_REMOTE_FAULT 0x0010
311#define PHY_AUTO_NEG_CAPABLE 0x0008
312#define PHY_LINK_STATUS 0x0004
313#define PHY_JABBER_DETECT 0x0002
314#define PHY_EXTENDED_CAPABILITY 0x0001
315
316#define KS884X_PHY_ID_1_OFFSET 0x04
317#define KS884X_PHY_ID_2_OFFSET 0x06
318
319/* PHY Identifier Registers */
320#define PHY_REG_ID_1 2
321#define PHY_REG_ID_2 3
322
323#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
324
325/* Auto-Negotiation Advertisement Register */
326#define PHY_REG_AUTO_NEGOTIATION 4
327
328#define PHY_AUTO_NEG_NEXT_PAGE 0x8000
329#define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
330/* Not supported. */
331#define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
332#define PHY_AUTO_NEG_SYM_PAUSE 0x0400
333#define PHY_AUTO_NEG_100BT4 0x0200
334#define PHY_AUTO_NEG_100BTX_FD 0x0100
335#define PHY_AUTO_NEG_100BTX 0x0080
336#define PHY_AUTO_NEG_10BT_FD 0x0040
337#define PHY_AUTO_NEG_10BT 0x0020
338#define PHY_AUTO_NEG_SELECTOR 0x001F
339#define PHY_AUTO_NEG_802_3 0x0001
340
341#define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
342
343#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
344
345/* Auto-Negotiation Link Partner Ability Register */
346#define PHY_REG_REMOTE_CAPABILITY 5
347
348#define PHY_REMOTE_NEXT_PAGE 0x8000
349#define PHY_REMOTE_ACKNOWLEDGE 0x4000
350#define PHY_REMOTE_REMOTE_FAULT 0x2000
351#define PHY_REMOTE_SYM_PAUSE 0x0400
352#define PHY_REMOTE_100BTX_FD 0x0100
353#define PHY_REMOTE_100BTX 0x0080
354#define PHY_REMOTE_10BT_FD 0x0040
355#define PHY_REMOTE_10BT 0x0020
356
357/* P1VCT */
358#define KS884X_P1VCT_P 0x04F0
359#define KS884X_P1PHYCTRL_P 0x04F2
360
361/* P2VCT */
362#define KS884X_P2VCT_P 0x04F4
363#define KS884X_P2PHYCTRL_P 0x04F6
364
365#define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
366#define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
367
368#define KS884X_PHY_LINK_MD_OFFSET 0x00
369
370#define PHY_START_CABLE_DIAG 0x8000
371#define PHY_CABLE_DIAG_RESULT 0x6000
372#define PHY_CABLE_STAT_NORMAL 0x0000
373#define PHY_CABLE_STAT_OPEN 0x2000
374#define PHY_CABLE_STAT_SHORT 0x4000
375#define PHY_CABLE_STAT_FAILED 0x6000
376#define PHY_CABLE_10M_SHORT 0x1000
377#define PHY_CABLE_FAULT_COUNTER 0x01FF
378
379#define KS884X_PHY_PHY_CTRL_OFFSET 0x02
380
381#define PHY_STAT_REVERSED_POLARITY 0x0020
382#define PHY_STAT_MDIX 0x0010
383#define PHY_FORCE_LINK 0x0008
384#define PHY_POWER_SAVING_DISABLE 0x0004
385#define PHY_REMOTE_LOOPBACK 0x0002
386
387/* SIDER */
388#define KS884X_SIDER_P 0x0400
389#define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
390#define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
391
392#define REG_FAMILY_ID 0x88
393
394#define REG_CHIP_ID_41 0x8810
395#define REG_CHIP_ID_42 0x8800
396
397#define KS884X_CHIP_ID_MASK_41 0xFF10
398#define KS884X_CHIP_ID_MASK 0xFFF0
399#define KS884X_CHIP_ID_SHIFT 4
400#define KS884X_REVISION_MASK 0x000E
401#define KS884X_REVISION_SHIFT 1
402#define KS8842_START 0x0001
403
404#define CHIP_IP_41_M 0x8810
405#define CHIP_IP_42_M 0x8800
406#define CHIP_IP_61_M 0x8890
407#define CHIP_IP_62_M 0x8880
408
409#define CHIP_IP_41_P 0x8850
410#define CHIP_IP_42_P 0x8840
411#define CHIP_IP_61_P 0x88D0
412#define CHIP_IP_62_P 0x88C0
413
414/* SGCR1 */
415#define KS8842_SGCR1_P 0x0402
416#define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
417
418#define SWITCH_PASS_ALL 0x8000
419#define SWITCH_TX_FLOW_CTRL 0x2000
420#define SWITCH_RX_FLOW_CTRL 0x1000
421#define SWITCH_CHECK_LENGTH 0x0800
422#define SWITCH_AGING_ENABLE 0x0400
423#define SWITCH_FAST_AGING 0x0200
424#define SWITCH_AGGR_BACKOFF 0x0100
425#define SWITCH_PASS_PAUSE 0x0008
426#define SWITCH_LINK_AUTO_AGING 0x0001
427
428/* SGCR2 */
429#define KS8842_SGCR2_P 0x0404
430#define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
431
432#define SWITCH_VLAN_ENABLE 0x8000
433#define SWITCH_IGMP_SNOOP 0x4000
434#define IPV6_MLD_SNOOP_ENABLE 0x2000
435#define IPV6_MLD_SNOOP_OPTION 0x1000
436#define PRIORITY_SCHEME_SELECT 0x0800
437#define SWITCH_MIRROR_RX_TX 0x0100
438#define UNICAST_VLAN_BOUNDARY 0x0080
439#define MULTICAST_STORM_DISABLE 0x0040
440#define SWITCH_BACK_PRESSURE 0x0020
441#define FAIR_FLOW_CTRL 0x0010
442#define NO_EXC_COLLISION_DROP 0x0008
443#define SWITCH_HUGE_PACKET 0x0004
444#define SWITCH_LEGAL_PACKET 0x0002
445#define SWITCH_BUF_RESERVE 0x0001
446
447/* SGCR3 */
448#define KS8842_SGCR3_P 0x0406
449#define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
450
451#define BROADCAST_STORM_RATE_LO 0xFF00
452#define SWITCH_REPEATER 0x0080
453#define SWITCH_HALF_DUPLEX 0x0040
454#define SWITCH_FLOW_CTRL 0x0020
455#define SWITCH_10_MBIT 0x0010
456#define SWITCH_REPLACE_NULL_VID 0x0008
457#define BROADCAST_STORM_RATE_HI 0x0007
458
459#define BROADCAST_STORM_RATE 0x07FF
460
461/* SGCR4 */
462#define KS8842_SGCR4_P 0x0408
463
464/* SGCR5 */
465#define KS8842_SGCR5_P 0x040A
466#define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
467
468#define LED_MODE 0x8200
469#define LED_SPEED_DUPLEX_ACT 0x0000
470#define LED_SPEED_DUPLEX_LINK_ACT 0x8000
471#define LED_DUPLEX_10_100 0x0200
472
473/* SGCR6 */
474#define KS8842_SGCR6_P 0x0410
475#define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
476
477#define KS8842_PRIORITY_MASK 3
478#define KS8842_PRIORITY_SHIFT 2
479
480/* SGCR7 */
481#define KS8842_SGCR7_P 0x0412
482#define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
483
484#define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
485#define SWITCH_UNK_DEF_PORT_3 0x0004
486#define SWITCH_UNK_DEF_PORT_2 0x0002
487#define SWITCH_UNK_DEF_PORT_1 0x0001
488
489/* MACAR1 */
490#define KS8842_MACAR1_P 0x0470
491#define KS8842_MACAR2_P 0x0472
492#define KS8842_MACAR3_P 0x0474
493#define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
494#define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
495#define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
496#define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
497#define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
498#define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
499
500/* TOSR1 */
501#define KS8842_TOSR1_P 0x0480
502#define KS8842_TOSR2_P 0x0482
503#define KS8842_TOSR3_P 0x0484
504#define KS8842_TOSR4_P 0x0486
505#define KS8842_TOSR5_P 0x0488
506#define KS8842_TOSR6_P 0x048A
507#define KS8842_TOSR7_P 0x0490
508#define KS8842_TOSR8_P 0x0492
509#define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
510#define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
511#define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
512#define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
513#define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
514#define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
515
516#define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
517#define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
518
519/* P1CR1 */
520#define KS8842_P1CR1_P 0x0500
521#define KS8842_P1CR2_P 0x0502
522#define KS8842_P1VIDR_P 0x0504
523#define KS8842_P1CR3_P 0x0506
524#define KS8842_P1IRCR_P 0x0508
525#define KS8842_P1ERCR_P 0x050A
526#define KS884X_P1SCSLMD_P 0x0510
527#define KS884X_P1CR4_P 0x0512
528#define KS884X_P1SR_P 0x0514
529
530/* P2CR1 */
531#define KS8842_P2CR1_P 0x0520
532#define KS8842_P2CR2_P 0x0522
533#define KS8842_P2VIDR_P 0x0524
534#define KS8842_P2CR3_P 0x0526
535#define KS8842_P2IRCR_P 0x0528
536#define KS8842_P2ERCR_P 0x052A
537#define KS884X_P2SCSLMD_P 0x0530
538#define KS884X_P2CR4_P 0x0532
539#define KS884X_P2SR_P 0x0534
540
541/* P3CR1 */
542#define KS8842_P3CR1_P 0x0540
543#define KS8842_P3CR2_P 0x0542
544#define KS8842_P3VIDR_P 0x0544
545#define KS8842_P3CR3_P 0x0546
546#define KS8842_P3IRCR_P 0x0548
547#define KS8842_P3ERCR_P 0x054A
548
549#define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
550#define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
551#define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
552
553#define PORT_CTRL_ADDR(port, addr) \
554 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
555 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
556
557#define KS8842_PORT_CTRL_1_OFFSET 0x00
558
559#define PORT_BROADCAST_STORM 0x0080
560#define PORT_DIFFSERV_ENABLE 0x0040
561#define PORT_802_1P_ENABLE 0x0020
562#define PORT_BASED_PRIORITY_MASK 0x0018
563#define PORT_BASED_PRIORITY_BASE 0x0003
564#define PORT_BASED_PRIORITY_SHIFT 3
565#define PORT_BASED_PRIORITY_0 0x0000
566#define PORT_BASED_PRIORITY_1 0x0008
567#define PORT_BASED_PRIORITY_2 0x0010
568#define PORT_BASED_PRIORITY_3 0x0018
569#define PORT_INSERT_TAG 0x0004
570#define PORT_REMOVE_TAG 0x0002
571#define PORT_PRIO_QUEUE_ENABLE 0x0001
572
573#define KS8842_PORT_CTRL_2_OFFSET 0x02
574
575#define PORT_INGRESS_VLAN_FILTER 0x4000
576#define PORT_DISCARD_NON_VID 0x2000
577#define PORT_FORCE_FLOW_CTRL 0x1000
578#define PORT_BACK_PRESSURE 0x0800
579#define PORT_TX_ENABLE 0x0400
580#define PORT_RX_ENABLE 0x0200
581#define PORT_LEARN_DISABLE 0x0100
582#define PORT_MIRROR_SNIFFER 0x0080
583#define PORT_MIRROR_RX 0x0040
584#define PORT_MIRROR_TX 0x0020
585#define PORT_USER_PRIORITY_CEILING 0x0008
586#define PORT_VLAN_MEMBERSHIP 0x0007
587
588#define KS8842_PORT_CTRL_VID_OFFSET 0x04
589
590#define PORT_DEFAULT_VID 0x0001
591
592#define KS8842_PORT_CTRL_3_OFFSET 0x06
593
594#define PORT_INGRESS_LIMIT_MODE 0x000C
595#define PORT_INGRESS_ALL 0x0000
596#define PORT_INGRESS_UNICAST 0x0004
597#define PORT_INGRESS_MULTICAST 0x0008
598#define PORT_INGRESS_BROADCAST 0x000C
599#define PORT_COUNT_IFG 0x0002
600#define PORT_COUNT_PREAMBLE 0x0001
601
602#define KS8842_PORT_IN_RATE_OFFSET 0x08
603#define KS8842_PORT_OUT_RATE_OFFSET 0x0A
604
605#define PORT_PRIORITY_RATE 0x0F
606#define PORT_PRIORITY_RATE_SHIFT 4
607
608#define KS884X_PORT_LINK_MD 0x10
609
610#define PORT_CABLE_10M_SHORT 0x8000
611#define PORT_CABLE_DIAG_RESULT 0x6000
612#define PORT_CABLE_STAT_NORMAL 0x0000
613#define PORT_CABLE_STAT_OPEN 0x2000
614#define PORT_CABLE_STAT_SHORT 0x4000
615#define PORT_CABLE_STAT_FAILED 0x6000
616#define PORT_START_CABLE_DIAG 0x1000
617#define PORT_FORCE_LINK 0x0800
618#define PORT_POWER_SAVING_DISABLE 0x0400
619#define PORT_PHY_REMOTE_LOOPBACK 0x0200
620#define PORT_CABLE_FAULT_COUNTER 0x01FF
621
622#define KS884X_PORT_CTRL_4_OFFSET 0x12
623
624#define PORT_LED_OFF 0x8000
625#define PORT_TX_DISABLE 0x4000
626#define PORT_AUTO_NEG_RESTART 0x2000
627#define PORT_REMOTE_FAULT_DISABLE 0x1000
628#define PORT_POWER_DOWN 0x0800
629#define PORT_AUTO_MDIX_DISABLE 0x0400
630#define PORT_FORCE_MDIX 0x0200
631#define PORT_LOOPBACK 0x0100
632#define PORT_AUTO_NEG_ENABLE 0x0080
633#define PORT_FORCE_100_MBIT 0x0040
634#define PORT_FORCE_FULL_DUPLEX 0x0020
635#define PORT_AUTO_NEG_SYM_PAUSE 0x0010
636#define PORT_AUTO_NEG_100BTX_FD 0x0008
637#define PORT_AUTO_NEG_100BTX 0x0004
638#define PORT_AUTO_NEG_10BT_FD 0x0002
639#define PORT_AUTO_NEG_10BT 0x0001
640
641#define KS884X_PORT_STATUS_OFFSET 0x14
642
643#define PORT_HP_MDIX 0x8000
644#define PORT_REVERSED_POLARITY 0x2000
645#define PORT_RX_FLOW_CTRL 0x0800
646#define PORT_TX_FLOW_CTRL 0x1000
647#define PORT_STATUS_SPEED_100MBIT 0x0400
648#define PORT_STATUS_FULL_DUPLEX 0x0200
649#define PORT_REMOTE_FAULT 0x0100
650#define PORT_MDIX_STATUS 0x0080
651#define PORT_AUTO_NEG_COMPLETE 0x0040
652#define PORT_STATUS_LINK_GOOD 0x0020
653#define PORT_REMOTE_SYM_PAUSE 0x0010
654#define PORT_REMOTE_100BTX_FD 0x0008
655#define PORT_REMOTE_100BTX 0x0004
656#define PORT_REMOTE_10BT_FD 0x0002
657#define PORT_REMOTE_10BT 0x0001
658
659/*
660#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
661#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
662#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
663#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
664#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
665#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
666*/
667
668#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
669#define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
670#define STATIC_MAC_TABLE_VALID 0x00080000
671#define STATIC_MAC_TABLE_OVERRIDE 0x00100000
672#define STATIC_MAC_TABLE_USE_FID 0x00200000
673#define STATIC_MAC_TABLE_FID 0x03C00000
674
675#define STATIC_MAC_FWD_PORTS_SHIFT 16
676#define STATIC_MAC_FID_SHIFT 22
677
678/*
679#define VLAN_TABLE_VID 00-00000000-00000FFF
680#define VLAN_TABLE_FID 00-00000000-0000F000
681#define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
682#define VLAN_TABLE_VALID 00-00000000-00080000
683*/
684
685#define VLAN_TABLE_VID 0x00000FFF
686#define VLAN_TABLE_FID 0x0000F000
687#define VLAN_TABLE_MEMBERSHIP 0x00070000
688#define VLAN_TABLE_VALID 0x00080000
689
690#define VLAN_TABLE_FID_SHIFT 12
691#define VLAN_TABLE_MEMBERSHIP_SHIFT 16
692
693/*
694#define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
695#define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
696#define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
697#define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
698#define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
699#define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
700#define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
701#define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
702*/
703
704#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
705#define DYNAMIC_MAC_TABLE_FID 0x000F0000
706#define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
707#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
708#define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
709
710#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
711#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
712#define DYNAMIC_MAC_TABLE_RESERVED 0x78
713#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
714
715#define DYNAMIC_MAC_FID_SHIFT 16
716#define DYNAMIC_MAC_SRC_PORT_SHIFT 20
717#define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
718#define DYNAMIC_MAC_ENTRIES_SHIFT 24
719#define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
720
721/*
722#define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
723#define MIB_COUNTER_VALID 00-00000000-40000000
724#define MIB_COUNTER_OVERFLOW 00-00000000-80000000
725*/
726
727#define MIB_COUNTER_VALUE 0x3FFFFFFF
728#define MIB_COUNTER_VALID 0x40000000
729#define MIB_COUNTER_OVERFLOW 0x80000000
730
731#define MIB_PACKET_DROPPED 0x0000FFFF
732
733#define KS_MIB_PACKET_DROPPED_TX_0 0x100
734#define KS_MIB_PACKET_DROPPED_TX_1 0x101
735#define KS_MIB_PACKET_DROPPED_TX 0x102
736#define KS_MIB_PACKET_DROPPED_RX_0 0x103
737#define KS_MIB_PACKET_DROPPED_RX_1 0x104
738#define KS_MIB_PACKET_DROPPED_RX 0x105
739
740/* Change default LED mode. */
741#define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
742
743#define MAC_ADDR_LEN 6
744#define MAC_ADDR_ORDER(i) (MAC_ADDR_LEN - 1 - (i))
745
746#define MAX_ETHERNET_BODY_SIZE 1500
747#define ETHERNET_HEADER_SIZE 14
748
749#define MAX_ETHERNET_PACKET_SIZE \
750 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
751
752#define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
753#define MAX_RX_BUF_SIZE (1912 + 4)
754
755#define ADDITIONAL_ENTRIES 16
756#define MAX_MULTICAST_LIST 32
757
758#define HW_MULTICAST_SIZE 8
759
760#define HW_TO_DEV_PORT(port) (port - 1)
761
762enum {
763 media_connected,
764 media_disconnected
765};
766
767enum {
768 OID_COUNTER_UNKOWN,
769
770 OID_COUNTER_FIRST,
771
772 /* total transmit errors */
773 OID_COUNTER_XMIT_ERROR,
774
775 /* total receive errors */
776 OID_COUNTER_RCV_ERROR,
777
778 OID_COUNTER_LAST
779};
780
781/*
782 * Hardware descriptor definitions
783 */
784
785#define DESC_ALIGNMENT 16
786#define BUFFER_ALIGNMENT 8
787
788#define NUM_OF_RX_DESC 64
789#define NUM_OF_TX_DESC 64
790
791#define KS_DESC_RX_FRAME_LEN 0x000007FF
792#define KS_DESC_RX_FRAME_TYPE 0x00008000
793#define KS_DESC_RX_ERROR_CRC 0x00010000
794#define KS_DESC_RX_ERROR_RUNT 0x00020000
795#define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
796#define KS_DESC_RX_ERROR_PHY 0x00080000
797#define KS884X_DESC_RX_PORT_MASK 0x00300000
798#define KS_DESC_RX_MULTICAST 0x01000000
799#define KS_DESC_RX_ERROR 0x02000000
800#define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
801#define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
802#define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
803#define KS_DESC_RX_LAST 0x20000000
804#define KS_DESC_RX_FIRST 0x40000000
805#define KS_DESC_RX_ERROR_COND \
806 (KS_DESC_RX_ERROR_CRC | \
807 KS_DESC_RX_ERROR_RUNT | \
808 KS_DESC_RX_ERROR_PHY | \
809 KS_DESC_RX_ERROR_TOO_LONG)
810
811#define KS_DESC_HW_OWNED 0x80000000
812
813#define KS_DESC_BUF_SIZE 0x000007FF
814#define KS884X_DESC_TX_PORT_MASK 0x00300000
815#define KS_DESC_END_OF_RING 0x02000000
816#define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
817#define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
818#define KS_DESC_TX_CSUM_GEN_IP 0x10000000
819#define KS_DESC_TX_LAST 0x20000000
820#define KS_DESC_TX_FIRST 0x40000000
821#define KS_DESC_TX_INTERRUPT 0x80000000
822
823#define KS_DESC_PORT_SHIFT 20
824
825#define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
826
827#define KS_DESC_TX_MASK \
828 (KS_DESC_TX_INTERRUPT | \
829 KS_DESC_TX_FIRST | \
830 KS_DESC_TX_LAST | \
831 KS_DESC_TX_CSUM_GEN_IP | \
832 KS_DESC_TX_CSUM_GEN_TCP | \
833 KS_DESC_TX_CSUM_GEN_UDP | \
834 KS_DESC_BUF_SIZE)
835
836struct ksz_desc_rx_stat {
837#ifdef __BIG_ENDIAN_BITFIELD
838 u32 hw_owned:1;
839 u32 first_desc:1;
840 u32 last_desc:1;
841 u32 csum_err_ip:1;
842 u32 csum_err_tcp:1;
843 u32 csum_err_udp:1;
844 u32 error:1;
845 u32 multicast:1;
846 u32 src_port:4;
847 u32 err_phy:1;
848 u32 err_too_long:1;
849 u32 err_runt:1;
850 u32 err_crc:1;
851 u32 frame_type:1;
852 u32 reserved1:4;
853 u32 frame_len:11;
854#else
855 u32 frame_len:11;
856 u32 reserved1:4;
857 u32 frame_type:1;
858 u32 err_crc:1;
859 u32 err_runt:1;
860 u32 err_too_long:1;
861 u32 err_phy:1;
862 u32 src_port:4;
863 u32 multicast:1;
864 u32 error:1;
865 u32 csum_err_udp:1;
866 u32 csum_err_tcp:1;
867 u32 csum_err_ip:1;
868 u32 last_desc:1;
869 u32 first_desc:1;
870 u32 hw_owned:1;
871#endif
872};
873
874struct ksz_desc_tx_stat {
875#ifdef __BIG_ENDIAN_BITFIELD
876 u32 hw_owned:1;
877 u32 reserved1:31;
878#else
879 u32 reserved1:31;
880 u32 hw_owned:1;
881#endif
882};
883
884struct ksz_desc_rx_buf {
885#ifdef __BIG_ENDIAN_BITFIELD
886 u32 reserved4:6;
887 u32 end_of_ring:1;
888 u32 reserved3:14;
889 u32 buf_size:11;
890#else
891 u32 buf_size:11;
892 u32 reserved3:14;
893 u32 end_of_ring:1;
894 u32 reserved4:6;
895#endif
896};
897
898struct ksz_desc_tx_buf {
899#ifdef __BIG_ENDIAN_BITFIELD
900 u32 intr:1;
901 u32 first_seg:1;
902 u32 last_seg:1;
903 u32 csum_gen_ip:1;
904 u32 csum_gen_tcp:1;
905 u32 csum_gen_udp:1;
906 u32 end_of_ring:1;
907 u32 reserved4:1;
908 u32 dest_port:4;
909 u32 reserved3:9;
910 u32 buf_size:11;
911#else
912 u32 buf_size:11;
913 u32 reserved3:9;
914 u32 dest_port:4;
915 u32 reserved4:1;
916 u32 end_of_ring:1;
917 u32 csum_gen_udp:1;
918 u32 csum_gen_tcp:1;
919 u32 csum_gen_ip:1;
920 u32 last_seg:1;
921 u32 first_seg:1;
922 u32 intr:1;
923#endif
924};
925
926union desc_stat {
927 struct ksz_desc_rx_stat rx;
928 struct ksz_desc_tx_stat tx;
929 u32 data;
930};
931
932union desc_buf {
933 struct ksz_desc_rx_buf rx;
934 struct ksz_desc_tx_buf tx;
935 u32 data;
936};
937
938/**
939 * struct ksz_hw_desc - Hardware descriptor data structure
940 * @ctrl: Descriptor control value.
941 * @buf: Descriptor buffer value.
942 * @addr: Physical address of memory buffer.
943 * @next: Pointer to next hardware descriptor.
944 */
945struct ksz_hw_desc {
946 union desc_stat ctrl;
947 union desc_buf buf;
948 u32 addr;
949 u32 next;
950};
951
952/**
953 * struct ksz_sw_desc - Software descriptor data structure
954 * @ctrl: Descriptor control value.
955 * @buf: Descriptor buffer value.
956 * @buf_size: Current buffers size value in hardware descriptor.
957 */
958struct ksz_sw_desc {
959 union desc_stat ctrl;
960 union desc_buf buf;
961 u32 buf_size;
962};
963
964/**
965 * struct ksz_dma_buf - OS dependent DMA buffer data structure
966 * @skb: Associated socket buffer.
967 * @dma: Associated physical DMA address.
968 * len: Actual len used.
969 */
970struct ksz_dma_buf {
971 struct sk_buff *skb;
972 dma_addr_t dma;
973 int len;
974};
975
976/**
977 * struct ksz_desc - Descriptor structure
978 * @phw: Hardware descriptor pointer to uncached physical memory.
979 * @sw: Cached memory to hold hardware descriptor values for
980 * manipulation.
981 * @dma_buf: Operating system dependent data structure to hold physical
982 * memory buffer allocation information.
983 */
984struct ksz_desc {
985 struct ksz_hw_desc *phw;
986 struct ksz_sw_desc sw;
987 struct ksz_dma_buf dma_buf;
988};
989
990#define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
991
992/**
993 * struct ksz_desc_info - Descriptor information data structure
994 * @ring: First descriptor in the ring.
995 * @cur: Current descriptor being manipulated.
996 * @ring_virt: First hardware descriptor in the ring.
997 * @ring_phys: The physical address of the first descriptor of the ring.
998 * @size: Size of hardware descriptor.
999 * @alloc: Number of descriptors allocated.
1000 * @avail: Number of descriptors available for use.
1001 * @last: Index for last descriptor released to hardware.
1002 * @next: Index for next descriptor available for use.
1003 * @mask: Mask for index wrapping.
1004 */
1005struct ksz_desc_info {
1006 struct ksz_desc *ring;
1007 struct ksz_desc *cur;
1008 struct ksz_hw_desc *ring_virt;
1009 u32 ring_phys;
1010 int size;
1011 int alloc;
1012 int avail;
1013 int last;
1014 int next;
1015 int mask;
1016};
1017
1018/*
1019 * KSZ8842 switch definitions
1020 */
1021
1022enum {
1023 TABLE_STATIC_MAC = 0,
1024 TABLE_VLAN,
1025 TABLE_DYNAMIC_MAC,
1026 TABLE_MIB
1027};
1028
1029#define LEARNED_MAC_TABLE_ENTRIES 1024
1030#define STATIC_MAC_TABLE_ENTRIES 8
1031
1032/**
1033 * struct ksz_mac_table - Static MAC table data structure
1034 * @mac_addr: MAC address to filter.
1035 * @vid: VID value.
1036 * @fid: FID value.
1037 * @ports: Port membership.
1038 * @override: Override setting.
1039 * @use_fid: FID use setting.
1040 * @valid: Valid setting indicating the entry is being used.
1041 */
1042struct ksz_mac_table {
1043 u8 mac_addr[MAC_ADDR_LEN];
1044 u16 vid;
1045 u8 fid;
1046 u8 ports;
1047 u8 override:1;
1048 u8 use_fid:1;
1049 u8 valid:1;
1050};
1051
1052#define VLAN_TABLE_ENTRIES 16
1053
1054/**
1055 * struct ksz_vlan_table - VLAN table data structure
1056 * @vid: VID value.
1057 * @fid: FID value.
1058 * @member: Port membership.
1059 */
1060struct ksz_vlan_table {
1061 u16 vid;
1062 u8 fid;
1063 u8 member;
1064};
1065
1066#define DIFFSERV_ENTRIES 64
1067#define PRIO_802_1P_ENTRIES 8
1068#define PRIO_QUEUES 4
1069
1070#define SWITCH_PORT_NUM 2
1071#define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1072#define HOST_MASK (1 << SWITCH_PORT_NUM)
1073#define PORT_MASK 7
1074
1075#define MAIN_PORT 0
1076#define OTHER_PORT 1
1077#define HOST_PORT SWITCH_PORT_NUM
1078
1079#define PORT_COUNTER_NUM 0x20
1080#define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1081
1082#define MIB_COUNTER_RX_LO_PRIORITY 0x00
1083#define MIB_COUNTER_RX_HI_PRIORITY 0x01
1084#define MIB_COUNTER_RX_UNDERSIZE 0x02
1085#define MIB_COUNTER_RX_FRAGMENT 0x03
1086#define MIB_COUNTER_RX_OVERSIZE 0x04
1087#define MIB_COUNTER_RX_JABBER 0x05
1088#define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1089#define MIB_COUNTER_RX_CRC_ERR 0x07
1090#define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1091#define MIB_COUNTER_RX_CTRL_8808 0x09
1092#define MIB_COUNTER_RX_PAUSE 0x0A
1093#define MIB_COUNTER_RX_BROADCAST 0x0B
1094#define MIB_COUNTER_RX_MULTICAST 0x0C
1095#define MIB_COUNTER_RX_UNICAST 0x0D
1096#define MIB_COUNTER_RX_OCTET_64 0x0E
1097#define MIB_COUNTER_RX_OCTET_65_127 0x0F
1098#define MIB_COUNTER_RX_OCTET_128_255 0x10
1099#define MIB_COUNTER_RX_OCTET_256_511 0x11
1100#define MIB_COUNTER_RX_OCTET_512_1023 0x12
1101#define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1102#define MIB_COUNTER_TX_LO_PRIORITY 0x14
1103#define MIB_COUNTER_TX_HI_PRIORITY 0x15
1104#define MIB_COUNTER_TX_LATE_COLLISION 0x16
1105#define MIB_COUNTER_TX_PAUSE 0x17
1106#define MIB_COUNTER_TX_BROADCAST 0x18
1107#define MIB_COUNTER_TX_MULTICAST 0x19
1108#define MIB_COUNTER_TX_UNICAST 0x1A
1109#define MIB_COUNTER_TX_DEFERRED 0x1B
1110#define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1111#define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1112#define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1113#define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1114
1115#define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1116#define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1117
1118/**
1119 * struct ksz_port_mib - Port MIB data structure
1120 * @cnt_ptr: Current pointer to MIB counter index.
1121 * @link_down: Indication the link has just gone down.
1122 * @state: Connection status of the port.
1123 * @mib_start: The starting counter index. Some ports do not start at 0.
1124 * @counter: 64-bit MIB counter value.
1125 * @dropped: Temporary buffer to remember last read packet dropped values.
1126 *
1127 * MIB counters needs to be read periodically so that counters do not get
1128 * overflowed and give incorrect values. A right balance is needed to
1129 * satisfy this condition and not waste too much CPU time.
1130 *
1131 * It is pointless to read MIB counters when the port is disconnected. The
1132 * @state provides the connection status so that MIB counters are read only
1133 * when the port is connected. The @link_down indicates the port is just
1134 * disconnected so that all MIB counters are read one last time to update the
1135 * information.
1136 */
1137struct ksz_port_mib {
1138 u8 cnt_ptr;
1139 u8 link_down;
1140 u8 state;
1141 u8 mib_start;
1142
1143 u64 counter[TOTAL_PORT_COUNTER_NUM];
1144 u32 dropped[2];
1145};
1146
1147/**
1148 * struct ksz_port_cfg - Port configuration data structure
1149 * @vid: VID value.
1150 * @member: Port membership.
1151 * @port_prio: Port priority.
1152 * @rx_rate: Receive priority rate.
1153 * @tx_rate: Transmit priority rate.
1154 * @stp_state: Current Spanning Tree Protocol state.
1155 */
1156struct ksz_port_cfg {
1157 u16 vid;
1158 u8 member;
1159 u8 port_prio;
1160 u32 rx_rate[PRIO_QUEUES];
1161 u32 tx_rate[PRIO_QUEUES];
1162 int stp_state;
1163};
1164
1165/**
1166 * struct ksz_switch - KSZ8842 switch data structure
1167 * @mac_table: MAC table entries information.
1168 * @vlan_table: VLAN table entries information.
1169 * @port_cfg: Port configuration information.
1170 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1171 * (bit7 ~ bit2) field.
1172 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1173 * Tag priority field.
1174 * @br_addr: Bridge address. Used for STP.
1175 * @other_addr: Other MAC address. Used for multiple network device mode.
1176 * @broad_per: Broadcast storm percentage.
1177 * @member: Current port membership. Used for STP.
1178 */
1179struct ksz_switch {
1180 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1181 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1182 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1183
1184 u8 diffserv[DIFFSERV_ENTRIES];
1185 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1186
1187 u8 br_addr[MAC_ADDR_LEN];
1188 u8 other_addr[MAC_ADDR_LEN];
1189
1190 u8 broad_per;
1191 u8 member;
1192};
1193
1194#define TX_RATE_UNIT 10000
1195
1196/**
1197 * struct ksz_port_info - Port information data structure
1198 * @state: Connection status of the port.
1199 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1200 * @duplex: Duplex mode.
1201 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1202 * @partner: Auto-negotiation partner setting. Used to determine link.
1203 * @port_id: Port index to access actual hardware register.
1204 * @pdev: Pointer to OS dependent network device.
1205 */
1206struct ksz_port_info {
1207 uint state;
1208 uint tx_rate;
1209 u8 duplex;
1210 u8 advertised;
1211 u8 partner;
1212 u8 port_id;
1213 void *pdev;
1214};
1215
1216#define MAX_TX_HELD_SIZE 52000
1217
1218/* Hardware features and bug fixes. */
1219#define LINK_INT_WORKING (1 << 0)
1220#define SMALL_PACKET_TX_BUG (1 << 1)
1221#define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1222#define IPV6_CSUM_GEN_HACK (1 << 3)
1223#define RX_HUGE_FRAME (1 << 4)
1224#define STP_SUPPORT (1 << 8)
1225
1226/* Software overrides. */
1227#define PAUSE_FLOW_CTRL (1 << 0)
1228#define FAST_AGING (1 << 1)
1229
1230/**
1231 * struct ksz_hw - KSZ884X hardware data structure
1232 * @io: Virtual address assigned.
1233 * @ksz_switch: Pointer to KSZ8842 switch.
1234 * @port_info: Port information.
1235 * @port_mib: Port MIB information.
1236 * @dev_count: Number of network devices this hardware supports.
1237 * @dst_ports: Destination ports in switch for transmission.
1238 * @id: Hardware ID. Used for display only.
1239 * @mib_cnt: Number of MIB counters this hardware has.
1240 * @mib_port_cnt: Number of ports with MIB counters.
1241 * @tx_cfg: Cached transmit control settings.
1242 * @rx_cfg: Cached receive control settings.
1243 * @intr_mask: Current interrupt mask.
1244 * @intr_set: Current interrup set.
1245 * @intr_blocked: Interrupt blocked.
1246 * @rx_desc_info: Receive descriptor information.
1247 * @tx_desc_info: Transmit descriptor information.
1248 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1249 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1250 * @tx_size: Transmit data size. Used for TX optimization.
1251 * The maximum is defined by MAX_TX_HELD_SIZE.
1252 * @perm_addr: Permanent MAC address.
1253 * @override_addr: Overrided MAC address.
1254 * @address: Additional MAC address entries.
1255 * @addr_list_size: Additional MAC address list size.
1256 * @mac_override: Indication of MAC address overrided.
1257 * @promiscuous: Counter to keep track of promiscuous mode set.
1258 * @all_multi: Counter to keep track of all multicast mode set.
1259 * @multi_list: Multicast address entries.
1260 * @multi_bits: Cached multicast hash table settings.
1261 * @multi_list_size: Multicast address list size.
1262 * @enabled: Indication of hardware enabled.
1263 * @rx_stop: Indication of receive process stop.
1264 * @features: Hardware features to enable.
1265 * @overrides: Hardware features to override.
1266 * @parent: Pointer to parent, network device private structure.
1267 */
1268struct ksz_hw {
1269 void __iomem *io;
1270
1271 struct ksz_switch *ksz_switch;
1272 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1273 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1274 int dev_count;
1275 int dst_ports;
1276 int id;
1277 int mib_cnt;
1278 int mib_port_cnt;
1279
1280 u32 tx_cfg;
1281 u32 rx_cfg;
1282 u32 intr_mask;
1283 u32 intr_set;
1284 uint intr_blocked;
1285
1286 struct ksz_desc_info rx_desc_info;
1287 struct ksz_desc_info tx_desc_info;
1288
1289 int tx_int_cnt;
1290 int tx_int_mask;
1291 int tx_size;
1292
1293 u8 perm_addr[MAC_ADDR_LEN];
1294 u8 override_addr[MAC_ADDR_LEN];
1295 u8 address[ADDITIONAL_ENTRIES][MAC_ADDR_LEN];
1296 u8 addr_list_size;
1297 u8 mac_override;
1298 u8 promiscuous;
1299 u8 all_multi;
1300 u8 multi_list[MAX_MULTICAST_LIST][MAC_ADDR_LEN];
1301 u8 multi_bits[HW_MULTICAST_SIZE];
1302 u8 multi_list_size;
1303
1304 u8 enabled;
1305 u8 rx_stop;
1306 u8 reserved2[1];
1307
1308 uint features;
1309 uint overrides;
1310
1311 void *parent;
1312};
1313
1314enum {
1315 PHY_NO_FLOW_CTRL,
1316 PHY_FLOW_CTRL,
1317 PHY_TX_ONLY,
1318 PHY_RX_ONLY
1319};
1320
1321/**
1322 * struct ksz_port - Virtual port data structure
1323 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1324 * duplex, and 0 for auto, which normally results in full
1325 * duplex.
1326 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1327 * 0 for auto, which normally results in 100 Mbit.
1328 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1329 * force.
1330 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1331 * control, and PHY_FLOW_CTRL for flow control.
1332 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1333 * Mbit PHY.
1334 * @first_port: Index of first port this port supports.
1335 * @mib_port_cnt: Number of ports with MIB counters.
1336 * @port_cnt: Number of ports this port supports.
1337 * @counter: Port statistics counter.
1338 * @hw: Pointer to hardware structure.
1339 * @linked: Pointer to port information linked to this port.
1340 */
1341struct ksz_port {
1342 u8 duplex;
1343 u8 speed;
1344 u8 force_link;
1345 u8 flow_ctrl;
1346
1347 int first_port;
1348 int mib_port_cnt;
1349 int port_cnt;
1350 u64 counter[OID_COUNTER_LAST];
1351
1352 struct ksz_hw *hw;
1353 struct ksz_port_info *linked;
1354};
1355
1356/**
1357 * struct ksz_timer_info - Timer information data structure
1358 * @timer: Kernel timer.
1359 * @cnt: Running timer counter.
1360 * @max: Number of times to run timer; -1 for infinity.
1361 * @period: Timer period in jiffies.
1362 */
1363struct ksz_timer_info {
1364 struct timer_list timer;
1365 int cnt;
1366 int max;
1367 int period;
1368};
1369
1370/**
1371 * struct ksz_shared_mem - OS dependent shared memory data structure
1372 * @dma_addr: Physical DMA address allocated.
1373 * @alloc_size: Allocation size.
1374 * @phys: Actual physical address used.
1375 * @alloc_virt: Virtual address allocated.
1376 * @virt: Actual virtual address used.
1377 */
1378struct ksz_shared_mem {
1379 dma_addr_t dma_addr;
1380 uint alloc_size;
1381 uint phys;
1382 u8 *alloc_virt;
1383 u8 *virt;
1384};
1385
1386/**
1387 * struct ksz_counter_info - OS dependent counter information data structure
1388 * @counter: Wait queue to wakeup after counters are read.
1389 * @time: Next time in jiffies to read counter.
1390 * @read: Indication of counters read in full or not.
1391 */
1392struct ksz_counter_info {
1393 wait_queue_head_t counter;
1394 unsigned long time;
1395 int read;
1396};
1397
1398/**
1399 * struct dev_info - Network device information data structure
1400 * @dev: Pointer to network device.
1401 * @pdev: Pointer to PCI device.
1402 * @hw: Hardware structure.
1403 * @desc_pool: Physical memory used for descriptor pool.
1404 * @hwlock: Spinlock to prevent hardware from accessing.
1405 * @lock: Mutex lock to prevent device from accessing.
1406 * @dev_rcv: Receive process function used.
1407 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1408 * @skb_index: Buffer index for receiving fragments.
1409 * @skb_len: Buffer length for receiving fragments.
1410 * @mib_read: Workqueue to read MIB counters.
1411 * @mib_timer_info: Timer to read MIB counters.
1412 * @counter: Used for MIB reading.
1413 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1414 * the maximum is MAX_RX_BUF_SIZE.
1415 * @opened: Counter to keep track of device open.
1416 * @rx_tasklet: Receive processing tasklet.
1417 * @tx_tasklet: Transmit processing tasklet.
1418 * @wol_enable: Wake-on-LAN enable set by ethtool.
1419 * @wol_support: Wake-on-LAN support used by ethtool.
1420 * @pme_wait: Used for KSZ8841 power management.
1421 */
1422struct dev_info {
1423 struct net_device *dev;
1424 struct pci_dev *pdev;
1425
1426 struct ksz_hw hw;
1427 struct ksz_shared_mem desc_pool;
1428
1429 spinlock_t hwlock;
1430 struct mutex lock;
1431
1432 int (*dev_rcv)(struct dev_info *);
1433
1434 struct sk_buff *last_skb;
1435 int skb_index;
1436 int skb_len;
1437
1438 struct work_struct mib_read;
1439 struct ksz_timer_info mib_timer_info;
1440 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1441
1442 int mtu;
1443 int opened;
1444
1445 struct tasklet_struct rx_tasklet;
1446 struct tasklet_struct tx_tasklet;
1447
1448 int wol_enable;
1449 int wol_support;
1450 unsigned long pme_wait;
1451};
1452
1453/**
1454 * struct dev_priv - Network device private data structure
1455 * @adapter: Adapter device information.
1456 * @port: Port information.
1457 * @monitor_time_info: Timer to monitor ports.
1458 * @stats: Network statistics.
1459 * @proc_sem: Semaphore for proc accessing.
1460 * @id: Device ID.
1461 * @mii_if: MII interface information.
1462 * @advertising: Temporary variable to store advertised settings.
1463 * @msg_enable: The message flags controlling driver output.
1464 * @media_state: The connection status of the device.
1465 * @multicast: The all multicast state of the device.
1466 * @promiscuous: The promiscuous state of the device.
1467 */
1468struct dev_priv {
1469 struct dev_info *adapter;
1470 struct ksz_port port;
1471 struct ksz_timer_info monitor_timer_info;
1472 struct net_device_stats stats;
1473
1474 struct semaphore proc_sem;
1475 int id;
1476
1477 struct mii_if_info mii_if;
1478 u32 advertising;
1479
1480 u32 msg_enable;
1481 int media_state;
1482 int multicast;
1483 int promiscuous;
1484};
1485
1486#define ks_info(_ks, _msg...) dev_info(&(_ks)->pdev->dev, _msg)
1487#define ks_warn(_ks, _msg...) dev_warn(&(_ks)->pdev->dev, _msg)
1488#define ks_dbg(_ks, _msg...) dev_dbg(&(_ks)->pdev->dev, _msg)
1489#define ks_err(_ks, _msg...) dev_err(&(_ks)->pdev->dev, _msg)
1490
1491#define DRV_NAME "KSZ884X PCI"
1492#define DEVICE_NAME "KSZ884x PCI"
1493#define DRV_VERSION "1.0.0"
1494#define DRV_RELDATE "Feb 8, 2010"
1495
1496static char version[] __devinitdata =
1497 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1498
1499static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1500
1501/*
1502 * Interrupt processing primary routines
1503 */
1504
1505static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1506{
1507 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1508}
1509
1510static inline void hw_dis_intr(struct ksz_hw *hw)
1511{
1512 hw->intr_blocked = hw->intr_mask;
1513 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1514 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1515}
1516
1517static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1518{
1519 hw->intr_set = interrupt;
1520 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1521}
1522
1523static inline void hw_ena_intr(struct ksz_hw *hw)
1524{
1525 hw->intr_blocked = 0;
1526 hw_set_intr(hw, hw->intr_mask);
1527}
1528
1529static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1530{
1531 hw->intr_mask &= ~(bit);
1532}
1533
1534static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1535{
1536 u32 read_intr;
1537
1538 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1539 hw->intr_set = read_intr & ~interrupt;
1540 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1541 hw_dis_intr_bit(hw, interrupt);
1542}
1543
1544/**
1545 * hw_turn_on_intr - turn on specified interrupts
1546 * @hw: The hardware instance.
1547 * @bit: The interrupt bits to be on.
1548 *
1549 * This routine turns on the specified interrupts in the interrupt mask so that
1550 * those interrupts will be enabled.
1551 */
1552static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1553{
1554 hw->intr_mask |= bit;
1555
1556 if (!hw->intr_blocked)
1557 hw_set_intr(hw, hw->intr_mask);
1558}
1559
1560static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1561{
1562 u32 read_intr;
1563
1564 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1565 hw->intr_set = read_intr | interrupt;
1566 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1567}
1568
1569static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1570{
1571 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1572 *status = *status & hw->intr_set;
1573}
1574
1575static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1576{
1577 if (interrupt)
1578 hw_ena_intr(hw);
1579}
1580
1581/**
1582 * hw_block_intr - block hardware interrupts
1583 *
1584 * This function blocks all interrupts of the hardware and returns the current
1585 * interrupt enable mask so that interrupts can be restored later.
1586 *
1587 * Return the current interrupt enable mask.
1588 */
1589static uint hw_block_intr(struct ksz_hw *hw)
1590{
1591 uint interrupt = 0;
1592
1593 if (!hw->intr_blocked) {
1594 hw_dis_intr(hw);
1595 interrupt = hw->intr_blocked;
1596 }
1597 return interrupt;
1598}
1599
1600/*
1601 * Hardware descriptor routines
1602 */
1603
1604static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1605{
1606 status.rx.hw_owned = 0;
1607 desc->phw->ctrl.data = cpu_to_le32(status.data);
1608}
1609
1610static inline void release_desc(struct ksz_desc *desc)
1611{
1612 desc->sw.ctrl.tx.hw_owned = 1;
1613 if (desc->sw.buf_size != desc->sw.buf.data) {
1614 desc->sw.buf_size = desc->sw.buf.data;
1615 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1616 }
1617 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1618}
1619
1620static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1621{
1622 *desc = &info->ring[info->last];
1623 info->last++;
1624 info->last &= info->mask;
1625 info->avail--;
1626 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1627}
1628
1629static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1630{
1631 desc->phw->addr = cpu_to_le32(addr);
1632}
1633
1634static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1635{
1636 desc->sw.buf.rx.buf_size = len;
1637}
1638
1639static inline void get_tx_pkt(struct ksz_desc_info *info,
1640 struct ksz_desc **desc)
1641{
1642 *desc = &info->ring[info->next];
1643 info->next++;
1644 info->next &= info->mask;
1645 info->avail--;
1646 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1647}
1648
1649static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1650{
1651 desc->phw->addr = cpu_to_le32(addr);
1652}
1653
1654static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1655{
1656 desc->sw.buf.tx.buf_size = len;
1657}
1658
1659/* Switch functions */
1660
1661#define TABLE_READ 0x10
1662#define TABLE_SEL_SHIFT 2
1663
1664#define HW_DELAY(hw, reg) \
1665 do { \
1666 u16 dummy; \
1667 dummy = readw(hw->io + reg); \
1668 } while (0)
1669
1670/**
1671 * sw_r_table - read 4 bytes of data from switch table
1672 * @hw: The hardware instance.
1673 * @table: The table selector.
1674 * @addr: The address of the table entry.
1675 * @data: Buffer to store the read data.
1676 *
1677 * This routine reads 4 bytes of data from the table of the switch.
1678 * Hardware interrupts are disabled to minimize corruption of read data.
1679 */
1680static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1681{
1682 u16 ctrl_addr;
1683 uint interrupt;
1684
1685 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1686
1687 interrupt = hw_block_intr(hw);
1688
1689 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1690 HW_DELAY(hw, KS884X_IACR_OFFSET);
1691 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1692
1693 hw_restore_intr(hw, interrupt);
1694}
1695
1696/**
1697 * sw_w_table_64 - write 8 bytes of data to the switch table
1698 * @hw: The hardware instance.
1699 * @table: The table selector.
1700 * @addr: The address of the table entry.
1701 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1702 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1703 *
1704 * This routine writes 8 bytes of data to the table of the switch.
1705 * Hardware interrupts are disabled to minimize corruption of written data.
1706 */
1707static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1708 u32 data_lo)
1709{
1710 u16 ctrl_addr;
1711 uint interrupt;
1712
1713 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1714
1715 interrupt = hw_block_intr(hw);
1716
1717 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1718 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1719
1720 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1721 HW_DELAY(hw, KS884X_IACR_OFFSET);
1722
1723 hw_restore_intr(hw, interrupt);
1724}
1725
1726/**
1727 * sw_w_sta_mac_table - write to the static MAC table
1728 * @hw: The hardware instance.
1729 * @addr: The address of the table entry.
1730 * @mac_addr: The MAC address.
1731 * @ports: The port members.
1732 * @override: The flag to override the port receive/transmit settings.
1733 * @valid: The flag to indicate entry is valid.
1734 * @use_fid: The flag to indicate the FID is valid.
1735 * @fid: The FID value.
1736 *
1737 * This routine writes an entry of the static MAC table of the switch. It
1738 * calls sw_w_table_64() to write the data.
1739 */
1740static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1741 u8 ports, int override, int valid, int use_fid, u8 fid)
1742{
1743 u32 data_hi;
1744 u32 data_lo;
1745
1746 data_lo = ((u32) mac_addr[2] << 24) |
1747 ((u32) mac_addr[3] << 16) |
1748 ((u32) mac_addr[4] << 8) | mac_addr[5];
1749 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1750 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1751
1752 if (override)
1753 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1754 if (use_fid) {
1755 data_hi |= STATIC_MAC_TABLE_USE_FID;
1756 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1757 }
1758 if (valid)
1759 data_hi |= STATIC_MAC_TABLE_VALID;
1760
1761 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1762}
1763
1764/**
1765 * sw_r_vlan_table - read from the VLAN table
1766 * @hw: The hardware instance.
1767 * @addr: The address of the table entry.
1768 * @vid: Buffer to store the VID.
1769 * @fid: Buffer to store the VID.
1770 * @member: Buffer to store the port membership.
1771 *
1772 * This function reads an entry of the VLAN table of the switch. It calls
1773 * sw_r_table() to get the data.
1774 *
1775 * Return 0 if the entry is valid; otherwise -1.
1776 */
1777static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1778 u8 *member)
1779{
1780 u32 data;
1781
1782 sw_r_table(hw, TABLE_VLAN, addr, &data);
1783 if (data & VLAN_TABLE_VALID) {
1784 *vid = (u16)(data & VLAN_TABLE_VID);
1785 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1786 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1787 VLAN_TABLE_MEMBERSHIP_SHIFT);
1788 return 0;
1789 }
1790 return -1;
1791}
1792
1793/**
1794 * port_r_mib_cnt - read MIB counter
1795 * @hw: The hardware instance.
1796 * @port: The port index.
1797 * @addr: The address of the counter.
1798 * @cnt: Buffer to store the counter.
1799 *
1800 * This routine reads a MIB counter of the port.
1801 * Hardware interrupts are disabled to minimize corruption of read data.
1802 */
1803static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1804{
1805 u32 data;
1806 u16 ctrl_addr;
1807 uint interrupt;
1808 int timeout;
1809
1810 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1811
1812 interrupt = hw_block_intr(hw);
1813
1814 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1815 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1816 HW_DELAY(hw, KS884X_IACR_OFFSET);
1817
1818 for (timeout = 100; timeout > 0; timeout--) {
1819 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1820
1821 if (data & MIB_COUNTER_VALID) {
1822 if (data & MIB_COUNTER_OVERFLOW)
1823 *cnt += MIB_COUNTER_VALUE + 1;
1824 *cnt += data & MIB_COUNTER_VALUE;
1825 break;
1826 }
1827 }
1828
1829 hw_restore_intr(hw, interrupt);
1830}
1831
1832/**
1833 * port_r_mib_pkt - read dropped packet counts
1834 * @hw: The hardware instance.
1835 * @port: The port index.
1836 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1837 *
1838 * This routine reads the dropped packet counts of the port.
1839 * Hardware interrupts are disabled to minimize corruption of read data.
1840 */
1841static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1842{
1843 u32 cur;
1844 u32 data;
1845 u16 ctrl_addr;
1846 uint interrupt;
1847 int index;
1848
1849 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1850 do {
1851 interrupt = hw_block_intr(hw);
1852
1853 ctrl_addr = (u16) index;
1854 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1855 << 8);
1856 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1857 HW_DELAY(hw, KS884X_IACR_OFFSET);
1858 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1859
1860 hw_restore_intr(hw, interrupt);
1861
1862 data &= MIB_PACKET_DROPPED;
1863 cur = *last;
1864 if (data != cur) {
1865 *last = data;
1866 if (data < cur)
1867 data += MIB_PACKET_DROPPED + 1;
1868 data -= cur;
1869 *cnt += data;
1870 }
1871 ++last;
1872 ++cnt;
1873 index -= KS_MIB_PACKET_DROPPED_TX -
1874 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1875 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1876}
1877
1878/**
1879 * port_r_cnt - read MIB counters periodically
1880 * @hw: The hardware instance.
1881 * @port: The port index.
1882 *
1883 * This routine is used to read the counters of the port periodically to avoid
1884 * counter overflow. The hardware should be acquired first before calling this
1885 * routine.
1886 *
1887 * Return non-zero when not all counters not read.
1888 */
1889static int port_r_cnt(struct ksz_hw *hw, int port)
1890{
1891 struct ksz_port_mib *mib = &hw->port_mib[port];
1892
1893 if (mib->mib_start < PORT_COUNTER_NUM)
1894 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1895 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1896 &mib->counter[mib->cnt_ptr]);
1897 ++mib->cnt_ptr;
1898 }
1899 if (hw->mib_cnt > PORT_COUNTER_NUM)
1900 port_r_mib_pkt(hw, port, mib->dropped,
1901 &mib->counter[PORT_COUNTER_NUM]);
1902 mib->cnt_ptr = 0;
1903 return 0;
1904}
1905
1906/**
1907 * port_init_cnt - initialize MIB counter values
1908 * @hw: The hardware instance.
1909 * @port: The port index.
1910 *
1911 * This routine is used to initialize all counters to zero if the hardware
1912 * cannot do it after reset.
1913 */
1914static void port_init_cnt(struct ksz_hw *hw, int port)
1915{
1916 struct ksz_port_mib *mib = &hw->port_mib[port];
1917
1918 mib->cnt_ptr = 0;
1919 if (mib->mib_start < PORT_COUNTER_NUM)
1920 do {
1921 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1922 &mib->counter[mib->cnt_ptr]);
1923 ++mib->cnt_ptr;
1924 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1925 if (hw->mib_cnt > PORT_COUNTER_NUM)
1926 port_r_mib_pkt(hw, port, mib->dropped,
1927 &mib->counter[PORT_COUNTER_NUM]);
1928 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1929 mib->cnt_ptr = 0;
1930}
1931
1932/*
1933 * Port functions
1934 */
1935
1936/**
1937 * port_chk - check port register bits
1938 * @hw: The hardware instance.
1939 * @port: The port index.
1940 * @offset: The offset of the port register.
1941 * @bits: The data bits to check.
1942 *
1943 * This function checks whether the specified bits of the port register are set
1944 * or not.
1945 *
1946 * Return 0 if the bits are not set.
1947 */
1948static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1949{
1950 u32 addr;
1951 u16 data;
1952
1953 PORT_CTRL_ADDR(port, addr);
1954 addr += offset;
1955 data = readw(hw->io + addr);
1956 return (data & bits) == bits;
1957}
1958
1959/**
1960 * port_cfg - set port register bits
1961 * @hw: The hardware instance.
1962 * @port: The port index.
1963 * @offset: The offset of the port register.
1964 * @bits: The data bits to set.
1965 * @set: The flag indicating whether the bits are to be set or not.
1966 *
1967 * This routine sets or resets the specified bits of the port register.
1968 */
1969static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1970 int set)
1971{
1972 u32 addr;
1973 u16 data;
1974
1975 PORT_CTRL_ADDR(port, addr);
1976 addr += offset;
1977 data = readw(hw->io + addr);
1978 if (set)
1979 data |= bits;
1980 else
1981 data &= ~bits;
1982 writew(data, hw->io + addr);
1983}
1984
1985/**
1986 * port_chk_shift - check port bit
1987 * @hw: The hardware instance.
1988 * @port: The port index.
1989 * @offset: The offset of the register.
1990 * @shift: Number of bits to shift.
1991 *
1992 * This function checks whether the specified port is set in the register or
1993 * not.
1994 *
1995 * Return 0 if the port is not set.
1996 */
1997static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1998{
1999 u16 data;
2000 u16 bit = 1 << port;
2001
2002 data = readw(hw->io + addr);
2003 data >>= shift;
2004 return (data & bit) == bit;
2005}
2006
2007/**
2008 * port_cfg_shift - set port bit
2009 * @hw: The hardware instance.
2010 * @port: The port index.
2011 * @offset: The offset of the register.
2012 * @shift: Number of bits to shift.
2013 * @set: The flag indicating whether the port is to be set or not.
2014 *
2015 * This routine sets or resets the specified port in the register.
2016 */
2017static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2018 int set)
2019{
2020 u16 data;
2021 u16 bits = 1 << port;
2022
2023 data = readw(hw->io + addr);
2024 bits <<= shift;
2025 if (set)
2026 data |= bits;
2027 else
2028 data &= ~bits;
2029 writew(data, hw->io + addr);
2030}
2031
2032/**
2033 * port_r8 - read byte from port register
2034 * @hw: The hardware instance.
2035 * @port: The port index.
2036 * @offset: The offset of the port register.
2037 * @data: Buffer to store the data.
2038 *
2039 * This routine reads a byte from the port register.
2040 */
2041static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2042{
2043 u32 addr;
2044
2045 PORT_CTRL_ADDR(port, addr);
2046 addr += offset;
2047 *data = readb(hw->io + addr);
2048}
2049
2050/**
2051 * port_r16 - read word from port register.
2052 * @hw: The hardware instance.
2053 * @port: The port index.
2054 * @offset: The offset of the port register.
2055 * @data: Buffer to store the data.
2056 *
2057 * This routine reads a word from the port register.
2058 */
2059static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2060{
2061 u32 addr;
2062
2063 PORT_CTRL_ADDR(port, addr);
2064 addr += offset;
2065 *data = readw(hw->io + addr);
2066}
2067
2068/**
2069 * port_w16 - write word to port register.
2070 * @hw: The hardware instance.
2071 * @port: The port index.
2072 * @offset: The offset of the port register.
2073 * @data: Data to write.
2074 *
2075 * This routine writes a word to the port register.
2076 */
2077static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2078{
2079 u32 addr;
2080
2081 PORT_CTRL_ADDR(port, addr);
2082 addr += offset;
2083 writew(data, hw->io + addr);
2084}
2085
2086/**
2087 * sw_chk - check switch register bits
2088 * @hw: The hardware instance.
2089 * @addr: The address of the switch register.
2090 * @bits: The data bits to check.
2091 *
2092 * This function checks whether the specified bits of the switch register are
2093 * set or not.
2094 *
2095 * Return 0 if the bits are not set.
2096 */
2097static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2098{
2099 u16 data;
2100
2101 data = readw(hw->io + addr);
2102 return (data & bits) == bits;
2103}
2104
2105/**
2106 * sw_cfg - set switch register bits
2107 * @hw: The hardware instance.
2108 * @addr: The address of the switch register.
2109 * @bits: The data bits to set.
2110 * @set: The flag indicating whether the bits are to be set or not.
2111 *
2112 * This function sets or resets the specified bits of the switch register.
2113 */
2114static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2115{
2116 u16 data;
2117
2118 data = readw(hw->io + addr);
2119 if (set)
2120 data |= bits;
2121 else
2122 data &= ~bits;
2123 writew(data, hw->io + addr);
2124}
2125
2126/* Bandwidth */
2127
2128static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2129{
2130 port_cfg(hw, p,
2131 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2132}
2133
2134static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2135{
2136 return port_chk(hw, p,
2137 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2138}
2139
2140/* Driver set switch broadcast storm protection at 10% rate. */
2141#define BROADCAST_STORM_PROTECTION_RATE 10
2142
2143/* 148,800 frames * 67 ms / 100 */
2144#define BROADCAST_STORM_VALUE 9969
2145
2146/**
2147 * sw_cfg_broad_storm - configure broadcast storm threshold
2148 * @hw: The hardware instance.
2149 * @percent: Broadcast storm threshold in percent of transmit rate.
2150 *
2151 * This routine configures the broadcast storm threshold of the switch.
2152 */
2153static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2154{
2155 u16 data;
2156 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2157
2158 if (value > BROADCAST_STORM_RATE)
2159 value = BROADCAST_STORM_RATE;
2160
2161 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2162 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2163 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2164 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2165}
2166
2167/**
2168 * sw_get_board_storm - get broadcast storm threshold
2169 * @hw: The hardware instance.
2170 * @percent: Buffer to store the broadcast storm threshold percentage.
2171 *
2172 * This routine retrieves the broadcast storm threshold of the switch.
2173 */
2174static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2175{
2176 int num;
2177 u16 data;
2178
2179 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2180 num = (data & BROADCAST_STORM_RATE_HI);
2181 num <<= 8;
2182 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2183 num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE;
2184 *percent = (u8) num;
2185}
2186
2187/**
2188 * sw_dis_broad_storm - disable broadstorm
2189 * @hw: The hardware instance.
2190 * @port: The port index.
2191 *
2192 * This routine disables the broadcast storm limit function of the switch.
2193 */
2194static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2195{
2196 port_cfg_broad_storm(hw, port, 0);
2197}
2198
2199/**
2200 * sw_ena_broad_storm - enable broadcast storm
2201 * @hw: The hardware instance.
2202 * @port: The port index.
2203 *
2204 * This routine enables the broadcast storm limit function of the switch.
2205 */
2206static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2207{
2208 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2209 port_cfg_broad_storm(hw, port, 1);
2210}
2211
2212/**
2213 * sw_init_broad_storm - initialize broadcast storm
2214 * @hw: The hardware instance.
2215 *
2216 * This routine initializes the broadcast storm limit function of the switch.
2217 */
2218static void sw_init_broad_storm(struct ksz_hw *hw)
2219{
2220 int port;
2221
2222 hw->ksz_switch->broad_per = 1;
2223 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2224 for (port = 0; port < TOTAL_PORT_NUM; port++)
2225 sw_dis_broad_storm(hw, port);
2226 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2227}
2228
2229/**
2230 * hw_cfg_broad_storm - configure broadcast storm
2231 * @hw: The hardware instance.
2232 * @percent: Broadcast storm threshold in percent of transmit rate.
2233 *
2234 * This routine configures the broadcast storm threshold of the switch.
2235 * It is called by user functions. The hardware should be acquired first.
2236 */
2237static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2238{
2239 if (percent > 100)
2240 percent = 100;
2241
2242 sw_cfg_broad_storm(hw, percent);
2243 sw_get_broad_storm(hw, &percent);
2244 hw->ksz_switch->broad_per = percent;
2245}
2246
2247/**
2248 * sw_dis_prio_rate - disable switch priority rate
2249 * @hw: The hardware instance.
2250 * @port: The port index.
2251 *
2252 * This routine disables the priority rate function of the switch.
2253 */
2254static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2255{
2256 u32 addr;
2257
2258 PORT_CTRL_ADDR(port, addr);
2259 addr += KS8842_PORT_IN_RATE_OFFSET;
2260 writel(0, hw->io + addr);
2261}
2262
2263/**
2264 * sw_init_prio_rate - initialize switch prioirty rate
2265 * @hw: The hardware instance.
2266 *
2267 * This routine initializes the priority rate function of the switch.
2268 */
2269static void sw_init_prio_rate(struct ksz_hw *hw)
2270{
2271 int port;
2272 int prio;
2273 struct ksz_switch *sw = hw->ksz_switch;
2274
2275 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2276 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2277 sw->port_cfg[port].rx_rate[prio] =
2278 sw->port_cfg[port].tx_rate[prio] = 0;
2279 }
2280 sw_dis_prio_rate(hw, port);
2281 }
2282}
2283
2284/* Communication */
2285
2286static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2287{
2288 port_cfg(hw, p,
2289 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2290}
2291
2292static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2293{
2294 port_cfg(hw, p,
2295 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2296}
2297
2298static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2299{
2300 return port_chk(hw, p,
2301 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2302}
2303
2304static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2305{
2306 return port_chk(hw, p,
2307 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2308}
2309
2310/* Spanning Tree */
2311
2312static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set)
2313{
2314 port_cfg(hw, p,
2315 KS8842_PORT_CTRL_2_OFFSET, PORT_LEARN_DISABLE, set);
2316}
2317
2318static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2319{
2320 port_cfg(hw, p,
2321 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2322}
2323
2324static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2325{
2326 port_cfg(hw, p,
2327 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2328}
2329
2330static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2331{
2332 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2333}
2334
2335static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2336{
2337 if (!(hw->overrides & FAST_AGING)) {
2338 sw_cfg_fast_aging(hw, 1);
2339 mdelay(1);
2340 sw_cfg_fast_aging(hw, 0);
2341 }
2342}
2343
2344/* VLAN */
2345
2346static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2347{
2348 port_cfg(hw, p,
2349 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2350}
2351
2352static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2353{
2354 port_cfg(hw, p,
2355 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2356}
2357
2358static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2359{
2360 return port_chk(hw, p,
2361 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2362}
2363
2364static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2365{
2366 return port_chk(hw, p,
2367 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2368}
2369
2370static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2371{
2372 port_cfg(hw, p,
2373 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2374}
2375
2376static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2377{
2378 port_cfg(hw, p,
2379 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2380}
2381
2382static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2383{
2384 return port_chk(hw, p,
2385 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2386}
2387
2388static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2389{
2390 return port_chk(hw, p,
2391 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2392}
2393
2394/* Mirroring */
2395
2396static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2397{
2398 port_cfg(hw, p,
2399 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2400}
2401
2402static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2403{
2404 port_cfg(hw, p,
2405 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2406}
2407
2408static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2409{
2410 port_cfg(hw, p,
2411 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2412}
2413
2414static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2415{
2416 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2417}
2418
2419static void sw_init_mirror(struct ksz_hw *hw)
2420{
2421 int port;
2422
2423 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2424 port_cfg_mirror_sniffer(hw, port, 0);
2425 port_cfg_mirror_rx(hw, port, 0);
2426 port_cfg_mirror_tx(hw, port, 0);
2427 }
2428 sw_cfg_mirror_rx_tx(hw, 0);
2429}
2430
2431static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2432{
2433 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2434 SWITCH_UNK_DEF_PORT_ENABLE, set);
2435}
2436
2437static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2438{
2439 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2440 SWITCH_UNK_DEF_PORT_ENABLE);
2441}
2442
2443static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2444{
2445 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2446}
2447
2448static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2449{
2450 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2451}
2452
2453/* Priority */
2454
2455static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2456{
2457 port_cfg(hw, p,
2458 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2459}
2460
2461static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2462{
2463 port_cfg(hw, p,
2464 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2465}
2466
2467static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2468{
2469 port_cfg(hw, p,
2470 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2471}
2472
2473static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2474{
2475 port_cfg(hw, p,
2476 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2477}
2478
2479static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2480{
2481 return port_chk(hw, p,
2482 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2483}
2484
2485static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2486{
2487 return port_chk(hw, p,
2488 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2489}
2490
2491static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2492{
2493 return port_chk(hw, p,
2494 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2495}
2496
2497static inline int port_chk_prio(struct ksz_hw *hw, int p)
2498{
2499 return port_chk(hw, p,
2500 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2501}
2502
2503/**
2504 * sw_dis_diffserv - disable switch DiffServ priority
2505 * @hw: The hardware instance.
2506 * @port: The port index.
2507 *
2508 * This routine disables the DiffServ priority function of the switch.
2509 */
2510static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2511{
2512 port_cfg_diffserv(hw, port, 0);
2513}
2514
2515/**
2516 * sw_dis_802_1p - disable switch 802.1p priority
2517 * @hw: The hardware instance.
2518 * @port: The port index.
2519 *
2520 * This routine disables the 802.1p priority function of the switch.
2521 */
2522static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2523{
2524 port_cfg_802_1p(hw, port, 0);
2525}
2526
2527/**
2528 * sw_cfg_replace_null_vid -
2529 * @hw: The hardware instance.
2530 * @set: The flag to disable or enable.
2531 *
2532 */
2533static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2534{
2535 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2536}
2537
2538/**
2539 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2540 * @hw: The hardware instance.
2541 * @port: The port index.
2542 * @set: The flag to disable or enable.
2543 *
2544 * This routine enables the 802.1p priority re-mapping function of the switch.
2545 * That allows 802.1p priority field to be replaced with the port's default
2546 * tag's priority value if the ingress packet's 802.1p priority has a higher
2547 * priority than port's default tag's priority.
2548 */
2549static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2550{
2551 port_cfg_replace_vid(hw, port, set);
2552}
2553
2554/**
2555 * sw_cfg_port_based - configure switch port based priority
2556 * @hw: The hardware instance.
2557 * @port: The port index.
2558 * @prio: The priority to set.
2559 *
2560 * This routine configures the port based priority of the switch.
2561 */
2562static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2563{
2564 u16 data;
2565
2566 if (prio > PORT_BASED_PRIORITY_BASE)
2567 prio = PORT_BASED_PRIORITY_BASE;
2568
2569 hw->ksz_switch->port_cfg[port].port_prio = prio;
2570
2571 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2572 data &= ~PORT_BASED_PRIORITY_MASK;
2573 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2574 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2575}
2576
2577/**
2578 * sw_dis_multi_queue - disable transmit multiple queues
2579 * @hw: The hardware instance.
2580 * @port: The port index.
2581 *
2582 * This routine disables the transmit multiple queues selection of the switch
2583 * port. Only single transmit queue on the port.
2584 */
2585static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2586{
2587 port_cfg_prio(hw, port, 0);
2588}
2589
2590/**
2591 * sw_init_prio - initialize switch priority
2592 * @hw: The hardware instance.
2593 *
2594 * This routine initializes the switch QoS priority functions.
2595 */
2596static void sw_init_prio(struct ksz_hw *hw)
2597{
2598 int port;
2599 int tos;
2600 struct ksz_switch *sw = hw->ksz_switch;
2601
2602 /*
2603 * Init all the 802.1p tag priority value to be assigned to different
2604 * priority queue.
2605 */
2606 sw->p_802_1p[0] = 0;
2607 sw->p_802_1p[1] = 0;
2608 sw->p_802_1p[2] = 1;
2609 sw->p_802_1p[3] = 1;
2610 sw->p_802_1p[4] = 2;
2611 sw->p_802_1p[5] = 2;
2612 sw->p_802_1p[6] = 3;
2613 sw->p_802_1p[7] = 3;
2614
2615 /*
2616 * Init all the DiffServ priority value to be assigned to priority
2617 * queue 0.
2618 */
2619 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2620 sw->diffserv[tos] = 0;
2621
2622 /* All QoS functions disabled. */
2623 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2624 sw_dis_multi_queue(hw, port);
2625 sw_dis_diffserv(hw, port);
2626 sw_dis_802_1p(hw, port);
2627 sw_cfg_replace_vid(hw, port, 0);
2628
2629 sw->port_cfg[port].port_prio = 0;
2630 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2631 }
2632 sw_cfg_replace_null_vid(hw, 0);
2633}
2634
2635/**
2636 * port_get_def_vid - get port default VID.
2637 * @hw: The hardware instance.
2638 * @port: The port index.
2639 * @vid: Buffer to store the VID.
2640 *
2641 * This routine retrieves the default VID of the port.
2642 */
2643static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2644{
2645 u32 addr;
2646
2647 PORT_CTRL_ADDR(port, addr);
2648 addr += KS8842_PORT_CTRL_VID_OFFSET;
2649 *vid = readw(hw->io + addr);
2650}
2651
2652/**
2653 * sw_init_vlan - initialize switch VLAN
2654 * @hw: The hardware instance.
2655 *
2656 * This routine initializes the VLAN function of the switch.
2657 */
2658static void sw_init_vlan(struct ksz_hw *hw)
2659{
2660 int port;
2661 int entry;
2662 struct ksz_switch *sw = hw->ksz_switch;
2663
2664 /* Read 16 VLAN entries from device's VLAN table. */
2665 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2666 sw_r_vlan_table(hw, entry,
2667 &sw->vlan_table[entry].vid,
2668 &sw->vlan_table[entry].fid,
2669 &sw->vlan_table[entry].member);
2670 }
2671
2672 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2673 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2674 sw->port_cfg[port].member = PORT_MASK;
2675 }
2676}
2677
2678/**
2679 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2680 * @hw: The hardware instance.
2681 * @port: The port index.
2682 * @member: The port-based VLAN membership.
2683 *
2684 * This routine configures the port-based VLAN membership of the port.
2685 */
2686static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2687{
2688 u32 addr;
2689 u8 data;
2690
2691 PORT_CTRL_ADDR(port, addr);
2692 addr += KS8842_PORT_CTRL_2_OFFSET;
2693
2694 data = readb(hw->io + addr);
2695 data &= ~PORT_VLAN_MEMBERSHIP;
2696 data |= (member & PORT_MASK);
2697 writeb(data, hw->io + addr);
2698
2699 hw->ksz_switch->port_cfg[port].member = member;
2700}
2701
2702/**
2703 * sw_get_addr - get the switch MAC address.
2704 * @hw: The hardware instance.
2705 * @mac_addr: Buffer to store the MAC address.
2706 *
2707 * This function retrieves the MAC address of the switch.
2708 */
2709static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2710{
2711 int i;
2712
2713 for (i = 0; i < 6; i += 2) {
2714 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2715 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2716 }
2717}
2718
2719/**
2720 * sw_set_addr - configure switch MAC address
2721 * @hw: The hardware instance.
2722 * @mac_addr: The MAC address.
2723 *
2724 * This function configures the MAC address of the switch.
2725 */
2726static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2727{
2728 int i;
2729
2730 for (i = 0; i < 6; i += 2) {
2731 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2732 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2733 }
2734}
2735
2736/**
2737 * sw_set_global_ctrl - set switch global control
2738 * @hw: The hardware instance.
2739 *
2740 * This routine sets the global control of the switch function.
2741 */
2742static void sw_set_global_ctrl(struct ksz_hw *hw)
2743{
2744 u16 data;
2745
2746 /* Enable switch MII flow control. */
2747 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2748 data |= SWITCH_FLOW_CTRL;
2749 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2750
2751 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2752
2753 /* Enable aggressive back off algorithm in half duplex mode. */
2754 data |= SWITCH_AGGR_BACKOFF;
2755
2756 /* Enable automatic fast aging when link changed detected. */
2757 data |= SWITCH_AGING_ENABLE;
2758 data |= SWITCH_LINK_AUTO_AGING;
2759
2760 if (hw->overrides & FAST_AGING)
2761 data |= SWITCH_FAST_AGING;
2762 else
2763 data &= ~SWITCH_FAST_AGING;
2764 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2765
2766 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2767
2768 /* Enable no excessive collision drop. */
2769 data |= NO_EXC_COLLISION_DROP;
2770 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2771}
2772
2773enum {
2774 STP_STATE_DISABLED = 0,
2775 STP_STATE_LISTENING,
2776 STP_STATE_LEARNING,
2777 STP_STATE_FORWARDING,
2778 STP_STATE_BLOCKED,
2779 STP_STATE_SIMPLE
2780};
2781
2782/**
2783 * port_set_stp_state - configure port spanning tree state
2784 * @hw: The hardware instance.
2785 * @port: The port index.
2786 * @state: The spanning tree state.
2787 *
2788 * This routine configures the spanning tree state of the port.
2789 */
2790static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2791{
2792 u16 data;
2793
2794 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2795 switch (state) {
2796 case STP_STATE_DISABLED:
2797 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2798 data |= PORT_LEARN_DISABLE;
2799 break;
2800 case STP_STATE_LISTENING:
2801/*
2802 * No need to turn on transmit because of port direct mode.
2803 * Turning on receive is required if static MAC table is not setup.
2804 */
2805 data &= ~PORT_TX_ENABLE;
2806 data |= PORT_RX_ENABLE;
2807 data |= PORT_LEARN_DISABLE;
2808 break;
2809 case STP_STATE_LEARNING:
2810 data &= ~PORT_TX_ENABLE;
2811 data |= PORT_RX_ENABLE;
2812 data &= ~PORT_LEARN_DISABLE;
2813 break;
2814 case STP_STATE_FORWARDING:
2815 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2816 data &= ~PORT_LEARN_DISABLE;
2817 break;
2818 case STP_STATE_BLOCKED:
2819/*
2820 * Need to setup static MAC table with override to keep receiving BPDU
2821 * messages. See sw_init_stp routine.
2822 */
2823 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2824 data |= PORT_LEARN_DISABLE;
2825 break;
2826 case STP_STATE_SIMPLE:
2827 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2828 data |= PORT_LEARN_DISABLE;
2829 break;
2830 }
2831 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2832 hw->ksz_switch->port_cfg[port].stp_state = state;
2833}
2834
2835#define STP_ENTRY 0
2836#define BROADCAST_ENTRY 1
2837#define BRIDGE_ADDR_ENTRY 2
2838#define IPV6_ADDR_ENTRY 3
2839
2840/**
2841 * sw_clr_sta_mac_table - clear static MAC table
2842 * @hw: The hardware instance.
2843 *
2844 * This routine clears the static MAC table.
2845 */
2846static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2847{
2848 struct ksz_mac_table *entry;
2849 int i;
2850
2851 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2852 entry = &hw->ksz_switch->mac_table[i];
2853 sw_w_sta_mac_table(hw, i,
2854 entry->mac_addr, entry->ports,
2855 entry->override, 0,
2856 entry->use_fid, entry->fid);
2857 }
2858}
2859
2860/**
2861 * sw_init_stp - initialize switch spanning tree support
2862 * @hw: The hardware instance.
2863 *
2864 * This routine initializes the spanning tree support of the switch.
2865 */
2866static void sw_init_stp(struct ksz_hw *hw)
2867{
2868 struct ksz_mac_table *entry;
2869
2870 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2871 entry->mac_addr[0] = 0x01;
2872 entry->mac_addr[1] = 0x80;
2873 entry->mac_addr[2] = 0xC2;
2874 entry->mac_addr[3] = 0x00;
2875 entry->mac_addr[4] = 0x00;
2876 entry->mac_addr[5] = 0x00;
2877 entry->ports = HOST_MASK;
2878 entry->override = 1;
2879 entry->valid = 1;
2880 sw_w_sta_mac_table(hw, STP_ENTRY,
2881 entry->mac_addr, entry->ports,
2882 entry->override, entry->valid,
2883 entry->use_fid, entry->fid);
2884}
2885
2886/**
2887 * sw_block_addr - block certain packets from the host port
2888 * @hw: The hardware instance.
2889 *
2890 * This routine blocks certain packets from reaching to the host port.
2891 */
2892static void sw_block_addr(struct ksz_hw *hw)
2893{
2894 struct ksz_mac_table *entry;
2895 int i;
2896
2897 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2898 entry = &hw->ksz_switch->mac_table[i];
2899 entry->valid = 0;
2900 sw_w_sta_mac_table(hw, i,
2901 entry->mac_addr, entry->ports,
2902 entry->override, entry->valid,
2903 entry->use_fid, entry->fid);
2904 }
2905}
2906
2907#define PHY_LINK_SUPPORT \
2908 (PHY_AUTO_NEG_ASYM_PAUSE | \
2909 PHY_AUTO_NEG_SYM_PAUSE | \
2910 PHY_AUTO_NEG_100BT4 | \
2911 PHY_AUTO_NEG_100BTX_FD | \
2912 PHY_AUTO_NEG_100BTX | \
2913 PHY_AUTO_NEG_10BT_FD | \
2914 PHY_AUTO_NEG_10BT)
2915
2916static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2917{
2918 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2919}
2920
2921static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2922{
2923 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2924}
2925
2926static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2927{
2928 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2929}
2930
2931static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2932{
2933 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2934}
2935
2936static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2937{
2938 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2939}
2940
2941static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2942{
2943 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2944}
2945
2946static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2947{
2948 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2949}
2950
2951static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2952{
2953 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2954}
2955
2956static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2957{
2958 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2959}
2960
2961static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2962{
2963 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2964}
2965
2966static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2967{
2968 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2969}
2970
2971static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2972{
2973 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2974}
2975
2976/**
2977 * hw_r_phy - read data from PHY register
2978 * @hw: The hardware instance.
2979 * @port: Port to read.
2980 * @reg: PHY register to read.
2981 * @val: Buffer to store the read data.
2982 *
2983 * This routine reads data from the PHY register.
2984 */
2985static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2986{
2987 int phy;
2988
2989 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2990 *val = readw(hw->io + phy);
2991}
2992
2993/**
2994 * port_w_phy - write data to PHY register
2995 * @hw: The hardware instance.
2996 * @port: Port to write.
2997 * @reg: PHY register to write.
2998 * @val: Word data to write.
2999 *
3000 * This routine writes data to the PHY register.
3001 */
3002static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
3003{
3004 int phy;
3005
3006 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
3007 writew(val, hw->io + phy);
3008}
3009
3010/*
3011 * EEPROM access functions
3012 */
3013
3014#define AT93C_CODE 0
3015#define AT93C_WR_OFF 0x00
3016#define AT93C_WR_ALL 0x10
3017#define AT93C_ER_ALL 0x20
3018#define AT93C_WR_ON 0x30
3019
3020#define AT93C_WRITE 1
3021#define AT93C_READ 2
3022#define AT93C_ERASE 3
3023
3024#define EEPROM_DELAY 4
3025
3026static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3027{
3028 u16 data;
3029
3030 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3031 data &= ~gpio;
3032 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3033}
3034
3035static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3036{
3037 u16 data;
3038
3039 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3040 data |= gpio;
3041 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3042}
3043
3044static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3045{
3046 u16 data;
3047
3048 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3049 return (u8)(data & gpio);
3050}
3051
3052static void eeprom_clk(struct ksz_hw *hw)
3053{
3054 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3055 udelay(EEPROM_DELAY);
3056 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3057 udelay(EEPROM_DELAY);
3058}
3059
3060static u16 spi_r(struct ksz_hw *hw)
3061{
3062 int i;
3063 u16 temp = 0;
3064
3065 for (i = 15; i >= 0; i--) {
3066 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3067 udelay(EEPROM_DELAY);
3068
3069 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3070
3071 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3072 udelay(EEPROM_DELAY);
3073 }
3074 return temp;
3075}
3076
3077static void spi_w(struct ksz_hw *hw, u16 data)
3078{
3079 int i;
3080
3081 for (i = 15; i >= 0; i--) {
3082 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3083 drop_gpio(hw, EEPROM_DATA_OUT);
3084 eeprom_clk(hw);
3085 }
3086}
3087
3088static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3089{
3090 int i;
3091
3092 /* Initial start bit */
3093 raise_gpio(hw, EEPROM_DATA_OUT);
3094 eeprom_clk(hw);
3095
3096 /* AT93C operation */
3097 for (i = 1; i >= 0; i--) {
3098 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3099 drop_gpio(hw, EEPROM_DATA_OUT);
3100 eeprom_clk(hw);
3101 }
3102
3103 /* Address location */
3104 for (i = 5; i >= 0; i--) {
3105 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3106 drop_gpio(hw, EEPROM_DATA_OUT);
3107 eeprom_clk(hw);
3108 }
3109}
3110
3111#define EEPROM_DATA_RESERVED 0
3112#define EEPROM_DATA_MAC_ADDR_0 1
3113#define EEPROM_DATA_MAC_ADDR_1 2
3114#define EEPROM_DATA_MAC_ADDR_2 3
3115#define EEPROM_DATA_SUBSYS_ID 4
3116#define EEPROM_DATA_SUBSYS_VEN_ID 5
3117#define EEPROM_DATA_PM_CAP 6
3118
3119/* User defined EEPROM data */
3120#define EEPROM_DATA_OTHER_MAC_ADDR 9
3121
3122/**
3123 * eeprom_read - read from AT93C46 EEPROM
3124 * @hw: The hardware instance.
3125 * @reg: The register offset.
3126 *
3127 * This function reads a word from the AT93C46 EEPROM.
3128 *
3129 * Return the data value.
3130 */
3131static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3132{
3133 u16 data;
3134
3135 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3136
3137 spi_reg(hw, AT93C_READ, reg);
3138 data = spi_r(hw);
3139
3140 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3141
3142 return data;
3143}
3144
3145/**
3146 * eeprom_write - write to AT93C46 EEPROM
3147 * @hw: The hardware instance.
3148 * @reg: The register offset.
3149 * @data: The data value.
3150 *
3151 * This procedure writes a word to the AT93C46 EEPROM.
3152 */
3153static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3154{
3155 int timeout;
3156
3157 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3158
3159 /* Enable write. */
3160 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3161 drop_gpio(hw, EEPROM_CHIP_SELECT);
3162 udelay(1);
3163
3164 /* Erase the register. */
3165 raise_gpio(hw, EEPROM_CHIP_SELECT);
3166 spi_reg(hw, AT93C_ERASE, reg);
3167 drop_gpio(hw, EEPROM_CHIP_SELECT);
3168 udelay(1);
3169
3170 /* Check operation complete. */
3171 raise_gpio(hw, EEPROM_CHIP_SELECT);
3172 timeout = 8;
3173 mdelay(2);
3174 do {
3175 mdelay(1);
3176 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3177 drop_gpio(hw, EEPROM_CHIP_SELECT);
3178 udelay(1);
3179
3180 /* Write the register. */
3181 raise_gpio(hw, EEPROM_CHIP_SELECT);
3182 spi_reg(hw, AT93C_WRITE, reg);
3183 spi_w(hw, data);
3184 drop_gpio(hw, EEPROM_CHIP_SELECT);
3185 udelay(1);
3186
3187 /* Check operation complete. */
3188 raise_gpio(hw, EEPROM_CHIP_SELECT);
3189 timeout = 8;
3190 mdelay(2);
3191 do {
3192 mdelay(1);
3193 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3194 drop_gpio(hw, EEPROM_CHIP_SELECT);
3195 udelay(1);
3196
3197 /* Disable write. */
3198 raise_gpio(hw, EEPROM_CHIP_SELECT);
3199 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3200
3201 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3202}
3203
3204/*
3205 * Link detection routines
3206 */
3207
3208static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3209{
3210 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3211 switch (port->flow_ctrl) {
3212 case PHY_FLOW_CTRL:
3213 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3214 break;
3215 /* Not supported. */
3216 case PHY_TX_ONLY:
3217 case PHY_RX_ONLY:
3218 default:
3219 break;
3220 }
3221 return ctrl;
3222}
3223
3224static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3225{
3226 u32 rx_cfg;
3227 u32 tx_cfg;
3228
3229 rx_cfg = hw->rx_cfg;
3230 tx_cfg = hw->tx_cfg;
3231 if (rx)
3232 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3233 else
3234 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3235 if (tx)
3236 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3237 else
3238 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3239 if (hw->enabled) {
3240 if (rx_cfg != hw->rx_cfg)
3241 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3242 if (tx_cfg != hw->tx_cfg)
3243 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3244 }
3245}
3246
3247static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3248 u16 local, u16 remote)
3249{
3250 int rx;
3251 int tx;
3252
3253 if (hw->overrides & PAUSE_FLOW_CTRL)
3254 return;
3255
3256 rx = tx = 0;
3257 if (port->force_link)
3258 rx = tx = 1;
3259 if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3260 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3261 rx = tx = 1;
3262 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3263 (local & PHY_AUTO_NEG_PAUSE) ==
3264 PHY_AUTO_NEG_ASYM_PAUSE) {
3265 tx = 1;
3266 }
3267 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3268 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3269 rx = 1;
3270 }
3271 if (!hw->ksz_switch)
3272 set_flow_ctrl(hw, rx, tx);
3273}
3274
3275static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3276 struct ksz_port_info *info, u16 link_status)
3277{
3278 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3279 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3280 u32 cfg = hw->tx_cfg;
3281
3282 /* Disable flow control in the half duplex mode. */
3283 if (1 == info->duplex)
3284 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3285 if (hw->enabled && cfg != hw->tx_cfg)
3286 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3287 }
3288}
3289
3290/**
3291 * port_get_link_speed - get current link status
3292 * @port: The port instance.
3293 *
3294 * This routine reads PHY registers to determine the current link status of the
3295 * switch ports.
3296 */
3297static void port_get_link_speed(struct ksz_port *port)
3298{
3299 uint interrupt;
3300 struct ksz_port_info *info;
3301 struct ksz_port_info *linked = NULL;
3302 struct ksz_hw *hw = port->hw;
3303 u16 data;
3304 u16 status;
3305 u8 local;
3306 u8 remote;
3307 int i;
3308 int p;
3309 int change = 0;
3310
3311 interrupt = hw_block_intr(hw);
3312
3313 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3314 info = &hw->port_info[p];
3315 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3316 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3317
3318 /*
3319 * Link status is changing all the time even when there is no
3320 * cable connection!
3321 */
3322 remote = status & (PORT_AUTO_NEG_COMPLETE |
3323 PORT_STATUS_LINK_GOOD);
3324 local = (u8) data;
3325
3326 /* No change to status. */
3327 if (local == info->advertised && remote == info->partner)
3328 continue;
3329
3330 info->advertised = local;
3331 info->partner = remote;
3332 if (status & PORT_STATUS_LINK_GOOD) {
3333
3334 /* Remember the first linked port. */
3335 if (!linked)
3336 linked = info;
3337
3338 info->tx_rate = 10 * TX_RATE_UNIT;
3339 if (status & PORT_STATUS_SPEED_100MBIT)
3340 info->tx_rate = 100 * TX_RATE_UNIT;
3341
3342 info->duplex = 1;
3343 if (status & PORT_STATUS_FULL_DUPLEX)
3344 info->duplex = 2;
3345
3346 if (media_connected != info->state) {
3347 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3348 &data);
3349 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3350 &status);
3351 determine_flow_ctrl(hw, port, data, status);
3352 if (hw->ksz_switch) {
3353 port_cfg_back_pressure(hw, p,
3354 (1 == info->duplex));
3355 }
3356 change |= 1 << i;
3357 port_cfg_change(hw, port, info, status);
3358 }
3359 info->state = media_connected;
3360 } else {
3361 if (media_disconnected != info->state) {
3362 change |= 1 << i;
3363
3364 /* Indicate the link just goes down. */
3365 hw->port_mib[p].link_down = 1;
3366 }
3367 info->state = media_disconnected;
3368 }
3369 hw->port_mib[p].state = (u8) info->state;
3370 }
3371
3372 if (linked && media_disconnected == port->linked->state)
3373 port->linked = linked;
3374
3375 hw_restore_intr(hw, interrupt);
3376}
3377
3378#define PHY_RESET_TIMEOUT 10
3379
3380/**
3381 * port_set_link_speed - set port speed
3382 * @port: The port instance.
3383 *
3384 * This routine sets the link speed of the switch ports.
3385 */
3386static void port_set_link_speed(struct ksz_port *port)
3387{
3388 struct ksz_port_info *info;
3389 struct ksz_hw *hw = port->hw;
3390 u16 data;
3391 u16 cfg;
3392 u8 status;
3393 int i;
3394 int p;
3395
3396 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3397 info = &hw->port_info[p];
3398
3399 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3400 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3401
3402 cfg = 0;
3403 if (status & PORT_STATUS_LINK_GOOD)
3404 cfg = data;
3405
3406 data |= PORT_AUTO_NEG_ENABLE;
3407 data = advertised_flow_ctrl(port, data);
3408
3409 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3410 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3411
3412 /* Check if manual configuration is specified by the user. */
3413 if (port->speed || port->duplex) {
3414 if (10 == port->speed)
3415 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3416 PORT_AUTO_NEG_100BTX);
3417 else if (100 == port->speed)
3418 data &= ~(PORT_AUTO_NEG_10BT_FD |
3419 PORT_AUTO_NEG_10BT);
3420 if (1 == port->duplex)
3421 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3422 PORT_AUTO_NEG_10BT_FD);
3423 else if (2 == port->duplex)
3424 data &= ~(PORT_AUTO_NEG_100BTX |
3425 PORT_AUTO_NEG_10BT);
3426 }
3427 if (data != cfg) {
3428 data |= PORT_AUTO_NEG_RESTART;
3429 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3430 }
3431 }
3432}
3433
3434/**
3435 * port_force_link_speed - force port speed
3436 * @port: The port instance.
3437 *
3438 * This routine forces the link speed of the switch ports.
3439 */
3440static void port_force_link_speed(struct ksz_port *port)
3441{
3442 struct ksz_hw *hw = port->hw;
3443 u16 data;
3444 int i;
3445 int phy;
3446 int p;
3447
3448 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3449 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3450 hw_r_phy_ctrl(hw, phy, &data);
3451
3452 data &= ~PHY_AUTO_NEG_ENABLE;
3453
3454 if (10 == port->speed)
3455 data &= ~PHY_SPEED_100MBIT;
3456 else if (100 == port->speed)
3457 data |= PHY_SPEED_100MBIT;
3458 if (1 == port->duplex)
3459 data &= ~PHY_FULL_DUPLEX;
3460 else if (2 == port->duplex)
3461 data |= PHY_FULL_DUPLEX;
3462 hw_w_phy_ctrl(hw, phy, data);
3463 }
3464}
3465
3466static void port_set_power_saving(struct ksz_port *port, int enable)
3467{
3468 struct ksz_hw *hw = port->hw;
3469 int i;
3470 int p;
3471
3472 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3473 port_cfg(hw, p,
3474 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3475}
3476
3477/*
3478 * KSZ8841 power management functions
3479 */
3480
3481/**
3482 * hw_chk_wol_pme_status - check PMEN pin
3483 * @hw: The hardware instance.
3484 *
3485 * This function is used to check PMEN pin is asserted.
3486 *
3487 * Return 1 if PMEN pin is asserted; otherwise, 0.
3488 */
3489static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3490{
3491 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3492 struct pci_dev *pdev = hw_priv->pdev;
3493 u16 data;
3494
3495 if (!pdev->pm_cap)
3496 return 0;
3497 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3498 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3499}
3500
3501/**
3502 * hw_clr_wol_pme_status - clear PMEN pin
3503 * @hw: The hardware instance.
3504 *
3505 * This routine is used to clear PME_Status to deassert PMEN pin.
3506 */
3507static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3508{
3509 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3510 struct pci_dev *pdev = hw_priv->pdev;
3511 u16 data;
3512
3513 if (!pdev->pm_cap)
3514 return;
3515
3516 /* Clear PME_Status to deassert PMEN pin. */
3517 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3518 data |= PCI_PM_CTRL_PME_STATUS;
3519 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3520}
3521
3522/**
3523 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3524 * @hw: The hardware instance.
3525 * @set: The flag indicating whether to enable or disable.
3526 *
3527 * This routine is used to enable or disable Wake-on-LAN.
3528 */
3529static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3530{
3531 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3532 struct pci_dev *pdev = hw_priv->pdev;
3533 u16 data;
3534
3535 if (!pdev->pm_cap)
3536 return;
3537 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3538 data &= ~PCI_PM_CTRL_STATE_MASK;
3539 if (set)
3540 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3541 else
3542 data &= ~PCI_PM_CTRL_PME_ENABLE;
3543 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3544}
3545
3546/**
3547 * hw_cfg_wol - configure Wake-on-LAN features
3548 * @hw: The hardware instance.
3549 * @frame: The pattern frame bit.
3550 * @set: The flag indicating whether to enable or disable.
3551 *
3552 * This routine is used to enable or disable certain Wake-on-LAN features.
3553 */
3554static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3555{
3556 u16 data;
3557
3558 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3559 if (set)
3560 data |= frame;
3561 else
3562 data &= ~frame;
3563 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3564}
3565
3566/**
3567 * hw_set_wol_frame - program Wake-on-LAN pattern
3568 * @hw: The hardware instance.
3569 * @i: The frame index.
3570 * @mask_size: The size of the mask.
3571 * @mask: Mask to ignore certain bytes in the pattern.
3572 * @frame_size: The size of the frame.
3573 * @pattern: The frame data.
3574 *
3575 * This routine is used to program Wake-on-LAN pattern.
3576 */
3577static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3578 u8 *mask, uint frame_size, u8 *pattern)
3579{
3580 int bits;
3581 int from;
3582 int len;
3583 int to;
3584 u32 crc;
3585 u8 data[64];
3586 u8 val = 0;
3587
3588 if (frame_size > mask_size * 8)
3589 frame_size = mask_size * 8;
3590 if (frame_size > 64)
3591 frame_size = 64;
3592
3593 i *= 0x10;
3594 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3595 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3596
3597 bits = len = from = to = 0;
3598 do {
3599 if (bits) {
3600 if ((val & 1))
3601 data[to++] = pattern[from];
3602 val >>= 1;
3603 ++from;
3604 --bits;
3605 } else {
3606 val = mask[len];
3607 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3608 + len);
3609 ++len;
3610 if (val)
3611 bits = 8;
3612 else
3613 from += 8;
3614 }
3615 } while (from < (int) frame_size);
3616 if (val) {
3617 bits = mask[len - 1];
3618 val <<= (from % 8);
3619 bits &= ~val;
3620 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3621 1);
3622 }
3623 crc = ether_crc(to, data);
3624 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3625}
3626
3627/**
3628 * hw_add_wol_arp - add ARP pattern
3629 * @hw: The hardware instance.
3630 * @ip_addr: The IPv4 address assigned to the device.
3631 *
3632 * This routine is used to add ARP pattern for waking up the host.
3633 */
3634static void hw_add_wol_arp(struct ksz_hw *hw, u8 *ip_addr)
3635{
3636 u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3637 u8 pattern[42] = {
3638 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3639 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3640 0x08, 0x06,
3641 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3643 0x00, 0x00, 0x00, 0x00,
3644 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3645 0x00, 0x00, 0x00, 0x00 };
3646
3647 memcpy(&pattern[38], ip_addr, 4);
3648 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3649}
3650
3651/**
3652 * hw_add_wol_bcast - add broadcast pattern
3653 * @hw: The hardware instance.
3654 *
3655 * This routine is used to add broadcast pattern for waking up the host.
3656 */
3657static void hw_add_wol_bcast(struct ksz_hw *hw)
3658{
3659 u8 mask[] = { 0x3F };
3660 u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3661
3662 hw_set_wol_frame(hw, 2, 1, mask, MAC_ADDR_LEN, pattern);
3663}
3664
3665/**
3666 * hw_add_wol_mcast - add multicast pattern
3667 * @hw: The hardware instance.
3668 *
3669 * This routine is used to add multicast pattern for waking up the host.
3670 *
3671 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3672 * by IPv6 ping command. Note that multicast packets are filtred through the
3673 * multicast hash table, so not all multicast packets can wake up the host.
3674 */
3675static void hw_add_wol_mcast(struct ksz_hw *hw)
3676{
3677 u8 mask[] = { 0x3F };
3678 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3679
3680 memcpy(&pattern[3], &hw->override_addr[3], 3);
3681 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3682}
3683
3684/**
3685 * hw_add_wol_ucast - add unicast pattern
3686 * @hw: The hardware instance.
3687 *
3688 * This routine is used to add unicast pattern to wakeup the host.
3689 *
3690 * It is assumed the unicast packet is directed to the device, as the hardware
3691 * can only receive them in normal case.
3692 */
3693static void hw_add_wol_ucast(struct ksz_hw *hw)
3694{
3695 u8 mask[] = { 0x3F };
3696
3697 hw_set_wol_frame(hw, 0, 1, mask, MAC_ADDR_LEN, hw->override_addr);
3698}
3699
3700/**
3701 * hw_enable_wol - enable Wake-on-LAN
3702 * @hw: The hardware instance.
3703 * @wol_enable: The Wake-on-LAN settings.
3704 * @net_addr: The IPv4 address assigned to the device.
3705 *
3706 * This routine is used to enable Wake-on-LAN depending on driver settings.
3707 */
3708static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, u8 *net_addr)
3709{
3710 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3711 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3712 hw_add_wol_ucast(hw);
3713 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3714 hw_add_wol_mcast(hw);
3715 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3716 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3717 hw_add_wol_arp(hw, net_addr);
3718}
3719
3720/**
3721 * hw_init - check driver is correct for the hardware
3722 * @hw: The hardware instance.
3723 *
3724 * This function checks the hardware is correct for this driver and sets the
3725 * hardware up for proper initialization.
3726 *
3727 * Return number of ports or 0 if not right.
3728 */
3729static int hw_init(struct ksz_hw *hw)
3730{
3731 int rc = 0;
3732 u16 data;
3733 u16 revision;
3734
3735 /* Set bus speed to 125MHz. */
3736 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3737
3738 /* Check KSZ884x chip ID. */
3739 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3740
3741 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3742 data &= KS884X_CHIP_ID_MASK_41;
3743 if (REG_CHIP_ID_41 == data)
3744 rc = 1;
3745 else if (REG_CHIP_ID_42 == data)
3746 rc = 2;
3747 else
3748 return 0;
3749
3750 /* Setup hardware features or bug workarounds. */
3751 if (revision <= 1) {
3752 hw->features |= SMALL_PACKET_TX_BUG;
3753 if (1 == rc)
3754 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3755 }
3756 hw->features |= IPV6_CSUM_GEN_HACK;
3757 return rc;
3758}
3759
3760/**
3761 * hw_reset - reset the hardware
3762 * @hw: The hardware instance.
3763 *
3764 * This routine resets the hardware.
3765 */
3766static void hw_reset(struct ksz_hw *hw)
3767{
3768 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3769
3770 /* Wait for device to reset. */
3771 mdelay(10);
3772
3773 /* Write 0 to clear device reset. */
3774 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3775}
3776
3777/**
3778 * hw_setup - setup the hardware
3779 * @hw: The hardware instance.
3780 *
3781 * This routine setup the hardware for proper operation.
3782 */
3783static void hw_setup(struct ksz_hw *hw)
3784{
3785#if SET_DEFAULT_LED
3786 u16 data;
3787
3788 /* Change default LED mode. */
3789 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3790 data &= ~LED_MODE;
3791 data |= SET_DEFAULT_LED;
3792 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3793#endif
3794
3795 /* Setup transmit control. */
3796 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3797 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3798
3799 /* Setup receive control. */
3800 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3801 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3802 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3803
3804 /* Hardware cannot handle UDP packet in IP fragments. */
3805 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3806
3807 if (hw->all_multi)
3808 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3809 if (hw->promiscuous)
3810 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3811}
3812
3813/**
3814 * hw_setup_intr - setup interrupt mask
3815 * @hw: The hardware instance.
3816 *
3817 * This routine setup the interrupt mask for proper operation.
3818 */
3819static void hw_setup_intr(struct ksz_hw *hw)
3820{
3821 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3822}
3823
3824static void ksz_check_desc_num(struct ksz_desc_info *info)
3825{
3826#define MIN_DESC_SHIFT 2
3827
3828 int alloc = info->alloc;
3829 int shift;
3830
3831 shift = 0;
3832 while (!(alloc & 1)) {
3833 shift++;
3834 alloc >>= 1;
3835 }
3836 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3837 printk(KERN_ALERT "Hardware descriptor numbers not right!\n");
3838 while (alloc) {
3839 shift++;
3840 alloc >>= 1;
3841 }
3842 if (shift < MIN_DESC_SHIFT)
3843 shift = MIN_DESC_SHIFT;
3844 alloc = 1 << shift;
3845 info->alloc = alloc;
3846 }
3847 info->mask = info->alloc - 1;
3848}
3849
3850static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3851{
3852 int i;
3853 u32 phys = desc_info->ring_phys;
3854 struct ksz_hw_desc *desc = desc_info->ring_virt;
3855 struct ksz_desc *cur = desc_info->ring;
3856 struct ksz_desc *previous = NULL;
3857
3858 for (i = 0; i < desc_info->alloc; i++) {
3859 cur->phw = desc++;
3860 phys += desc_info->size;
3861 previous = cur++;
3862 previous->phw->next = cpu_to_le32(phys);
3863 }
3864 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3865 previous->sw.buf.rx.end_of_ring = 1;
3866 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3867
3868 desc_info->avail = desc_info->alloc;
3869 desc_info->last = desc_info->next = 0;
3870
3871 desc_info->cur = desc_info->ring;
3872}
3873
3874/**
3875 * hw_set_desc_base - set descriptor base addresses
3876 * @hw: The hardware instance.
3877 * @tx_addr: The transmit descriptor base.
3878 * @rx_addr: The receive descriptor base.
3879 *
3880 * This routine programs the descriptor base addresses after reset.
3881 */
3882static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3883{
3884 /* Set base address of Tx/Rx descriptors. */
3885 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3886 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3887}
3888
3889static void hw_reset_pkts(struct ksz_desc_info *info)
3890{
3891 info->cur = info->ring;
3892 info->avail = info->alloc;
3893 info->last = info->next = 0;
3894}
3895
3896static inline void hw_resume_rx(struct ksz_hw *hw)
3897{
3898 writel(DMA_START, hw->io + KS_DMA_RX_START);
3899}
3900
3901/**
3902 * hw_start_rx - start receiving
3903 * @hw: The hardware instance.
3904 *
3905 * This routine starts the receive function of the hardware.
3906 */
3907static void hw_start_rx(struct ksz_hw *hw)
3908{
3909 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3910
3911 /* Notify when the receive stops. */
3912 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3913
3914 writel(DMA_START, hw->io + KS_DMA_RX_START);
3915 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3916 hw->rx_stop++;
3917
3918 /* Variable overflows. */
3919 if (0 == hw->rx_stop)
3920 hw->rx_stop = 2;
3921}
3922
3923/*
3924 * hw_stop_rx - stop receiving
3925 * @hw: The hardware instance.
3926 *
3927 * This routine stops the receive function of the hardware.
3928 */
3929static void hw_stop_rx(struct ksz_hw *hw)
3930{
3931 hw->rx_stop = 0;
3932 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3933 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3934}
3935
3936/**
3937 * hw_start_tx - start transmitting
3938 * @hw: The hardware instance.
3939 *
3940 * This routine starts the transmit function of the hardware.
3941 */
3942static void hw_start_tx(struct ksz_hw *hw)
3943{
3944 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3945}
3946
3947/**
3948 * hw_stop_tx - stop transmitting
3949 * @hw: The hardware instance.
3950 *
3951 * This routine stops the transmit function of the hardware.
3952 */
3953static void hw_stop_tx(struct ksz_hw *hw)
3954{
3955 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3956}
3957
3958/**
3959 * hw_disable - disable hardware
3960 * @hw: The hardware instance.
3961 *
3962 * This routine disables the hardware.
3963 */
3964static void hw_disable(struct ksz_hw *hw)
3965{
3966 hw_stop_rx(hw);
3967 hw_stop_tx(hw);
3968 hw->enabled = 0;
3969}
3970
3971/**
3972 * hw_enable - enable hardware
3973 * @hw: The hardware instance.
3974 *
3975 * This routine enables the hardware.
3976 */
3977static void hw_enable(struct ksz_hw *hw)
3978{
3979 hw_start_tx(hw);
3980 hw_start_rx(hw);
3981 hw->enabled = 1;
3982}
3983
3984/**
3985 * hw_alloc_pkt - allocate enough descriptors for transmission
3986 * @hw: The hardware instance.
3987 * @length: The length of the packet.
3988 * @physical: Number of descriptors required.
3989 *
3990 * This function allocates descriptors for transmission.
3991 *
3992 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3993 */
3994static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3995{
3996 /* Always leave one descriptor free. */
3997 if (hw->tx_desc_info.avail <= 1)
3998 return 0;
3999
4000 /* Allocate a descriptor for transmission and mark it current. */
4001 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
4002 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
4003
4004 /* Keep track of number of transmit descriptors used so far. */
4005 ++hw->tx_int_cnt;
4006 hw->tx_size += length;
4007
4008 /* Cannot hold on too much data. */
4009 if (hw->tx_size >= MAX_TX_HELD_SIZE)
4010 hw->tx_int_cnt = hw->tx_int_mask + 1;
4011
4012 if (physical > hw->tx_desc_info.avail)
4013 return 1;
4014
4015 return hw->tx_desc_info.avail;
4016}
4017
4018/**
4019 * hw_send_pkt - mark packet for transmission
4020 * @hw: The hardware instance.
4021 *
4022 * This routine marks the packet for transmission in PCI version.
4023 */
4024static void hw_send_pkt(struct ksz_hw *hw)
4025{
4026 struct ksz_desc *cur = hw->tx_desc_info.cur;
4027
4028 cur->sw.buf.tx.last_seg = 1;
4029
4030 /* Interrupt only after specified number of descriptors used. */
4031 if (hw->tx_int_cnt > hw->tx_int_mask) {
4032 cur->sw.buf.tx.intr = 1;
4033 hw->tx_int_cnt = 0;
4034 hw->tx_size = 0;
4035 }
4036
4037 /* KSZ8842 supports port directed transmission. */
4038 cur->sw.buf.tx.dest_port = hw->dst_ports;
4039
4040 release_desc(cur);
4041
4042 writel(0, hw->io + KS_DMA_TX_START);
4043}
4044
4045static int empty_addr(u8 *addr)
4046{
4047 u32 *addr1 = (u32 *) addr;
4048 u16 *addr2 = (u16 *) &addr[4];
4049
4050 return 0 == *addr1 && 0 == *addr2;
4051}
4052
4053/**
4054 * hw_set_addr - set MAC address
4055 * @hw: The hardware instance.
4056 *
4057 * This routine programs the MAC address of the hardware when the address is
4058 * overrided.
4059 */
4060static void hw_set_addr(struct ksz_hw *hw)
4061{
4062 int i;
4063
4064 for (i = 0; i < MAC_ADDR_LEN; i++)
4065 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4066 hw->io + KS884X_ADDR_0_OFFSET + i);
4067
4068 sw_set_addr(hw, hw->override_addr);
4069}
4070
4071/**
4072 * hw_read_addr - read MAC address
4073 * @hw: The hardware instance.
4074 *
4075 * This routine retrieves the MAC address of the hardware.
4076 */
4077static void hw_read_addr(struct ksz_hw *hw)
4078{
4079 int i;
4080
4081 for (i = 0; i < MAC_ADDR_LEN; i++)
4082 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4083 KS884X_ADDR_0_OFFSET + i);
4084
4085 if (!hw->mac_override) {
4086 memcpy(hw->override_addr, hw->perm_addr, MAC_ADDR_LEN);
4087 if (empty_addr(hw->override_addr)) {
4088 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS,
4089 MAC_ADDR_LEN);
4090 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4091 MAC_ADDR_LEN);
4092 hw->override_addr[5] += hw->id;
4093 hw_set_addr(hw);
4094 }
4095 }
4096}
4097
4098static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4099{
4100 int i;
4101 u32 mac_addr_lo;
4102 u32 mac_addr_hi;
4103
4104 mac_addr_hi = 0;
4105 for (i = 0; i < 2; i++) {
4106 mac_addr_hi <<= 8;
4107 mac_addr_hi |= mac_addr[i];
4108 }
4109 mac_addr_hi |= ADD_ADDR_ENABLE;
4110 mac_addr_lo = 0;
4111 for (i = 2; i < 6; i++) {
4112 mac_addr_lo <<= 8;
4113 mac_addr_lo |= mac_addr[i];
4114 }
4115 index *= ADD_ADDR_INCR;
4116
4117 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4118 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4119}
4120
4121static void hw_set_add_addr(struct ksz_hw *hw)
4122{
4123 int i;
4124
4125 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4126 if (empty_addr(hw->address[i]))
4127 writel(0, hw->io + ADD_ADDR_INCR * i +
4128 KS_ADD_ADDR_0_HI);
4129 else
4130 hw_ena_add_addr(hw, i, hw->address[i]);
4131 }
4132}
4133
4134static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4135{
4136 int i;
4137 int j = ADDITIONAL_ENTRIES;
4138
4139 if (!memcmp(hw->override_addr, mac_addr, MAC_ADDR_LEN))
4140 return 0;
4141 for (i = 0; i < hw->addr_list_size; i++) {
4142 if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN))
4143 return 0;
4144 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4145 j = i;
4146 }
4147 if (j < ADDITIONAL_ENTRIES) {
4148 memcpy(hw->address[j], mac_addr, MAC_ADDR_LEN);
4149 hw_ena_add_addr(hw, j, hw->address[j]);
4150 return 0;
4151 }
4152 return -1;
4153}
4154
4155static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4156{
4157 int i;
4158
4159 for (i = 0; i < hw->addr_list_size; i++) {
4160 if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) {
4161 memset(hw->address[i], 0, MAC_ADDR_LEN);
4162 writel(0, hw->io + ADD_ADDR_INCR * i +
4163 KS_ADD_ADDR_0_HI);
4164 return 0;
4165 }
4166 }
4167 return -1;
4168}
4169
4170/**
4171 * hw_clr_multicast - clear multicast addresses
4172 * @hw: The hardware instance.
4173 *
4174 * This routine removes all multicast addresses set in the hardware.
4175 */
4176static void hw_clr_multicast(struct ksz_hw *hw)
4177{
4178 int i;
4179
4180 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4181 hw->multi_bits[i] = 0;
4182
4183 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4184 }
4185}
4186
4187/**
4188 * hw_set_grp_addr - set multicast addresses
4189 * @hw: The hardware instance.
4190 *
4191 * This routine programs multicast addresses for the hardware to accept those
4192 * addresses.
4193 */
4194static void hw_set_grp_addr(struct ksz_hw *hw)
4195{
4196 int i;
4197 int index;
4198 int position;
4199 int value;
4200
4201 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4202
4203 for (i = 0; i < hw->multi_list_size; i++) {
4204 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4205 index = position >> 3;
4206 value = 1 << (position & 7);
4207 hw->multi_bits[index] |= (u8) value;
4208 }
4209
4210 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4211 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4212 i);
4213}
4214
4215/**
4216 * hw_set_multicast - enable or disable all multicast receiving
4217 * @hw: The hardware instance.
4218 * @multicast: To turn on or off the all multicast feature.
4219 *
4220 * This routine enables/disables the hardware to accept all multicast packets.
4221 */
4222static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4223{
4224 /* Stop receiving for reconfiguration. */
4225 hw_stop_rx(hw);
4226
4227 if (multicast)
4228 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4229 else
4230 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4231
4232 if (hw->enabled)
4233 hw_start_rx(hw);
4234}
4235
4236/**
4237 * hw_set_promiscuous - enable or disable promiscuous receiving
4238 * @hw: The hardware instance.
4239 * @prom: To turn on or off the promiscuous feature.
4240 *
4241 * This routine enables/disables the hardware to accept all packets.
4242 */
4243static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4244{
4245 /* Stop receiving for reconfiguration. */
4246 hw_stop_rx(hw);
4247
4248 if (prom)
4249 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4250 else
4251 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4252
4253 if (hw->enabled)
4254 hw_start_rx(hw);
4255}
4256
4257/**
4258 * sw_enable - enable the switch
4259 * @hw: The hardware instance.
4260 * @enable: The flag to enable or disable the switch
4261 *
4262 * This routine is used to enable/disable the switch in KSZ8842.
4263 */
4264static void sw_enable(struct ksz_hw *hw, int enable)
4265{
4266 int port;
4267
4268 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4269 if (hw->dev_count > 1) {
4270 /* Set port-base vlan membership with host port. */
4271 sw_cfg_port_base_vlan(hw, port,
4272 HOST_MASK | (1 << port));
4273 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4274 } else {
4275 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4276 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4277 }
4278 }
4279 if (hw->dev_count > 1)
4280 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4281 else
4282 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4283
4284 if (enable)
4285 enable = KS8842_START;
4286 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4287}
4288
4289/**
4290 * sw_setup - setup the switch
4291 * @hw: The hardware instance.
4292 *
4293 * This routine setup the hardware switch engine for default operation.
4294 */
4295static void sw_setup(struct ksz_hw *hw)
4296{
4297 int port;
4298
4299 sw_set_global_ctrl(hw);
4300
4301 /* Enable switch broadcast storm protection at 10% percent rate. */
4302 sw_init_broad_storm(hw);
4303 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4304 for (port = 0; port < SWITCH_PORT_NUM; port++)
4305 sw_ena_broad_storm(hw, port);
4306
4307 sw_init_prio(hw);
4308
4309 sw_init_mirror(hw);
4310
4311 sw_init_prio_rate(hw);
4312
4313 sw_init_vlan(hw);
4314
4315 if (hw->features & STP_SUPPORT)
4316 sw_init_stp(hw);
4317 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4318 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4319 hw->overrides |= PAUSE_FLOW_CTRL;
4320 sw_enable(hw, 1);
4321}
4322
4323/**
4324 * ksz_start_timer - start kernel timer
4325 * @info: Kernel timer information.
4326 * @time: The time tick.
4327 *
4328 * This routine starts the kernel timer after the specified time tick.
4329 */
4330static void ksz_start_timer(struct ksz_timer_info *info, int time)
4331{
4332 info->cnt = 0;
4333 info->timer.expires = jiffies + time;
4334 add_timer(&info->timer);
4335
4336 /* infinity */
4337 info->max = -1;
4338}
4339
4340/**
4341 * ksz_stop_timer - stop kernel timer
4342 * @info: Kernel timer information.
4343 *
4344 * This routine stops the kernel timer.
4345 */
4346static void ksz_stop_timer(struct ksz_timer_info *info)
4347{
4348 if (info->max) {
4349 info->max = 0;
4350 del_timer_sync(&info->timer);
4351 }
4352}
4353
4354static void ksz_init_timer(struct ksz_timer_info *info, int period,
4355 void (*function)(unsigned long), void *data)
4356{
4357 info->max = 0;
4358 info->period = period;
4359 init_timer(&info->timer);
4360 info->timer.function = function;
4361 info->timer.data = (unsigned long) data;
4362}
4363
4364static void ksz_update_timer(struct ksz_timer_info *info)
4365{
4366 ++info->cnt;
4367 if (info->max > 0) {
4368 if (info->cnt < info->max) {
4369 info->timer.expires = jiffies + info->period;
4370 add_timer(&info->timer);
4371 } else
4372 info->max = 0;
4373 } else if (info->max < 0) {
4374 info->timer.expires = jiffies + info->period;
4375 add_timer(&info->timer);
4376 }
4377}
4378
4379/**
4380 * ksz_alloc_soft_desc - allocate software descriptors
4381 * @desc_info: Descriptor information structure.
4382 * @transmit: Indication that descriptors are for transmit.
4383 *
4384 * This local function allocates software descriptors for manipulation in
4385 * memory.
4386 *
4387 * Return 0 if successful.
4388 */
4389static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4390{
4391 desc_info->ring = kmalloc(sizeof(struct ksz_desc) * desc_info->alloc,
4392 GFP_KERNEL);
4393 if (!desc_info->ring)
4394 return 1;
4395 memset((void *) desc_info->ring, 0,
4396 sizeof(struct ksz_desc) * desc_info->alloc);
4397 hw_init_desc(desc_info, transmit);
4398 return 0;
4399}
4400
4401/**
4402 * ksz_alloc_desc - allocate hardware descriptors
4403 * @adapter: Adapter information structure.
4404 *
4405 * This local function allocates hardware descriptors for receiving and
4406 * transmitting.
4407 *
4408 * Return 0 if successful.
4409 */
4410static int ksz_alloc_desc(struct dev_info *adapter)
4411{
4412 struct ksz_hw *hw = &adapter->hw;
4413 int offset;
4414
4415 /* Allocate memory for RX & TX descriptors. */
4416 adapter->desc_pool.alloc_size =
4417 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4418 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4419 DESC_ALIGNMENT;
4420
4421 adapter->desc_pool.alloc_virt =
4422 pci_alloc_consistent(
4423 adapter->pdev, adapter->desc_pool.alloc_size,
4424 &adapter->desc_pool.dma_addr);
4425 if (adapter->desc_pool.alloc_virt == NULL) {
4426 adapter->desc_pool.alloc_size = 0;
4427 return 1;
4428 }
4429 memset(adapter->desc_pool.alloc_virt, 0, adapter->desc_pool.alloc_size);
4430
4431 /* Align to the next cache line boundary. */
4432 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4433 (DESC_ALIGNMENT -
4434 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4435 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4436 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4437
4438 /* Allocate receive/transmit descriptors. */
4439 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4440 adapter->desc_pool.virt;
4441 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4442 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4443 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4444 (adapter->desc_pool.virt + offset);
4445 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4446
4447 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4448 return 1;
4449 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4450 return 1;
4451
4452 return 0;
4453}
4454
4455/**
4456 * free_dma_buf - release DMA buffer resources
4457 * @adapter: Adapter information structure.
4458 *
4459 * This routine is just a helper function to release the DMA buffer resources.
4460 */
4461static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4462 int direction)
4463{
4464 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4465 dev_kfree_skb(dma_buf->skb);
4466 dma_buf->skb = NULL;
4467 dma_buf->dma = 0;
4468}
4469
4470/**
4471 * ksz_init_rx_buffers - initialize receive descriptors
4472 * @adapter: Adapter information structure.
4473 *
4474 * This routine initializes DMA buffers for receiving.
4475 */
4476static void ksz_init_rx_buffers(struct dev_info *adapter)
4477{
4478 int i;
4479 struct ksz_desc *desc;
4480 struct ksz_dma_buf *dma_buf;
4481 struct ksz_hw *hw = &adapter->hw;
4482 struct ksz_desc_info *info = &hw->rx_desc_info;
4483
4484 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4485 get_rx_pkt(info, &desc);
4486
4487 dma_buf = DMA_BUFFER(desc);
4488 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4489 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4490 dma_buf->len = adapter->mtu;
4491 if (!dma_buf->skb)
4492 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4493 if (dma_buf->skb && !dma_buf->dma) {
4494 dma_buf->skb->dev = adapter->dev;
4495 dma_buf->dma = pci_map_single(
4496 adapter->pdev,
4497 skb_tail_pointer(dma_buf->skb),
4498 dma_buf->len,
4499 PCI_DMA_FROMDEVICE);
4500 }
4501
4502 /* Set descriptor. */
4503 set_rx_buf(desc, dma_buf->dma);
4504 set_rx_len(desc, dma_buf->len);
4505 release_desc(desc);
4506 }
4507}
4508
4509/**
4510 * ksz_alloc_mem - allocate memory for hardware descriptors
4511 * @adapter: Adapter information structure.
4512 *
4513 * This function allocates memory for use by hardware descriptors for receiving
4514 * and transmitting.
4515 *
4516 * Return 0 if successful.
4517 */
4518static int ksz_alloc_mem(struct dev_info *adapter)
4519{
4520 struct ksz_hw *hw = &adapter->hw;
4521
4522 /* Determine the number of receive and transmit descriptors. */
4523 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4524 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4525
4526 /* Determine how many descriptors to skip transmit interrupt. */
4527 hw->tx_int_cnt = 0;
4528 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4529 if (hw->tx_int_mask > 8)
4530 hw->tx_int_mask = 8;
4531 while (hw->tx_int_mask) {
4532 hw->tx_int_cnt++;
4533 hw->tx_int_mask >>= 1;
4534 }
4535 if (hw->tx_int_cnt) {
4536 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4537 hw->tx_int_cnt = 0;
4538 }
4539
4540 /* Determine the descriptor size. */
4541 hw->rx_desc_info.size =
4542 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4543 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4544 hw->tx_desc_info.size =
4545 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4546 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4547 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4548 printk(KERN_ALERT
4549 "Hardware descriptor size not right!\n");
4550 ksz_check_desc_num(&hw->rx_desc_info);
4551 ksz_check_desc_num(&hw->tx_desc_info);
4552
4553 /* Allocate descriptors. */
4554 if (ksz_alloc_desc(adapter))
4555 return 1;
4556
4557 return 0;
4558}
4559
4560/**
4561 * ksz_free_desc - free software and hardware descriptors
4562 * @adapter: Adapter information structure.
4563 *
4564 * This local routine frees the software and hardware descriptors allocated by
4565 * ksz_alloc_desc().
4566 */
4567static void ksz_free_desc(struct dev_info *adapter)
4568{
4569 struct ksz_hw *hw = &adapter->hw;
4570
4571 /* Reset descriptor. */
4572 hw->rx_desc_info.ring_virt = NULL;
4573 hw->tx_desc_info.ring_virt = NULL;
4574 hw->rx_desc_info.ring_phys = 0;
4575 hw->tx_desc_info.ring_phys = 0;
4576
4577 /* Free memory. */
4578 if (adapter->desc_pool.alloc_virt)
4579 pci_free_consistent(
4580 adapter->pdev,
4581 adapter->desc_pool.alloc_size,
4582 adapter->desc_pool.alloc_virt,
4583 adapter->desc_pool.dma_addr);
4584
4585 /* Reset resource pool. */
4586 adapter->desc_pool.alloc_size = 0;
4587 adapter->desc_pool.alloc_virt = NULL;
4588
4589 kfree(hw->rx_desc_info.ring);
4590 hw->rx_desc_info.ring = NULL;
4591 kfree(hw->tx_desc_info.ring);
4592 hw->tx_desc_info.ring = NULL;
4593}
4594
4595/**
4596 * ksz_free_buffers - free buffers used in the descriptors
4597 * @adapter: Adapter information structure.
4598 * @desc_info: Descriptor information structure.
4599 *
4600 * This local routine frees buffers used in the DMA buffers.
4601 */
4602static void ksz_free_buffers(struct dev_info *adapter,
4603 struct ksz_desc_info *desc_info, int direction)
4604{
4605 int i;
4606 struct ksz_dma_buf *dma_buf;
4607 struct ksz_desc *desc = desc_info->ring;
4608
4609 for (i = 0; i < desc_info->alloc; i++) {
4610 dma_buf = DMA_BUFFER(desc);
4611 if (dma_buf->skb)
4612 free_dma_buf(adapter, dma_buf, direction);
4613 desc++;
4614 }
4615}
4616
4617/**
4618 * ksz_free_mem - free all resources used by descriptors
4619 * @adapter: Adapter information structure.
4620 *
4621 * This local routine frees all the resources allocated by ksz_alloc_mem().
4622 */
4623static void ksz_free_mem(struct dev_info *adapter)
4624{
4625 /* Free transmit buffers. */
4626 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4627 PCI_DMA_TODEVICE);
4628
4629 /* Free receive buffers. */
4630 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4631 PCI_DMA_FROMDEVICE);
4632
4633 /* Free descriptors. */
4634 ksz_free_desc(adapter);
4635}
4636
4637static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4638 u64 *counter)
4639{
4640 int i;
4641 int mib;
4642 int port;
4643 struct ksz_port_mib *port_mib;
4644
4645 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4646 for (i = 0, port = first; i < cnt; i++, port++) {
4647 port_mib = &hw->port_mib[port];
4648 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4649 counter[mib] += port_mib->counter[mib];
4650 }
4651}
4652
4653/**
4654 * send_packet - send packet
4655 * @skb: Socket buffer.
4656 * @dev: Network device.
4657 *
4658 * This routine is used to send a packet out to the network.
4659 */
4660static void send_packet(struct sk_buff *skb, struct net_device *dev)
4661{
4662 struct ksz_desc *desc;
4663 struct ksz_desc *first;
4664 struct dev_priv *priv = netdev_priv(dev);
4665 struct dev_info *hw_priv = priv->adapter;
4666 struct ksz_hw *hw = &hw_priv->hw;
4667 struct ksz_desc_info *info = &hw->tx_desc_info;
4668 struct ksz_dma_buf *dma_buf;
4669 int len;
4670 int last_frag = skb_shinfo(skb)->nr_frags;
4671
4672 /*
4673 * KSZ8842 with multiple device interfaces needs to be told which port
4674 * to send.
4675 */
4676 if (hw->dev_count > 1)
4677 hw->dst_ports = 1 << priv->port.first_port;
4678
4679 /* Hardware will pad the length to 60. */
4680 len = skb->len;
4681
4682 /* Remember the very first descriptor. */
4683 first = info->cur;
4684 desc = first;
4685
4686 dma_buf = DMA_BUFFER(desc);
4687 if (last_frag) {
4688 int frag;
4689 skb_frag_t *this_frag;
4690
4691 dma_buf->len = skb->len - skb->data_len;
4692
4693 dma_buf->dma = pci_map_single(
4694 hw_priv->pdev, skb->data, dma_buf->len,
4695 PCI_DMA_TODEVICE);
4696 set_tx_buf(desc, dma_buf->dma);
4697 set_tx_len(desc, dma_buf->len);
4698
4699 frag = 0;
4700 do {
4701 this_frag = &skb_shinfo(skb)->frags[frag];
4702
4703 /* Get a new descriptor. */
4704 get_tx_pkt(info, &desc);
4705
4706 /* Keep track of descriptors used so far. */
4707 ++hw->tx_int_cnt;
4708
4709 dma_buf = DMA_BUFFER(desc);
4710 dma_buf->len = this_frag->size;
4711
4712 dma_buf->dma = pci_map_single(
4713 hw_priv->pdev,
4714 page_address(this_frag->page) +
4715 this_frag->page_offset,
4716 dma_buf->len,
4717 PCI_DMA_TODEVICE);
4718 set_tx_buf(desc, dma_buf->dma);
4719 set_tx_len(desc, dma_buf->len);
4720
4721 frag++;
4722 if (frag == last_frag)
4723 break;
4724
4725 /* Do not release the last descriptor here. */
4726 release_desc(desc);
4727 } while (1);
4728
4729 /* current points to the last descriptor. */
4730 info->cur = desc;
4731
4732 /* Release the first descriptor. */
4733 release_desc(first);
4734 } else {
4735 dma_buf->len = len;
4736
4737 dma_buf->dma = pci_map_single(
4738 hw_priv->pdev, skb->data, dma_buf->len,
4739 PCI_DMA_TODEVICE);
4740 set_tx_buf(desc, dma_buf->dma);
4741 set_tx_len(desc, dma_buf->len);
4742 }
4743
4744 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4745 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4746 (desc)->sw.buf.tx.csum_gen_udp = 1;
4747 }
4748
4749 /*
4750 * The last descriptor holds the packet so that it can be returned to
4751 * network subsystem after all descriptors are transmitted.
4752 */
4753 dma_buf->skb = skb;
4754
4755 hw_send_pkt(hw);
4756
4757 /* Update transmit statistics. */
4758 priv->stats.tx_packets++;
4759 priv->stats.tx_bytes += len;
4760}
4761
4762/**
4763 * transmit_cleanup - clean up transmit descriptors
4764 * @dev: Network device.
4765 *
4766 * This routine is called to clean up the transmitted buffers.
4767 */
4768static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4769{
4770 int last;
4771 union desc_stat status;
4772 struct ksz_hw *hw = &hw_priv->hw;
4773 struct ksz_desc_info *info = &hw->tx_desc_info;
4774 struct ksz_desc *desc;
4775 struct ksz_dma_buf *dma_buf;
4776 struct net_device *dev = NULL;
4777
4778 spin_lock(&hw_priv->hwlock);
4779 last = info->last;
4780
4781 while (info->avail < info->alloc) {
4782 /* Get next descriptor which is not hardware owned. */
4783 desc = &info->ring[last];
4784 status.data = le32_to_cpu(desc->phw->ctrl.data);
4785 if (status.tx.hw_owned) {
4786 if (normal)
4787 break;
4788 else
4789 reset_desc(desc, status);
4790 }
4791
4792 dma_buf = DMA_BUFFER(desc);
4793 pci_unmap_single(
4794 hw_priv->pdev, dma_buf->dma, dma_buf->len,
4795 PCI_DMA_TODEVICE);
4796
4797 /* This descriptor contains the last buffer in the packet. */
4798 if (dma_buf->skb) {
4799 dev = dma_buf->skb->dev;
4800
4801 /* Release the packet back to network subsystem. */
4802 dev_kfree_skb_irq(dma_buf->skb);
4803 dma_buf->skb = NULL;
4804 }
4805
4806 /* Free the transmitted descriptor. */
4807 last++;
4808 last &= info->mask;
4809 info->avail++;
4810 }
4811 info->last = last;
4812 spin_unlock(&hw_priv->hwlock);
4813
4814 /* Notify the network subsystem that the packet has been sent. */
4815 if (dev)
4816 dev->trans_start = jiffies;
4817}
4818
4819/**
4820 * transmit_done - transmit done processing
4821 * @dev: Network device.
4822 *
4823 * This routine is called when the transmit interrupt is triggered, indicating
4824 * either a packet is sent successfully or there are transmit errors.
4825 */
4826static void tx_done(struct dev_info *hw_priv)
4827{
4828 struct ksz_hw *hw = &hw_priv->hw;
4829 int port;
4830
4831 transmit_cleanup(hw_priv, 1);
4832
4833 for (port = 0; port < hw->dev_count; port++) {
4834 struct net_device *dev = hw->port_info[port].pdev;
4835
4836 if (netif_running(dev) && netif_queue_stopped(dev))
4837 netif_wake_queue(dev);
4838 }
4839}
4840
4841static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4842{
4843 skb->dev = old->dev;
4844 skb->protocol = old->protocol;
4845 skb->ip_summed = old->ip_summed;
4846 skb->csum = old->csum;
4847 skb_set_network_header(skb, ETH_HLEN);
4848
4849 dev_kfree_skb(old);
4850}
4851
4852/**
4853 * netdev_tx - send out packet
4854 * @skb: Socket buffer.
4855 * @dev: Network device.
4856 *
4857 * This function is used by the upper network layer to send out a packet.
4858 *
4859 * Return 0 if successful; otherwise an error code indicating failure.
4860 */
4861static int netdev_tx(struct sk_buff *skb, struct net_device *dev)
4862{
4863 struct dev_priv *priv = netdev_priv(dev);
4864 struct dev_info *hw_priv = priv->adapter;
4865 struct ksz_hw *hw = &hw_priv->hw;
4866 int left;
4867 int num = 1;
4868 int rc = 0;
4869
4870 if (hw->features & SMALL_PACKET_TX_BUG) {
4871 struct sk_buff *org_skb = skb;
4872
4873 if (skb->len <= 48) {
4874 if (skb_end_pointer(skb) - skb->data >= 50) {
4875 memset(&skb->data[skb->len], 0, 50 - skb->len);
4876 skb->len = 50;
4877 } else {
4878 skb = dev_alloc_skb(50);
4879 if (!skb)
4880 return NETDEV_TX_BUSY;
4881 memcpy(skb->data, org_skb->data, org_skb->len);
4882 memset(&skb->data[org_skb->len], 0,
4883 50 - org_skb->len);
4884 skb->len = 50;
4885 copy_old_skb(org_skb, skb);
4886 }
4887 }
4888 }
4889
4890 spin_lock_irq(&hw_priv->hwlock);
4891
4892 num = skb_shinfo(skb)->nr_frags + 1;
4893 left = hw_alloc_pkt(hw, skb->len, num);
4894 if (left) {
4895 if (left < num ||
4896 ((hw->features & IPV6_CSUM_GEN_HACK) &&
4897 (CHECKSUM_PARTIAL == skb->ip_summed) &&
4898 (ETH_P_IPV6 == htons(skb->protocol)))) {
4899 struct sk_buff *org_skb = skb;
4900
4901 skb = dev_alloc_skb(org_skb->len);
4902 if (!skb)
4903 return NETDEV_TX_BUSY;
4904 skb_copy_and_csum_dev(org_skb, skb->data);
4905 org_skb->ip_summed = 0;
4906 skb->len = org_skb->len;
4907 copy_old_skb(org_skb, skb);
4908 }
4909 send_packet(skb, dev);
4910 if (left <= num)
4911 netif_stop_queue(dev);
4912 } else {
4913 /* Stop the transmit queue until packet is allocated. */
4914 netif_stop_queue(dev);
4915 rc = NETDEV_TX_BUSY;
4916 }
4917
4918 spin_unlock_irq(&hw_priv->hwlock);
4919
4920 return rc;
4921}
4922
4923/**
4924 * netdev_tx_timeout - transmit timeout processing
4925 * @dev: Network device.
4926 *
4927 * This routine is called when the transmit timer expires. That indicates the
4928 * hardware is not running correctly because transmit interrupts are not
4929 * triggered to free up resources so that the transmit routine can continue
4930 * sending out packets. The hardware is reset to correct the problem.
4931 */
4932static void netdev_tx_timeout(struct net_device *dev)
4933{
4934 static unsigned long last_reset;
4935
4936 struct dev_priv *priv = netdev_priv(dev);
4937 struct dev_info *hw_priv = priv->adapter;
4938 struct ksz_hw *hw = &hw_priv->hw;
4939 int port;
4940
4941 if (hw->dev_count > 1) {
4942 /*
4943 * Only reset the hardware if time between calls is long
4944 * enough.
4945 */
4946 if (jiffies - last_reset <= dev->watchdog_timeo)
4947 hw_priv = NULL;
4948 }
4949
4950 last_reset = jiffies;
4951 if (hw_priv) {
4952 hw_dis_intr(hw);
4953 hw_disable(hw);
4954
4955 transmit_cleanup(hw_priv, 0);
4956 hw_reset_pkts(&hw->rx_desc_info);
4957 hw_reset_pkts(&hw->tx_desc_info);
4958 ksz_init_rx_buffers(hw_priv);
4959
4960 hw_reset(hw);
4961
4962 hw_set_desc_base(hw,
4963 hw->tx_desc_info.ring_phys,
4964 hw->rx_desc_info.ring_phys);
4965 hw_set_addr(hw);
4966 if (hw->all_multi)
4967 hw_set_multicast(hw, hw->all_multi);
4968 else if (hw->multi_list_size)
4969 hw_set_grp_addr(hw);
4970
4971 if (hw->dev_count > 1) {
4972 hw_set_add_addr(hw);
4973 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4974 struct net_device *port_dev;
4975
4976 port_set_stp_state(hw, port,
4977 STP_STATE_DISABLED);
4978
4979 port_dev = hw->port_info[port].pdev;
4980 if (netif_running(port_dev))
4981 port_set_stp_state(hw, port,
4982 STP_STATE_SIMPLE);
4983 }
4984 }
4985
4986 hw_enable(hw);
4987 hw_ena_intr(hw);
4988 }
4989
4990 dev->trans_start = jiffies;
4991 netif_wake_queue(dev);
4992}
4993
4994static inline void csum_verified(struct sk_buff *skb)
4995{
4996 unsigned short protocol;
4997 struct iphdr *iph;
4998
4999 protocol = skb->protocol;
5000 skb_reset_network_header(skb);
5001 iph = (struct iphdr *) skb_network_header(skb);
5002 if (protocol == htons(ETH_P_8021Q)) {
5003 protocol = iph->tot_len;
5004 skb_set_network_header(skb, VLAN_HLEN);
5005 iph = (struct iphdr *) skb_network_header(skb);
5006 }
5007 if (protocol == htons(ETH_P_IP)) {
5008 if (iph->protocol == IPPROTO_TCP)
5009 skb->ip_summed = CHECKSUM_UNNECESSARY;
5010 }
5011}
5012
5013static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
5014 struct ksz_desc *desc, union desc_stat status)
5015{
5016 int packet_len;
5017 struct dev_priv *priv = netdev_priv(dev);
5018 struct dev_info *hw_priv = priv->adapter;
5019 struct ksz_dma_buf *dma_buf;
5020 struct sk_buff *skb;
5021 int rx_status;
5022
5023 /* Received length includes 4-byte CRC. */
5024 packet_len = status.rx.frame_len - 4;
5025
5026 dma_buf = DMA_BUFFER(desc);
5027 pci_dma_sync_single_for_cpu(
5028 hw_priv->pdev, dma_buf->dma, packet_len + 4,
5029 PCI_DMA_FROMDEVICE);
5030
5031 do {
5032 /* skb->data != skb->head */
5033 skb = dev_alloc_skb(packet_len + 2);
5034 if (!skb) {
5035 priv->stats.rx_dropped++;
5036 return -ENOMEM;
5037 }
5038
5039 /*
5040 * Align socket buffer in 4-byte boundary for better
5041 * performance.
5042 */
5043 skb_reserve(skb, 2);
5044
5045 memcpy(skb_put(skb, packet_len),
5046 dma_buf->skb->data, packet_len);
5047 } while (0);
5048
5049 skb->dev = dev;
5050
5051 skb->protocol = eth_type_trans(skb, dev);
5052
5053 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5054 csum_verified(skb);
5055
5056 /* Update receive statistics. */
5057 priv->stats.rx_packets++;
5058 priv->stats.rx_bytes += packet_len;
5059
5060 /* Notify upper layer for received packet. */
5061 dev->last_rx = jiffies;
5062
5063 rx_status = netif_rx(skb);
5064
5065 return 0;
5066}
5067
5068static int dev_rcv_packets(struct dev_info *hw_priv)
5069{
5070 int next;
5071 union desc_stat status;
5072 struct ksz_hw *hw = &hw_priv->hw;
5073 struct net_device *dev = hw->port_info[0].pdev;
5074 struct ksz_desc_info *info = &hw->rx_desc_info;
5075 int left = info->alloc;
5076 struct ksz_desc *desc;
5077 int received = 0;
5078
5079 next = info->next;
5080 while (left--) {
5081 /* Get next descriptor which is not hardware owned. */
5082 desc = &info->ring[next];
5083 status.data = le32_to_cpu(desc->phw->ctrl.data);
5084 if (status.rx.hw_owned)
5085 break;
5086
5087 /* Status valid only when last descriptor bit is set. */
5088 if (status.rx.last_desc && status.rx.first_desc) {
5089 if (rx_proc(dev, hw, desc, status))
5090 goto release_packet;
5091 received++;
5092 }
5093
5094release_packet:
5095 release_desc(desc);
5096 next++;
5097 next &= info->mask;
5098 }
5099 info->next = next;
5100
5101 return received;
5102}
5103
5104static int port_rcv_packets(struct dev_info *hw_priv)
5105{
5106 int next;
5107 union desc_stat status;
5108 struct ksz_hw *hw = &hw_priv->hw;
5109 struct net_device *dev = hw->port_info[0].pdev;
5110 struct ksz_desc_info *info = &hw->rx_desc_info;
5111 int left = info->alloc;
5112 struct ksz_desc *desc;
5113 int received = 0;
5114
5115 next = info->next;
5116 while (left--) {
5117 /* Get next descriptor which is not hardware owned. */
5118 desc = &info->ring[next];
5119 status.data = le32_to_cpu(desc->phw->ctrl.data);
5120 if (status.rx.hw_owned)
5121 break;
5122
5123 if (hw->dev_count > 1) {
5124 /* Get received port number. */
5125 int p = HW_TO_DEV_PORT(status.rx.src_port);
5126
5127 dev = hw->port_info[p].pdev;
5128 if (!netif_running(dev))
5129 goto release_packet;
5130 }
5131
5132 /* Status valid only when last descriptor bit is set. */
5133 if (status.rx.last_desc && status.rx.first_desc) {
5134 if (rx_proc(dev, hw, desc, status))
5135 goto release_packet;
5136 received++;
5137 }
5138
5139release_packet:
5140 release_desc(desc);
5141 next++;
5142 next &= info->mask;
5143 }
5144 info->next = next;
5145
5146 return received;
5147}
5148
5149static int dev_rcv_special(struct dev_info *hw_priv)
5150{
5151 int next;
5152 union desc_stat status;
5153 struct ksz_hw *hw = &hw_priv->hw;
5154 struct net_device *dev = hw->port_info[0].pdev;
5155 struct ksz_desc_info *info = &hw->rx_desc_info;
5156 int left = info->alloc;
5157 struct ksz_desc *desc;
5158 int received = 0;
5159
5160 next = info->next;
5161 while (left--) {
5162 /* Get next descriptor which is not hardware owned. */
5163 desc = &info->ring[next];
5164 status.data = le32_to_cpu(desc->phw->ctrl.data);
5165 if (status.rx.hw_owned)
5166 break;
5167
5168 if (hw->dev_count > 1) {
5169 /* Get received port number. */
5170 int p = HW_TO_DEV_PORT(status.rx.src_port);
5171
5172 dev = hw->port_info[p].pdev;
5173 if (!netif_running(dev))
5174 goto release_packet;
5175 }
5176
5177 /* Status valid only when last descriptor bit is set. */
5178 if (status.rx.last_desc && status.rx.first_desc) {
5179 /*
5180 * Receive without error. With receive errors
5181 * disabled, packets with receive errors will be
5182 * dropped, so no need to check the error bit.
5183 */
5184 if (!status.rx.error || (status.data &
5185 KS_DESC_RX_ERROR_COND) ==
5186 KS_DESC_RX_ERROR_TOO_LONG) {
5187 if (rx_proc(dev, hw, desc, status))
5188 goto release_packet;
5189 received++;
5190 } else {
5191 struct dev_priv *priv = netdev_priv(dev);
5192
5193 /* Update receive error statistics. */
5194 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5195 }
5196 }
5197
5198release_packet:
5199 release_desc(desc);
5200 next++;
5201 next &= info->mask;
5202 }
5203 info->next = next;
5204
5205 return received;
5206}
5207
5208static void rx_proc_task(unsigned long data)
5209{
5210 struct dev_info *hw_priv = (struct dev_info *) data;
5211 struct ksz_hw *hw = &hw_priv->hw;
5212
5213 if (!hw->enabled)
5214 return;
5215 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5216
5217 /* In case receive process is suspended because of overrun. */
5218 hw_resume_rx(hw);
5219
5220 /* tasklets are interruptible. */
5221 spin_lock_irq(&hw_priv->hwlock);
5222 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5223 spin_unlock_irq(&hw_priv->hwlock);
5224 } else {
5225 hw_ack_intr(hw, KS884X_INT_RX);
5226 tasklet_schedule(&hw_priv->rx_tasklet);
5227 }
5228}
5229
5230static void tx_proc_task(unsigned long data)
5231{
5232 struct dev_info *hw_priv = (struct dev_info *) data;
5233 struct ksz_hw *hw = &hw_priv->hw;
5234
5235 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5236
5237 tx_done(hw_priv);
5238
5239 /* tasklets are interruptible. */
5240 spin_lock_irq(&hw_priv->hwlock);
5241 hw_turn_on_intr(hw, KS884X_INT_TX);
5242 spin_unlock_irq(&hw_priv->hwlock);
5243}
5244
5245static inline void handle_rx_stop(struct ksz_hw *hw)
5246{
5247 /* Receive just has been stopped. */
5248 if (0 == hw->rx_stop)
5249 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5250 else if (hw->rx_stop > 1) {
5251 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5252 hw_start_rx(hw);
5253 } else {
5254 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5255 hw->rx_stop = 0;
5256 }
5257 } else
5258 /* Receive just has been started. */
5259 hw->rx_stop++;
5260}
5261
5262/**
5263 * netdev_intr - interrupt handling
5264 * @irq: Interrupt number.
5265 * @dev_id: Network device.
5266 *
5267 * This function is called by upper network layer to signal interrupt.
5268 *
5269 * Return IRQ_HANDLED if interrupt is handled.
5270 */
5271static irqreturn_t netdev_intr(int irq, void *dev_id)
5272{
5273 uint int_enable = 0;
5274 struct net_device *dev = (struct net_device *) dev_id;
5275 struct dev_priv *priv = netdev_priv(dev);
5276 struct dev_info *hw_priv = priv->adapter;
5277 struct ksz_hw *hw = &hw_priv->hw;
5278
5279 hw_read_intr(hw, &int_enable);
5280
5281 /* Not our interrupt! */
5282 if (!int_enable)
5283 return IRQ_NONE;
5284
5285 do {
5286 hw_ack_intr(hw, int_enable);
5287 int_enable &= hw->intr_mask;
5288
5289 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5290 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5291 tasklet_schedule(&hw_priv->tx_tasklet);
5292 }
5293
5294 if (likely(int_enable & KS884X_INT_RX)) {
5295 hw_dis_intr_bit(hw, KS884X_INT_RX);
5296 tasklet_schedule(&hw_priv->rx_tasklet);
5297 }
5298
5299 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5300 priv->stats.rx_fifo_errors++;
5301 hw_resume_rx(hw);
5302 }
5303
5304 if (unlikely(int_enable & KS884X_INT_PHY)) {
5305 struct ksz_port *port = &priv->port;
5306
5307 hw->features |= LINK_INT_WORKING;
5308 port_get_link_speed(port);
5309 }
5310
5311 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5312 handle_rx_stop(hw);
5313 break;
5314 }
5315
5316 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5317 u32 data;
5318
5319 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5320 printk(KERN_INFO "Tx stopped\n");
5321 data = readl(hw->io + KS_DMA_TX_CTRL);
5322 if (!(data & DMA_TX_ENABLE))
5323 printk(KERN_INFO "Tx disabled\n");
5324 break;
5325 }
5326 } while (0);
5327
5328 hw_ena_intr(hw);
5329
5330 return IRQ_HANDLED;
5331}
5332
5333/*
5334 * Linux network device functions
5335 */
5336
5337static unsigned long next_jiffies;
5338
5339#ifdef CONFIG_NET_POLL_CONTROLLER
5340static void netdev_netpoll(struct net_device *dev)
5341{
5342 struct dev_priv *priv = netdev_priv(dev);
5343 struct dev_info *hw_priv = priv->adapter;
5344
5345 hw_dis_intr(&hw_priv->hw);
5346 netdev_intr(dev->irq, dev);
5347}
5348#endif
5349
5350static void bridge_change(struct ksz_hw *hw)
5351{
5352 int port;
5353 u8 member;
5354 struct ksz_switch *sw = hw->ksz_switch;
5355
5356 /* No ports in forwarding state. */
5357 if (!sw->member) {
5358 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5359 sw_block_addr(hw);
5360 }
5361 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5362 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5363 member = HOST_MASK | sw->member;
5364 else
5365 member = HOST_MASK | (1 << port);
5366 if (member != sw->port_cfg[port].member)
5367 sw_cfg_port_base_vlan(hw, port, member);
5368 }
5369}
5370
5371/**
5372 * netdev_close - close network device
5373 * @dev: Network device.
5374 *
5375 * This function process the close operation of network device. This is caused
5376 * by the user command "ifconfig ethX down."
5377 *
5378 * Return 0 if successful; otherwise an error code indicating failure.
5379 */
5380static int netdev_close(struct net_device *dev)
5381{
5382 struct dev_priv *priv = netdev_priv(dev);
5383 struct dev_info *hw_priv = priv->adapter;
5384 struct ksz_port *port = &priv->port;
5385 struct ksz_hw *hw = &hw_priv->hw;
5386 int pi;
5387
5388 netif_stop_queue(dev);
5389
5390 ksz_stop_timer(&priv->monitor_timer_info);
5391
5392 /* Need to shut the port manually in multiple device interfaces mode. */
5393 if (hw->dev_count > 1) {
5394 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5395
5396 /* Port is closed. Need to change bridge setting. */
5397 if (hw->features & STP_SUPPORT) {
5398 pi = 1 << port->first_port;
5399 if (hw->ksz_switch->member & pi) {
5400 hw->ksz_switch->member &= ~pi;
5401 bridge_change(hw);
5402 }
5403 }
5404 }
5405 if (port->first_port > 0)
5406 hw_del_addr(hw, dev->dev_addr);
5407 if (!hw_priv->wol_enable)
5408 port_set_power_saving(port, true);
5409
5410 if (priv->multicast)
5411 --hw->all_multi;
5412 if (priv->promiscuous)
5413 --hw->promiscuous;
5414
5415 hw_priv->opened--;
5416 if (!(hw_priv->opened)) {
5417 ksz_stop_timer(&hw_priv->mib_timer_info);
5418 flush_work(&hw_priv->mib_read);
5419
5420 hw_dis_intr(hw);
5421 hw_disable(hw);
5422 hw_clr_multicast(hw);
5423
5424 /* Delay for receive task to stop scheduling itself. */
5425 msleep(2000 / HZ);
5426
5427 tasklet_disable(&hw_priv->rx_tasklet);
5428 tasklet_disable(&hw_priv->tx_tasklet);
5429 free_irq(dev->irq, hw_priv->dev);
5430
5431 transmit_cleanup(hw_priv, 0);
5432 hw_reset_pkts(&hw->rx_desc_info);
5433 hw_reset_pkts(&hw->tx_desc_info);
5434
5435 /* Clean out static MAC table when the switch is shutdown. */
5436 if (hw->features & STP_SUPPORT)
5437 sw_clr_sta_mac_table(hw);
5438 }
5439
5440 return 0;
5441}
5442
5443static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5444{
5445 if (hw->ksz_switch) {
5446 u32 data;
5447
5448 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5449 if (hw->features & RX_HUGE_FRAME)
5450 data |= SWITCH_HUGE_PACKET;
5451 else
5452 data &= ~SWITCH_HUGE_PACKET;
5453 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5454 }
5455 if (hw->features & RX_HUGE_FRAME) {
5456 hw->rx_cfg |= DMA_RX_ERROR;
5457 hw_priv->dev_rcv = dev_rcv_special;
5458 } else {
5459 hw->rx_cfg &= ~DMA_RX_ERROR;
5460 if (hw->dev_count > 1)
5461 hw_priv->dev_rcv = port_rcv_packets;
5462 else
5463 hw_priv->dev_rcv = dev_rcv_packets;
5464 }
5465}
5466
5467static int prepare_hardware(struct net_device *dev)
5468{
5469 struct dev_priv *priv = netdev_priv(dev);
5470 struct dev_info *hw_priv = priv->adapter;
5471 struct ksz_hw *hw = &hw_priv->hw;
5472 int rc = 0;
5473
5474 /* Remember the network device that requests interrupts. */
5475 hw_priv->dev = dev;
5476 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5477 if (rc)
5478 return rc;
5479 tasklet_enable(&hw_priv->rx_tasklet);
5480 tasklet_enable(&hw_priv->tx_tasklet);
5481
5482 hw->promiscuous = 0;
5483 hw->all_multi = 0;
5484 hw->multi_list_size = 0;
5485
5486 hw_reset(hw);
5487
5488 hw_set_desc_base(hw,
5489 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5490 hw_set_addr(hw);
5491 hw_cfg_huge_frame(hw_priv, hw);
5492 ksz_init_rx_buffers(hw_priv);
5493 return 0;
5494}
5495
5496/**
5497 * netdev_open - open network device
5498 * @dev: Network device.
5499 *
5500 * This function process the open operation of network device. This is caused
5501 * by the user command "ifconfig ethX up."
5502 *
5503 * Return 0 if successful; otherwise an error code indicating failure.
5504 */
5505static int netdev_open(struct net_device *dev)
5506{
5507 struct dev_priv *priv = netdev_priv(dev);
5508 struct dev_info *hw_priv = priv->adapter;
5509 struct ksz_hw *hw = &hw_priv->hw;
5510 struct ksz_port *port = &priv->port;
5511 int i;
5512 int p;
5513 int rc = 0;
5514
5515 priv->multicast = 0;
5516 priv->promiscuous = 0;
5517
5518 /* Reset device statistics. */
5519 memset(&priv->stats, 0, sizeof(struct net_device_stats));
5520 memset((void *) port->counter, 0,
5521 (sizeof(u64) * OID_COUNTER_LAST));
5522
5523 if (!(hw_priv->opened)) {
5524 rc = prepare_hardware(dev);
5525 if (rc)
5526 return rc;
5527 for (i = 0; i < hw->mib_port_cnt; i++) {
5528 if (next_jiffies < jiffies)
5529 next_jiffies = jiffies + HZ * 2;
5530 else
5531 next_jiffies += HZ * 1;
5532 hw_priv->counter[i].time = next_jiffies;
5533 hw->port_mib[i].state = media_disconnected;
5534 port_init_cnt(hw, i);
5535 }
5536 if (hw->ksz_switch)
5537 hw->port_mib[HOST_PORT].state = media_connected;
5538 else {
5539 hw_add_wol_bcast(hw);
5540 hw_cfg_wol_pme(hw, 0);
5541 hw_clr_wol_pme_status(&hw_priv->hw);
5542 }
5543 }
5544 port_set_power_saving(port, false);
5545
5546 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5547 /*
5548 * Initialize to invalid value so that link detection
5549 * is done.
5550 */
5551 hw->port_info[p].partner = 0xFF;
5552 hw->port_info[p].state = media_disconnected;
5553 }
5554
5555 /* Need to open the port in multiple device interfaces mode. */
5556 if (hw->dev_count > 1) {
5557 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5558 if (port->first_port > 0)
5559 hw_add_addr(hw, dev->dev_addr);
5560 }
5561
5562 port_get_link_speed(port);
5563 if (port->force_link)
5564 port_force_link_speed(port);
5565 else
5566 port_set_link_speed(port);
5567
5568 if (!(hw_priv->opened)) {
5569 hw_setup_intr(hw);
5570 hw_enable(hw);
5571 hw_ena_intr(hw);
5572
5573 if (hw->mib_port_cnt)
5574 ksz_start_timer(&hw_priv->mib_timer_info,
5575 hw_priv->mib_timer_info.period);
5576 }
5577
5578 hw_priv->opened++;
5579
5580 ksz_start_timer(&priv->monitor_timer_info,
5581 priv->monitor_timer_info.period);
5582
5583 priv->media_state = port->linked->state;
5584
5585 if (media_connected == priv->media_state)
5586 netif_carrier_on(dev);
5587 else
5588 netif_carrier_off(dev);
5589 if (netif_msg_link(priv))
5590 printk(KERN_INFO "%s link %s\n", dev->name,
5591 (media_connected == priv->media_state ?
5592 "on" : "off"));
5593
5594 netif_start_queue(dev);
5595
5596 return 0;
5597}
5598
5599/* RX errors = rx_errors */
5600/* RX dropped = rx_dropped */
5601/* RX overruns = rx_fifo_errors */
5602/* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5603/* TX errors = tx_errors */
5604/* TX dropped = tx_dropped */
5605/* TX overruns = tx_fifo_errors */
5606/* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5607/* collisions = collisions */
5608
5609/**
5610 * netdev_query_statistics - query network device statistics
5611 * @dev: Network device.
5612 *
5613 * This function returns the statistics of the network device. The device
5614 * needs not be opened.
5615 *
5616 * Return network device statistics.
5617 */
5618static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5619{
5620 struct dev_priv *priv = netdev_priv(dev);
5621 struct ksz_port *port = &priv->port;
5622 struct ksz_hw *hw = &priv->adapter->hw;
5623 struct ksz_port_mib *mib;
5624 int i;
5625 int p;
5626
5627 priv->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5628 priv->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5629
5630 /* Reset to zero to add count later. */
5631 priv->stats.multicast = 0;
5632 priv->stats.collisions = 0;
5633 priv->stats.rx_length_errors = 0;
5634 priv->stats.rx_crc_errors = 0;
5635 priv->stats.rx_frame_errors = 0;
5636 priv->stats.tx_window_errors = 0;
5637
5638 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5639 mib = &hw->port_mib[p];
5640
5641 priv->stats.multicast += (unsigned long)
5642 mib->counter[MIB_COUNTER_RX_MULTICAST];
5643
5644 priv->stats.collisions += (unsigned long)
5645 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5646
5647 priv->stats.rx_length_errors += (unsigned long)(
5648 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5649 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5650 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5651 mib->counter[MIB_COUNTER_RX_JABBER]);
5652 priv->stats.rx_crc_errors += (unsigned long)
5653 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5654 priv->stats.rx_frame_errors += (unsigned long)(
5655 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5656 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5657
5658 priv->stats.tx_window_errors += (unsigned long)
5659 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5660 }
5661
5662 return &priv->stats;
5663}
5664
5665/**
5666 * netdev_set_mac_address - set network device MAC address
5667 * @dev: Network device.
5668 * @addr: Buffer of MAC address.
5669 *
5670 * This function is used to set the MAC address of the network device.
5671 *
5672 * Return 0 to indicate success.
5673 */
5674static int netdev_set_mac_address(struct net_device *dev, void *addr)
5675{
5676 struct dev_priv *priv = netdev_priv(dev);
5677 struct dev_info *hw_priv = priv->adapter;
5678 struct ksz_hw *hw = &hw_priv->hw;
5679 struct sockaddr *mac = addr;
5680 uint interrupt;
5681
5682 if (priv->port.first_port > 0)
5683 hw_del_addr(hw, dev->dev_addr);
5684 else {
5685 hw->mac_override = 1;
5686 memcpy(hw->override_addr, mac->sa_data, MAC_ADDR_LEN);
5687 }
5688
5689 memcpy(dev->dev_addr, mac->sa_data, MAX_ADDR_LEN);
5690
5691 interrupt = hw_block_intr(hw);
5692
5693 if (priv->port.first_port > 0)
5694 hw_add_addr(hw, dev->dev_addr);
5695 else
5696 hw_set_addr(hw);
5697 hw_restore_intr(hw, interrupt);
5698
5699 return 0;
5700}
5701
5702static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5703 struct ksz_hw *hw, int promiscuous)
5704{
5705 if (promiscuous != priv->promiscuous) {
5706 u8 prev_state = hw->promiscuous;
5707
5708 if (promiscuous)
5709 ++hw->promiscuous;
5710 else
5711 --hw->promiscuous;
5712 priv->promiscuous = promiscuous;
5713
5714 /* Turn on/off promiscuous mode. */
5715 if (hw->promiscuous <= 1 && prev_state <= 1)
5716 hw_set_promiscuous(hw, hw->promiscuous);
5717
5718 /*
5719 * Port is not in promiscuous mode, meaning it is released
5720 * from the bridge.
5721 */
5722 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5723 dev->br_port) {
5724 struct ksz_switch *sw = hw->ksz_switch;
5725 int port = priv->port.first_port;
5726
5727 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5728 port = 1 << port;
5729 if (sw->member & port) {
5730 sw->member &= ~port;
5731 bridge_change(hw);
5732 }
5733 }
5734 }
5735}
5736
5737static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5738 int multicast)
5739{
5740 if (multicast != priv->multicast) {
5741 u8 all_multi = hw->all_multi;
5742
5743 if (multicast)
5744 ++hw->all_multi;
5745 else
5746 --hw->all_multi;
5747 priv->multicast = multicast;
5748
5749 /* Turn on/off all multicast mode. */
5750 if (hw->all_multi <= 1 && all_multi <= 1)
5751 hw_set_multicast(hw, hw->all_multi);
5752 }
5753}
5754
5755/**
5756 * netdev_set_rx_mode
5757 * @dev: Network device.
5758 *
5759 * This routine is used to set multicast addresses or put the network device
5760 * into promiscuous mode.
5761 */
5762static void netdev_set_rx_mode(struct net_device *dev)
5763{
5764 struct dev_priv *priv = netdev_priv(dev);
5765 struct dev_info *hw_priv = priv->adapter;
5766 struct ksz_hw *hw = &hw_priv->hw;
5767 struct dev_mc_list *mc_ptr;
5768 int multicast = (dev->flags & IFF_ALLMULTI);
5769
5770 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5771
5772 if (hw_priv->hw.dev_count > 1)
5773 multicast |= (dev->flags & IFF_MULTICAST);
5774 dev_set_multicast(priv, hw, multicast);
5775
5776 /* Cannot use different hashes in multiple device interfaces mode. */
5777 if (hw_priv->hw.dev_count > 1)
5778 return;
5779
5780 if ((dev->flags & IFF_MULTICAST) && dev->mc_count) {
5781 int i = 0;
5782
5783 /* List too big to support so turn on all multicast mode. */
5784 if (dev->mc_count > MAX_MULTICAST_LIST) {
5785 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5786 hw->multi_list_size = MAX_MULTICAST_LIST;
5787 ++hw->all_multi;
5788 hw_set_multicast(hw, hw->all_multi);
5789 }
5790 return;
5791 }
5792
5793 for (mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
5794 if (!(*mc_ptr->dmi_addr & 1))
5795 continue;
5796 if (i >= MAX_MULTICAST_LIST)
5797 break;
5798 memcpy(hw->multi_list[i++], mc_ptr->dmi_addr,
5799 MAC_ADDR_LEN);
5800 }
5801 hw->multi_list_size = (u8) i;
5802 hw_set_grp_addr(hw);
5803 } else {
5804 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5805 --hw->all_multi;
5806 hw_set_multicast(hw, hw->all_multi);
5807 }
5808 hw->multi_list_size = 0;
5809 hw_clr_multicast(hw);
5810 }
5811}
5812
5813static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5814{
5815 struct dev_priv *priv = netdev_priv(dev);
5816 struct dev_info *hw_priv = priv->adapter;
5817 struct ksz_hw *hw = &hw_priv->hw;
5818 int hw_mtu;
5819
5820 if (netif_running(dev))
5821 return -EBUSY;
5822
5823 /* Cannot use different MTU in multiple device interfaces mode. */
5824 if (hw->dev_count > 1)
5825 if (dev != hw_priv->dev)
5826 return 0;
5827 if (new_mtu < 60)
5828 return -EINVAL;
5829
5830 if (dev->mtu != new_mtu) {
5831 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5832 if (hw_mtu > MAX_RX_BUF_SIZE)
5833 return -EINVAL;
5834 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5835 hw->features |= RX_HUGE_FRAME;
5836 hw_mtu = MAX_RX_BUF_SIZE;
5837 } else {
5838 hw->features &= ~RX_HUGE_FRAME;
5839 hw_mtu = REGULAR_RX_BUF_SIZE;
5840 }
5841 hw_mtu = (hw_mtu + 3) & ~3;
5842 hw_priv->mtu = hw_mtu;
5843 dev->mtu = new_mtu;
5844 }
5845 return 0;
5846}
5847
5848/**
5849 * netdev_ioctl - I/O control processing
5850 * @dev: Network device.
5851 * @ifr: Interface request structure.
5852 * @cmd: I/O control code.
5853 *
5854 * This function is used to process I/O control calls.
5855 *
5856 * Return 0 to indicate success.
5857 */
5858static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5859{
5860 struct dev_priv *priv = netdev_priv(dev);
5861 struct dev_info *hw_priv = priv->adapter;
5862 struct ksz_hw *hw = &hw_priv->hw;
5863 struct ksz_port *port = &priv->port;
5864 int rc;
5865 int result = 0;
5866 struct mii_ioctl_data *data = if_mii(ifr);
5867
5868 if (down_interruptible(&priv->proc_sem))
5869 return -ERESTARTSYS;
5870
5871 /* assume success */
5872 rc = 0;
5873 switch (cmd) {
5874 /* Get address of MII PHY in use. */
5875 case SIOCGMIIPHY:
5876 data->phy_id = priv->id;
5877
5878 /* Fallthrough... */
5879
5880 /* Read MII PHY register. */
5881 case SIOCGMIIREG:
5882 if (data->phy_id != priv->id || data->reg_num >= 6)
5883 result = -EIO;
5884 else
5885 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5886 &data->val_out);
5887 break;
5888
5889 /* Write MII PHY register. */
5890 case SIOCSMIIREG:
5891 if (!capable(CAP_NET_ADMIN))
5892 result = -EPERM;
5893 else if (data->phy_id != priv->id || data->reg_num >= 6)
5894 result = -EIO;
5895 else
5896 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5897 data->val_in);
5898 break;
5899
5900 default:
5901 result = -EOPNOTSUPP;
5902 }
5903
5904 up(&priv->proc_sem);
5905
5906 return result;
5907}
5908
5909/*
5910 * MII support
5911 */
5912
5913/**
5914 * mdio_read - read PHY register
5915 * @dev: Network device.
5916 * @phy_id: The PHY id.
5917 * @reg_num: The register number.
5918 *
5919 * This function returns the PHY register value.
5920 *
5921 * Return the register value.
5922 */
5923static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5924{
5925 struct dev_priv *priv = netdev_priv(dev);
5926 struct ksz_port *port = &priv->port;
5927 struct ksz_hw *hw = port->hw;
5928 u16 val_out;
5929
5930 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5931 return val_out;
5932}
5933
5934/**
5935 * mdio_write - set PHY register
5936 * @dev: Network device.
5937 * @phy_id: The PHY id.
5938 * @reg_num: The register number.
5939 * @val: The register value.
5940 *
5941 * This procedure sets the PHY register value.
5942 */
5943static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5944{
5945 struct dev_priv *priv = netdev_priv(dev);
5946 struct ksz_port *port = &priv->port;
5947 struct ksz_hw *hw = port->hw;
5948 int i;
5949 int pi;
5950
5951 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5952 hw_w_phy(hw, pi, reg_num << 1, val);
5953}
5954
5955/*
5956 * ethtool support
5957 */
5958
5959#define EEPROM_SIZE 0x40
5960
5961static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5962
5963#define ADVERTISED_ALL \
5964 (ADVERTISED_10baseT_Half | \
5965 ADVERTISED_10baseT_Full | \
5966 ADVERTISED_100baseT_Half | \
5967 ADVERTISED_100baseT_Full)
5968
5969/* These functions use the MII functions in mii.c. */
5970
5971/**
5972 * netdev_get_settings - get network device settings
5973 * @dev: Network device.
5974 * @cmd: Ethtool command.
5975 *
5976 * This function queries the PHY and returns its state in the ethtool command.
5977 *
5978 * Return 0 if successful; otherwise an error code.
5979 */
5980static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5981{
5982 struct dev_priv *priv = netdev_priv(dev);
5983 struct dev_info *hw_priv = priv->adapter;
5984
5985 mutex_lock(&hw_priv->lock);
5986 mii_ethtool_gset(&priv->mii_if, cmd);
5987 cmd->advertising |= SUPPORTED_TP;
5988 mutex_unlock(&hw_priv->lock);
5989
5990 /* Save advertised settings for workaround in next function. */
5991 priv->advertising = cmd->advertising;
5992 return 0;
5993}
5994
5995/**
5996 * netdev_set_settings - set network device settings
5997 * @dev: Network device.
5998 * @cmd: Ethtool command.
5999 *
6000 * This function sets the PHY according to the ethtool command.
6001 *
6002 * Return 0 if successful; otherwise an error code.
6003 */
6004static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6005{
6006 struct dev_priv *priv = netdev_priv(dev);
6007 struct dev_info *hw_priv = priv->adapter;
6008 struct ksz_port *port = &priv->port;
6009 int rc;
6010
6011 /*
6012 * ethtool utility does not change advertised setting if auto
6013 * negotiation is not specified explicitly.
6014 */
6015 if (cmd->autoneg && priv->advertising == cmd->advertising) {
6016 cmd->advertising |= ADVERTISED_ALL;
6017 if (10 == cmd->speed)
6018 cmd->advertising &=
6019 ~(ADVERTISED_100baseT_Full |
6020 ADVERTISED_100baseT_Half);
6021 else if (100 == cmd->speed)
6022 cmd->advertising &=
6023 ~(ADVERTISED_10baseT_Full |
6024 ADVERTISED_10baseT_Half);
6025 if (0 == cmd->duplex)
6026 cmd->advertising &=
6027 ~(ADVERTISED_100baseT_Full |
6028 ADVERTISED_10baseT_Full);
6029 else if (1 == cmd->duplex)
6030 cmd->advertising &=
6031 ~(ADVERTISED_100baseT_Half |
6032 ADVERTISED_10baseT_Half);
6033 }
6034 mutex_lock(&hw_priv->lock);
6035 if (cmd->autoneg &&
6036 (cmd->advertising & ADVERTISED_ALL) ==
6037 ADVERTISED_ALL) {
6038 port->duplex = 0;
6039 port->speed = 0;
6040 port->force_link = 0;
6041 } else {
6042 port->duplex = cmd->duplex + 1;
6043 if (cmd->speed != 1000)
6044 port->speed = cmd->speed;
6045 if (cmd->autoneg)
6046 port->force_link = 0;
6047 else
6048 port->force_link = 1;
6049 }
6050 rc = mii_ethtool_sset(&priv->mii_if, cmd);
6051 mutex_unlock(&hw_priv->lock);
6052 return rc;
6053}
6054
6055/**
6056 * netdev_nway_reset - restart auto-negotiation
6057 * @dev: Network device.
6058 *
6059 * This function restarts the PHY for auto-negotiation.
6060 *
6061 * Return 0 if successful; otherwise an error code.
6062 */
6063static int netdev_nway_reset(struct net_device *dev)
6064{
6065 struct dev_priv *priv = netdev_priv(dev);
6066 struct dev_info *hw_priv = priv->adapter;
6067 int rc;
6068
6069 mutex_lock(&hw_priv->lock);
6070 rc = mii_nway_restart(&priv->mii_if);
6071 mutex_unlock(&hw_priv->lock);
6072 return rc;
6073}
6074
6075/**
6076 * netdev_get_link - get network device link status
6077 * @dev: Network device.
6078 *
6079 * This function gets the link status from the PHY.
6080 *
6081 * Return true if PHY is linked and false otherwise.
6082 */
6083static u32 netdev_get_link(struct net_device *dev)
6084{
6085 struct dev_priv *priv = netdev_priv(dev);
6086 int rc;
6087
6088 rc = mii_link_ok(&priv->mii_if);
6089 return rc;
6090}
6091
6092/**
6093 * netdev_get_drvinfo - get network driver information
6094 * @dev: Network device.
6095 * @info: Ethtool driver info data structure.
6096 *
6097 * This procedure returns the driver information.
6098 */
6099static void netdev_get_drvinfo(struct net_device *dev,
6100 struct ethtool_drvinfo *info)
6101{
6102 struct dev_priv *priv = netdev_priv(dev);
6103 struct dev_info *hw_priv = priv->adapter;
6104
6105 strcpy(info->driver, DRV_NAME);
6106 strcpy(info->version, DRV_VERSION);
6107 strcpy(info->bus_info, pci_name(hw_priv->pdev));
6108}
6109
6110/**
6111 * netdev_get_regs_len - get length of register dump
6112 * @dev: Network device.
6113 *
6114 * This function returns the length of the register dump.
6115 *
6116 * Return length of the register dump.
6117 */
6118static struct hw_regs {
6119 int start;
6120 int end;
6121} hw_regs_range[] = {
6122 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6123 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6124 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6125 { KS884X_SIDER_P, KS8842_SGCR7_P },
6126 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6127 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6128 { 0, 0 }
6129};
6130
6131static int netdev_get_regs_len(struct net_device *dev)
6132{
6133 struct hw_regs *range = hw_regs_range;
6134 int regs_len = 0x10 * sizeof(u32);
6135
6136 while (range->end > range->start) {
6137 regs_len += (range->end - range->start + 3) / 4 * 4;
6138 range++;
6139 }
6140 return regs_len;
6141}
6142
6143/**
6144 * netdev_get_regs - get register dump
6145 * @dev: Network device.
6146 * @regs: Ethtool registers data structure.
6147 * @ptr: Buffer to store the register values.
6148 *
6149 * This procedure dumps the register values in the provided buffer.
6150 */
6151static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6152 void *ptr)
6153{
6154 struct dev_priv *priv = netdev_priv(dev);
6155 struct dev_info *hw_priv = priv->adapter;
6156 struct ksz_hw *hw = &hw_priv->hw;
6157 int *buf = (int *) ptr;
6158 struct hw_regs *range = hw_regs_range;
6159 int len;
6160
6161 mutex_lock(&hw_priv->lock);
6162 regs->version = 0;
6163 for (len = 0; len < 0x40; len += 4) {
6164 pci_read_config_dword(hw_priv->pdev, len, buf);
6165 buf++;
6166 }
6167 while (range->end > range->start) {
6168 for (len = range->start; len < range->end; len += 4) {
6169 *buf = readl(hw->io + len);
6170 buf++;
6171 }
6172 range++;
6173 }
6174 mutex_unlock(&hw_priv->lock);
6175}
6176
6177#define WOL_SUPPORT \
6178 (WAKE_PHY | WAKE_MAGIC | \
6179 WAKE_UCAST | WAKE_MCAST | \
6180 WAKE_BCAST | WAKE_ARP)
6181
6182/**
6183 * netdev_get_wol - get Wake-on-LAN support
6184 * @dev: Network device.
6185 * @wol: Ethtool Wake-on-LAN data structure.
6186 *
6187 * This procedure returns Wake-on-LAN support.
6188 */
6189static void netdev_get_wol(struct net_device *dev,
6190 struct ethtool_wolinfo *wol)
6191{
6192 struct dev_priv *priv = netdev_priv(dev);
6193 struct dev_info *hw_priv = priv->adapter;
6194
6195 wol->supported = hw_priv->wol_support;
6196 wol->wolopts = hw_priv->wol_enable;
6197 memset(&wol->sopass, 0, sizeof(wol->sopass));
6198}
6199
6200/**
6201 * netdev_set_wol - set Wake-on-LAN support
6202 * @dev: Network device.
6203 * @wol: Ethtool Wake-on-LAN data structure.
6204 *
6205 * This function sets Wake-on-LAN support.
6206 *
6207 * Return 0 if successful; otherwise an error code.
6208 */
6209static int netdev_set_wol(struct net_device *dev,
6210 struct ethtool_wolinfo *wol)
6211{
6212 struct dev_priv *priv = netdev_priv(dev);
6213 struct dev_info *hw_priv = priv->adapter;
6214
6215 /* Need to find a way to retrieve the device IP address. */
6216 u8 net_addr[] = { 192, 168, 1, 1 };
6217
6218 if (wol->wolopts & ~hw_priv->wol_support)
6219 return -EINVAL;
6220
6221 hw_priv->wol_enable = wol->wolopts;
6222
6223 /* Link wakeup cannot really be disabled. */
6224 if (wol->wolopts)
6225 hw_priv->wol_enable |= WAKE_PHY;
6226 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6227 return 0;
6228}
6229
6230/**
6231 * netdev_get_msglevel - get debug message level
6232 * @dev: Network device.
6233 *
6234 * This function returns current debug message level.
6235 *
6236 * Return current debug message flags.
6237 */
6238static u32 netdev_get_msglevel(struct net_device *dev)
6239{
6240 struct dev_priv *priv = netdev_priv(dev);
6241
6242 return priv->msg_enable;
6243}
6244
6245/**
6246 * netdev_set_msglevel - set debug message level
6247 * @dev: Network device.
6248 * @value: Debug message flags.
6249 *
6250 * This procedure sets debug message level.
6251 */
6252static void netdev_set_msglevel(struct net_device *dev, u32 value)
6253{
6254 struct dev_priv *priv = netdev_priv(dev);
6255
6256 priv->msg_enable = value;
6257}
6258
6259/**
6260 * netdev_get_eeprom_len - get EEPROM length
6261 * @dev: Network device.
6262 *
6263 * This function returns the length of the EEPROM.
6264 *
6265 * Return length of the EEPROM.
6266 */
6267static int netdev_get_eeprom_len(struct net_device *dev)
6268{
6269 return EEPROM_SIZE * 2;
6270}
6271
6272/**
6273 * netdev_get_eeprom - get EEPROM data
6274 * @dev: Network device.
6275 * @eeprom: Ethtool EEPROM data structure.
6276 * @data: Buffer to store the EEPROM data.
6277 *
6278 * This function dumps the EEPROM data in the provided buffer.
6279 *
6280 * Return 0 if successful; otherwise an error code.
6281 */
6282#define EEPROM_MAGIC 0x10A18842
6283
6284static int netdev_get_eeprom(struct net_device *dev,
6285 struct ethtool_eeprom *eeprom, u8 *data)
6286{
6287 struct dev_priv *priv = netdev_priv(dev);
6288 struct dev_info *hw_priv = priv->adapter;
6289 u8 *eeprom_byte = (u8 *) eeprom_data;
6290 int i;
6291 int len;
6292
6293 len = (eeprom->offset + eeprom->len + 1) / 2;
6294 for (i = eeprom->offset / 2; i < len; i++)
6295 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6296 eeprom->magic = EEPROM_MAGIC;
6297 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6298
6299 return 0;
6300}
6301
6302/**
6303 * netdev_set_eeprom - write EEPROM data
6304 * @dev: Network device.
6305 * @eeprom: Ethtool EEPROM data structure.
6306 * @data: Data buffer.
6307 *
6308 * This function modifies the EEPROM data one byte at a time.
6309 *
6310 * Return 0 if successful; otherwise an error code.
6311 */
6312static int netdev_set_eeprom(struct net_device *dev,
6313 struct ethtool_eeprom *eeprom, u8 *data)
6314{
6315 struct dev_priv *priv = netdev_priv(dev);
6316 struct dev_info *hw_priv = priv->adapter;
6317 u16 eeprom_word[EEPROM_SIZE];
6318 u8 *eeprom_byte = (u8 *) eeprom_word;
6319 int i;
6320 int len;
6321
6322 if (eeprom->magic != EEPROM_MAGIC)
6323 return 1;
6324
6325 len = (eeprom->offset + eeprom->len + 1) / 2;
6326 for (i = eeprom->offset / 2; i < len; i++)
6327 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6328 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6329 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6330 for (i = 0; i < EEPROM_SIZE; i++)
6331 if (eeprom_word[i] != eeprom_data[i]) {
6332 eeprom_data[i] = eeprom_word[i];
6333 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6334 }
6335
6336 return 0;
6337}
6338
6339/**
6340 * netdev_get_pauseparam - get flow control parameters
6341 * @dev: Network device.
6342 * @pause: Ethtool PAUSE settings data structure.
6343 *
6344 * This procedure returns the PAUSE control flow settings.
6345 */
6346static void netdev_get_pauseparam(struct net_device *dev,
6347 struct ethtool_pauseparam *pause)
6348{
6349 struct dev_priv *priv = netdev_priv(dev);
6350 struct dev_info *hw_priv = priv->adapter;
6351 struct ksz_hw *hw = &hw_priv->hw;
6352
6353 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6354 if (!hw->ksz_switch) {
6355 pause->rx_pause =
6356 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6357 pause->tx_pause =
6358 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6359 } else {
6360 pause->rx_pause =
6361 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6362 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6363 pause->tx_pause =
6364 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6365 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6366 }
6367}
6368
6369/**
6370 * netdev_set_pauseparam - set flow control parameters
6371 * @dev: Network device.
6372 * @pause: Ethtool PAUSE settings data structure.
6373 *
6374 * This function sets the PAUSE control flow settings.
6375 * Not implemented yet.
6376 *
6377 * Return 0 if successful; otherwise an error code.
6378 */
6379static int netdev_set_pauseparam(struct net_device *dev,
6380 struct ethtool_pauseparam *pause)
6381{
6382 struct dev_priv *priv = netdev_priv(dev);
6383 struct dev_info *hw_priv = priv->adapter;
6384 struct ksz_hw *hw = &hw_priv->hw;
6385 struct ksz_port *port = &priv->port;
6386
6387 mutex_lock(&hw_priv->lock);
6388 if (pause->autoneg) {
6389 if (!pause->rx_pause && !pause->tx_pause)
6390 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6391 else
6392 port->flow_ctrl = PHY_FLOW_CTRL;
6393 hw->overrides &= ~PAUSE_FLOW_CTRL;
6394 port->force_link = 0;
6395 if (hw->ksz_switch) {
6396 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6397 SWITCH_RX_FLOW_CTRL, 1);
6398 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6399 SWITCH_TX_FLOW_CTRL, 1);
6400 }
6401 port_set_link_speed(port);
6402 } else {
6403 hw->overrides |= PAUSE_FLOW_CTRL;
6404 if (hw->ksz_switch) {
6405 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6406 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6407 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6408 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6409 } else
6410 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6411 }
6412 mutex_unlock(&hw_priv->lock);
6413
6414 return 0;
6415}
6416
6417/**
6418 * netdev_get_ringparam - get tx/rx ring parameters
6419 * @dev: Network device.
6420 * @pause: Ethtool RING settings data structure.
6421 *
6422 * This procedure returns the TX/RX ring settings.
6423 */
6424static void netdev_get_ringparam(struct net_device *dev,
6425 struct ethtool_ringparam *ring)
6426{
6427 struct dev_priv *priv = netdev_priv(dev);
6428 struct dev_info *hw_priv = priv->adapter;
6429 struct ksz_hw *hw = &hw_priv->hw;
6430
6431 ring->tx_max_pending = (1 << 9);
6432 ring->tx_pending = hw->tx_desc_info.alloc;
6433 ring->rx_max_pending = (1 << 9);
6434 ring->rx_pending = hw->rx_desc_info.alloc;
6435}
6436
6437#define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6438
6439static struct {
6440 char string[ETH_GSTRING_LEN];
6441} ethtool_stats_keys[STATS_LEN] = {
6442 { "rx_lo_priority_octets" },
6443 { "rx_hi_priority_octets" },
6444 { "rx_undersize_packets" },
6445 { "rx_fragments" },
6446 { "rx_oversize_packets" },
6447 { "rx_jabbers" },
6448 { "rx_symbol_errors" },
6449 { "rx_crc_errors" },
6450 { "rx_align_errors" },
6451 { "rx_mac_ctrl_packets" },
6452 { "rx_pause_packets" },
6453 { "rx_bcast_packets" },
6454 { "rx_mcast_packets" },
6455 { "rx_ucast_packets" },
6456 { "rx_64_or_less_octet_packets" },
6457 { "rx_65_to_127_octet_packets" },
6458 { "rx_128_to_255_octet_packets" },
6459 { "rx_256_to_511_octet_packets" },
6460 { "rx_512_to_1023_octet_packets" },
6461 { "rx_1024_to_1522_octet_packets" },
6462
6463 { "tx_lo_priority_octets" },
6464 { "tx_hi_priority_octets" },
6465 { "tx_late_collisions" },
6466 { "tx_pause_packets" },
6467 { "tx_bcast_packets" },
6468 { "tx_mcast_packets" },
6469 { "tx_ucast_packets" },
6470 { "tx_deferred" },
6471 { "tx_total_collisions" },
6472 { "tx_excessive_collisions" },
6473 { "tx_single_collisions" },
6474 { "tx_mult_collisions" },
6475
6476 { "rx_discards" },
6477 { "tx_discards" },
6478};
6479
6480/**
6481 * netdev_get_strings - get statistics identity strings
6482 * @dev: Network device.
6483 * @stringset: String set identifier.
6484 * @buf: Buffer to store the strings.
6485 *
6486 * This procedure returns the strings used to identify the statistics.
6487 */
6488static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6489{
6490 struct dev_priv *priv = netdev_priv(dev);
6491 struct dev_info *hw_priv = priv->adapter;
6492 struct ksz_hw *hw = &hw_priv->hw;
6493
6494 if (ETH_SS_STATS == stringset)
6495 memcpy(buf, &ethtool_stats_keys,
6496 ETH_GSTRING_LEN * hw->mib_cnt);
6497}
6498
6499/**
6500 * netdev_get_sset_count - get statistics size
6501 * @dev: Network device.
6502 * @sset: The statistics set number.
6503 *
6504 * This function returns the size of the statistics to be reported.
6505 *
6506 * Return size of the statistics to be reported.
6507 */
6508static int netdev_get_sset_count(struct net_device *dev, int sset)
6509{
6510 struct dev_priv *priv = netdev_priv(dev);
6511 struct dev_info *hw_priv = priv->adapter;
6512 struct ksz_hw *hw = &hw_priv->hw;
6513
6514 switch (sset) {
6515 case ETH_SS_STATS:
6516 return hw->mib_cnt;
6517 default:
6518 return -EOPNOTSUPP;
6519 }
6520}
6521
6522/**
6523 * netdev_get_ethtool_stats - get network device statistics
6524 * @dev: Network device.
6525 * @stats: Ethtool statistics data structure.
6526 * @data: Buffer to store the statistics.
6527 *
6528 * This procedure returns the statistics.
6529 */
6530static void netdev_get_ethtool_stats(struct net_device *dev,
6531 struct ethtool_stats *stats, u64 *data)
6532{
6533 struct dev_priv *priv = netdev_priv(dev);
6534 struct dev_info *hw_priv = priv->adapter;
6535 struct ksz_hw *hw = &hw_priv->hw;
6536 struct ksz_port *port = &priv->port;
6537 int n_stats = stats->n_stats;
6538 int i;
6539 int n;
6540 int p;
6541 int rc;
6542 u64 counter[TOTAL_PORT_COUNTER_NUM];
6543
6544 mutex_lock(&hw_priv->lock);
6545 n = SWITCH_PORT_NUM;
6546 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6547 if (media_connected == hw->port_mib[p].state) {
6548 hw_priv->counter[p].read = 1;
6549
6550 /* Remember first port that requests read. */
6551 if (n == SWITCH_PORT_NUM)
6552 n = p;
6553 }
6554 }
6555 mutex_unlock(&hw_priv->lock);
6556
6557 if (n < SWITCH_PORT_NUM)
6558 schedule_work(&hw_priv->mib_read);
6559
6560 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6561 p = n;
6562 rc = wait_event_interruptible_timeout(
6563 hw_priv->counter[p].counter,
6564 2 == hw_priv->counter[p].read,
6565 HZ * 1);
6566 } else
6567 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6568 if (0 == i) {
6569 rc = wait_event_interruptible_timeout(
6570 hw_priv->counter[p].counter,
6571 2 == hw_priv->counter[p].read,
6572 HZ * 2);
6573 } else if (hw->port_mib[p].cnt_ptr) {
6574 rc = wait_event_interruptible_timeout(
6575 hw_priv->counter[p].counter,
6576 2 == hw_priv->counter[p].read,
6577 HZ * 1);
6578 }
6579 }
6580
6581 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6582 n = hw->mib_cnt;
6583 if (n > n_stats)
6584 n = n_stats;
6585 n_stats -= n;
6586 for (i = 0; i < n; i++)
6587 *data++ = counter[i];
6588}
6589
6590/**
6591 * netdev_get_rx_csum - get receive checksum support
6592 * @dev: Network device.
6593 *
6594 * This function gets receive checksum support setting.
6595 *
6596 * Return true if receive checksum is enabled; false otherwise.
6597 */
6598static u32 netdev_get_rx_csum(struct net_device *dev)
6599{
6600 struct dev_priv *priv = netdev_priv(dev);
6601 struct dev_info *hw_priv = priv->adapter;
6602 struct ksz_hw *hw = &hw_priv->hw;
6603
6604 return hw->rx_cfg &
6605 (DMA_RX_CSUM_UDP |
6606 DMA_RX_CSUM_TCP |
6607 DMA_RX_CSUM_IP);
6608}
6609
6610/**
6611 * netdev_set_rx_csum - set receive checksum support
6612 * @dev: Network device.
6613 * @data: Zero to disable receive checksum support.
6614 *
6615 * This function sets receive checksum support setting.
6616 *
6617 * Return 0 if successful; otherwise an error code.
6618 */
6619static int netdev_set_rx_csum(struct net_device *dev, u32 data)
6620{
6621 struct dev_priv *priv = netdev_priv(dev);
6622 struct dev_info *hw_priv = priv->adapter;
6623 struct ksz_hw *hw = &hw_priv->hw;
6624 u32 new_setting = hw->rx_cfg;
6625
6626 if (data)
6627 new_setting |=
6628 (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP |
6629 DMA_RX_CSUM_IP);
6630 else
6631 new_setting &=
6632 ~(DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP |
6633 DMA_RX_CSUM_IP);
6634 new_setting &= ~DMA_RX_CSUM_UDP;
6635 mutex_lock(&hw_priv->lock);
6636 if (new_setting != hw->rx_cfg) {
6637 hw->rx_cfg = new_setting;
6638 if (hw->enabled)
6639 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6640 }
6641 mutex_unlock(&hw_priv->lock);
6642 return 0;
6643}
6644
6645static struct ethtool_ops netdev_ethtool_ops = {
6646 .get_settings = netdev_get_settings,
6647 .set_settings = netdev_set_settings,
6648 .nway_reset = netdev_nway_reset,
6649 .get_link = netdev_get_link,
6650 .get_drvinfo = netdev_get_drvinfo,
6651 .get_regs_len = netdev_get_regs_len,
6652 .get_regs = netdev_get_regs,
6653 .get_wol = netdev_get_wol,
6654 .set_wol = netdev_set_wol,
6655 .get_msglevel = netdev_get_msglevel,
6656 .set_msglevel = netdev_set_msglevel,
6657 .get_eeprom_len = netdev_get_eeprom_len,
6658 .get_eeprom = netdev_get_eeprom,
6659 .set_eeprom = netdev_set_eeprom,
6660 .get_pauseparam = netdev_get_pauseparam,
6661 .set_pauseparam = netdev_set_pauseparam,
6662 .get_ringparam = netdev_get_ringparam,
6663 .get_strings = netdev_get_strings,
6664 .get_sset_count = netdev_get_sset_count,
6665 .get_ethtool_stats = netdev_get_ethtool_stats,
6666 .get_rx_csum = netdev_get_rx_csum,
6667 .set_rx_csum = netdev_set_rx_csum,
6668 .get_tx_csum = ethtool_op_get_tx_csum,
6669 .set_tx_csum = ethtool_op_set_tx_csum,
6670 .get_sg = ethtool_op_get_sg,
6671 .set_sg = ethtool_op_set_sg,
6672};
6673
6674/*
6675 * Hardware monitoring
6676 */
6677
6678static void update_link(struct net_device *dev, struct dev_priv *priv,
6679 struct ksz_port *port)
6680{
6681 if (priv->media_state != port->linked->state) {
6682 priv->media_state = port->linked->state;
6683 if (netif_running(dev)) {
6684 if (media_connected == priv->media_state)
6685 netif_carrier_on(dev);
6686 else
6687 netif_carrier_off(dev);
6688 if (netif_msg_link(priv))
6689 printk(KERN_INFO "%s link %s\n", dev->name,
6690 (media_connected == priv->media_state ?
6691 "on" : "off"));
6692 }
6693 }
6694}
6695
6696static void mib_read_work(struct work_struct *work)
6697{
6698 struct dev_info *hw_priv =
6699 container_of(work, struct dev_info, mib_read);
6700 struct ksz_hw *hw = &hw_priv->hw;
6701 struct ksz_port_mib *mib;
6702 int i;
6703
6704 next_jiffies = jiffies;
6705 for (i = 0; i < hw->mib_port_cnt; i++) {
6706 mib = &hw->port_mib[i];
6707
6708 /* Reading MIB counters or requested to read. */
6709 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6710
6711 /* Need to process receive interrupt. */
6712 if (port_r_cnt(hw, i))
6713 break;
6714 hw_priv->counter[i].read = 0;
6715
6716 /* Finish reading counters. */
6717 if (0 == mib->cnt_ptr) {
6718 hw_priv->counter[i].read = 2;
6719 wake_up_interruptible(
6720 &hw_priv->counter[i].counter);
6721 }
6722 } else if (jiffies >= hw_priv->counter[i].time) {
6723 /* Only read MIB counters when the port is connected. */
6724 if (media_connected == mib->state)
6725 hw_priv->counter[i].read = 1;
6726 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6727 hw_priv->counter[i].time = next_jiffies;
6728
6729 /* Port is just disconnected. */
6730 } else if (mib->link_down) {
6731 mib->link_down = 0;
6732
6733 /* Read counters one last time after link is lost. */
6734 hw_priv->counter[i].read = 1;
6735 }
6736 }
6737}
6738
6739static void mib_monitor(unsigned long ptr)
6740{
6741 struct dev_info *hw_priv = (struct dev_info *) ptr;
6742
6743 mib_read_work(&hw_priv->mib_read);
6744
6745 /* This is used to verify Wake-on-LAN is working. */
6746 if (hw_priv->pme_wait) {
6747 if (hw_priv->pme_wait <= jiffies) {
6748 hw_clr_wol_pme_status(&hw_priv->hw);
6749 hw_priv->pme_wait = 0;
6750 }
6751 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6752
6753 /* PME is asserted. Wait 2 seconds to clear it. */
6754 hw_priv->pme_wait = jiffies + HZ * 2;
6755 }
6756
6757 ksz_update_timer(&hw_priv->mib_timer_info);
6758}
6759
6760/**
6761 * dev_monitor - periodic monitoring
6762 * @ptr: Network device pointer.
6763 *
6764 * This routine is run in a kernel timer to monitor the network device.
6765 */
6766static void dev_monitor(unsigned long ptr)
6767{
6768 struct net_device *dev = (struct net_device *) ptr;
6769 struct dev_priv *priv = netdev_priv(dev);
6770 struct dev_info *hw_priv = priv->adapter;
6771 struct ksz_hw *hw = &hw_priv->hw;
6772 struct ksz_port *port = &priv->port;
6773
6774 if (!(hw->features & LINK_INT_WORKING))
6775 port_get_link_speed(port);
6776 update_link(dev, priv, port);
6777
6778 ksz_update_timer(&priv->monitor_timer_info);
6779}
6780
6781/*
6782 * Linux network device interface functions
6783 */
6784
6785/* Driver exported variables */
6786
6787static int msg_enable;
6788
6789static char *macaddr = ":";
6790static char *mac1addr = ":";
6791
6792/*
6793 * This enables multiple network device mode for KSZ8842, which contains a
6794 * switch with two physical ports. Some users like to take control of the
6795 * ports for running Spanning Tree Protocol. The driver will create an
6796 * additional eth? device for the other port.
6797 *
6798 * Some limitations are the network devices cannot have different MTU and
6799 * multicast hash tables.
6800 */
6801static int multi_dev;
6802
6803/*
6804 * As most users select multiple network device mode to use Spanning Tree
6805 * Protocol, this enables a feature in which most unicast and multicast packets
6806 * are forwarded inside the switch and not passed to the host. Only packets
6807 * that need the host's attention are passed to it. This prevents the host
6808 * wasting CPU time to examine each and every incoming packets and do the
6809 * forwarding itself.
6810 *
6811 * As the hack requires the private bridge header, the driver cannot compile
6812 * with just the kernel headers.
6813 *
6814 * Enabling STP support also turns on multiple network device mode.
6815 */
6816static int stp;
6817
6818/*
6819 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6820 * needs that. However, fast aging is used to flush the dynamic MAC table when
6821 * STP suport is enabled.
6822 */
6823static int fast_aging;
6824
6825/**
6826 * netdev_init - initalize network device.
6827 * @dev: Network device.
6828 *
6829 * This function initializes the network device.
6830 *
6831 * Return 0 if successful; otherwise an error code indicating failure.
6832 */
6833static int __init netdev_init(struct net_device *dev)
6834{
6835 struct dev_priv *priv = netdev_priv(dev);
6836
6837 /* 500 ms timeout */
6838 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6839 dev_monitor, dev);
6840
6841 /* 500 ms timeout */
6842 dev->watchdog_timeo = HZ / 2;
6843
6844 dev->features |= NETIF_F_IP_CSUM;
6845
6846 /*
6847 * Hardware does not really support IPv6 checksum generation, but
6848 * driver actually runs faster with this on. Refer IPV6_CSUM_GEN_HACK.
6849 */
6850 dev->features |= NETIF_F_IPV6_CSUM;
6851 dev->features |= NETIF_F_SG;
6852
6853 sema_init(&priv->proc_sem, 1);
6854
6855 priv->mii_if.phy_id_mask = 0x1;
6856 priv->mii_if.reg_num_mask = 0x7;
6857 priv->mii_if.dev = dev;
6858 priv->mii_if.mdio_read = mdio_read;
6859 priv->mii_if.mdio_write = mdio_write;
6860 priv->mii_if.phy_id = priv->port.first_port + 1;
6861
6862 priv->msg_enable = netif_msg_init(msg_enable,
6863 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6864
6865 return 0;
6866}
6867
6868static const struct net_device_ops netdev_ops = {
6869 .ndo_init = netdev_init,
6870 .ndo_open = netdev_open,
6871 .ndo_stop = netdev_close,
6872 .ndo_get_stats = netdev_query_statistics,
6873 .ndo_start_xmit = netdev_tx,
6874 .ndo_tx_timeout = netdev_tx_timeout,
6875 .ndo_change_mtu = netdev_change_mtu,
6876 .ndo_set_mac_address = netdev_set_mac_address,
6877 .ndo_do_ioctl = netdev_ioctl,
6878 .ndo_set_rx_mode = netdev_set_rx_mode,
6879#ifdef CONFIG_NET_POLL_CONTROLLER
6880 .ndo_poll_controller = netdev_netpoll,
6881#endif
6882};
6883
6884static void netdev_free(struct net_device *dev)
6885{
6886 if (dev->watchdog_timeo)
6887 unregister_netdev(dev);
6888
6889 free_netdev(dev);
6890}
6891
6892struct platform_info {
6893 struct dev_info dev_info;
6894 struct net_device *netdev[SWITCH_PORT_NUM];
6895};
6896
6897static int net_device_present;
6898
6899static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6900{
6901 int i;
6902 int j;
6903 int got_num;
6904 int num;
6905
6906 i = j = num = got_num = 0;
6907 while (j < MAC_ADDR_LEN) {
6908 if (macaddr[i]) {
6909 got_num = 1;
6910 if ('0' <= macaddr[i] && macaddr[i] <= '9')
6911 num = num * 16 + macaddr[i] - '0';
6912 else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
6913 num = num * 16 + 10 + macaddr[i] - 'A';
6914 else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
6915 num = num * 16 + 10 + macaddr[i] - 'a';
6916 else if (':' == macaddr[i])
6917 got_num = 2;
6918 else
6919 break;
6920 } else if (got_num)
6921 got_num = 2;
6922 else
6923 break;
6924 if (2 == got_num) {
6925 if (MAIN_PORT == port) {
6926 hw_priv->hw.override_addr[j++] = (u8) num;
6927 hw_priv->hw.override_addr[5] +=
6928 hw_priv->hw.id;
6929 } else {
6930 hw_priv->hw.ksz_switch->other_addr[j++] =
6931 (u8) num;
6932 hw_priv->hw.ksz_switch->other_addr[5] +=
6933 hw_priv->hw.id;
6934 }
6935 num = got_num = 0;
6936 }
6937 i++;
6938 }
6939 if (MAC_ADDR_LEN == j) {
6940 if (MAIN_PORT == port)
6941 hw_priv->hw.mac_override = 1;
6942 }
6943}
6944
6945#define KS884X_DMA_MASK (~0x0UL)
6946
6947static void read_other_addr(struct ksz_hw *hw)
6948{
6949 int i;
6950 u16 data[3];
6951 struct ksz_switch *sw = hw->ksz_switch;
6952
6953 for (i = 0; i < 3; i++)
6954 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6955 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6956 sw->other_addr[5] = (u8) data[0];
6957 sw->other_addr[4] = (u8)(data[0] >> 8);
6958 sw->other_addr[3] = (u8) data[1];
6959 sw->other_addr[2] = (u8)(data[1] >> 8);
6960 sw->other_addr[1] = (u8) data[2];
6961 sw->other_addr[0] = (u8)(data[2] >> 8);
6962 }
6963}
6964
6965#ifndef PCI_VENDOR_ID_MICREL_KS
6966#define PCI_VENDOR_ID_MICREL_KS 0x16c6
6967#endif
6968
6969static int __init pcidev_init(struct pci_dev *pdev,
6970 const struct pci_device_id *id)
6971{
6972 struct net_device *dev;
6973 struct dev_priv *priv;
6974 struct dev_info *hw_priv;
6975 struct ksz_hw *hw;
6976 struct platform_info *info;
6977 struct ksz_port *port;
6978 unsigned long reg_base;
6979 unsigned long reg_len;
6980 int cnt;
6981 int i;
6982 int mib_port_count;
6983 int pi;
6984 int port_count;
6985 int result;
6986 char banner[80];
6987 struct ksz_switch *sw = NULL;
6988
6989 result = pci_enable_device(pdev);
6990 if (result)
6991 return result;
6992
6993 result = -ENODEV;
6994
6995 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6996 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6997 return result;
6998
6999 reg_base = pci_resource_start(pdev, 0);
7000 reg_len = pci_resource_len(pdev, 0);
7001 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
7002 return result;
7003
7004 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
7005 return result;
7006 pci_set_master(pdev);
7007
7008 result = -ENOMEM;
7009
7010 info = kmalloc(sizeof(struct platform_info), GFP_KERNEL);
7011 if (!info)
7012 goto pcidev_init_dev_err;
7013 memset(info, 0, sizeof(struct platform_info));
7014
7015 hw_priv = &info->dev_info;
7016 hw_priv->pdev = pdev;
7017
7018 hw = &hw_priv->hw;
7019
7020 hw->io = ioremap(reg_base, reg_len);
7021 if (!hw->io)
7022 goto pcidev_init_io_err;
7023
7024 cnt = hw_init(hw);
7025 if (!cnt) {
7026 if (msg_enable & NETIF_MSG_PROBE)
7027 printk(KERN_ALERT "chip not detected\n");
7028 result = -ENODEV;
7029 goto pcidev_init_alloc_err;
7030 }
7031
7032 sprintf(banner, "%s\n", version);
7033 banner[13] = cnt + '0';
7034 ks_info(hw_priv, "%s", banner);
7035 ks_dbg(hw_priv, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
7036
7037 /* Assume device is KSZ8841. */
7038 hw->dev_count = 1;
7039 port_count = 1;
7040 mib_port_count = 1;
7041 hw->addr_list_size = 0;
7042 hw->mib_cnt = PORT_COUNTER_NUM;
7043 hw->mib_port_cnt = 1;
7044
7045 /* KSZ8842 has a switch with multiple ports. */
7046 if (2 == cnt) {
7047 if (fast_aging)
7048 hw->overrides |= FAST_AGING;
7049
7050 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
7051
7052 /* Multiple network device interfaces are required. */
7053 if (multi_dev) {
7054 hw->dev_count = SWITCH_PORT_NUM;
7055 hw->addr_list_size = SWITCH_PORT_NUM - 1;
7056 }
7057
7058 /* Single network device has multiple ports. */
7059 if (1 == hw->dev_count) {
7060 port_count = SWITCH_PORT_NUM;
7061 mib_port_count = SWITCH_PORT_NUM;
7062 }
7063 hw->mib_port_cnt = TOTAL_PORT_NUM;
7064 hw->ksz_switch = kmalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7065 if (!hw->ksz_switch)
7066 goto pcidev_init_alloc_err;
7067 memset(hw->ksz_switch, 0, sizeof(struct ksz_switch));
7068
7069 sw = hw->ksz_switch;
7070 }
7071 for (i = 0; i < hw->mib_port_cnt; i++)
7072 hw->port_mib[i].mib_start = 0;
7073
7074 hw->parent = hw_priv;
7075
7076 /* Default MTU is 1500. */
7077 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7078
7079 if (ksz_alloc_mem(hw_priv))
7080 goto pcidev_init_mem_err;
7081
7082 hw_priv->hw.id = net_device_present;
7083
7084 spin_lock_init(&hw_priv->hwlock);
7085 mutex_init(&hw_priv->lock);
7086
7087 /* tasklet is enabled. */
7088 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
7089 (unsigned long) hw_priv);
7090 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
7091 (unsigned long) hw_priv);
7092
7093 /* tasklet_enable will decrement the atomic counter. */
7094 tasklet_disable(&hw_priv->rx_tasklet);
7095 tasklet_disable(&hw_priv->tx_tasklet);
7096
7097 for (i = 0; i < TOTAL_PORT_NUM; i++)
7098 init_waitqueue_head(&hw_priv->counter[i].counter);
7099
7100 if (macaddr[0] != ':')
7101 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7102
7103 /* Read MAC address and initialize override address if not overrided. */
7104 hw_read_addr(hw);
7105
7106 /* Multiple device interfaces mode requires a second MAC address. */
7107 if (hw->dev_count > 1) {
7108 memcpy(sw->other_addr, hw->override_addr, MAC_ADDR_LEN);
7109 read_other_addr(hw);
7110 if (mac1addr[0] != ':')
7111 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7112 }
7113
7114 hw_setup(hw);
7115 if (hw->ksz_switch)
7116 sw_setup(hw);
7117 else {
7118 hw_priv->wol_support = WOL_SUPPORT;
7119 hw_priv->wol_enable = 0;
7120 }
7121
7122 INIT_WORK(&hw_priv->mib_read, mib_read_work);
7123
7124 /* 500 ms timeout */
7125 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7126 mib_monitor, hw_priv);
7127
7128 for (i = 0; i < hw->dev_count; i++) {
7129 dev = alloc_etherdev(sizeof(struct dev_priv));
7130 if (!dev)
7131 goto pcidev_init_reg_err;
7132 info->netdev[i] = dev;
7133
7134 priv = netdev_priv(dev);
7135 priv->adapter = hw_priv;
7136 priv->id = net_device_present++;
7137
7138 port = &priv->port;
7139 port->port_cnt = port_count;
7140 port->mib_port_cnt = mib_port_count;
7141 port->first_port = i;
7142 port->flow_ctrl = PHY_FLOW_CTRL;
7143
7144 port->hw = hw;
7145 port->linked = &hw->port_info[port->first_port];
7146
7147 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7148 hw->port_info[pi].port_id = pi;
7149 hw->port_info[pi].pdev = dev;
7150 hw->port_info[pi].state = media_disconnected;
7151 }
7152
7153 dev->mem_start = (unsigned long) hw->io;
7154 dev->mem_end = dev->mem_start + reg_len - 1;
7155 dev->irq = pdev->irq;
7156 if (MAIN_PORT == i)
7157 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7158 MAC_ADDR_LEN);
7159 else {
7160 memcpy(dev->dev_addr, sw->other_addr,
7161 MAC_ADDR_LEN);
7162 if (!memcmp(sw->other_addr, hw->override_addr,
7163 MAC_ADDR_LEN))
7164 dev->dev_addr[5] += port->first_port;
7165 }
7166
7167 dev->netdev_ops = &netdev_ops;
7168 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7169 if (register_netdev(dev))
7170 goto pcidev_init_reg_err;
7171 port_set_power_saving(port, true);
7172 }
7173
7174 pci_dev_get(hw_priv->pdev);
7175 pci_set_drvdata(pdev, info);
7176 return 0;
7177
7178pcidev_init_reg_err:
7179 for (i = 0; i < hw->dev_count; i++) {
7180 if (info->netdev[i]) {
7181 netdev_free(info->netdev[i]);
7182 info->netdev[i] = NULL;
7183 }
7184 }
7185
7186pcidev_init_mem_err:
7187 ksz_free_mem(hw_priv);
7188 kfree(hw->ksz_switch);
7189
7190pcidev_init_alloc_err:
7191 iounmap(hw->io);
7192
7193pcidev_init_io_err:
7194 kfree(info);
7195
7196pcidev_init_dev_err:
7197 release_mem_region(reg_base, reg_len);
7198
7199 return result;
7200}
7201
7202static void pcidev_exit(struct pci_dev *pdev)
7203{
7204 int i;
7205 struct platform_info *info = pci_get_drvdata(pdev);
7206 struct dev_info *hw_priv = &info->dev_info;
7207
7208 pci_set_drvdata(pdev, NULL);
7209
7210 release_mem_region(pci_resource_start(pdev, 0),
7211 pci_resource_len(pdev, 0));
7212 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7213 if (info->netdev[i])
7214 netdev_free(info->netdev[i]);
7215 }
7216 if (hw_priv->hw.io)
7217 iounmap(hw_priv->hw.io);
7218 ksz_free_mem(hw_priv);
7219 kfree(hw_priv->hw.ksz_switch);
7220 pci_dev_put(hw_priv->pdev);
7221 kfree(info);
7222}
7223
7224#ifdef CONFIG_PM
7225static int pcidev_resume(struct pci_dev *pdev)
7226{
7227 int i;
7228 struct platform_info *info = pci_get_drvdata(pdev);
7229 struct dev_info *hw_priv = &info->dev_info;
7230 struct ksz_hw *hw = &hw_priv->hw;
7231
7232 pci_set_power_state(pdev, PCI_D0);
7233 pci_restore_state(pdev);
7234 pci_enable_wake(pdev, PCI_D0, 0);
7235
7236 if (hw_priv->wol_enable)
7237 hw_cfg_wol_pme(hw, 0);
7238 for (i = 0; i < hw->dev_count; i++) {
7239 if (info->netdev[i]) {
7240 struct net_device *dev = info->netdev[i];
7241
7242 if (netif_running(dev)) {
7243 netdev_open(dev);
7244 netif_device_attach(dev);
7245 }
7246 }
7247 }
7248 return 0;
7249}
7250
7251static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7252{
7253 int i;
7254 struct platform_info *info = pci_get_drvdata(pdev);
7255 struct dev_info *hw_priv = &info->dev_info;
7256 struct ksz_hw *hw = &hw_priv->hw;
7257
7258 /* Need to find a way to retrieve the device IP address. */
7259 u8 net_addr[] = { 192, 168, 1, 1 };
7260
7261 for (i = 0; i < hw->dev_count; i++) {
7262 if (info->netdev[i]) {
7263 struct net_device *dev = info->netdev[i];
7264
7265 if (netif_running(dev)) {
7266 netif_device_detach(dev);
7267 netdev_close(dev);
7268 }
7269 }
7270 }
7271 if (hw_priv->wol_enable) {
7272 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7273 hw_cfg_wol_pme(hw, 1);
7274 }
7275
7276 pci_save_state(pdev);
7277 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7278 pci_set_power_state(pdev, pci_choose_state(pdev, state));
7279 return 0;
7280}
7281#endif
7282
7283static char pcidev_name[] = "ksz884xp";
7284
7285static struct pci_device_id pcidev_table[] = {
7286 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7288 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7290 { 0 }
7291};
7292
7293MODULE_DEVICE_TABLE(pci, pcidev_table);
7294
7295static struct pci_driver pci_device_driver = {
7296#ifdef CONFIG_PM
7297 .suspend = pcidev_suspend,
7298 .resume = pcidev_resume,
7299#endif
7300 .name = pcidev_name,
7301 .id_table = pcidev_table,
7302 .probe = pcidev_init,
7303 .remove = pcidev_exit
7304};
7305
7306static int __init ksz884x_init_module(void)
7307{
7308 return pci_register_driver(&pci_device_driver);
7309}
7310
7311static void __exit ksz884x_cleanup_module(void)
7312{
7313 pci_unregister_driver(&pci_device_driver);
7314}
7315
7316module_init(ksz884x_init_module);
7317module_exit(ksz884x_cleanup_module);
7318
7319MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7320MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7321MODULE_LICENSE("GPL");
7322
7323module_param_named(message, msg_enable, int, 0);
7324MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7325
7326module_param(macaddr, charp, 0);
7327module_param(mac1addr, charp, 0);
7328module_param(fast_aging, int, 0);
7329module_param(multi_dev, int, 0);
7330module_param(stp, int, 0);
7331MODULE_PARM_DESC(macaddr, "MAC address");
7332MODULE_PARM_DESC(mac1addr, "Second MAC address");
7333MODULE_PARM_DESC(fast_aging, "Fast aging");
7334MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7335MODULE_PARM_DESC(stp, "STP support");