diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-08-12 22:48:01 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-12 22:48:01 -0400 |
commit | e290861f99131fc42d98012a9ea2dc185f08f8f9 (patch) | |
tree | 5c8b92d095d74d03b281711c81bac54bd59989cd /drivers/net/ixgbe | |
parent | b4a757367d36cebddcd332a4024d92f1e87af370 (diff) | |
parent | dbefd606a3b3634799b625f4900336e61c89e868 (diff) |
Merge branch 'sh/stable-updates'
Diffstat (limited to 'drivers/net/ixgbe')
-rw-r--r-- | drivers/net/ixgbe/ixgbe.h | 3 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_82598.c | 67 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_dcb_nl.c | 24 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_ethtool.c | 11 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_main.c | 77 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_type.h | 8 |
6 files changed, 157 insertions, 33 deletions
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h index cd22323cfd22..e11d83d5852b 100644 --- a/drivers/net/ixgbe/ixgbe.h +++ b/drivers/net/ixgbe/ixgbe.h | |||
@@ -96,6 +96,8 @@ | |||
96 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 | 96 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 |
97 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 | 97 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
98 | 98 | ||
99 | #define IXGBE_MAX_RSC_INT_RATE 162760 | ||
100 | |||
99 | /* wrapper around a pointer to a socket buffer, | 101 | /* wrapper around a pointer to a socket buffer, |
100 | * so a DMA handle can be stored along with the buffer */ | 102 | * so a DMA handle can be stored along with the buffer */ |
101 | struct ixgbe_tx_buffer { | 103 | struct ixgbe_tx_buffer { |
@@ -327,6 +329,7 @@ struct ixgbe_adapter { | |||
327 | #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25) | 329 | #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25) |
328 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26) | 330 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26) |
329 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27) | 331 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27) |
332 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 28) | ||
330 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29) | 333 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29) |
331 | 334 | ||
332 | u32 flags2; | 335 | u32 flags2; |
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c index b9923047ce11..522c03bc1dad 100644 --- a/drivers/net/ixgbe/ixgbe_82598.c +++ b/drivers/net/ixgbe/ixgbe_82598.c | |||
@@ -50,6 +50,51 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, | |||
50 | u8 *eeprom_data); | 50 | u8 *eeprom_data); |
51 | 51 | ||
52 | /** | 52 | /** |
53 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | ||
54 | * @hw: pointer to the HW structure | ||
55 | * | ||
56 | * The defaults for 82598 should be in the range of 50us to 50ms, | ||
57 | * however the hardware default for these parts is 500us to 1ms which is less | ||
58 | * than the 10ms recommended by the pci-e spec. To address this we need to | ||
59 | * increase the value to either 10ms to 250ms for capability version 1 config, | ||
60 | * or 16ms to 55ms for version 2. | ||
61 | **/ | ||
62 | void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) | ||
63 | { | ||
64 | struct ixgbe_adapter *adapter = hw->back; | ||
65 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | ||
66 | u16 pcie_devctl2; | ||
67 | |||
68 | /* only take action if timeout value is defaulted to 0 */ | ||
69 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | ||
70 | goto out; | ||
71 | |||
72 | /* | ||
73 | * if capababilities version is type 1 we can write the | ||
74 | * timeout of 10ms to 250ms through the GCR register | ||
75 | */ | ||
76 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | ||
77 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | ||
78 | goto out; | ||
79 | } | ||
80 | |||
81 | /* | ||
82 | * for version 2 capabilities we need to write the config space | ||
83 | * directly in order to set the completion timeout value for | ||
84 | * 16ms to 55ms | ||
85 | */ | ||
86 | pci_read_config_word(adapter->pdev, | ||
87 | IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); | ||
88 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; | ||
89 | pci_write_config_word(adapter->pdev, | ||
90 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | ||
91 | out: | ||
92 | /* disable completion timeout resend */ | ||
93 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | ||
94 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | ||
95 | } | ||
96 | |||
97 | /** | ||
53 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count | 98 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count |
54 | * @hw: pointer to hardware structure | 99 | * @hw: pointer to hardware structure |
55 | * | 100 | * |
@@ -153,6 +198,26 @@ out: | |||
153 | } | 198 | } |
154 | 199 | ||
155 | /** | 200 | /** |
201 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | ||
202 | * @hw: pointer to hardware structure | ||
203 | * | ||
204 | * Starts the hardware using the generic start_hw function. | ||
205 | * Then set pcie completion timeout | ||
206 | **/ | ||
207 | s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) | ||
208 | { | ||
209 | s32 ret_val = 0; | ||
210 | |||
211 | ret_val = ixgbe_start_hw_generic(hw); | ||
212 | |||
213 | /* set the completion timeout for interface */ | ||
214 | if (ret_val == 0) | ||
215 | ixgbe_set_pcie_completion_timeout(hw); | ||
216 | |||
217 | return ret_val; | ||
218 | } | ||
219 | |||
220 | /** | ||
156 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities | 221 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
157 | * @hw: pointer to hardware structure | 222 | * @hw: pointer to hardware structure |
158 | * @speed: pointer to link speed | 223 | * @speed: pointer to link speed |
@@ -1085,7 +1150,7 @@ out: | |||
1085 | static struct ixgbe_mac_operations mac_ops_82598 = { | 1150 | static struct ixgbe_mac_operations mac_ops_82598 = { |
1086 | .init_hw = &ixgbe_init_hw_generic, | 1151 | .init_hw = &ixgbe_init_hw_generic, |
1087 | .reset_hw = &ixgbe_reset_hw_82598, | 1152 | .reset_hw = &ixgbe_reset_hw_82598, |
1088 | .start_hw = &ixgbe_start_hw_generic, | 1153 | .start_hw = &ixgbe_start_hw_82598, |
1089 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, | 1154 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
1090 | .get_media_type = &ixgbe_get_media_type_82598, | 1155 | .get_media_type = &ixgbe_get_media_type_82598, |
1091 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, | 1156 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c index da2c8514b8d0..1c7265732900 100644 --- a/drivers/net/ixgbe/ixgbe_dcb_nl.c +++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c | |||
@@ -139,6 +139,18 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state) | |||
139 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | 139 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; |
140 | } | 140 | } |
141 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; | 141 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
142 | #ifdef IXGBE_FCOE | ||
143 | /* Turn on FCoE offload */ | ||
144 | if ((adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) && | ||
145 | (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))) { | ||
146 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | ||
147 | adapter->ring_feature[RING_F_FCOE].indices = | ||
148 | IXGBE_FCRETA_SIZE; | ||
149 | netdev->features |= NETIF_F_FCOE_CRC; | ||
150 | netdev->features |= NETIF_F_FSO; | ||
151 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; | ||
152 | } | ||
153 | #endif /* IXGBE_FCOE */ | ||
142 | ixgbe_init_interrupt_scheme(adapter); | 154 | ixgbe_init_interrupt_scheme(adapter); |
143 | if (netif_running(netdev)) | 155 | if (netif_running(netdev)) |
144 | netdev->netdev_ops->ndo_open(netdev); | 156 | netdev->netdev_ops->ndo_open(netdev); |
@@ -156,6 +168,18 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state) | |||
156 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | 168 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; |
157 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | 169 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
158 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | 170 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; |
171 | |||
172 | #ifdef IXGBE_FCOE | ||
173 | /* Turn off FCoE offload */ | ||
174 | if (adapter->flags & (IXGBE_FLAG_FCOE_CAPABLE | | ||
175 | IXGBE_FLAG_FCOE_ENABLED)) { | ||
176 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | ||
177 | adapter->ring_feature[RING_F_FCOE].indices = 0; | ||
178 | netdev->features &= ~NETIF_F_FCOE_CRC; | ||
179 | netdev->features &= ~NETIF_F_FSO; | ||
180 | netdev->fcoe_ddp_xid = 0; | ||
181 | } | ||
182 | #endif /* IXGBE_FCOE */ | ||
159 | ixgbe_init_interrupt_scheme(adapter); | 183 | ixgbe_init_interrupt_scheme(adapter); |
160 | if (netif_running(netdev)) | 184 | if (netif_running(netdev)) |
161 | netdev->netdev_ops->ndo_open(netdev); | 185 | netdev->netdev_ops->ndo_open(netdev); |
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c index 2a978008fd6e..79144e950a34 100644 --- a/drivers/net/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ixgbe/ixgbe_ethtool.c | |||
@@ -1975,7 +1975,10 @@ static int ixgbe_set_coalesce(struct net_device *netdev, | |||
1975 | * any other value means disable eitr, which is best | 1975 | * any other value means disable eitr, which is best |
1976 | * served by setting the interrupt rate very high | 1976 | * served by setting the interrupt rate very high |
1977 | */ | 1977 | */ |
1978 | adapter->eitr_param = IXGBE_MAX_INT_RATE; | 1978 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
1979 | adapter->eitr_param = IXGBE_MAX_RSC_INT_RATE; | ||
1980 | else | ||
1981 | adapter->eitr_param = IXGBE_MAX_INT_RATE; | ||
1979 | adapter->itr_setting = 0; | 1982 | adapter->itr_setting = 0; |
1980 | } | 1983 | } |
1981 | 1984 | ||
@@ -1999,13 +2002,13 @@ static int ixgbe_set_flags(struct net_device *netdev, u32 data) | |||
1999 | 2002 | ||
2000 | ethtool_op_set_flags(netdev, data); | 2003 | ethtool_op_set_flags(netdev, data); |
2001 | 2004 | ||
2002 | if (!(adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)) | 2005 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) |
2003 | return 0; | 2006 | return 0; |
2004 | 2007 | ||
2005 | /* if state changes we need to update adapter->flags and reset */ | 2008 | /* if state changes we need to update adapter->flags and reset */ |
2006 | if ((!!(data & ETH_FLAG_LRO)) != | 2009 | if ((!!(data & ETH_FLAG_LRO)) != |
2007 | (!!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED))) { | 2010 | (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) { |
2008 | adapter->flags ^= IXGBE_FLAG2_RSC_ENABLED; | 2011 | adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; |
2009 | if (netif_running(netdev)) | 2012 | if (netif_running(netdev)) |
2010 | ixgbe_reinit_locked(adapter); | 2013 | ixgbe_reinit_locked(adapter); |
2011 | else | 2014 | else |
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index e3442f47f932..110c65ab5cb5 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <linux/in.h> | 34 | #include <linux/in.h> |
35 | #include <linux/ip.h> | 35 | #include <linux/ip.h> |
36 | #include <linux/tcp.h> | 36 | #include <linux/tcp.h> |
37 | #include <linux/pkt_sched.h> | ||
37 | #include <linux/ipv6.h> | 38 | #include <linux/ipv6.h> |
38 | #include <net/checksum.h> | 39 | #include <net/checksum.h> |
39 | #include <net/ip6_checksum.h> | 40 | #include <net/ip6_checksum.h> |
@@ -510,8 +511,11 @@ static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, | |||
510 | * @skb: skb currently being received and modified | 511 | * @skb: skb currently being received and modified |
511 | **/ | 512 | **/ |
512 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, | 513 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
513 | u32 status_err, struct sk_buff *skb) | 514 | union ixgbe_adv_rx_desc *rx_desc, |
515 | struct sk_buff *skb) | ||
514 | { | 516 | { |
517 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); | ||
518 | |||
515 | skb->ip_summed = CHECKSUM_NONE; | 519 | skb->ip_summed = CHECKSUM_NONE; |
516 | 520 | ||
517 | /* Rx csum disabled */ | 521 | /* Rx csum disabled */ |
@@ -529,6 +533,16 @@ static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, | |||
529 | return; | 533 | return; |
530 | 534 | ||
531 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | 535 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { |
536 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | ||
537 | |||
538 | /* | ||
539 | * 82599 errata, UDP frames with a 0 checksum can be marked as | ||
540 | * checksum errors. | ||
541 | */ | ||
542 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | ||
543 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | ||
544 | return; | ||
545 | |||
532 | adapter->hw_csum_rx_error++; | 546 | adapter->hw_csum_rx_error++; |
533 | return; | 547 | return; |
534 | } | 548 | } |
@@ -766,7 +780,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, | |||
766 | prefetch(next_rxd); | 780 | prefetch(next_rxd); |
767 | cleaned_count++; | 781 | cleaned_count++; |
768 | 782 | ||
769 | if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE) | 783 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
770 | rsc_count = ixgbe_get_rsc_count(rx_desc); | 784 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
771 | 785 | ||
772 | if (rsc_count) { | 786 | if (rsc_count) { |
@@ -802,7 +816,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, | |||
802 | goto next_desc; | 816 | goto next_desc; |
803 | } | 817 | } |
804 | 818 | ||
805 | ixgbe_rx_checksum(adapter, staterr, skb); | 819 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
806 | 820 | ||
807 | /* probably a little skewed due to removing CRC */ | 821 | /* probably a little skewed due to removing CRC */ |
808 | total_rx_bytes += skb->len; | 822 | total_rx_bytes += skb->len; |
@@ -2022,7 +2036,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |||
2022 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); | 2036 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
2023 | } | 2037 | } |
2024 | } else { | 2038 | } else { |
2025 | if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) && | 2039 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
2026 | (netdev->mtu <= ETH_DATA_LEN)) | 2040 | (netdev->mtu <= ETH_DATA_LEN)) |
2027 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; | 2041 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
2028 | else | 2042 | else |
@@ -2151,7 +2165,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |||
2151 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | 2165 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2152 | } | 2166 | } |
2153 | 2167 | ||
2154 | if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) { | 2168 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
2155 | /* Enable 82599 HW-RSC */ | 2169 | /* Enable 82599 HW-RSC */ |
2156 | for (i = 0; i < adapter->num_rx_queues; i++) { | 2170 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2157 | j = adapter->rx_ring[i].reg_idx; | 2171 | j = adapter->rx_ring[i].reg_idx; |
@@ -3798,16 +3812,17 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |||
3798 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; | 3812 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
3799 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | 3813 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
3800 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; | 3814 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
3801 | adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE; | 3815 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
3802 | adapter->flags |= IXGBE_FLAG2_RSC_ENABLED; | 3816 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; |
3803 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | 3817 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3804 | adapter->ring_feature[RING_F_FDIR].indices = | 3818 | adapter->ring_feature[RING_F_FDIR].indices = |
3805 | IXGBE_MAX_FDIR_INDICES; | 3819 | IXGBE_MAX_FDIR_INDICES; |
3806 | adapter->atr_sample_rate = 20; | 3820 | adapter->atr_sample_rate = 20; |
3807 | adapter->fdir_pballoc = 0; | 3821 | adapter->fdir_pballoc = 0; |
3808 | #ifdef IXGBE_FCOE | 3822 | #ifdef IXGBE_FCOE |
3809 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | 3823 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
3810 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; | 3824 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; |
3825 | adapter->ring_feature[RING_F_FCOE].indices = 0; | ||
3811 | #endif /* IXGBE_FCOE */ | 3826 | #endif /* IXGBE_FCOE */ |
3812 | } | 3827 | } |
3813 | 3828 | ||
@@ -5125,9 +5140,6 @@ static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
5125 | int count = 0; | 5140 | int count = 0; |
5126 | unsigned int f; | 5141 | unsigned int f; |
5127 | 5142 | ||
5128 | r_idx = skb->queue_mapping; | ||
5129 | tx_ring = &adapter->tx_ring[r_idx]; | ||
5130 | |||
5131 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | 5143 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
5132 | tx_flags |= vlan_tx_tag_get(skb); | 5144 | tx_flags |= vlan_tx_tag_get(skb); |
5133 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | 5145 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
@@ -5137,11 +5149,19 @@ static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
5137 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | 5149 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
5138 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | 5150 | tx_flags |= IXGBE_TX_FLAGS_VLAN; |
5139 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | 5151 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5140 | tx_flags |= (skb->queue_mapping << 13); | 5152 | if (skb->priority != TC_PRIO_CONTROL) { |
5141 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | 5153 | tx_flags |= (skb->queue_mapping << 13); |
5142 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | 5154 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
5155 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | ||
5156 | } else { | ||
5157 | skb->queue_mapping = | ||
5158 | adapter->ring_feature[RING_F_DCB].indices-1; | ||
5159 | } | ||
5143 | } | 5160 | } |
5144 | 5161 | ||
5162 | r_idx = skb->queue_mapping; | ||
5163 | tx_ring = &adapter->tx_ring[r_idx]; | ||
5164 | |||
5145 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | 5165 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && |
5146 | (skb->protocol == htons(ETH_P_FCOE))) | 5166 | (skb->protocol == htons(ETH_P_FCOE))) |
5147 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | 5167 | tx_flags |= IXGBE_TX_FLAGS_FCOE; |
@@ -5340,12 +5360,19 @@ static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |||
5340 | static void ixgbe_netpoll(struct net_device *netdev) | 5360 | static void ixgbe_netpoll(struct net_device *netdev) |
5341 | { | 5361 | { |
5342 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | 5362 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
5363 | int i; | ||
5343 | 5364 | ||
5344 | disable_irq(adapter->pdev->irq); | ||
5345 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | 5365 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
5346 | ixgbe_intr(adapter->pdev->irq, netdev); | 5366 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
5367 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | ||
5368 | for (i = 0; i < num_q_vectors; i++) { | ||
5369 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | ||
5370 | ixgbe_msix_clean_many(0, q_vector); | ||
5371 | } | ||
5372 | } else { | ||
5373 | ixgbe_intr(adapter->pdev->irq, netdev); | ||
5374 | } | ||
5347 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | 5375 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
5348 | enable_irq(adapter->pdev->irq); | ||
5349 | } | 5376 | } |
5350 | #endif | 5377 | #endif |
5351 | 5378 | ||
@@ -5580,23 +5607,18 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev, | |||
5580 | #endif | 5607 | #endif |
5581 | 5608 | ||
5582 | #ifdef IXGBE_FCOE | 5609 | #ifdef IXGBE_FCOE |
5583 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | 5610 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
5584 | if (hw->mac.ops.get_device_caps) { | 5611 | if (hw->mac.ops.get_device_caps) { |
5585 | hw->mac.ops.get_device_caps(hw, &device_caps); | 5612 | hw->mac.ops.get_device_caps(hw, &device_caps); |
5586 | if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) { | 5613 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
5587 | netdev->features |= NETIF_F_FCOE_CRC; | 5614 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; |
5588 | netdev->features |= NETIF_F_FSO; | ||
5589 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; | ||
5590 | } else { | ||
5591 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | ||
5592 | } | ||
5593 | } | 5615 | } |
5594 | } | 5616 | } |
5595 | #endif /* IXGBE_FCOE */ | 5617 | #endif /* IXGBE_FCOE */ |
5596 | if (pci_using_dac) | 5618 | if (pci_using_dac) |
5597 | netdev->features |= NETIF_F_HIGHDMA; | 5619 | netdev->features |= NETIF_F_HIGHDMA; |
5598 | 5620 | ||
5599 | if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) | 5621 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
5600 | netdev->features |= NETIF_F_LRO; | 5622 | netdev->features |= NETIF_F_LRO; |
5601 | 5623 | ||
5602 | /* make sure the EEPROM is good */ | 5624 | /* make sure the EEPROM is good */ |
@@ -5638,7 +5660,6 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev, | |||
5638 | adapter->wol = 0; | 5660 | adapter->wol = 0; |
5639 | break; | 5661 | break; |
5640 | } | 5662 | } |
5641 | device_init_wakeup(&adapter->pdev->dev, true); | ||
5642 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | 5663 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
5643 | 5664 | ||
5644 | /* pick up the PCI bus settings for reporting later */ | 5665 | /* pick up the PCI bus settings for reporting later */ |
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index fa87309dc087..be90eb4575f6 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h | |||
@@ -718,6 +718,12 @@ | |||
718 | #define IXGBE_ECC_STATUS_82599 0x110E0 | 718 | #define IXGBE_ECC_STATUS_82599 0x110E0 |
719 | #define IXGBE_BAR_CTRL_82599 0x110F4 | 719 | #define IXGBE_BAR_CTRL_82599 0x110F4 |
720 | 720 | ||
721 | /* PCI Express Control */ | ||
722 | #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 | ||
723 | #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 | ||
724 | #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 | ||
725 | #define IXGBE_GCR_CAP_VER2 0x00040000 | ||
726 | |||
721 | /* Time Sync Registers */ | 727 | /* Time Sync Registers */ |
722 | #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ | 728 | #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ |
723 | #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ | 729 | #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ |
@@ -1521,6 +1527,7 @@ | |||
1521 | 1527 | ||
1522 | /* PCI Bus Info */ | 1528 | /* PCI Bus Info */ |
1523 | #define IXGBE_PCI_LINK_STATUS 0xB2 | 1529 | #define IXGBE_PCI_LINK_STATUS 0xB2 |
1530 | #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 | ||
1524 | #define IXGBE_PCI_LINK_WIDTH 0x3F0 | 1531 | #define IXGBE_PCI_LINK_WIDTH 0x3F0 |
1525 | #define IXGBE_PCI_LINK_WIDTH_1 0x10 | 1532 | #define IXGBE_PCI_LINK_WIDTH_1 0x10 |
1526 | #define IXGBE_PCI_LINK_WIDTH_2 0x20 | 1533 | #define IXGBE_PCI_LINK_WIDTH_2 0x20 |
@@ -1531,6 +1538,7 @@ | |||
1531 | #define IXGBE_PCI_LINK_SPEED_5000 0x2 | 1538 | #define IXGBE_PCI_LINK_SPEED_5000 0x2 |
1532 | #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E | 1539 | #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E |
1533 | #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 | 1540 | #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 |
1541 | #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 | ||
1534 | 1542 | ||
1535 | /* Number of 100 microseconds we wait for PCI Express master disable */ | 1543 | /* Number of 100 microseconds we wait for PCI Express master disable */ |
1536 | #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 | 1544 | #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 |