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authorAlexander Duyck <alexander.h.duyck@intel.com>2010-08-19 09:34:27 -0400
committerDavid S. Miller <davem@davemloft.net>2010-08-19 19:40:48 -0400
commit179b4096e25c190fc987832e0037b40507cc7ca0 (patch)
treee9bfe0f3cdc31b1e4d575b3457cdbd6126fd4de6 /drivers/net/ixgbe
parent67ebd79141e2dd503b0bc4898d06d07f07fc2635 (diff)
ixgbe: combine two modifications of TXDCTL into one
In ixgbe_up_complete we were doing a read-modify-write of TXDCTL followed by another one just a few lines further down. Instead of performing two separate read-modify-writes it would make more sense to combine the two into one. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe')
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c18
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index fffb1ce4f6ea..5d90f699fa78 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -3411,6 +3411,12 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3411 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3411 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3412 } 3412 }
3413 3413
3414 if (hw->mac.type == ixgbe_mac_82599EB) {
3415 /* DMATXCTL.EN must be set after all Tx queue config is done */
3416 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3417 dmatxctl |= IXGBE_DMATXCTL_TE;
3418 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3419 }
3414 for (i = 0; i < adapter->num_tx_queues; i++) { 3420 for (i = 0; i < adapter->num_tx_queues; i++) {
3415 j = adapter->tx_ring[i]->reg_idx; 3421 j = adapter->tx_ring[i]->reg_idx;
3416 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); 3422 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
@@ -3421,18 +3427,6 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3421 /* enable WTHRESH=8 descriptors, to encourage burst writeback */ 3427 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3422 txdctl |= (8 << 16); 3428 txdctl |= (8 << 16);
3423 } 3429 }
3424 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3425 }
3426
3427 if (hw->mac.type == ixgbe_mac_82599EB) {
3428 /* DMATXCTL.EN must be set after all Tx queue config is done */
3429 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3430 dmatxctl |= IXGBE_DMATXCTL_TE;
3431 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3432 }
3433 for (i = 0; i < adapter->num_tx_queues; i++) {
3434 j = adapter->tx_ring[i]->reg_idx;
3435 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3436 txdctl |= IXGBE_TXDCTL_ENABLE; 3430 txdctl |= IXGBE_TXDCTL_ENABLE;
3437 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); 3431 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3438 if (hw->mac.type == ixgbe_mac_82599EB) { 3432 if (hw->mac.type == ixgbe_mac_82599EB) {