intel drivers: repair missing flush operations

after review of all intel drivers, found several instances where
drivers had the incorrect pattern of:
memory mapped write();
delay();

which should always be:
memory mapped write();
write flush(); /* aka memory mapped read */
delay();

explanation:
The reason for including the flush is that writes can be held
(posted) in PCI/PCIe bridges, but the read always has to complete
synchronously and therefore has to flush all pending writes to a
device.  If a write is held and followed by a delay, the delay
means nothing because the write may not have reached hardware
(maybe even not until the next read)

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by:  Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index dc649553a0a6..82d4244c6e10 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -1378,6 +1378,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
 
         /* Disable all the interrupts */
         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+        IXGBE_WRITE_FLUSH(&adapter->hw);
         usleep_range(10000, 20000);
 
         /* Test each interrupt */
@@ -1398,6 +1399,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
                                         ~mask & 0x00007FFF);
                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                         ~mask & 0x00007FFF);
+                        IXGBE_WRITE_FLUSH(&adapter->hw);
                         usleep_range(10000, 20000);
 
                         if (adapter->test_icr & mask) {
@@ -1415,6 +1417,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
                 adapter->test_icr = 0;
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
+                IXGBE_WRITE_FLUSH(&adapter->hw);
                 usleep_range(10000, 20000);
 
                 if (!(adapter->test_icr &mask)) {
@@ -1435,6 +1438,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
                                         ~mask & 0x00007FFF);
                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                         ~mask & 0x00007FFF);
+                        IXGBE_WRITE_FLUSH(&adapter->hw);
                         usleep_range(10000, 20000);
 
                         if (adapter->test_icr) {
@@ -1446,6 +1450,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
 
         /* Disable all the interrupts */
         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+        IXGBE_WRITE_FLUSH(&adapter->hw);
         usleep_range(10000, 20000);
 
         /* Unhook test interrupt handler */