ixgbe: DCB, PFC not cleared until reset occurs

The PFC configuration is not cleared until the device is reset. This
has not been a problem because setting DCB attributes forced a
hardware reset. Now that we no longer require this reset to occur
PFC remains configured even after being disabled until the
device is reset.

This removes a goto in the PFC hardware set routines for 82598 and
82599 devices that was short circuiting the clear.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 26 insertions, 28 deletions

diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 0a482bbf1bd2..025af8c53ddb 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -253,13 +253,6 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
 {
         u32 i, reg, rx_pba_size;
 
-        /* If PFC is disabled globally then fall back to LFC. */
-        if (!pfc_en) {
-                for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
-                        hw->mac.ops.fc_enable(hw, i);
-                goto out;
-        }
-
         /* Configure PFC Tx thresholds per TC */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
                 int enabled = pfc_en & (1 << i);
@@ -278,28 +271,33 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
         }
 
-        /* Configure pause time (2 TCs per register) */
-        reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
-        for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
-                IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
-
-        /* Configure flow control refresh threshold value */
-        IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
-
-        /* Enable Transmit PFC */
-        reg = IXGBE_FCCFG_TFCE_PRIORITY;
-        IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
+        if (pfc_en) {
+                /* Configure pause time (2 TCs per register) */
+                reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
+                for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
+                        IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
+
+                /* Configure flow control refresh threshold value */
+                IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
+
+
+                reg = IXGBE_FCCFG_TFCE_PRIORITY;
+                IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
+                /*
+                 * Enable Receive PFC
+                 * We will always honor XOFF frames we receive when
+                 * we are in PFC mode.
+                 */
+                reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+                reg &= ~IXGBE_MFLCN_RFCE;
+                reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
+                IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
+
+        } else {
+                for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
+                        hw->mac.ops.fc_enable(hw, i);
+        }
 
-        /*
-         * Enable Receive PFC
-         * We will always honor XOFF frames we receive when
-         * we are in PFC mode.
-         */
-        reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
-        reg &= ~IXGBE_MFLCN_RFCE;
-        reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
-        IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
-out:
         return 0;
 }