ixgbe: DCB, abstract out dcb_config from DCB hardware configuration

Currently the routines that configure the HW for DCB require a
ixgbe_dcb_config structure. This structure was designed to support
the CEE standard and does not match the IEEE standard well.

This patch changes the HW routines in ixgbe_dcb_8259x.{ch} to use
raw pfc and bandwidth values. This requires some parsing of the DCB
configuration but makes the HW routines independent of the data
structure that contains the DCB configuration.

The primary advantage to doing this is we can do HW setup directly
from the 802.1Qaz ops without having to arbitrarily encapsulate this
data into the CEE structure.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 45 insertions, 41 deletions

diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index 19aa80640f68..d1288060cbd0 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -38,15 +38,14 @@
  *
  * Configure packet buffers for DCB mode.
  */
-static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
-                                                 struct ixgbe_dcb_config *dcb_config)
+static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
 {
         s32 ret_val = 0;
         u32 value = IXGBE_RXPBSIZE_64KB;
         u8  i = 0;
 
         /* Setup Rx packet buffer sizes */
-        switch (dcb_config->rx_pba_cfg) {
+        switch (rx_pba) {
         case pba_80_48:
                 /* Setup the first four at 80KB */
                 value = IXGBE_RXPBSIZE_80KB;
@@ -78,10 +77,11 @@ static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
  *
  * Configure Rx Data Arbiter and credits for each traffic class.
  */
-static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
-                                      struct ixgbe_dcb_config *dcb_config)
+s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
+                                        u16 *refill,
+                                        u16 *max,
+                                        u8 *prio_type)
 {
-        struct tc_bw_alloc    *p;
         u32    reg           = 0;
         u32    credit_refill = 0;
         u32    credit_max    = 0;
@@ -102,13 +102,12 @@ static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
-                credit_refill = p->data_credits_refill;
-                credit_max    = p->data_credits_max;
+                credit_refill = refill[i];
+                credit_max    = max[i];
 
                 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_RT2CR_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
@@ -135,10 +134,12 @@ static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
  *
  * Configure Tx Descriptor Arbiter and credits for each traffic class.
  */
-static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
-                                           struct ixgbe_dcb_config *dcb_config)
+s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
+                                                u16 *refill,
+                                                u16 *max,
+                                                u8 *bwg_id,
+                                                u8 *prio_type)
 {
-        struct tc_bw_alloc *p;
         u32    reg, max_credits;
         u8     i;
 
@@ -156,16 +157,15 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
-                max_credits = dcb_config->tc_config[i].desc_credits_max;
+                max_credits = max[i];
                 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
-                reg |= p->data_credits_refill;
-                reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
+                reg |= refill[i];
+                reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
 
-                if (p->prio_type == prio_group)
+                if (prio_type[i] == prio_group)
                         reg |= IXGBE_TDTQ2TCCR_GSP;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_TDTQ2TCCR_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
@@ -181,10 +181,12 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
  *
  * Configure Tx Data Arbiter and credits for each traffic class.
  */
-static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
-                                           struct ixgbe_dcb_config *dcb_config)
+s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
+                                                u16 *refill,
+                                                u16 *max,
+                                                u8 *bwg_id,
+                                                u8 *prio_type)
 {
-        struct tc_bw_alloc *p;
         u32 reg;
         u8 i;
 
@@ -198,15 +200,14 @@ static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
-                reg = p->data_credits_refill;
-                reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
-                reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
+                reg = refill[i];
+                reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
+                reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
 
-                if (p->prio_type == prio_group)
+                if (prio_type[i] == prio_group)
                         reg |= IXGBE_TDPT2TCCR_GSP;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_TDPT2TCCR_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
@@ -227,13 +228,12 @@ static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
  *
  * Configure Priority Flow Control for each traffic class.
  */
-s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
-                               struct ixgbe_dcb_config *dcb_config)
+s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
 {
         u32 reg, rx_pba_size;
         u8  i;
 
-        if (!dcb_config->pfc_mode_enable)
+        if (!pfc_en)
                 goto out;
 
         /* Enable Transmit Priority Flow Control */
@@ -254,19 +254,20 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
          * for each traffic class.
          */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+                int enabled = pfc_en & (1 << i);
                 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
                 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
                 reg = (rx_pba_size - hw->fc.low_water) << 10;
 
-                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
-                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
+                if (enabled == pfc_enabled_tx ||
+                    enabled == pfc_enabled_full)
                         reg |= IXGBE_FCRTL_XONE;
 
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
 
                 reg = (rx_pba_size - hw->fc.high_water) << 10;
-                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
-                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
+                if (enabled == pfc_enabled_tx ||
+                    enabled == pfc_enabled_full)
                         reg |= IXGBE_FCRTH_FCEN;
 
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
@@ -323,13 +324,16 @@ static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
  * Configure dcb settings and enable dcb mode.
  */
 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
-                              struct ixgbe_dcb_config *dcb_config)
+                              u8 rx_pba, u8 pfc_en, u16 *refill,
+                              u16 *max, u8 *bwg_id, u8 *prio_type)
 {
-        ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
-        ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
-        ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
-        ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
-        ixgbe_dcb_config_pfc_82598(hw, dcb_config);
+        ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
+        ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
+        ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
+                                               bwg_id, prio_type);
+        ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
+                                               bwg_id, prio_type);
+        ixgbe_dcb_config_pfc_82598(hw, pfc_en);
         ixgbe_dcb_config_tc_stats_82598(hw);
 
         return 0;