diff options
author | Emil Tantilov <emil.s.tantilov@intel.com> | 2011-02-19 03:43:44 -0500 |
---|---|---|
committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-03-03 07:20:18 -0500 |
commit | 8c7bea32c4ebe02dbb574a49db418036da177326 (patch) | |
tree | b6c0928b4fb646a661d8b08ca72634dcab503805 /drivers/net/ixgbe/ixgbe_common.c | |
parent | 63d778df6d817ea69cadd701abbfa1c491623b50 (diff) |
ixgbe: Numerous whitespace / formatting cleanups
This patch contains a number of whitespace and formatting cleanups.
Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_common.c')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_common.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index a12f7c73e27d..33f568cff060 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c | |||
@@ -1188,7 +1188,7 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) | |||
1188 | if (status == 0) { | 1188 | if (status == 0) { |
1189 | checksum = hw->eeprom.ops.calc_checksum(hw); | 1189 | checksum = hw->eeprom.ops.calc_checksum(hw); |
1190 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, | 1190 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, |
1191 | checksum); | 1191 | checksum); |
1192 | } else { | 1192 | } else { |
1193 | hw_dbg(hw, "EEPROM read failed\n"); | 1193 | hw_dbg(hw, "EEPROM read failed\n"); |
1194 | } | 1194 | } |
@@ -1555,7 +1555,9 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1555 | * 2: Tx flow control is enabled (we can send pause frames but | 1555 | * 2: Tx flow control is enabled (we can send pause frames but |
1556 | * we do not support receiving pause frames). | 1556 | * we do not support receiving pause frames). |
1557 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | 1557 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
1558 | #ifdef CONFIG_DCB | ||
1558 | * 4: Priority Flow Control is enabled. | 1559 | * 4: Priority Flow Control is enabled. |
1560 | #endif | ||
1559 | * other: Invalid. | 1561 | * other: Invalid. |
1560 | */ | 1562 | */ |
1561 | switch (hw->fc.current_mode) { | 1563 | switch (hw->fc.current_mode) { |
@@ -2392,7 +2394,6 @@ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) | |||
2392 | { | 2394 | { |
2393 | int i; | 2395 | int i; |
2394 | 2396 | ||
2395 | |||
2396 | for (i = 0; i < 128; i++) | 2397 | for (i = 0; i < 128; i++) |
2397 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); | 2398 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); |
2398 | 2399 | ||
@@ -2621,7 +2622,7 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) | |||
2621 | * Reads the links register to determine if link is up and the current speed | 2622 | * Reads the links register to determine if link is up and the current speed |
2622 | **/ | 2623 | **/ |
2623 | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | 2624 | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, |
2624 | bool *link_up, bool link_up_wait_to_complete) | 2625 | bool *link_up, bool link_up_wait_to_complete) |
2625 | { | 2626 | { |
2626 | u32 links_reg, links_orig; | 2627 | u32 links_reg, links_orig; |
2627 | u32 i; | 2628 | u32 i; |