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authorMallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com>2010-05-13 13:33:41 -0400
committerDavid S. Miller <davem@davemloft.net>2010-05-14 00:07:34 -0400
commit21ce849ba5cc178740c6532ba3dded852296ad91 (patch)
treebbf2070fa966bce5a49485df254cfdb653d30aa6 /drivers/net/ixgbe/ixgbe_82599.c
parente8171aaad7ec335b8cbd71f56eb08b545f0c404f (diff)
ixgbe: Refactor common code between 82598 & 82599 to accommodate new hardware
Some of the following MAC functions are moved from 82598 & 82599 specific hardware files to common.[ch] to accommodate new silicon changes. Also fixed some white space issues * get_san_mac_addr, check_link, set_vmdq, clear_vmdq, clear_vfta, * set_vfta, fc_enable, init_uta_tables Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_82599.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c403
1 files changed, 11 insertions, 392 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 38c384031c4c..dc197a4b0676 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -133,27 +133,6 @@ setup_sfp_out:
133 return ret_val; 133 return ret_val;
134} 134}
135 135
136/**
137 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
138 * @hw: pointer to hardware structure
139 *
140 * Read PCIe configuration space, and get the MSI-X vector count from
141 * the capabilities table.
142 **/
143static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
144{
145 struct ixgbe_adapter *adapter = hw->back;
146 u16 msix_count;
147 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
148 &msix_count);
149 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
150
151 /* MSI-X count is zero-based in HW, so increment to give proper value */
152 msix_count++;
153
154 return msix_count;
155}
156
157static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 136static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
158{ 137{
159 struct ixgbe_mac_info *mac = &hw->mac; 138 struct ixgbe_mac_info *mac = &hw->mac;
@@ -165,7 +144,7 @@ static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
165 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
166 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
167 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
168 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw); 147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
169 148
170 return 0; 149 return 0;
171} 150}
@@ -735,60 +714,6 @@ out:
735} 714}
736 715
737/** 716/**
738 * ixgbe_check_mac_link_82599 - Determine link and speed status
739 * @hw: pointer to hardware structure
740 * @speed: pointer to link speed
741 * @link_up: true when link is up
742 * @link_up_wait_to_complete: bool used to wait for link up or not
743 *
744 * Reads the links register to determine if link is up and the current speed
745 **/
746static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
747 ixgbe_link_speed *speed,
748 bool *link_up,
749 bool link_up_wait_to_complete)
750{
751 u32 links_reg;
752 u32 i;
753
754 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
755 if (link_up_wait_to_complete) {
756 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
757 if (links_reg & IXGBE_LINKS_UP) {
758 *link_up = true;
759 break;
760 } else {
761 *link_up = false;
762 }
763 msleep(100);
764 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
765 }
766 } else {
767 if (links_reg & IXGBE_LINKS_UP)
768 *link_up = true;
769 else
770 *link_up = false;
771 }
772
773 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
774 IXGBE_LINKS_SPEED_10G_82599)
775 *speed = IXGBE_LINK_SPEED_10GB_FULL;
776 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
777 IXGBE_LINKS_SPEED_1G_82599)
778 *speed = IXGBE_LINK_SPEED_1GB_FULL;
779 else
780 *speed = IXGBE_LINK_SPEED_100_FULL;
781
782 /* if link is down, zero out the current_mode */
783 if (*link_up == false) {
784 hw->fc.current_mode = ixgbe_fc_none;
785 hw->fc.fc_was_autonegged = false;
786 }
787
788 return 0;
789}
790
791/**
792 * ixgbe_setup_mac_link_82599 - Set MAC link speed 717 * ixgbe_setup_mac_link_82599 - Set MAC link speed
793 * @hw: pointer to hardware structure 718 * @hw: pointer to hardware structure
794 * @speed: new link speed 719 * @speed: new link speed
@@ -1050,243 +975,6 @@ reset_hw_out:
1050} 975}
1051 976
1052/** 977/**
1053 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1054 * @hw: pointer to hardware struct
1055 * @rar: receive address register index to disassociate
1056 * @vmdq: VMDq pool index to remove from the rar
1057 **/
1058static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1059{
1060 u32 mpsar_lo, mpsar_hi;
1061 u32 rar_entries = hw->mac.num_rar_entries;
1062
1063 if (rar < rar_entries) {
1064 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1065 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1066
1067 if (!mpsar_lo && !mpsar_hi)
1068 goto done;
1069
1070 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1071 if (mpsar_lo) {
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1073 mpsar_lo = 0;
1074 }
1075 if (mpsar_hi) {
1076 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1077 mpsar_hi = 0;
1078 }
1079 } else if (vmdq < 32) {
1080 mpsar_lo &= ~(1 << vmdq);
1081 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1082 } else {
1083 mpsar_hi &= ~(1 << (vmdq - 32));
1084 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1085 }
1086
1087 /* was that the last pool using this rar? */
1088 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1089 hw->mac.ops.clear_rar(hw, rar);
1090 } else {
1091 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1092 }
1093
1094done:
1095 return 0;
1096}
1097
1098/**
1099 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1100 * @hw: pointer to hardware struct
1101 * @rar: receive address register index to associate with a VMDq index
1102 * @vmdq: VMDq pool index
1103 **/
1104static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1105{
1106 u32 mpsar;
1107 u32 rar_entries = hw->mac.num_rar_entries;
1108
1109 if (rar < rar_entries) {
1110 if (vmdq < 32) {
1111 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1112 mpsar |= 1 << vmdq;
1113 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1114 } else {
1115 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1116 mpsar |= 1 << (vmdq - 32);
1117 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1118 }
1119 } else {
1120 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1121 }
1122 return 0;
1123}
1124
1125/**
1126 * ixgbe_set_vfta_82599 - Set VLAN filter table
1127 * @hw: pointer to hardware structure
1128 * @vlan: VLAN id to write to VLAN filter
1129 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1130 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1131 *
1132 * Turn on/off specified VLAN in the VLAN filter table.
1133 **/
1134static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1135 bool vlan_on)
1136{
1137 u32 regindex;
1138 u32 vlvf_index;
1139 u32 bitindex;
1140 u32 bits;
1141 u32 first_empty_slot;
1142 u32 vt_ctl;
1143
1144 if (vlan > 4095)
1145 return IXGBE_ERR_PARAM;
1146
1147 /*
1148 * this is a 2 part operation - first the VFTA, then the
1149 * VLVF and VLVFB if vind is set
1150 */
1151
1152 /* Part 1
1153 * The VFTA is a bitstring made up of 128 32-bit registers
1154 * that enable the particular VLAN id, much like the MTA:
1155 * bits[11-5]: which register
1156 * bits[4-0]: which bit in the register
1157 */
1158 regindex = (vlan >> 5) & 0x7F;
1159 bitindex = vlan & 0x1F;
1160 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1161 if (vlan_on)
1162 bits |= (1 << bitindex);
1163 else
1164 bits &= ~(1 << bitindex);
1165 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1166
1167
1168 /* Part 2
1169 * If VT mode is set
1170 * Either vlan_on
1171 * make sure the vlan is in VLVF
1172 * set the vind bit in the matching VLVFB
1173 * Or !vlan_on
1174 * clear the pool bit and possibly the vind
1175 */
1176 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1177 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1178 goto out;
1179
1180 /* find the vlanid or the first empty slot */
1181 first_empty_slot = 0;
1182
1183 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1184 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1185 if (!bits && !first_empty_slot)
1186 first_empty_slot = vlvf_index;
1187 else if ((bits & 0x0FFF) == vlan)
1188 break;
1189 }
1190
1191 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1192 if (first_empty_slot)
1193 vlvf_index = first_empty_slot;
1194 else {
1195 hw_dbg(hw, "No space in VLVF.\n");
1196 goto out;
1197 }
1198 }
1199
1200 if (vlan_on) {
1201 /* set the pool bit */
1202 if (vind < 32) {
1203 bits = IXGBE_READ_REG(hw,
1204 IXGBE_VLVFB(vlvf_index * 2));
1205 bits |= (1 << vind);
1206 IXGBE_WRITE_REG(hw,
1207 IXGBE_VLVFB(vlvf_index * 2), bits);
1208 } else {
1209 bits = IXGBE_READ_REG(hw,
1210 IXGBE_VLVFB((vlvf_index * 2) + 1));
1211 bits |= (1 << (vind - 32));
1212 IXGBE_WRITE_REG(hw,
1213 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1214 }
1215 } else {
1216 /* clear the pool bit */
1217 if (vind < 32) {
1218 bits = IXGBE_READ_REG(hw,
1219 IXGBE_VLVFB(vlvf_index * 2));
1220 bits &= ~(1 << vind);
1221 IXGBE_WRITE_REG(hw,
1222 IXGBE_VLVFB(vlvf_index * 2), bits);
1223 bits |= IXGBE_READ_REG(hw,
1224 IXGBE_VLVFB((vlvf_index * 2) + 1));
1225 } else {
1226 bits = IXGBE_READ_REG(hw,
1227 IXGBE_VLVFB((vlvf_index * 2) + 1));
1228 bits &= ~(1 << (vind - 32));
1229 IXGBE_WRITE_REG(hw,
1230 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1231 bits |= IXGBE_READ_REG(hw,
1232 IXGBE_VLVFB(vlvf_index * 2));
1233 }
1234 }
1235
1236 if (bits) {
1237 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1238 (IXGBE_VLVF_VIEN | vlan));
1239 /* if bits is non-zero then some pools/VFs are still
1240 * using this VLAN ID. Force the VFTA entry to on */
1241 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1242 bits |= (1 << bitindex);
1243 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1244 }
1245 else
1246 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
1247
1248out:
1249 return 0;
1250}
1251
1252/**
1253 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1254 * @hw: pointer to hardware structure
1255 *
1256 * Clears the VLAN filer table, and the VMDq index associated with the filter
1257 **/
1258static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1259{
1260 u32 offset;
1261
1262 for (offset = 0; offset < hw->mac.vft_size; offset++)
1263 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1264
1265 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1266 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1267 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1268 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1269 }
1270
1271 return 0;
1272}
1273
1274/**
1275 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1276 * @hw: pointer to hardware structure
1277 **/
1278static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1279{
1280 int i;
1281 hw_dbg(hw, " Clearing UTA\n");
1282
1283 for (i = 0; i < 128; i++)
1284 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1285
1286 return 0;
1287}
1288
1289/**
1290 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 978 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1291 * @hw: pointer to hardware structure 979 * @hw: pointer to hardware structure
1292 **/ 980 **/
@@ -2550,75 +2238,6 @@ static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2550} 2238}
2551 2239
2552/** 2240/**
2553 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2554 * @hw: pointer to hardware structure
2555 * @san_mac_offset: SAN MAC address offset
2556 *
2557 * This function will read the EEPROM location for the SAN MAC address
2558 * pointer, and returns the value at that location. This is used in both
2559 * get and set mac_addr routines.
2560 **/
2561static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2562 u16 *san_mac_offset)
2563{
2564 /*
2565 * First read the EEPROM pointer to see if the MAC addresses are
2566 * available.
2567 */
2568 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2569
2570 return 0;
2571}
2572
2573/**
2574 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2575 * @hw: pointer to hardware structure
2576 * @san_mac_addr: SAN MAC address
2577 *
2578 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2579 * per-port, so set_lan_id() must be called before reading the addresses.
2580 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2581 * upon for non-SFP connections, so we must call it here.
2582 **/
2583static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2584{
2585 u16 san_mac_data, san_mac_offset;
2586 u8 i;
2587
2588 /*
2589 * First read the EEPROM pointer to see if the MAC addresses are
2590 * available. If they're not, no point in calling set_lan_id() here.
2591 */
2592 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2593
2594 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2595 /*
2596 * No addresses available in this EEPROM. It's not an
2597 * error though, so just wipe the local address and return.
2598 */
2599 for (i = 0; i < 6; i++)
2600 san_mac_addr[i] = 0xFF;
2601
2602 goto san_mac_addr_out;
2603 }
2604
2605 /* make sure we know which port we need to program */
2606 hw->mac.ops.set_lan_id(hw);
2607 /* apply the port offset to the address offset */
2608 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2609 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2610 for (i = 0; i < 3; i++) {
2611 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2612 san_mac_addr[i * 2] = (u8)(san_mac_data);
2613 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2614 san_mac_offset++;
2615 }
2616
2617san_mac_addr_out:
2618 return 0;
2619}
2620
2621/**
2622 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2241 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2623 * @hw: pointer to hardware structure 2242 * @hw: pointer to hardware structure
2624 * 2243 *
@@ -2720,7 +2339,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2720 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, 2339 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2721 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2340 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2722 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2341 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2723 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599, 2342 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2724 .get_device_caps = &ixgbe_get_device_caps_82599, 2343 .get_device_caps = &ixgbe_get_device_caps_82599,
2725 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599, 2344 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
2726 .stop_adapter = &ixgbe_stop_adapter_generic, 2345 .stop_adapter = &ixgbe_stop_adapter_generic,
@@ -2729,7 +2348,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2729 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2348 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2730 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2349 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2731 .setup_link = &ixgbe_setup_mac_link_82599, 2350 .setup_link = &ixgbe_setup_mac_link_82599,
2732 .check_link = &ixgbe_check_mac_link_82599, 2351 .check_link = &ixgbe_check_mac_link_generic,
2733 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2352 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2734 .led_on = &ixgbe_led_on_generic, 2353 .led_on = &ixgbe_led_on_generic,
2735 .led_off = &ixgbe_led_off_generic, 2354 .led_off = &ixgbe_led_off_generic,
@@ -2737,23 +2356,23 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2737 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2356 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2738 .set_rar = &ixgbe_set_rar_generic, 2357 .set_rar = &ixgbe_set_rar_generic,
2739 .clear_rar = &ixgbe_clear_rar_generic, 2358 .clear_rar = &ixgbe_clear_rar_generic,
2740 .set_vmdq = &ixgbe_set_vmdq_82599, 2359 .set_vmdq = &ixgbe_set_vmdq_generic,
2741 .clear_vmdq = &ixgbe_clear_vmdq_82599, 2360 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2742 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2361 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2743 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, 2362 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2744 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2363 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2745 .enable_mc = &ixgbe_enable_mc_generic, 2364 .enable_mc = &ixgbe_enable_mc_generic,
2746 .disable_mc = &ixgbe_disable_mc_generic, 2365 .disable_mc = &ixgbe_disable_mc_generic,
2747 .clear_vfta = &ixgbe_clear_vfta_82599, 2366 .clear_vfta = &ixgbe_clear_vfta_generic,
2748 .set_vfta = &ixgbe_set_vfta_82599, 2367 .set_vfta = &ixgbe_set_vfta_generic,
2749 .fc_enable = &ixgbe_fc_enable_generic, 2368 .fc_enable = &ixgbe_fc_enable_generic,
2750 .init_uta_tables = &ixgbe_init_uta_tables_82599, 2369 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2751 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2370 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2752}; 2371};
2753 2372
2754static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2373static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2755 .init_params = &ixgbe_init_eeprom_params_generic, 2374 .init_params = &ixgbe_init_eeprom_params_generic,
2756 .read = &ixgbe_read_eeprom_generic, 2375 .read = &ixgbe_read_eerd_generic,
2757 .write = &ixgbe_write_eeprom_generic, 2376 .write = &ixgbe_write_eeprom_generic,
2758 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2377 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2759 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2378 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
@@ -2762,7 +2381,7 @@ static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2762static struct ixgbe_phy_operations phy_ops_82599 = { 2381static struct ixgbe_phy_operations phy_ops_82599 = {
2763 .identify = &ixgbe_identify_phy_82599, 2382 .identify = &ixgbe_identify_phy_82599,
2764 .identify_sfp = &ixgbe_identify_sfp_module_generic, 2383 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2765 .init = &ixgbe_init_phy_ops_82599, 2384 .init = &ixgbe_init_phy_ops_82599,
2766 .reset = &ixgbe_reset_phy_generic, 2385 .reset = &ixgbe_reset_phy_generic,
2767 .read_reg = &ixgbe_read_phy_reg_generic, 2386 .read_reg = &ixgbe_read_phy_reg_generic,
2768 .write_reg = &ixgbe_write_phy_reg_generic, 2387 .write_reg = &ixgbe_write_phy_reg_generic,