ixgbe: consolidate packet buffer allocation

Consolidate packet buffer allocation currently being
done in the DCB path and main path. This allows the
feature set and packet buffer requirements to be done
once.

This is prep work to allow DCB to coexist with other
features namely, flow director.

CC: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 42 insertions, 0 deletions

diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 8179e5060a18..bb417d746a16 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1242,6 +1242,47 @@ static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
         }
 }
 
+/**
+ * ixgbe_set_rxpba_82598 - Configure packet buffers
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure packet buffers.
+ */
+static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,
+                                  int strategy)
+{
+        u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
+        u8  i = 0;
+
+        if (!num_pb)
+                return;
+
+        /* Setup Rx packet buffer sizes */
+        switch (strategy) {
+        case PBA_STRATEGY_WEIGHTED:
+                /* Setup the first four at 80KB */
+                rxpktsize = IXGBE_RXPBSIZE_80KB;
+                for (; i < 4; i++)
+                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+                /* Setup the last four at 48KB...don't re-init i */
+                rxpktsize = IXGBE_RXPBSIZE_48KB;
+                /* Fall Through */
+        case PBA_STRATEGY_EQUAL:
+        default:
+                /* Divide the remaining Rx packet buffer evenly among the TCs */
+                for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+                break;
+        }
+
+        /* Setup Tx packet buffer sizes */
+        for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+                IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
+
+        return;
+}
+
 static struct ixgbe_mac_operations mac_ops_82598 = {
         .init_hw                = &ixgbe_init_hw_generic,
         .reset_hw               = &ixgbe_reset_hw_82598,
@@ -1257,6 +1298,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
         .setup_link             = &ixgbe_setup_mac_link_82598,
+        .set_rxpba              = &ixgbe_set_rxpba_82598,
         .check_link             = &ixgbe_check_mac_link_82598,
         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
         .led_on                 = &ixgbe_led_on_generic,