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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/ixgbe/ixgbe.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/ixgbe/ixgbe.h')
-rw-r--r--drivers/net/ixgbe/ixgbe.h295
1 files changed, 190 insertions, 105 deletions
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 9e15eb93860e..e467b20ed1f0 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -28,10 +28,13 @@
28#ifndef _IXGBE_H_ 28#ifndef _IXGBE_H_
29#define _IXGBE_H_ 29#define _IXGBE_H_
30 30
31#include <linux/bitops.h>
31#include <linux/types.h> 32#include <linux/types.h>
32#include <linux/pci.h> 33#include <linux/pci.h>
33#include <linux/netdevice.h> 34#include <linux/netdevice.h>
35#include <linux/cpumask.h>
34#include <linux/aer.h> 36#include <linux/aer.h>
37#include <linux/if_vlan.h>
35 38
36#include "ixgbe_type.h" 39#include "ixgbe_type.h"
37#include "ixgbe_common.h" 40#include "ixgbe_common.h"
@@ -58,10 +61,8 @@
58#define IXGBE_MIN_RXD 64 61#define IXGBE_MIN_RXD 64
59 62
60/* flow control */ 63/* flow control */
61#define IXGBE_DEFAULT_FCRTL 0x10000
62#define IXGBE_MIN_FCRTL 0x40 64#define IXGBE_MIN_FCRTL 0x40
63#define IXGBE_MAX_FCRTL 0x7FF80 65#define IXGBE_MAX_FCRTL 0x7FF80
64#define IXGBE_DEFAULT_FCRTH 0x20000
65#define IXGBE_MIN_FCRTH 0x600 66#define IXGBE_MIN_FCRTH 0x600
66#define IXGBE_MAX_FCRTH 0x7FFF0 67#define IXGBE_MAX_FCRTH 0x7FFF0
67#define IXGBE_DEFAULT_FCPAUSE 0xFFFF 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
@@ -69,15 +70,20 @@
69#define IXGBE_MAX_FCPAUSE 0xFFFF 70#define IXGBE_MAX_FCPAUSE 0xFFFF
70 71
71/* Supported Rx Buffer Sizes */ 72/* Supported Rx Buffer Sizes */
72#define IXGBE_RXBUFFER_64 64 /* Used for packet split */ 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
73#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
74#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
75#define IXGBE_RXBUFFER_2048 2048 74#define IXGBE_RXBUFFER_2048 2048
76#define IXGBE_RXBUFFER_4096 4096 75#define IXGBE_RXBUFFER_4096 4096
77#define IXGBE_RXBUFFER_8192 8192 76#define IXGBE_RXBUFFER_8192 8192
78#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
79 78
80#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
81 87
82#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
83 89
@@ -100,6 +106,7 @@
100#define IXGBE_MAX_VF_FUNCTIONS 64 106#define IXGBE_MAX_VF_FUNCTIONS 64
101#define IXGBE_MAX_VFTA_ENTRIES 128 107#define IXGBE_MAX_VFTA_ENTRIES 128
102#define MAX_EMULATION_MAC_ADDRS 16 108#define MAX_EMULATION_MAC_ADDRS 16
109#define IXGBE_MAX_PF_MACVLANS 15
103#define VMDQ_P(p) ((p) + adapter->num_vfs) 110#define VMDQ_P(p) ((p) + adapter->num_vfs)
104 111
105struct vf_data_storage { 112struct vf_data_storage {
@@ -112,6 +119,16 @@ struct vf_data_storage {
112 bool pf_set_mac; 119 bool pf_set_mac;
113 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 120 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
114 u16 pf_qos; 121 u16 pf_qos;
122 u16 tx_rate;
123};
124
125struct vf_macvlans {
126 struct list_head l;
127 int vf;
128 int rar_entry;
129 bool free;
130 bool is_macvlan;
131 u8 vf_macvlan[ETH_ALEN];
115}; 132};
116 133
117/* wrapper around a pointer to a socket buffer, 134/* wrapper around a pointer to a socket buffer,
@@ -122,7 +139,9 @@ struct ixgbe_tx_buffer {
122 unsigned long time_stamp; 139 unsigned long time_stamp;
123 u16 length; 140 u16 length;
124 u16 next_to_watch; 141 u16 next_to_watch;
125 u16 mapped_as_page; 142 unsigned int bytecount;
143 u16 gso_segs;
144 u8 mapped_as_page;
126}; 145};
127 146
128struct ixgbe_rx_buffer { 147struct ixgbe_rx_buffer {
@@ -138,12 +157,56 @@ struct ixgbe_queue_stats {
138 u64 bytes; 157 u64 bytes;
139}; 158};
140 159
160struct ixgbe_tx_queue_stats {
161 u64 restart_queue;
162 u64 tx_busy;
163 u64 completed;
164 u64 tx_done_old;
165};
166
167struct ixgbe_rx_queue_stats {
168 u64 rsc_count;
169 u64 rsc_flush;
170 u64 non_eop_descs;
171 u64 alloc_rx_page_failed;
172 u64 alloc_rx_buff_failed;
173};
174
175enum ixbge_ring_state_t {
176 __IXGBE_TX_FDIR_INIT_DONE,
177 __IXGBE_TX_DETECT_HANG,
178 __IXGBE_HANG_CHECK_ARMED,
179 __IXGBE_RX_PS_ENABLED,
180 __IXGBE_RX_RSC_ENABLED,
181};
182
183#define ring_is_ps_enabled(ring) \
184 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
185#define set_ring_ps_enabled(ring) \
186 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
187#define clear_ring_ps_enabled(ring) \
188 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
189#define check_for_tx_hang(ring) \
190 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
191#define set_check_for_tx_hang(ring) \
192 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
193#define clear_check_for_tx_hang(ring) \
194 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
195#define ring_is_rsc_enabled(ring) \
196 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
197#define set_ring_rsc_enabled(ring) \
198 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
199#define clear_ring_rsc_enabled(ring) \
200 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
141struct ixgbe_ring { 201struct ixgbe_ring {
142 void *desc; /* descriptor ring memory */ 202 void *desc; /* descriptor ring memory */
203 struct device *dev; /* device for DMA mapping */
204 struct net_device *netdev; /* netdev ring belongs to */
143 union { 205 union {
144 struct ixgbe_tx_buffer *tx_buffer_info; 206 struct ixgbe_tx_buffer *tx_buffer_info;
145 struct ixgbe_rx_buffer *rx_buffer_info; 207 struct ixgbe_rx_buffer *rx_buffer_info;
146 }; 208 };
209 unsigned long state;
147 u8 atr_sample_rate; 210 u8 atr_sample_rate;
148 u8 atr_count; 211 u8 atr_count;
149 u16 count; /* amount of descriptors */ 212 u16 count; /* amount of descriptors */
@@ -152,37 +215,31 @@ struct ixgbe_ring {
152 u16 next_to_clean; 215 u16 next_to_clean;
153 216
154 u8 queue_index; /* needed for multiqueue queue management */ 217 u8 queue_index; /* needed for multiqueue queue management */
155 218 u8 reg_idx; /* holds the special value that gets
156#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
157 u8 flags; /* per ring feature flags */
158 u16 head;
159 u16 tail;
160
161 unsigned int total_bytes;
162 unsigned int total_packets;
163
164#ifdef CONFIG_IXGBE_DCA
165 /* cpu for tx queue */
166 int cpu;
167#endif
168
169 u16 work_limit; /* max work per interrupt */
170 u16 reg_idx; /* holds the special value that gets
171 * the hardware register offset 219 * the hardware register offset
172 * associated with this ring, which is 220 * associated with this ring, which is
173 * different for DCB and RSS modes 221 * different for DCB and RSS modes
174 */ 222 */
223 u8 dcb_tc;
224
225 u16 work_limit; /* max work per interrupt */
226
227 u8 __iomem *tail;
228
229 unsigned int total_bytes;
230 unsigned int total_packets;
175 231
176 struct ixgbe_queue_stats stats; 232 struct ixgbe_queue_stats stats;
177 unsigned long reinit_state; 233 struct u64_stats_sync syncp;
234 union {
235 struct ixgbe_tx_queue_stats tx_stats;
236 struct ixgbe_rx_queue_stats rx_stats;
237 };
178 int numa_node; 238 int numa_node;
179 u64 rsc_count; /* stat for coalesced packets */
180 u64 rsc_flush; /* stats for flushed packets */
181 u32 restart_queue; /* track tx queue restarts */
182 u32 non_eop_descs; /* track hardware descriptor chaining */
183
184 unsigned int size; /* length in bytes */ 239 unsigned int size; /* length in bytes */
185 dma_addr_t dma; /* phys. address of descriptor ring */ 240 dma_addr_t dma; /* phys. address of descriptor ring */
241 struct rcu_head rcu;
242 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
186} ____cacheline_internodealigned_in_smp; 243} ____cacheline_internodealigned_in_smp;
187 244
188enum ixgbe_ring_f_enum { 245enum ixgbe_ring_f_enum {
@@ -198,7 +255,7 @@ enum ixgbe_ring_f_enum {
198 RING_F_ARRAY_SIZE /* must be last in enum set */ 255 RING_F_ARRAY_SIZE /* must be last in enum set */
199}; 256};
200 257
201#define IXGBE_MAX_DCB_INDICES 8 258#define IXGBE_MAX_DCB_INDICES 64
202#define IXGBE_MAX_RSS_INDICES 16 259#define IXGBE_MAX_RSS_INDICES 16
203#define IXGBE_MAX_VMDQ_INDICES 64 260#define IXGBE_MAX_VMDQ_INDICES 64
204#define IXGBE_MAX_FDIR_INDICES 64 261#define IXGBE_MAX_FDIR_INDICES 64
@@ -228,6 +285,9 @@ struct ixgbe_q_vector {
228 unsigned int v_idx; /* index of q_vector within array, also used for 285 unsigned int v_idx; /* index of q_vector within array, also used for
229 * finding the bit in EICR and friends that 286 * finding the bit in EICR and friends that
230 * represents the vector for this ring */ 287 * represents the vector for this ring */
288#ifdef CONFIG_IXGBE_DCA
289 int cpu; /* CPU for DCA */
290#endif
231 struct napi_struct napi; 291 struct napi_struct napi;
232 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ 292 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
233 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ 293 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
@@ -236,6 +296,8 @@ struct ixgbe_q_vector {
236 u8 tx_itr; 296 u8 tx_itr;
237 u8 rx_itr; 297 u8 rx_itr;
238 u32 eitr; 298 u32 eitr;
299 cpumask_var_t affinity_mask;
300 char name[IFNAMSIZ + 9];
239}; 301};
240 302
241/* Helper macros to switch between ints/sec and what the register uses. 303/* Helper macros to switch between ints/sec and what the register uses.
@@ -251,11 +313,11 @@ struct ixgbe_q_vector {
251 (R)->next_to_clean - (R)->next_to_use - 1) 313 (R)->next_to_clean - (R)->next_to_use - 1)
252 314
253#define IXGBE_RX_DESC_ADV(R, i) \ 315#define IXGBE_RX_DESC_ADV(R, i) \
254 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i])) 316 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
255#define IXGBE_TX_DESC_ADV(R, i) \ 317#define IXGBE_TX_DESC_ADV(R, i) \
256 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i])) 318 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
257#define IXGBE_TX_CTXTDESC_ADV(R, i) \ 319#define IXGBE_TX_CTXTDESC_ADV(R, i) \
258 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i])) 320 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
259 321
260#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 322#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
261#ifdef IXGBE_FCOE 323#ifdef IXGBE_FCOE
@@ -279,15 +341,61 @@ struct ixgbe_q_vector {
279 341
280/* board specific private data structure */ 342/* board specific private data structure */
281struct ixgbe_adapter { 343struct ixgbe_adapter {
282 struct timer_list watchdog_timer; 344 unsigned long state;
283 struct vlan_group *vlgrp; 345
346 /* Some features need tri-state capability,
347 * thus the additional *_CAPABLE flags.
348 */
349 u32 flags;
350#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
351#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
352#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
353#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
354#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
355#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
356#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
357#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
358#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
359#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
360#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
361#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
362#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
363#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
364#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
365#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
366#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
367#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
368#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
369#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
370#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
371#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
372#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
373#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
374#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
375#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
376#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
377
378 u32 flags2;
379#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
380#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
381#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
382#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
383#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
384#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
385#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
386#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
387
388 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
284 u16 bd_number; 389 u16 bd_number;
285 struct work_struct reset_task;
286 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 390 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
287 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9]; 391
392 /* DCB parameters */
393 struct ieee_pfc *ixgbe_ieee_pfc;
394 struct ieee_ets *ixgbe_ieee_ets;
288 struct ixgbe_dcb_config dcb_cfg; 395 struct ixgbe_dcb_config dcb_cfg;
289 struct ixgbe_dcb_config temp_dcb_cfg; 396 struct ixgbe_dcb_config temp_dcb_cfg;
290 u8 dcb_set_bitmap; 397 u8 dcb_set_bitmap;
398 u8 dcbx_cap;
291 enum ixgbe_fc_mode last_lfc_mode; 399 enum ixgbe_fc_mode last_lfc_mode;
292 400
293 /* Interrupt Throttle Rate */ 401 /* Interrupt Throttle Rate */
@@ -321,43 +429,6 @@ struct ixgbe_adapter {
321 u32 alloc_rx_page_failed; 429 u32 alloc_rx_page_failed;
322 u32 alloc_rx_buff_failed; 430 u32 alloc_rx_buff_failed;
323 431
324 /* Some features need tri-state capability,
325 * thus the additional *_CAPABLE flags.
326 */
327 u32 flags;
328#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
329#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
330#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
331#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
332#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
333#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
334#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
335#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
336#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
337#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
338#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
339#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
340#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
341#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
342#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
343#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
344#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
345#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
346#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
347#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
348#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
349#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
350#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
351#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
352#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
353#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
354#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
355#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
356
357 u32 flags2;
358#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
359#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
360#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
361/* default to trying for four seconds */ 432/* default to trying for four seconds */
362#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 433#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
363 434
@@ -378,7 +449,6 @@ struct ixgbe_adapter {
378 u32 rx_eitr_param; 449 u32 rx_eitr_param;
379 u32 tx_eitr_param; 450 u32 tx_eitr_param;
380 451
381 unsigned long state;
382 u64 tx_busy; 452 u64 tx_busy;
383 unsigned int tx_ring_count; 453 unsigned int tx_ring_count;
384 unsigned int rx_ring_count; 454 unsigned int rx_ring_count;
@@ -387,15 +457,12 @@ struct ixgbe_adapter {
387 bool link_up; 457 bool link_up;
388 unsigned long link_check_timeout; 458 unsigned long link_check_timeout;
389 459
390 struct work_struct watchdog_task; 460 struct work_struct service_task;
391 struct work_struct sfp_task; 461 struct timer_list service_timer;
392 struct timer_list sfp_timer;
393 struct work_struct multispeed_fiber_task;
394 struct work_struct sfp_config_module_task;
395 u32 fdir_pballoc; 462 u32 fdir_pballoc;
396 u32 atr_sample_rate; 463 u32 atr_sample_rate;
464 unsigned long fdir_overflow; /* number of times ATR was backed off */
397 spinlock_t fdir_perfect_lock; 465 spinlock_t fdir_perfect_lock;
398 struct work_struct fdir_reinit_task;
399#ifdef IXGBE_FCOE 466#ifdef IXGBE_FCOE
400 struct ixgbe_fcoe fcoe; 467 struct ixgbe_fcoe fcoe;
401#endif /* IXGBE_FCOE */ 468#endif /* IXGBE_FCOE */
@@ -405,30 +472,44 @@ struct ixgbe_adapter {
405 u16 eeprom_version; 472 u16 eeprom_version;
406 473
407 int node; 474 int node;
408 struct work_struct check_overtemp_task; 475 u32 led_reg;
409 u32 interrupt_event; 476 u32 interrupt_event;
477 char lsc_int_name[IFNAMSIZ + 9];
410 478
411 /* SR-IOV */ 479 /* SR-IOV */
412 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 480 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
413 unsigned int num_vfs; 481 unsigned int num_vfs;
414 struct vf_data_storage *vfinfo; 482 struct vf_data_storage *vfinfo;
483 int vf_rate_link_speed;
484 struct vf_macvlans vf_mvs;
485 struct vf_macvlans *mv_list;
486 bool antispoofing_enabled;
415}; 487};
416 488
417enum ixbge_state_t { 489enum ixbge_state_t {
418 __IXGBE_TESTING, 490 __IXGBE_TESTING,
419 __IXGBE_RESETTING, 491 __IXGBE_RESETTING,
420 __IXGBE_DOWN, 492 __IXGBE_DOWN,
421 __IXGBE_FDIR_INIT_DONE, 493 __IXGBE_SERVICE_SCHED,
422 __IXGBE_SFP_MODULE_NOT_FOUND 494 __IXGBE_IN_SFP_INIT,
495};
496
497struct ixgbe_rsc_cb {
498 dma_addr_t dma;
499 u16 skb_cnt;
500 bool delay_unmap;
423}; 501};
502#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
424 503
425enum ixgbe_boards { 504enum ixgbe_boards {
426 board_82598, 505 board_82598,
427 board_82599, 506 board_82599,
507 board_X540,
428}; 508};
429 509
430extern struct ixgbe_info ixgbe_82598_info; 510extern struct ixgbe_info ixgbe_82598_info;
431extern struct ixgbe_info ixgbe_82599_info; 511extern struct ixgbe_info ixgbe_82599_info;
512extern struct ixgbe_info ixgbe_X540_info;
432#ifdef CONFIG_IXGBE_DCB 513#ifdef CONFIG_IXGBE_DCB
433extern const struct dcbnl_rtnl_ops dcbnl_ops; 514extern const struct dcbnl_rtnl_ops dcbnl_ops;
434extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, 515extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
@@ -444,40 +525,42 @@ extern void ixgbe_down(struct ixgbe_adapter *adapter);
444extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 525extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
445extern void ixgbe_reset(struct ixgbe_adapter *adapter); 526extern void ixgbe_reset(struct ixgbe_adapter *adapter);
446extern void ixgbe_set_ethtool_ops(struct net_device *netdev); 527extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
447extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 528extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
448extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 529extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
449extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 530extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
450extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 531extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
532extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
533extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
534extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
535 struct ixgbe_ring *);
451extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); 536extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
452extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 537extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
453extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 538extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
539extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
540 struct ixgbe_adapter *,
541 struct ixgbe_ring *);
542extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
543 struct ixgbe_tx_buffer *);
544extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
454extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 545extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
455extern int ethtool_ioctl(struct ifreq *ifr); 546extern int ethtool_ioctl(struct ifreq *ifr);
456extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 547extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
457extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); 548extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
458extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); 549extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
459extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 550extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
460 struct ixgbe_atr_input *input, 551 union ixgbe_atr_hash_dword input,
552 union ixgbe_atr_hash_dword common,
461 u8 queue); 553 u8 queue);
462extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 554extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
463 struct ixgbe_atr_input *input, 555 union ixgbe_atr_input *input,
464 struct ixgbe_atr_input_masks *input_masks, 556 struct ixgbe_atr_input_masks *input_masks,
465 u16 soft_id, u8 queue); 557 u16 soft_id, u8 queue);
466extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, 558extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
467 u16 vlan_id); 559 struct ixgbe_ring *ring);
468extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, 560extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
469 u32 src_addr); 561 struct ixgbe_ring *ring);
470extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
471 u32 dst_addr);
472extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
473 u16 src_port);
474extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
475 u16 dst_port);
476extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
477 u16 flex_byte);
478extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
479 u8 l4type);
480extern void ixgbe_set_rx_mode(struct net_device *netdev); 562extern void ixgbe_set_rx_mode(struct net_device *netdev);
563extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
481#ifdef IXGBE_FCOE 564#ifdef IXGBE_FCOE
482extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 565extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
483extern int ixgbe_fso(struct ixgbe_adapter *adapter, 566extern int ixgbe_fso(struct ixgbe_adapter *adapter,
@@ -489,6 +572,8 @@ extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
489 struct sk_buff *skb); 572 struct sk_buff *skb);
490extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 573extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
491 struct scatterlist *sgl, unsigned int sgc); 574 struct scatterlist *sgl, unsigned int sgc);
575extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
576 struct scatterlist *sgl, unsigned int sgc);
492extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 577extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
493extern int ixgbe_fcoe_enable(struct net_device *netdev); 578extern int ixgbe_fcoe_enable(struct net_device *netdev);
494extern int ixgbe_fcoe_disable(struct net_device *netdev); 579extern int ixgbe_fcoe_disable(struct net_device *netdev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-19 04:20:51 -0400