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authorJoe Perches <joe@perches.com>2010-04-26 20:50:58 -0400
committerDavid S. Miller <davem@davemloft.net>2010-04-27 15:53:30 -0400
commitd328bc839eac685cdd91f5d9d8ad95c070252038 (patch)
tree29554a44d55d4b8433ed525556412eb9f3bee910 /drivers/net/ixgb/ixgb_hw.c
parentc0dfb90e5b2d41c907de9b624657a6688541837e (diff)
ixgb: Use pr_<level> and netdev_<level>
Convert DEBUGOUTx to pr_debug Convert DEBUGFUNC to more commonly used ENTER Convert mac address output to %pM Use #define pr_fmt Convert a few printks to pr_<level> Improve ixgb_mc_addr_list_update: use a temporary for current mc address Use etherdevice.h functions for mac address testing Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgb/ixgb_hw.c')
-rw-r--r--drivers/net/ixgb/ixgb_hw.c147
1 files changed, 61 insertions, 86 deletions
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
index ff67a84e6802..cd247b8d2b73 100644
--- a/drivers/net/ixgb/ixgb_hw.c
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -30,9 +30,13 @@
30 * Shared functions for accessing and configuring the adapter 30 * Shared functions for accessing and configuring the adapter
31 */ 31 */
32 32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
33#include "ixgb_hw.h" 35#include "ixgb_hw.h"
34#include "ixgb_ids.h" 36#include "ixgb_ids.h"
35 37
38#include <linux/etherdevice.h>
39
36/* Local function prototypes */ 40/* Local function prototypes */
37 41
38static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr); 42static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
@@ -120,13 +124,13 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
120 u32 ctrl_reg; 124 u32 ctrl_reg;
121 u32 icr_reg; 125 u32 icr_reg;
122 126
123 DEBUGFUNC("ixgb_adapter_stop"); 127 ENTER();
124 128
125 /* If we are stopped or resetting exit gracefully and wait to be 129 /* If we are stopped or resetting exit gracefully and wait to be
126 * started again before accessing the hardware. 130 * started again before accessing the hardware.
127 */ 131 */
128 if (hw->adapter_stopped) { 132 if (hw->adapter_stopped) {
129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 133 pr_debug("Exiting because the adapter is already stopped!!!\n");
130 return false; 134 return false;
131 } 135 }
132 136
@@ -136,7 +140,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
136 hw->adapter_stopped = true; 140 hw->adapter_stopped = true;
137 141
138 /* Clear interrupt mask to stop board from generating interrupts */ 142 /* Clear interrupt mask to stop board from generating interrupts */
139 DEBUGOUT("Masking off all interrupts\n"); 143 pr_debug("Masking off all interrupts\n");
140 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); 144 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
141 145
142 /* Disable the Transmit and Receive units. Then delay to allow 146 /* Disable the Transmit and Receive units. Then delay to allow
@@ -152,12 +156,12 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
152 * the current PCI configuration. The global reset bit is self- 156 * the current PCI configuration. The global reset bit is self-
153 * clearing, and should clear within a microsecond. 157 * clearing, and should clear within a microsecond.
154 */ 158 */
155 DEBUGOUT("Issuing a global reset to MAC\n"); 159 pr_debug("Issuing a global reset to MAC\n");
156 160
157 ctrl_reg = ixgb_mac_reset(hw); 161 ctrl_reg = ixgb_mac_reset(hw);
158 162
159 /* Clear interrupt mask to stop board from generating interrupts */ 163 /* Clear interrupt mask to stop board from generating interrupts */
160 DEBUGOUT("Masking off all interrupts\n"); 164 pr_debug("Masking off all interrupts\n");
161 IXGB_WRITE_REG(hw, IMC, 0xffffffff); 165 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
162 166
163 /* Clear any pending interrupt events. */ 167 /* Clear any pending interrupt events. */
@@ -183,7 +187,7 @@ ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
183 u16 vendor_name[5]; 187 u16 vendor_name[5];
184 ixgb_xpak_vendor xpak_vendor; 188 ixgb_xpak_vendor xpak_vendor;
185 189
186 DEBUGFUNC("ixgb_identify_xpak_vendor"); 190 ENTER();
187 191
188 /* Read the first few bytes of the vendor string from the XPAK NVR 192 /* Read the first few bytes of the vendor string from the XPAK NVR
189 * registers. These are standard XENPAK/XPAK registers, so all XPAK 193 * registers. These are standard XENPAK/XPAK registers, so all XPAK
@@ -222,12 +226,12 @@ ixgb_identify_phy(struct ixgb_hw *hw)
222 ixgb_phy_type phy_type; 226 ixgb_phy_type phy_type;
223 ixgb_xpak_vendor xpak_vendor; 227 ixgb_xpak_vendor xpak_vendor;
224 228
225 DEBUGFUNC("ixgb_identify_phy"); 229 ENTER();
226 230
227 /* Infer the transceiver/phy type from the device id */ 231 /* Infer the transceiver/phy type from the device id */
228 switch (hw->device_id) { 232 switch (hw->device_id) {
229 case IXGB_DEVICE_ID_82597EX: 233 case IXGB_DEVICE_ID_82597EX:
230 DEBUGOUT("Identified TXN17401 optics\n"); 234 pr_debug("Identified TXN17401 optics\n");
231 phy_type = ixgb_phy_type_txn17401; 235 phy_type = ixgb_phy_type_txn17401;
232 break; 236 break;
233 237
@@ -237,30 +241,30 @@ ixgb_identify_phy(struct ixgb_hw *hw)
237 * type of optics. */ 241 * type of optics. */
238 xpak_vendor = ixgb_identify_xpak_vendor(hw); 242 xpak_vendor = ixgb_identify_xpak_vendor(hw);
239 if (xpak_vendor == ixgb_xpak_vendor_intel) { 243 if (xpak_vendor == ixgb_xpak_vendor_intel) {
240 DEBUGOUT("Identified TXN17201 optics\n"); 244 pr_debug("Identified TXN17201 optics\n");
241 phy_type = ixgb_phy_type_txn17201; 245 phy_type = ixgb_phy_type_txn17201;
242 } else { 246 } else {
243 DEBUGOUT("Identified G6005 optics\n"); 247 pr_debug("Identified G6005 optics\n");
244 phy_type = ixgb_phy_type_g6005; 248 phy_type = ixgb_phy_type_g6005;
245 } 249 }
246 break; 250 break;
247 case IXGB_DEVICE_ID_82597EX_LR: 251 case IXGB_DEVICE_ID_82597EX_LR:
248 DEBUGOUT("Identified G6104 optics\n"); 252 pr_debug("Identified G6104 optics\n");
249 phy_type = ixgb_phy_type_g6104; 253 phy_type = ixgb_phy_type_g6104;
250 break; 254 break;
251 case IXGB_DEVICE_ID_82597EX_CX4: 255 case IXGB_DEVICE_ID_82597EX_CX4:
252 DEBUGOUT("Identified CX4\n"); 256 pr_debug("Identified CX4\n");
253 xpak_vendor = ixgb_identify_xpak_vendor(hw); 257 xpak_vendor = ixgb_identify_xpak_vendor(hw);
254 if (xpak_vendor == ixgb_xpak_vendor_intel) { 258 if (xpak_vendor == ixgb_xpak_vendor_intel) {
255 DEBUGOUT("Identified TXN17201 optics\n"); 259 pr_debug("Identified TXN17201 optics\n");
256 phy_type = ixgb_phy_type_txn17201; 260 phy_type = ixgb_phy_type_txn17201;
257 } else { 261 } else {
258 DEBUGOUT("Identified G6005 optics\n"); 262 pr_debug("Identified G6005 optics\n");
259 phy_type = ixgb_phy_type_g6005; 263 phy_type = ixgb_phy_type_g6005;
260 } 264 }
261 break; 265 break;
262 default: 266 default:
263 DEBUGOUT("Unknown physical layer module\n"); 267 pr_debug("Unknown physical layer module\n");
264 phy_type = ixgb_phy_type_unknown; 268 phy_type = ixgb_phy_type_unknown;
265 break; 269 break;
266 } 270 }
@@ -296,18 +300,18 @@ ixgb_init_hw(struct ixgb_hw *hw)
296 u32 ctrl_reg; 300 u32 ctrl_reg;
297 bool status; 301 bool status;
298 302
299 DEBUGFUNC("ixgb_init_hw"); 303 ENTER();
300 304
301 /* Issue a global reset to the MAC. This will reset the chip's 305 /* Issue a global reset to the MAC. This will reset the chip's
302 * transmit, receive, DMA, and link units. It will not effect 306 * transmit, receive, DMA, and link units. It will not effect
303 * the current PCI configuration. The global reset bit is self- 307 * the current PCI configuration. The global reset bit is self-
304 * clearing, and should clear within a microsecond. 308 * clearing, and should clear within a microsecond.
305 */ 309 */
306 DEBUGOUT("Issuing a global reset to MAC\n"); 310 pr_debug("Issuing a global reset to MAC\n");
307 311
308 ctrl_reg = ixgb_mac_reset(hw); 312 ctrl_reg = ixgb_mac_reset(hw);
309 313
310 DEBUGOUT("Issuing an EE reset to MAC\n"); 314 pr_debug("Issuing an EE reset to MAC\n");
311#ifdef HP_ZX1 315#ifdef HP_ZX1
312 /* Workaround for 82597EX reset errata */ 316 /* Workaround for 82597EX reset errata */
313 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); 317 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
@@ -335,7 +339,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
335 * If it is not valid, we fail hardware init. 339 * If it is not valid, we fail hardware init.
336 */ 340 */
337 if (!mac_addr_valid(hw->curr_mac_addr)) { 341 if (!mac_addr_valid(hw->curr_mac_addr)) {
338 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); 342 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
339 return(false); 343 return(false);
340 } 344 }
341 345
@@ -346,7 +350,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
346 ixgb_get_bus_info(hw); 350 ixgb_get_bus_info(hw);
347 351
348 /* Zero out the Multicast HASH table */ 352 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n"); 353 pr_debug("Zeroing the MTA\n");
350 for (i = 0; i < IXGB_MC_TBL_SIZE; i++) 354 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
351 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 355 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
352 356
@@ -379,7 +383,7 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
379{ 383{
380 u32 i; 384 u32 i;
381 385
382 DEBUGFUNC("ixgb_init_rx_addrs"); 386 ENTER();
383 387
384 /* 388 /*
385 * If the current mac address is valid, assume it is a software override 389 * If the current mac address is valid, assume it is a software override
@@ -391,28 +395,19 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
391 /* Get the MAC address from the eeprom for later reference */ 395 /* Get the MAC address from the eeprom for later reference */
392 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); 396 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
393 397
394 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", 398 pr_debug("Keeping Permanent MAC Addr = %pM\n",
395 hw->curr_mac_addr[0], 399 hw->curr_mac_addr);
396 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
397 DEBUGOUT3("%.2X %.2X %.2X\n",
398 hw->curr_mac_addr[3],
399 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
400 } else { 400 } else {
401 401
402 /* Setup the receive address. */ 402 /* Setup the receive address. */
403 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 403 pr_debug("Overriding MAC Address in RAR[0]\n");
404 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 404 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
405 hw->curr_mac_addr[0],
406 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
407 DEBUGOUT3("%.2X %.2X %.2X\n",
408 hw->curr_mac_addr[3],
409 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
410 405
411 ixgb_rar_set(hw, hw->curr_mac_addr, 0); 406 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
412 } 407 }
413 408
414 /* Zero out the other 15 receive addresses. */ 409 /* Zero out the other 15 receive addresses. */
415 DEBUGOUT("Clearing RAR[1-15]\n"); 410 pr_debug("Clearing RAR[1-15]\n");
416 for (i = 1; i < IXGB_RAR_ENTRIES; i++) { 411 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
417 /* Write high reg first to disable the AV bit first */ 412 /* Write high reg first to disable the AV bit first */
418 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 413 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -444,64 +439,50 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
444 u32 hash_value; 439 u32 hash_value;
445 u32 i; 440 u32 i;
446 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */ 441 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
442 u8 *mca;
447 443
448 DEBUGFUNC("ixgb_mc_addr_list_update"); 444 ENTER();
449 445
450 /* Set the new number of MC addresses that we are being requested to use. */ 446 /* Set the new number of MC addresses that we are being requested to use. */
451 hw->num_mc_addrs = mc_addr_count; 447 hw->num_mc_addrs = mc_addr_count;
452 448
453 /* Clear RAR[1-15] */ 449 /* Clear RAR[1-15] */
454 DEBUGOUT(" Clearing RAR[1-15]\n"); 450 pr_debug("Clearing RAR[1-15]\n");
455 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 451 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
456 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 452 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
457 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 453 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
458 } 454 }
459 455
460 /* Clear the MTA */ 456 /* Clear the MTA */
461 DEBUGOUT(" Clearing MTA\n"); 457 pr_debug("Clearing MTA\n");
462 for (i = 0; i < IXGB_MC_TBL_SIZE; i++) 458 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
463 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 459 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
464 460
465 /* Add the new addresses */ 461 /* Add the new addresses */
462 mca = mc_addr_list;
466 for (i = 0; i < mc_addr_count; i++) { 463 for (i = 0; i < mc_addr_count; i++) {
467 DEBUGOUT(" Adding the multicast addresses:\n"); 464 pr_debug("Adding the multicast addresses:\n");
468 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 465 pr_debug("MC Addr #%d = %pM\n", i, mca);
469 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
470 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
471 1],
472 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
473 2],
474 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
475 3],
476 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
477 4],
478 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
479 5]);
480 466
481 /* Place this multicast address in the RAR if there is room, * 467 /* Place this multicast address in the RAR if there is room, *
482 * else put it in the MTA 468 * else put it in the MTA
483 */ 469 */
484 if (rar_used_count < IXGB_RAR_ENTRIES) { 470 if (rar_used_count < IXGB_RAR_ENTRIES) {
485 ixgb_rar_set(hw, 471 ixgb_rar_set(hw, mca, rar_used_count);
486 mc_addr_list + 472 pr_debug("Added a multicast address to RAR[%d]\n", i);
487 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
488 rar_used_count);
489 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
490 rar_used_count++; 473 rar_used_count++;
491 } else { 474 } else {
492 hash_value = ixgb_hash_mc_addr(hw, 475 hash_value = ixgb_hash_mc_addr(hw, mca);
493 mc_addr_list +
494 (i *
495 (IXGB_ETH_LENGTH_OF_ADDRESS
496 + pad)));
497 476
498 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 477 pr_debug("Hash value = 0x%03X\n", hash_value);
499 478
500 ixgb_mta_set(hw, hash_value); 479 ixgb_mta_set(hw, hash_value);
501 } 480 }
481
482 mca += IXGB_ETH_LENGTH_OF_ADDRESS + pad;
502 } 483 }
503 484
504 DEBUGOUT("MC Update Complete\n"); 485 pr_debug("MC Update Complete\n");
505 return; 486 return;
506} 487}
507 488
@@ -520,7 +501,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw,
520{ 501{
521 u32 hash_value = 0; 502 u32 hash_value = 0;
522 503
523 DEBUGFUNC("ixgb_hash_mc_addr"); 504 ENTER();
524 505
525 /* The portion of the address that is used for the hash table is 506 /* The portion of the address that is used for the hash table is
526 * determined by the mc_filter_type setting. 507 * determined by the mc_filter_type setting.
@@ -547,7 +528,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw,
547 break; 528 break;
548 default: 529 default:
549 /* Invalid mc_filter_type, what should we do? */ 530 /* Invalid mc_filter_type, what should we do? */
550 DEBUGOUT("MC filter type param set incorrectly\n"); 531 pr_debug("MC filter type param set incorrectly\n");
551 ASSERT(0); 532 ASSERT(0);
552 break; 533 break;
553 } 534 }
@@ -603,7 +584,7 @@ ixgb_rar_set(struct ixgb_hw *hw,
603{ 584{
604 u32 rar_low, rar_high; 585 u32 rar_low, rar_high;
605 586
606 DEBUGFUNC("ixgb_rar_set"); 587 ENTER();
607 588
608 /* HW expects these in little endian so we reverse the byte order 589 /* HW expects these in little endian so we reverse the byte order
609 * from network order (big endian) to little endian 590 * from network order (big endian) to little endian
@@ -666,7 +647,7 @@ ixgb_setup_fc(struct ixgb_hw *hw)
666 u32 pap_reg = 0; /* by default, assume no pause time */ 647 u32 pap_reg = 0; /* by default, assume no pause time */
667 bool status = true; 648 bool status = true;
668 649
669 DEBUGFUNC("ixgb_setup_fc"); 650 ENTER();
670 651
671 /* Get the current control reg 0 settings */ 652 /* Get the current control reg 0 settings */
672 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 653 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
@@ -710,7 +691,7 @@ ixgb_setup_fc(struct ixgb_hw *hw)
710 break; 691 break;
711 default: 692 default:
712 /* We should never get here. The value should be 0-3. */ 693 /* We should never get here. The value should be 0-3. */
713 DEBUGOUT("Flow control param set incorrectly\n"); 694 pr_debug("Flow control param set incorrectly\n");
714 ASSERT(0); 695 ASSERT(0);
715 break; 696 break;
716 } 697 }
@@ -940,7 +921,7 @@ ixgb_check_for_link(struct ixgb_hw *hw)
940 u32 status_reg; 921 u32 status_reg;
941 u32 xpcss_reg; 922 u32 xpcss_reg;
942 923
943 DEBUGFUNC("ixgb_check_for_link"); 924 ENTER();
944 925
945 xpcss_reg = IXGB_READ_REG(hw, XPCSS); 926 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
946 status_reg = IXGB_READ_REG(hw, STATUS); 927 status_reg = IXGB_READ_REG(hw, STATUS);
@@ -950,7 +931,7 @@ ixgb_check_for_link(struct ixgb_hw *hw)
950 hw->link_up = true; 931 hw->link_up = true;
951 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 932 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
952 (status_reg & IXGB_STATUS_LU)) { 933 (status_reg & IXGB_STATUS_LU)) {
953 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); 934 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
954 hw->link_up = ixgb_link_reset(hw); 935 hw->link_up = ixgb_link_reset(hw);
955 } else { 936 } else {
956 /* 937 /*
@@ -981,8 +962,7 @@ bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
981 newRFC = IXGB_READ_REG(hw, RFC); 962 newRFC = IXGB_READ_REG(hw, RFC);
982 if ((hw->lastLFC + 250 < newLFC) 963 if ((hw->lastLFC + 250 < newLFC)
983 || (hw->lastRFC + 250 < newRFC)) { 964 || (hw->lastRFC + 250 < newRFC)) {
984 DEBUGOUT 965 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
985 ("BAD LINK! too many LFC/RFC since last check\n");
986 bad_link_returncode = true; 966 bad_link_returncode = true;
987 } 967 }
988 hw->lastLFC = newLFC; 968 hw->lastLFC = newLFC;
@@ -1002,11 +982,11 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
1002{ 982{
1003 volatile u32 temp_reg; 983 volatile u32 temp_reg;
1004 984
1005 DEBUGFUNC("ixgb_clear_hw_cntrs"); 985 ENTER();
1006 986
1007 /* if we are stopped or resetting exit gracefully */ 987 /* if we are stopped or resetting exit gracefully */
1008 if (hw->adapter_stopped) { 988 if (hw->adapter_stopped) {
1009 DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 989 pr_debug("Exiting because the adapter is stopped!!!\n");
1010 return; 990 return;
1011 } 991 }
1012 992
@@ -1156,26 +1136,21 @@ static bool
1156mac_addr_valid(u8 *mac_addr) 1136mac_addr_valid(u8 *mac_addr)
1157{ 1137{
1158 bool is_valid = true; 1138 bool is_valid = true;
1159 DEBUGFUNC("mac_addr_valid"); 1139 ENTER();
1160 1140
1161 /* Make sure it is not a multicast address */ 1141 /* Make sure it is not a multicast address */
1162 if (IS_MULTICAST(mac_addr)) { 1142 if (is_multicast_ether_addr(mac_addr)) {
1163 DEBUGOUT("MAC address is multicast\n"); 1143 pr_debug("MAC address is multicast\n");
1164 is_valid = false; 1144 is_valid = false;
1165 } 1145 }
1166 /* Not a broadcast address */ 1146 /* Not a broadcast address */
1167 else if (IS_BROADCAST(mac_addr)) { 1147 else if (is_broadcast_ether_addr(mac_addr)) {
1168 DEBUGOUT("MAC address is broadcast\n"); 1148 pr_debug("MAC address is broadcast\n");
1169 is_valid = false; 1149 is_valid = false;
1170 } 1150 }
1171 /* Reject the zero address */ 1151 /* Reject the zero address */
1172 else if (mac_addr[0] == 0 && 1152 else if (is_zero_ether_addr(mac_addr)) {
1173 mac_addr[1] == 0 && 1153 pr_debug("MAC address is all zeros\n");
1174 mac_addr[2] == 0 &&
1175 mac_addr[3] == 0 &&
1176 mac_addr[4] == 0 &&
1177 mac_addr[5] == 0) {
1178 DEBUGOUT("MAC address is all zeros\n");
1179 is_valid = false; 1154 is_valid = false;
1180 } 1155 }
1181 return (is_valid); 1156 return (is_valid);