diff options
author | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
---|---|---|
committer | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
commit | ada47b5fe13d89735805b566185f4885f5a3f750 (patch) | |
tree | 644b88f8a71896307d71438e9b3af49126ffb22b /drivers/net/igb/igb_main.c | |
parent | 43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff) | |
parent | 3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff) |
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/net/igb/igb_main.c')
-rw-r--r-- | drivers/net/igb/igb_main.c | 3738 |
1 files changed, 2163 insertions, 1575 deletions
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 714c3a4a44ef..c9baa2aa98cd 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <linux/pagemap.h> | 32 | #include <linux/pagemap.h> |
33 | #include <linux/netdevice.h> | 33 | #include <linux/netdevice.h> |
34 | #include <linux/ipv6.h> | 34 | #include <linux/ipv6.h> |
35 | #include <linux/slab.h> | ||
35 | #include <net/checksum.h> | 36 | #include <net/checksum.h> |
36 | #include <net/ip6_checksum.h> | 37 | #include <net/ip6_checksum.h> |
37 | #include <linux/net_tstamp.h> | 38 | #include <linux/net_tstamp.h> |
@@ -49,7 +50,7 @@ | |||
49 | #endif | 50 | #endif |
50 | #include "igb.h" | 51 | #include "igb.h" |
51 | 52 | ||
52 | #define DRV_VERSION "1.3.16-k2" | 53 | #define DRV_VERSION "2.1.0-k2" |
53 | char igb_driver_name[] = "igb"; | 54 | char igb_driver_name[] = "igb"; |
54 | char igb_driver_version[] = DRV_VERSION; | 55 | char igb_driver_version[] = DRV_VERSION; |
55 | static const char igb_driver_string[] = | 56 | static const char igb_driver_string[] = |
@@ -60,12 +61,19 @@ static const struct e1000_info *igb_info_tbl[] = { | |||
60 | [board_82575] = &e1000_82575_info, | 61 | [board_82575] = &e1000_82575_info, |
61 | }; | 62 | }; |
62 | 63 | ||
63 | static struct pci_device_id igb_pci_tbl[] = { | 64 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, | ||
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | ||
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, | ||
68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | ||
69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | ||
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, | 70 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, | 71 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
72 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, | ||
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, | 73 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | 74 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, |
68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, | 75 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
76 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, | ||
69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, | 77 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
70 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, | 78 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
71 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | 79 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, |
@@ -81,6 +89,7 @@ static int igb_setup_all_tx_resources(struct igb_adapter *); | |||
81 | static int igb_setup_all_rx_resources(struct igb_adapter *); | 89 | static int igb_setup_all_rx_resources(struct igb_adapter *); |
82 | static void igb_free_all_tx_resources(struct igb_adapter *); | 90 | static void igb_free_all_tx_resources(struct igb_adapter *); |
83 | static void igb_free_all_rx_resources(struct igb_adapter *); | 91 | static void igb_free_all_rx_resources(struct igb_adapter *); |
92 | static void igb_setup_mrqc(struct igb_adapter *); | ||
84 | void igb_update_stats(struct igb_adapter *); | 93 | void igb_update_stats(struct igb_adapter *); |
85 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | 94 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
86 | static void __devexit igb_remove(struct pci_dev *pdev); | 95 | static void __devexit igb_remove(struct pci_dev *pdev); |
@@ -89,7 +98,6 @@ static int igb_open(struct net_device *); | |||
89 | static int igb_close(struct net_device *); | 98 | static int igb_close(struct net_device *); |
90 | static void igb_configure_tx(struct igb_adapter *); | 99 | static void igb_configure_tx(struct igb_adapter *); |
91 | static void igb_configure_rx(struct igb_adapter *); | 100 | static void igb_configure_rx(struct igb_adapter *); |
92 | static void igb_setup_rctl(struct igb_adapter *); | ||
93 | static void igb_clean_all_tx_rings(struct igb_adapter *); | 101 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
94 | static void igb_clean_all_rx_rings(struct igb_adapter *); | 102 | static void igb_clean_all_rx_rings(struct igb_adapter *); |
95 | static void igb_clean_tx_ring(struct igb_ring *); | 103 | static void igb_clean_tx_ring(struct igb_ring *); |
@@ -98,28 +106,22 @@ static void igb_set_rx_mode(struct net_device *); | |||
98 | static void igb_update_phy_info(unsigned long); | 106 | static void igb_update_phy_info(unsigned long); |
99 | static void igb_watchdog(unsigned long); | 107 | static void igb_watchdog(unsigned long); |
100 | static void igb_watchdog_task(struct work_struct *); | 108 | static void igb_watchdog_task(struct work_struct *); |
101 | static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, | 109 | static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); |
102 | struct net_device *, | ||
103 | struct igb_ring *); | ||
104 | static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, | ||
105 | struct net_device *); | ||
106 | static struct net_device_stats *igb_get_stats(struct net_device *); | 110 | static struct net_device_stats *igb_get_stats(struct net_device *); |
107 | static int igb_change_mtu(struct net_device *, int); | 111 | static int igb_change_mtu(struct net_device *, int); |
108 | static int igb_set_mac(struct net_device *, void *); | 112 | static int igb_set_mac(struct net_device *, void *); |
113 | static void igb_set_uta(struct igb_adapter *adapter); | ||
109 | static irqreturn_t igb_intr(int irq, void *); | 114 | static irqreturn_t igb_intr(int irq, void *); |
110 | static irqreturn_t igb_intr_msi(int irq, void *); | 115 | static irqreturn_t igb_intr_msi(int irq, void *); |
111 | static irqreturn_t igb_msix_other(int irq, void *); | 116 | static irqreturn_t igb_msix_other(int irq, void *); |
112 | static irqreturn_t igb_msix_rx(int irq, void *); | 117 | static irqreturn_t igb_msix_ring(int irq, void *); |
113 | static irqreturn_t igb_msix_tx(int irq, void *); | ||
114 | #ifdef CONFIG_IGB_DCA | 118 | #ifdef CONFIG_IGB_DCA |
115 | static void igb_update_rx_dca(struct igb_ring *); | 119 | static void igb_update_dca(struct igb_q_vector *); |
116 | static void igb_update_tx_dca(struct igb_ring *); | ||
117 | static void igb_setup_dca(struct igb_adapter *); | 120 | static void igb_setup_dca(struct igb_adapter *); |
118 | #endif /* CONFIG_IGB_DCA */ | 121 | #endif /* CONFIG_IGB_DCA */ |
119 | static bool igb_clean_tx_irq(struct igb_ring *); | 122 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
120 | static int igb_poll(struct napi_struct *, int); | 123 | static int igb_poll(struct napi_struct *, int); |
121 | static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int); | 124 | static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int); |
122 | static void igb_alloc_rx_buffers_adv(struct igb_ring *, int); | ||
123 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); | 125 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
124 | static void igb_tx_timeout(struct net_device *); | 126 | static void igb_tx_timeout(struct net_device *); |
125 | static void igb_reset_task(struct work_struct *); | 127 | static void igb_reset_task(struct work_struct *); |
@@ -127,56 +129,18 @@ static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |||
127 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | 129 | static void igb_vlan_rx_add_vid(struct net_device *, u16); |
128 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | 130 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); |
129 | static void igb_restore_vlan(struct igb_adapter *); | 131 | static void igb_restore_vlan(struct igb_adapter *); |
132 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); | ||
130 | static void igb_ping_all_vfs(struct igb_adapter *); | 133 | static void igb_ping_all_vfs(struct igb_adapter *); |
131 | static void igb_msg_task(struct igb_adapter *); | 134 | static void igb_msg_task(struct igb_adapter *); |
132 | static int igb_rcv_msg_from_vf(struct igb_adapter *, u32); | ||
133 | static inline void igb_set_rah_pool(struct e1000_hw *, int , int); | ||
134 | static void igb_vmm_control(struct igb_adapter *); | 135 | static void igb_vmm_control(struct igb_adapter *); |
135 | static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *); | 136 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
136 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); | 137 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
137 | 138 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); | |
138 | static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn) | 139 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, |
139 | { | 140 | int vf, u16 vlan, u8 qos); |
140 | u32 reg_data; | 141 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); |
141 | 142 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, | |
142 | reg_data = rd32(E1000_VMOLR(vfn)); | 143 | struct ifla_vf_info *ivi); |
143 | reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */ | ||
144 | E1000_VMOLR_ROPE | /* Accept packets matched in UTA */ | ||
145 | E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */ | ||
146 | E1000_VMOLR_AUPE | /* Accept untagged packets */ | ||
147 | E1000_VMOLR_STRVLAN; /* Strip vlan tags */ | ||
148 | wr32(E1000_VMOLR(vfn), reg_data); | ||
149 | } | ||
150 | |||
151 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, | ||
152 | int vfn) | ||
153 | { | ||
154 | struct e1000_hw *hw = &adapter->hw; | ||
155 | u32 vmolr; | ||
156 | |||
157 | /* if it isn't the PF check to see if VFs are enabled and | ||
158 | * increase the size to support vlan tags */ | ||
159 | if (vfn < adapter->vfs_allocated_count && | ||
160 | adapter->vf_data[vfn].vlans_enabled) | ||
161 | size += VLAN_TAG_SIZE; | ||
162 | |||
163 | vmolr = rd32(E1000_VMOLR(vfn)); | ||
164 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | ||
165 | vmolr |= size | E1000_VMOLR_LPE; | ||
166 | wr32(E1000_VMOLR(vfn), vmolr); | ||
167 | |||
168 | return 0; | ||
169 | } | ||
170 | |||
171 | static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry) | ||
172 | { | ||
173 | u32 reg_data; | ||
174 | |||
175 | reg_data = rd32(E1000_RAH(entry)); | ||
176 | reg_data &= ~E1000_RAH_POOL_MASK; | ||
177 | reg_data |= E1000_RAH_POOL_1 << pool;; | ||
178 | wr32(E1000_RAH(entry), reg_data); | ||
179 | } | ||
180 | 144 | ||
181 | #ifdef CONFIG_PM | 145 | #ifdef CONFIG_PM |
182 | static int igb_suspend(struct pci_dev *, pm_message_t); | 146 | static int igb_suspend(struct pci_dev *, pm_message_t); |
@@ -228,46 +192,12 @@ static struct pci_driver igb_driver = { | |||
228 | .err_handler = &igb_err_handler | 192 | .err_handler = &igb_err_handler |
229 | }; | 193 | }; |
230 | 194 | ||
231 | static int global_quad_port_a; /* global quad port a indication */ | ||
232 | |||
233 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | 195 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); |
234 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | 196 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); |
235 | MODULE_LICENSE("GPL"); | 197 | MODULE_LICENSE("GPL"); |
236 | MODULE_VERSION(DRV_VERSION); | 198 | MODULE_VERSION(DRV_VERSION); |
237 | 199 | ||
238 | /** | 200 | /** |
239 | * Scale the NIC clock cycle by a large factor so that | ||
240 | * relatively small clock corrections can be added or | ||
241 | * substracted at each clock tick. The drawbacks of a | ||
242 | * large factor are a) that the clock register overflows | ||
243 | * more quickly (not such a big deal) and b) that the | ||
244 | * increment per tick has to fit into 24 bits. | ||
245 | * | ||
246 | * Note that | ||
247 | * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * | ||
248 | * IGB_TSYNC_SCALE | ||
249 | * TIMINCA += TIMINCA * adjustment [ppm] / 1e9 | ||
250 | * | ||
251 | * The base scale factor is intentionally a power of two | ||
252 | * so that the division in %struct timecounter can be done with | ||
253 | * a shift. | ||
254 | */ | ||
255 | #define IGB_TSYNC_SHIFT (19) | ||
256 | #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT) | ||
257 | |||
258 | /** | ||
259 | * The duration of one clock cycle of the NIC. | ||
260 | * | ||
261 | * @todo This hard-coded value is part of the specification and might change | ||
262 | * in future hardware revisions. Add revision check. | ||
263 | */ | ||
264 | #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16 | ||
265 | |||
266 | #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24) | ||
267 | # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA | ||
268 | #endif | ||
269 | |||
270 | /** | ||
271 | * igb_read_clock - read raw cycle counter (to be used by time counter) | 201 | * igb_read_clock - read raw cycle counter (to be used by time counter) |
272 | */ | 202 | */ |
273 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | 203 | static cycle_t igb_read_clock(const struct cyclecounter *tc) |
@@ -275,11 +205,21 @@ static cycle_t igb_read_clock(const struct cyclecounter *tc) | |||
275 | struct igb_adapter *adapter = | 205 | struct igb_adapter *adapter = |
276 | container_of(tc, struct igb_adapter, cycles); | 206 | container_of(tc, struct igb_adapter, cycles); |
277 | struct e1000_hw *hw = &adapter->hw; | 207 | struct e1000_hw *hw = &adapter->hw; |
278 | u64 stamp; | 208 | u64 stamp = 0; |
209 | int shift = 0; | ||
279 | 210 | ||
280 | stamp = rd32(E1000_SYSTIML); | 211 | /* |
281 | stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL; | 212 | * The timestamp latches on lowest register read. For the 82580 |
213 | * the lowest register is SYSTIMR instead of SYSTIML. However we never | ||
214 | * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it. | ||
215 | */ | ||
216 | if (hw->mac.type == e1000_82580) { | ||
217 | stamp = rd32(E1000_SYSTIMR) >> 8; | ||
218 | shift = IGB_82580_TSYNC_SHIFT; | ||
219 | } | ||
282 | 220 | ||
221 | stamp |= (u64)rd32(E1000_SYSTIML) << shift; | ||
222 | stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32); | ||
283 | return stamp; | 223 | return stamp; |
284 | } | 224 | } |
285 | 225 | ||
@@ -320,17 +260,6 @@ static char *igb_get_time_str(struct igb_adapter *adapter, | |||
320 | #endif | 260 | #endif |
321 | 261 | ||
322 | /** | 262 | /** |
323 | * igb_desc_unused - calculate if we have unused descriptors | ||
324 | **/ | ||
325 | static int igb_desc_unused(struct igb_ring *ring) | ||
326 | { | ||
327 | if (ring->next_to_clean > ring->next_to_use) | ||
328 | return ring->next_to_clean - ring->next_to_use - 1; | ||
329 | |||
330 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | ||
331 | } | ||
332 | |||
333 | /** | ||
334 | * igb_init_module - Driver Registration Routine | 263 | * igb_init_module - Driver Registration Routine |
335 | * | 264 | * |
336 | * igb_init_module is the first routine called when the driver is | 265 | * igb_init_module is the first routine called when the driver is |
@@ -344,12 +273,9 @@ static int __init igb_init_module(void) | |||
344 | 273 | ||
345 | printk(KERN_INFO "%s\n", igb_copyright); | 274 | printk(KERN_INFO "%s\n", igb_copyright); |
346 | 275 | ||
347 | global_quad_port_a = 0; | ||
348 | |||
349 | #ifdef CONFIG_IGB_DCA | 276 | #ifdef CONFIG_IGB_DCA |
350 | dca_register_notify(&dca_notifier); | 277 | dca_register_notify(&dca_notifier); |
351 | #endif | 278 | #endif |
352 | |||
353 | ret = pci_register_driver(&igb_driver); | 279 | ret = pci_register_driver(&igb_driver); |
354 | return ret; | 280 | return ret; |
355 | } | 281 | } |
@@ -382,8 +308,8 @@ module_exit(igb_exit_module); | |||
382 | **/ | 308 | **/ |
383 | static void igb_cache_ring_register(struct igb_adapter *adapter) | 309 | static void igb_cache_ring_register(struct igb_adapter *adapter) |
384 | { | 310 | { |
385 | int i; | 311 | int i = 0, j = 0; |
386 | unsigned int rbase_offset = adapter->vfs_allocated_count; | 312 | u32 rbase_offset = adapter->vfs_allocated_count; |
387 | 313 | ||
388 | switch (adapter->hw.mac.type) { | 314 | switch (adapter->hw.mac.type) { |
389 | case e1000_82576: | 315 | case e1000_82576: |
@@ -392,23 +318,41 @@ static void igb_cache_ring_register(struct igb_adapter *adapter) | |||
392 | * In order to avoid collision we start at the first free queue | 318 | * In order to avoid collision we start at the first free queue |
393 | * and continue consuming queues in the same sequence | 319 | * and continue consuming queues in the same sequence |
394 | */ | 320 | */ |
395 | for (i = 0; i < adapter->num_rx_queues; i++) | 321 | if (adapter->vfs_allocated_count) { |
396 | adapter->rx_ring[i].reg_idx = rbase_offset + | 322 | for (; i < adapter->rss_queues; i++) |
397 | Q_IDX_82576(i); | 323 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
398 | for (i = 0; i < adapter->num_tx_queues; i++) | 324 | Q_IDX_82576(i); |
399 | adapter->tx_ring[i].reg_idx = rbase_offset + | 325 | for (; j < adapter->rss_queues; j++) |
400 | Q_IDX_82576(i); | 326 | adapter->tx_ring[j]->reg_idx = rbase_offset + |
401 | break; | 327 | Q_IDX_82576(j); |
328 | } | ||
402 | case e1000_82575: | 329 | case e1000_82575: |
330 | case e1000_82580: | ||
403 | default: | 331 | default: |
404 | for (i = 0; i < adapter->num_rx_queues; i++) | 332 | for (; i < adapter->num_rx_queues; i++) |
405 | adapter->rx_ring[i].reg_idx = i; | 333 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
406 | for (i = 0; i < adapter->num_tx_queues; i++) | 334 | for (; j < adapter->num_tx_queues; j++) |
407 | adapter->tx_ring[i].reg_idx = i; | 335 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
408 | break; | 336 | break; |
409 | } | 337 | } |
410 | } | 338 | } |
411 | 339 | ||
340 | static void igb_free_queues(struct igb_adapter *adapter) | ||
341 | { | ||
342 | int i; | ||
343 | |||
344 | for (i = 0; i < adapter->num_tx_queues; i++) { | ||
345 | kfree(adapter->tx_ring[i]); | ||
346 | adapter->tx_ring[i] = NULL; | ||
347 | } | ||
348 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
349 | kfree(adapter->rx_ring[i]); | ||
350 | adapter->rx_ring[i] = NULL; | ||
351 | } | ||
352 | adapter->num_rx_queues = 0; | ||
353 | adapter->num_tx_queues = 0; | ||
354 | } | ||
355 | |||
412 | /** | 356 | /** |
413 | * igb_alloc_queues - Allocate memory for all rings | 357 | * igb_alloc_queues - Allocate memory for all rings |
414 | * @adapter: board private structure to initialize | 358 | * @adapter: board private structure to initialize |
@@ -418,64 +362,63 @@ static void igb_cache_ring_register(struct igb_adapter *adapter) | |||
418 | **/ | 362 | **/ |
419 | static int igb_alloc_queues(struct igb_adapter *adapter) | 363 | static int igb_alloc_queues(struct igb_adapter *adapter) |
420 | { | 364 | { |
365 | struct igb_ring *ring; | ||
421 | int i; | 366 | int i; |
422 | 367 | ||
423 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | ||
424 | sizeof(struct igb_ring), GFP_KERNEL); | ||
425 | if (!adapter->tx_ring) | ||
426 | return -ENOMEM; | ||
427 | |||
428 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | ||
429 | sizeof(struct igb_ring), GFP_KERNEL); | ||
430 | if (!adapter->rx_ring) { | ||
431 | kfree(adapter->tx_ring); | ||
432 | return -ENOMEM; | ||
433 | } | ||
434 | |||
435 | adapter->rx_ring->buddy = adapter->tx_ring; | ||
436 | |||
437 | for (i = 0; i < adapter->num_tx_queues; i++) { | 368 | for (i = 0; i < adapter->num_tx_queues; i++) { |
438 | struct igb_ring *ring = &(adapter->tx_ring[i]); | 369 | ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); |
370 | if (!ring) | ||
371 | goto err; | ||
439 | ring->count = adapter->tx_ring_count; | 372 | ring->count = adapter->tx_ring_count; |
440 | ring->adapter = adapter; | ||
441 | ring->queue_index = i; | 373 | ring->queue_index = i; |
374 | ring->pdev = adapter->pdev; | ||
375 | ring->netdev = adapter->netdev; | ||
376 | /* For 82575, context index must be unique per ring. */ | ||
377 | if (adapter->hw.mac.type == e1000_82575) | ||
378 | ring->flags = IGB_RING_FLAG_TX_CTX_IDX; | ||
379 | adapter->tx_ring[i] = ring; | ||
442 | } | 380 | } |
381 | |||
443 | for (i = 0; i < adapter->num_rx_queues; i++) { | 382 | for (i = 0; i < adapter->num_rx_queues; i++) { |
444 | struct igb_ring *ring = &(adapter->rx_ring[i]); | 383 | ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); |
384 | if (!ring) | ||
385 | goto err; | ||
445 | ring->count = adapter->rx_ring_count; | 386 | ring->count = adapter->rx_ring_count; |
446 | ring->adapter = adapter; | ||
447 | ring->queue_index = i; | 387 | ring->queue_index = i; |
448 | ring->itr_register = E1000_ITR; | 388 | ring->pdev = adapter->pdev; |
449 | 389 | ring->netdev = adapter->netdev; | |
450 | /* set a default napi handler for each rx_ring */ | 390 | ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
451 | netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64); | 391 | ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */ |
392 | /* set flag indicating ring supports SCTP checksum offload */ | ||
393 | if (adapter->hw.mac.type >= e1000_82576) | ||
394 | ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM; | ||
395 | adapter->rx_ring[i] = ring; | ||
452 | } | 396 | } |
453 | 397 | ||
454 | igb_cache_ring_register(adapter); | 398 | igb_cache_ring_register(adapter); |
455 | return 0; | ||
456 | } | ||
457 | |||
458 | static void igb_free_queues(struct igb_adapter *adapter) | ||
459 | { | ||
460 | int i; | ||
461 | 399 | ||
462 | for (i = 0; i < adapter->num_rx_queues; i++) | 400 | return 0; |
463 | netif_napi_del(&adapter->rx_ring[i].napi); | ||
464 | 401 | ||
465 | adapter->num_rx_queues = 0; | 402 | err: |
466 | adapter->num_tx_queues = 0; | 403 | igb_free_queues(adapter); |
467 | 404 | ||
468 | kfree(adapter->tx_ring); | 405 | return -ENOMEM; |
469 | kfree(adapter->rx_ring); | ||
470 | } | 406 | } |
471 | 407 | ||
472 | #define IGB_N0_QUEUE -1 | 408 | #define IGB_N0_QUEUE -1 |
473 | static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | 409 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
474 | int tx_queue, int msix_vector) | ||
475 | { | 410 | { |
476 | u32 msixbm = 0; | 411 | u32 msixbm = 0; |
412 | struct igb_adapter *adapter = q_vector->adapter; | ||
477 | struct e1000_hw *hw = &adapter->hw; | 413 | struct e1000_hw *hw = &adapter->hw; |
478 | u32 ivar, index; | 414 | u32 ivar, index; |
415 | int rx_queue = IGB_N0_QUEUE; | ||
416 | int tx_queue = IGB_N0_QUEUE; | ||
417 | |||
418 | if (q_vector->rx_ring) | ||
419 | rx_queue = q_vector->rx_ring->reg_idx; | ||
420 | if (q_vector->tx_ring) | ||
421 | tx_queue = q_vector->tx_ring->reg_idx; | ||
479 | 422 | ||
480 | switch (hw->mac.type) { | 423 | switch (hw->mac.type) { |
481 | case e1000_82575: | 424 | case e1000_82575: |
@@ -483,16 +426,14 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
483 | bitmask for the EICR/EIMS/EIMC registers. To assign one | 426 | bitmask for the EICR/EIMS/EIMC registers. To assign one |
484 | or more queues to a vector, we write the appropriate bits | 427 | or more queues to a vector, we write the appropriate bits |
485 | into the MSIXBM register for that vector. */ | 428 | into the MSIXBM register for that vector. */ |
486 | if (rx_queue > IGB_N0_QUEUE) { | 429 | if (rx_queue > IGB_N0_QUEUE) |
487 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; | 430 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
488 | adapter->rx_ring[rx_queue].eims_value = msixbm; | 431 | if (tx_queue > IGB_N0_QUEUE) |
489 | } | ||
490 | if (tx_queue > IGB_N0_QUEUE) { | ||
491 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; | 432 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
492 | adapter->tx_ring[tx_queue].eims_value = | 433 | if (!adapter->msix_entries && msix_vector == 0) |
493 | E1000_EICR_TX_QUEUE0 << tx_queue; | 434 | msixbm |= E1000_EIMS_OTHER; |
494 | } | ||
495 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | 435 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
436 | q_vector->eims_value = msixbm; | ||
496 | break; | 437 | break; |
497 | case e1000_82576: | 438 | case e1000_82576: |
498 | /* 82576 uses a table-based method for assigning vectors. | 439 | /* 82576 uses a table-based method for assigning vectors. |
@@ -500,7 +441,40 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
500 | a vector number along with a "valid" bit. Sadly, the layout | 441 | a vector number along with a "valid" bit. Sadly, the layout |
501 | of the table is somewhat counterintuitive. */ | 442 | of the table is somewhat counterintuitive. */ |
502 | if (rx_queue > IGB_N0_QUEUE) { | 443 | if (rx_queue > IGB_N0_QUEUE) { |
503 | index = (rx_queue >> 1) + adapter->vfs_allocated_count; | 444 | index = (rx_queue & 0x7); |
445 | ivar = array_rd32(E1000_IVAR0, index); | ||
446 | if (rx_queue < 8) { | ||
447 | /* vector goes into low byte of register */ | ||
448 | ivar = ivar & 0xFFFFFF00; | ||
449 | ivar |= msix_vector | E1000_IVAR_VALID; | ||
450 | } else { | ||
451 | /* vector goes into third byte of register */ | ||
452 | ivar = ivar & 0xFF00FFFF; | ||
453 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | ||
454 | } | ||
455 | array_wr32(E1000_IVAR0, index, ivar); | ||
456 | } | ||
457 | if (tx_queue > IGB_N0_QUEUE) { | ||
458 | index = (tx_queue & 0x7); | ||
459 | ivar = array_rd32(E1000_IVAR0, index); | ||
460 | if (tx_queue < 8) { | ||
461 | /* vector goes into second byte of register */ | ||
462 | ivar = ivar & 0xFFFF00FF; | ||
463 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | ||
464 | } else { | ||
465 | /* vector goes into high byte of register */ | ||
466 | ivar = ivar & 0x00FFFFFF; | ||
467 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | ||
468 | } | ||
469 | array_wr32(E1000_IVAR0, index, ivar); | ||
470 | } | ||
471 | q_vector->eims_value = 1 << msix_vector; | ||
472 | break; | ||
473 | case e1000_82580: | ||
474 | /* 82580 uses the same table-based approach as 82576 but has fewer | ||
475 | entries as a result we carry over for queues greater than 4. */ | ||
476 | if (rx_queue > IGB_N0_QUEUE) { | ||
477 | index = (rx_queue >> 1); | ||
504 | ivar = array_rd32(E1000_IVAR0, index); | 478 | ivar = array_rd32(E1000_IVAR0, index); |
505 | if (rx_queue & 0x1) { | 479 | if (rx_queue & 0x1) { |
506 | /* vector goes into third byte of register */ | 480 | /* vector goes into third byte of register */ |
@@ -511,11 +485,10 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
511 | ivar = ivar & 0xFFFFFF00; | 485 | ivar = ivar & 0xFFFFFF00; |
512 | ivar |= msix_vector | E1000_IVAR_VALID; | 486 | ivar |= msix_vector | E1000_IVAR_VALID; |
513 | } | 487 | } |
514 | adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; | ||
515 | array_wr32(E1000_IVAR0, index, ivar); | 488 | array_wr32(E1000_IVAR0, index, ivar); |
516 | } | 489 | } |
517 | if (tx_queue > IGB_N0_QUEUE) { | 490 | if (tx_queue > IGB_N0_QUEUE) { |
518 | index = (tx_queue >> 1) + adapter->vfs_allocated_count; | 491 | index = (tx_queue >> 1); |
519 | ivar = array_rd32(E1000_IVAR0, index); | 492 | ivar = array_rd32(E1000_IVAR0, index); |
520 | if (tx_queue & 0x1) { | 493 | if (tx_queue & 0x1) { |
521 | /* vector goes into high byte of register */ | 494 | /* vector goes into high byte of register */ |
@@ -526,14 +499,20 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
526 | ivar = ivar & 0xFFFF00FF; | 499 | ivar = ivar & 0xFFFF00FF; |
527 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | 500 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; |
528 | } | 501 | } |
529 | adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; | ||
530 | array_wr32(E1000_IVAR0, index, ivar); | 502 | array_wr32(E1000_IVAR0, index, ivar); |
531 | } | 503 | } |
504 | q_vector->eims_value = 1 << msix_vector; | ||
532 | break; | 505 | break; |
533 | default: | 506 | default: |
534 | BUG(); | 507 | BUG(); |
535 | break; | 508 | break; |
536 | } | 509 | } |
510 | |||
511 | /* add q_vector eims value to global eims_enable_mask */ | ||
512 | adapter->eims_enable_mask |= q_vector->eims_value; | ||
513 | |||
514 | /* configure q_vector to set itr on first interrupt */ | ||
515 | q_vector->set_itr = 1; | ||
537 | } | 516 | } |
538 | 517 | ||
539 | /** | 518 | /** |
@@ -549,43 +528,10 @@ static void igb_configure_msix(struct igb_adapter *adapter) | |||
549 | struct e1000_hw *hw = &adapter->hw; | 528 | struct e1000_hw *hw = &adapter->hw; |
550 | 529 | ||
551 | adapter->eims_enable_mask = 0; | 530 | adapter->eims_enable_mask = 0; |
552 | if (hw->mac.type == e1000_82576) | ||
553 | /* Turn on MSI-X capability first, or our settings | ||
554 | * won't stick. And it will take days to debug. */ | ||
555 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | ||
556 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | ||
557 | E1000_GPIE_NSICR); | ||
558 | |||
559 | for (i = 0; i < adapter->num_tx_queues; i++) { | ||
560 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | ||
561 | igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); | ||
562 | adapter->eims_enable_mask |= tx_ring->eims_value; | ||
563 | if (tx_ring->itr_val) | ||
564 | writel(tx_ring->itr_val, | ||
565 | hw->hw_addr + tx_ring->itr_register); | ||
566 | else | ||
567 | writel(1, hw->hw_addr + tx_ring->itr_register); | ||
568 | } | ||
569 | |||
570 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
571 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | ||
572 | rx_ring->buddy = NULL; | ||
573 | igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); | ||
574 | adapter->eims_enable_mask |= rx_ring->eims_value; | ||
575 | if (rx_ring->itr_val) | ||
576 | writel(rx_ring->itr_val, | ||
577 | hw->hw_addr + rx_ring->itr_register); | ||
578 | else | ||
579 | writel(1, hw->hw_addr + rx_ring->itr_register); | ||
580 | } | ||
581 | |||
582 | 531 | ||
583 | /* set vector for other causes, i.e. link changes */ | 532 | /* set vector for other causes, i.e. link changes */ |
584 | switch (hw->mac.type) { | 533 | switch (hw->mac.type) { |
585 | case e1000_82575: | 534 | case e1000_82575: |
586 | array_wr32(E1000_MSIXBM(0), vector++, | ||
587 | E1000_EIMS_OTHER); | ||
588 | |||
589 | tmp = rd32(E1000_CTRL_EXT); | 535 | tmp = rd32(E1000_CTRL_EXT); |
590 | /* enable MSI-X PBA support*/ | 536 | /* enable MSI-X PBA support*/ |
591 | tmp |= E1000_CTRL_EXT_PBA_CLR; | 537 | tmp |= E1000_CTRL_EXT_PBA_CLR; |
@@ -595,22 +541,38 @@ static void igb_configure_msix(struct igb_adapter *adapter) | |||
595 | tmp |= E1000_CTRL_EXT_IRCA; | 541 | tmp |= E1000_CTRL_EXT_IRCA; |
596 | 542 | ||
597 | wr32(E1000_CTRL_EXT, tmp); | 543 | wr32(E1000_CTRL_EXT, tmp); |
598 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; | 544 | |
545 | /* enable msix_other interrupt */ | ||
546 | array_wr32(E1000_MSIXBM(0), vector++, | ||
547 | E1000_EIMS_OTHER); | ||
599 | adapter->eims_other = E1000_EIMS_OTHER; | 548 | adapter->eims_other = E1000_EIMS_OTHER; |
600 | 549 | ||
601 | break; | 550 | break; |
602 | 551 | ||
603 | case e1000_82576: | 552 | case e1000_82576: |
553 | case e1000_82580: | ||
554 | /* Turn on MSI-X capability first, or our settings | ||
555 | * won't stick. And it will take days to debug. */ | ||
556 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | ||
557 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | ||
558 | E1000_GPIE_NSICR); | ||
559 | |||
560 | /* enable msix_other interrupt */ | ||
561 | adapter->eims_other = 1 << vector; | ||
604 | tmp = (vector++ | E1000_IVAR_VALID) << 8; | 562 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
605 | wr32(E1000_IVAR_MISC, tmp); | ||
606 | 563 | ||
607 | adapter->eims_enable_mask = (1 << (vector)) - 1; | 564 | wr32(E1000_IVAR_MISC, tmp); |
608 | adapter->eims_other = 1 << (vector - 1); | ||
609 | break; | 565 | break; |
610 | default: | 566 | default: |
611 | /* do nothing, since nothing else supports MSI-X */ | 567 | /* do nothing, since nothing else supports MSI-X */ |
612 | break; | 568 | break; |
613 | } /* switch (hw->mac.type) */ | 569 | } /* switch (hw->mac.type) */ |
570 | |||
571 | adapter->eims_enable_mask |= adapter->eims_other; | ||
572 | |||
573 | for (i = 0; i < adapter->num_q_vectors; i++) | ||
574 | igb_assign_vector(adapter->q_vector[i], vector++); | ||
575 | |||
614 | wrfl(); | 576 | wrfl(); |
615 | } | 577 | } |
616 | 578 | ||
@@ -623,43 +585,40 @@ static void igb_configure_msix(struct igb_adapter *adapter) | |||
623 | static int igb_request_msix(struct igb_adapter *adapter) | 585 | static int igb_request_msix(struct igb_adapter *adapter) |
624 | { | 586 | { |
625 | struct net_device *netdev = adapter->netdev; | 587 | struct net_device *netdev = adapter->netdev; |
588 | struct e1000_hw *hw = &adapter->hw; | ||
626 | int i, err = 0, vector = 0; | 589 | int i, err = 0, vector = 0; |
627 | 590 | ||
628 | vector = 0; | 591 | err = request_irq(adapter->msix_entries[vector].vector, |
629 | 592 | igb_msix_other, 0, netdev->name, adapter); | |
630 | for (i = 0; i < adapter->num_tx_queues; i++) { | 593 | if (err) |
631 | struct igb_ring *ring = &(adapter->tx_ring[i]); | 594 | goto out; |
632 | sprintf(ring->name, "%s-tx-%d", netdev->name, i); | 595 | vector++; |
633 | err = request_irq(adapter->msix_entries[vector].vector, | 596 | |
634 | &igb_msix_tx, 0, ring->name, | 597 | for (i = 0; i < adapter->num_q_vectors; i++) { |
635 | &(adapter->tx_ring[i])); | 598 | struct igb_q_vector *q_vector = adapter->q_vector[i]; |
636 | if (err) | 599 | |
637 | goto out; | 600 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); |
638 | ring->itr_register = E1000_EITR(0) + (vector << 2); | 601 | |
639 | ring->itr_val = 976; /* ~4000 ints/sec */ | 602 | if (q_vector->rx_ring && q_vector->tx_ring) |
640 | vector++; | 603 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, |
641 | } | 604 | q_vector->rx_ring->queue_index); |
642 | for (i = 0; i < adapter->num_rx_queues; i++) { | 605 | else if (q_vector->tx_ring) |
643 | struct igb_ring *ring = &(adapter->rx_ring[i]); | 606 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, |
644 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | 607 | q_vector->tx_ring->queue_index); |
645 | sprintf(ring->name, "%s-rx-%d", netdev->name, i); | 608 | else if (q_vector->rx_ring) |
609 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, | ||
610 | q_vector->rx_ring->queue_index); | ||
646 | else | 611 | else |
647 | memcpy(ring->name, netdev->name, IFNAMSIZ); | 612 | sprintf(q_vector->name, "%s-unused", netdev->name); |
613 | |||
648 | err = request_irq(adapter->msix_entries[vector].vector, | 614 | err = request_irq(adapter->msix_entries[vector].vector, |
649 | &igb_msix_rx, 0, ring->name, | 615 | igb_msix_ring, 0, q_vector->name, |
650 | &(adapter->rx_ring[i])); | 616 | q_vector); |
651 | if (err) | 617 | if (err) |
652 | goto out; | 618 | goto out; |
653 | ring->itr_register = E1000_EITR(0) + (vector << 2); | ||
654 | ring->itr_val = adapter->itr; | ||
655 | vector++; | 619 | vector++; |
656 | } | 620 | } |
657 | 621 | ||
658 | err = request_irq(adapter->msix_entries[vector].vector, | ||
659 | &igb_msix_other, 0, netdev->name, netdev); | ||
660 | if (err) | ||
661 | goto out; | ||
662 | |||
663 | igb_configure_msix(adapter); | 622 | igb_configure_msix(adapter); |
664 | return 0; | 623 | return 0; |
665 | out: | 624 | out: |
@@ -672,11 +631,46 @@ static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |||
672 | pci_disable_msix(adapter->pdev); | 631 | pci_disable_msix(adapter->pdev); |
673 | kfree(adapter->msix_entries); | 632 | kfree(adapter->msix_entries); |
674 | adapter->msix_entries = NULL; | 633 | adapter->msix_entries = NULL; |
675 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) | 634 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
676 | pci_disable_msi(adapter->pdev); | 635 | pci_disable_msi(adapter->pdev); |
677 | return; | 636 | } |
678 | } | 637 | } |
679 | 638 | ||
639 | /** | ||
640 | * igb_free_q_vectors - Free memory allocated for interrupt vectors | ||
641 | * @adapter: board private structure to initialize | ||
642 | * | ||
643 | * This function frees the memory allocated to the q_vectors. In addition if | ||
644 | * NAPI is enabled it will delete any references to the NAPI struct prior | ||
645 | * to freeing the q_vector. | ||
646 | **/ | ||
647 | static void igb_free_q_vectors(struct igb_adapter *adapter) | ||
648 | { | ||
649 | int v_idx; | ||
650 | |||
651 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | ||
652 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | ||
653 | adapter->q_vector[v_idx] = NULL; | ||
654 | if (!q_vector) | ||
655 | continue; | ||
656 | netif_napi_del(&q_vector->napi); | ||
657 | kfree(q_vector); | ||
658 | } | ||
659 | adapter->num_q_vectors = 0; | ||
660 | } | ||
661 | |||
662 | /** | ||
663 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts | ||
664 | * | ||
665 | * This function resets the device so that it has 0 rx queues, tx queues, and | ||
666 | * MSI-X interrupts allocated. | ||
667 | */ | ||
668 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | ||
669 | { | ||
670 | igb_free_queues(adapter); | ||
671 | igb_free_q_vectors(adapter); | ||
672 | igb_reset_interrupt_capability(adapter); | ||
673 | } | ||
680 | 674 | ||
681 | /** | 675 | /** |
682 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | 676 | * igb_set_interrupt_capability - set MSI or MSI-X if supported |
@@ -690,11 +684,21 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |||
690 | int numvecs, i; | 684 | int numvecs, i; |
691 | 685 | ||
692 | /* Number of supported queues. */ | 686 | /* Number of supported queues. */ |
693 | /* Having more queues than CPUs doesn't make sense. */ | 687 | adapter->num_rx_queues = adapter->rss_queues; |
694 | adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); | 688 | adapter->num_tx_queues = adapter->rss_queues; |
695 | adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus()); | 689 | |
690 | /* start with one vector for every rx queue */ | ||
691 | numvecs = adapter->num_rx_queues; | ||
692 | |||
693 | /* if tx handler is separate add 1 for every tx queue */ | ||
694 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) | ||
695 | numvecs += adapter->num_tx_queues; | ||
696 | 696 | ||
697 | numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; | 697 | /* store the number of vectors reserved for queues */ |
698 | adapter->num_q_vectors = numvecs; | ||
699 | |||
700 | /* add 1 vector for link status interrupts */ | ||
701 | numvecs++; | ||
698 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), | 702 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
699 | GFP_KERNEL); | 703 | GFP_KERNEL); |
700 | if (!adapter->msix_entries) | 704 | if (!adapter->msix_entries) |
@@ -728,8 +732,12 @@ msi_only: | |||
728 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | 732 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); |
729 | } | 733 | } |
730 | #endif | 734 | #endif |
735 | adapter->vfs_allocated_count = 0; | ||
736 | adapter->rss_queues = 1; | ||
737 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | ||
731 | adapter->num_rx_queues = 1; | 738 | adapter->num_rx_queues = 1; |
732 | adapter->num_tx_queues = 1; | 739 | adapter->num_tx_queues = 1; |
740 | adapter->num_q_vectors = 1; | ||
733 | if (!pci_enable_msi(adapter->pdev)) | 741 | if (!pci_enable_msi(adapter->pdev)) |
734 | adapter->flags |= IGB_FLAG_HAS_MSI; | 742 | adapter->flags |= IGB_FLAG_HAS_MSI; |
735 | out: | 743 | out: |
@@ -739,6 +747,133 @@ out: | |||
739 | } | 747 | } |
740 | 748 | ||
741 | /** | 749 | /** |
750 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors | ||
751 | * @adapter: board private structure to initialize | ||
752 | * | ||
753 | * We allocate one q_vector per queue interrupt. If allocation fails we | ||
754 | * return -ENOMEM. | ||
755 | **/ | ||
756 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) | ||
757 | { | ||
758 | struct igb_q_vector *q_vector; | ||
759 | struct e1000_hw *hw = &adapter->hw; | ||
760 | int v_idx; | ||
761 | |||
762 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | ||
763 | q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL); | ||
764 | if (!q_vector) | ||
765 | goto err_out; | ||
766 | q_vector->adapter = adapter; | ||
767 | q_vector->itr_register = hw->hw_addr + E1000_EITR(0); | ||
768 | q_vector->itr_val = IGB_START_ITR; | ||
769 | netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64); | ||
770 | adapter->q_vector[v_idx] = q_vector; | ||
771 | } | ||
772 | return 0; | ||
773 | |||
774 | err_out: | ||
775 | igb_free_q_vectors(adapter); | ||
776 | return -ENOMEM; | ||
777 | } | ||
778 | |||
779 | static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter, | ||
780 | int ring_idx, int v_idx) | ||
781 | { | ||
782 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | ||
783 | |||
784 | q_vector->rx_ring = adapter->rx_ring[ring_idx]; | ||
785 | q_vector->rx_ring->q_vector = q_vector; | ||
786 | q_vector->itr_val = adapter->rx_itr_setting; | ||
787 | if (q_vector->itr_val && q_vector->itr_val <= 3) | ||
788 | q_vector->itr_val = IGB_START_ITR; | ||
789 | } | ||
790 | |||
791 | static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter, | ||
792 | int ring_idx, int v_idx) | ||
793 | { | ||
794 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | ||
795 | |||
796 | q_vector->tx_ring = adapter->tx_ring[ring_idx]; | ||
797 | q_vector->tx_ring->q_vector = q_vector; | ||
798 | q_vector->itr_val = adapter->tx_itr_setting; | ||
799 | if (q_vector->itr_val && q_vector->itr_val <= 3) | ||
800 | q_vector->itr_val = IGB_START_ITR; | ||
801 | } | ||
802 | |||
803 | /** | ||
804 | * igb_map_ring_to_vector - maps allocated queues to vectors | ||
805 | * | ||
806 | * This function maps the recently allocated queues to vectors. | ||
807 | **/ | ||
808 | static int igb_map_ring_to_vector(struct igb_adapter *adapter) | ||
809 | { | ||
810 | int i; | ||
811 | int v_idx = 0; | ||
812 | |||
813 | if ((adapter->num_q_vectors < adapter->num_rx_queues) || | ||
814 | (adapter->num_q_vectors < adapter->num_tx_queues)) | ||
815 | return -ENOMEM; | ||
816 | |||
817 | if (adapter->num_q_vectors >= | ||
818 | (adapter->num_rx_queues + adapter->num_tx_queues)) { | ||
819 | for (i = 0; i < adapter->num_rx_queues; i++) | ||
820 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | ||
821 | for (i = 0; i < adapter->num_tx_queues; i++) | ||
822 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | ||
823 | } else { | ||
824 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
825 | if (i < adapter->num_tx_queues) | ||
826 | igb_map_tx_ring_to_vector(adapter, i, v_idx); | ||
827 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | ||
828 | } | ||
829 | for (; i < adapter->num_tx_queues; i++) | ||
830 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | ||
831 | } | ||
832 | return 0; | ||
833 | } | ||
834 | |||
835 | /** | ||
836 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors | ||
837 | * | ||
838 | * This function initializes the interrupts and allocates all of the queues. | ||
839 | **/ | ||
840 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter) | ||
841 | { | ||
842 | struct pci_dev *pdev = adapter->pdev; | ||
843 | int err; | ||
844 | |||
845 | igb_set_interrupt_capability(adapter); | ||
846 | |||
847 | err = igb_alloc_q_vectors(adapter); | ||
848 | if (err) { | ||
849 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | ||
850 | goto err_alloc_q_vectors; | ||
851 | } | ||
852 | |||
853 | err = igb_alloc_queues(adapter); | ||
854 | if (err) { | ||
855 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | ||
856 | goto err_alloc_queues; | ||
857 | } | ||
858 | |||
859 | err = igb_map_ring_to_vector(adapter); | ||
860 | if (err) { | ||
861 | dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n"); | ||
862 | goto err_map_queues; | ||
863 | } | ||
864 | |||
865 | |||
866 | return 0; | ||
867 | err_map_queues: | ||
868 | igb_free_queues(adapter); | ||
869 | err_alloc_queues: | ||
870 | igb_free_q_vectors(adapter); | ||
871 | err_alloc_q_vectors: | ||
872 | igb_reset_interrupt_capability(adapter); | ||
873 | return err; | ||
874 | } | ||
875 | |||
876 | /** | ||
742 | * igb_request_irq - initialize interrupts | 877 | * igb_request_irq - initialize interrupts |
743 | * | 878 | * |
744 | * Attempts to configure interrupts using the best available | 879 | * Attempts to configure interrupts using the best available |
@@ -747,7 +882,7 @@ out: | |||
747 | static int igb_request_irq(struct igb_adapter *adapter) | 882 | static int igb_request_irq(struct igb_adapter *adapter) |
748 | { | 883 | { |
749 | struct net_device *netdev = adapter->netdev; | 884 | struct net_device *netdev = adapter->netdev; |
750 | struct e1000_hw *hw = &adapter->hw; | 885 | struct pci_dev *pdev = adapter->pdev; |
751 | int err = 0; | 886 | int err = 0; |
752 | 887 | ||
753 | if (adapter->msix_entries) { | 888 | if (adapter->msix_entries) { |
@@ -755,39 +890,46 @@ static int igb_request_irq(struct igb_adapter *adapter) | |||
755 | if (!err) | 890 | if (!err) |
756 | goto request_done; | 891 | goto request_done; |
757 | /* fall back to MSI */ | 892 | /* fall back to MSI */ |
758 | igb_reset_interrupt_capability(adapter); | 893 | igb_clear_interrupt_scheme(adapter); |
759 | if (!pci_enable_msi(adapter->pdev)) | 894 | if (!pci_enable_msi(adapter->pdev)) |
760 | adapter->flags |= IGB_FLAG_HAS_MSI; | 895 | adapter->flags |= IGB_FLAG_HAS_MSI; |
761 | igb_free_all_tx_resources(adapter); | 896 | igb_free_all_tx_resources(adapter); |
762 | igb_free_all_rx_resources(adapter); | 897 | igb_free_all_rx_resources(adapter); |
898 | adapter->num_tx_queues = 1; | ||
763 | adapter->num_rx_queues = 1; | 899 | adapter->num_rx_queues = 1; |
764 | igb_alloc_queues(adapter); | 900 | adapter->num_q_vectors = 1; |
765 | } else { | 901 | err = igb_alloc_q_vectors(adapter); |
766 | switch (hw->mac.type) { | 902 | if (err) { |
767 | case e1000_82575: | 903 | dev_err(&pdev->dev, |
768 | wr32(E1000_MSIXBM(0), | 904 | "Unable to allocate memory for vectors\n"); |
769 | (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); | 905 | goto request_done; |
770 | break; | ||
771 | case e1000_82576: | ||
772 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | ||
773 | break; | ||
774 | default: | ||
775 | break; | ||
776 | } | 906 | } |
907 | err = igb_alloc_queues(adapter); | ||
908 | if (err) { | ||
909 | dev_err(&pdev->dev, | ||
910 | "Unable to allocate memory for queues\n"); | ||
911 | igb_free_q_vectors(adapter); | ||
912 | goto request_done; | ||
913 | } | ||
914 | igb_setup_all_tx_resources(adapter); | ||
915 | igb_setup_all_rx_resources(adapter); | ||
916 | } else { | ||
917 | igb_assign_vector(adapter->q_vector[0], 0); | ||
777 | } | 918 | } |
778 | 919 | ||
779 | if (adapter->flags & IGB_FLAG_HAS_MSI) { | 920 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
780 | err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, | 921 | err = request_irq(adapter->pdev->irq, igb_intr_msi, 0, |
781 | netdev->name, netdev); | 922 | netdev->name, adapter); |
782 | if (!err) | 923 | if (!err) |
783 | goto request_done; | 924 | goto request_done; |
925 | |||
784 | /* fall back to legacy interrupts */ | 926 | /* fall back to legacy interrupts */ |
785 | igb_reset_interrupt_capability(adapter); | 927 | igb_reset_interrupt_capability(adapter); |
786 | adapter->flags &= ~IGB_FLAG_HAS_MSI; | 928 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
787 | } | 929 | } |
788 | 930 | ||
789 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, | 931 | err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED, |
790 | netdev->name, netdev); | 932 | netdev->name, adapter); |
791 | 933 | ||
792 | if (err) | 934 | if (err) |
793 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", | 935 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
@@ -799,23 +941,19 @@ request_done: | |||
799 | 941 | ||
800 | static void igb_free_irq(struct igb_adapter *adapter) | 942 | static void igb_free_irq(struct igb_adapter *adapter) |
801 | { | 943 | { |
802 | struct net_device *netdev = adapter->netdev; | ||
803 | |||
804 | if (adapter->msix_entries) { | 944 | if (adapter->msix_entries) { |
805 | int vector = 0, i; | 945 | int vector = 0, i; |
806 | 946 | ||
807 | for (i = 0; i < adapter->num_tx_queues; i++) | 947 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
808 | free_irq(adapter->msix_entries[vector++].vector, | ||
809 | &(adapter->tx_ring[i])); | ||
810 | for (i = 0; i < adapter->num_rx_queues; i++) | ||
811 | free_irq(adapter->msix_entries[vector++].vector, | ||
812 | &(adapter->rx_ring[i])); | ||
813 | 948 | ||
814 | free_irq(adapter->msix_entries[vector++].vector, netdev); | 949 | for (i = 0; i < adapter->num_q_vectors; i++) { |
815 | return; | 950 | struct igb_q_vector *q_vector = adapter->q_vector[i]; |
951 | free_irq(adapter->msix_entries[vector++].vector, | ||
952 | q_vector); | ||
953 | } | ||
954 | } else { | ||
955 | free_irq(adapter->pdev->irq, adapter); | ||
816 | } | 956 | } |
817 | |||
818 | free_irq(adapter->pdev->irq, netdev); | ||
819 | } | 957 | } |
820 | 958 | ||
821 | /** | 959 | /** |
@@ -826,6 +964,11 @@ static void igb_irq_disable(struct igb_adapter *adapter) | |||
826 | { | 964 | { |
827 | struct e1000_hw *hw = &adapter->hw; | 965 | struct e1000_hw *hw = &adapter->hw; |
828 | 966 | ||
967 | /* | ||
968 | * we need to be careful when disabling interrupts. The VFs are also | ||
969 | * mapped into these registers and so clearing the bits can cause | ||
970 | * issues on the VF drivers so we only need to clear what we set | ||
971 | */ | ||
829 | if (adapter->msix_entries) { | 972 | if (adapter->msix_entries) { |
830 | u32 regval = rd32(E1000_EIAM); | 973 | u32 regval = rd32(E1000_EIAM); |
831 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | 974 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); |
@@ -849,41 +992,47 @@ static void igb_irq_enable(struct igb_adapter *adapter) | |||
849 | struct e1000_hw *hw = &adapter->hw; | 992 | struct e1000_hw *hw = &adapter->hw; |
850 | 993 | ||
851 | if (adapter->msix_entries) { | 994 | if (adapter->msix_entries) { |
995 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC; | ||
852 | u32 regval = rd32(E1000_EIAC); | 996 | u32 regval = rd32(E1000_EIAC); |
853 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | 997 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); |
854 | regval = rd32(E1000_EIAM); | 998 | regval = rd32(E1000_EIAM); |
855 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | 999 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); |
856 | wr32(E1000_EIMS, adapter->eims_enable_mask); | 1000 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
857 | if (adapter->vfs_allocated_count) | 1001 | if (adapter->vfs_allocated_count) { |
858 | wr32(E1000_MBVFIMR, 0xFF); | 1002 | wr32(E1000_MBVFIMR, 0xFF); |
859 | wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB | | 1003 | ims |= E1000_IMS_VMMB; |
860 | E1000_IMS_DOUTSYNC)); | 1004 | } |
1005 | if (adapter->hw.mac.type == e1000_82580) | ||
1006 | ims |= E1000_IMS_DRSTA; | ||
1007 | |||
1008 | wr32(E1000_IMS, ims); | ||
861 | } else { | 1009 | } else { |
862 | wr32(E1000_IMS, IMS_ENABLE_MASK); | 1010 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
863 | wr32(E1000_IAM, IMS_ENABLE_MASK); | 1011 | E1000_IMS_DRSTA); |
1012 | wr32(E1000_IAM, IMS_ENABLE_MASK | | ||
1013 | E1000_IMS_DRSTA); | ||
864 | } | 1014 | } |
865 | } | 1015 | } |
866 | 1016 | ||
867 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | 1017 | static void igb_update_mng_vlan(struct igb_adapter *adapter) |
868 | { | 1018 | { |
869 | struct net_device *netdev = adapter->netdev; | 1019 | struct e1000_hw *hw = &adapter->hw; |
870 | u16 vid = adapter->hw.mng_cookie.vlan_id; | 1020 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
871 | u16 old_vid = adapter->mng_vlan_id; | 1021 | u16 old_vid = adapter->mng_vlan_id; |
872 | if (adapter->vlgrp) { | ||
873 | if (!vlan_group_get_device(adapter->vlgrp, vid)) { | ||
874 | if (adapter->hw.mng_cookie.status & | ||
875 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | ||
876 | igb_vlan_rx_add_vid(netdev, vid); | ||
877 | adapter->mng_vlan_id = vid; | ||
878 | } else | ||
879 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | ||
880 | 1022 | ||
881 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | 1023 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { |
882 | (vid != old_vid) && | 1024 | /* add VID to filter table */ |
883 | !vlan_group_get_device(adapter->vlgrp, old_vid)) | 1025 | igb_vfta_set(hw, vid, true); |
884 | igb_vlan_rx_kill_vid(netdev, old_vid); | 1026 | adapter->mng_vlan_id = vid; |
885 | } else | 1027 | } else { |
886 | adapter->mng_vlan_id = vid; | 1028 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; |
1029 | } | ||
1030 | |||
1031 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | ||
1032 | (vid != old_vid) && | ||
1033 | !vlan_group_get_device(adapter->vlgrp, old_vid)) { | ||
1034 | /* remove VID from filter table */ | ||
1035 | igb_vfta_set(hw, old_vid, false); | ||
887 | } | 1036 | } |
888 | } | 1037 | } |
889 | 1038 | ||
@@ -907,7 +1056,6 @@ static void igb_release_hw_control(struct igb_adapter *adapter) | |||
907 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | 1056 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); |
908 | } | 1057 | } |
909 | 1058 | ||
910 | |||
911 | /** | 1059 | /** |
912 | * igb_get_hw_control - get control of the h/w from f/w | 1060 | * igb_get_hw_control - get control of the h/w from f/w |
913 | * @adapter: address of board private structure | 1061 | * @adapter: address of board private structure |
@@ -942,8 +1090,11 @@ static void igb_configure(struct igb_adapter *adapter) | |||
942 | 1090 | ||
943 | igb_restore_vlan(adapter); | 1091 | igb_restore_vlan(adapter); |
944 | 1092 | ||
945 | igb_configure_tx(adapter); | 1093 | igb_setup_tctl(adapter); |
1094 | igb_setup_mrqc(adapter); | ||
946 | igb_setup_rctl(adapter); | 1095 | igb_setup_rctl(adapter); |
1096 | |||
1097 | igb_configure_tx(adapter); | ||
947 | igb_configure_rx(adapter); | 1098 | igb_configure_rx(adapter); |
948 | 1099 | ||
949 | igb_rx_fifo_flush_82575(&adapter->hw); | 1100 | igb_rx_fifo_flush_82575(&adapter->hw); |
@@ -952,20 +1103,39 @@ static void igb_configure(struct igb_adapter *adapter) | |||
952 | * at least 1 descriptor unused to make sure | 1103 | * at least 1 descriptor unused to make sure |
953 | * next_to_use != next_to_clean */ | 1104 | * next_to_use != next_to_clean */ |
954 | for (i = 0; i < adapter->num_rx_queues; i++) { | 1105 | for (i = 0; i < adapter->num_rx_queues; i++) { |
955 | struct igb_ring *ring = &adapter->rx_ring[i]; | 1106 | struct igb_ring *ring = adapter->rx_ring[i]; |
956 | igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring)); | 1107 | igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring)); |
957 | } | 1108 | } |
1109 | } | ||
958 | 1110 | ||
959 | 1111 | /** | |
960 | adapter->tx_queue_len = netdev->tx_queue_len; | 1112 | * igb_power_up_link - Power up the phy/serdes link |
1113 | * @adapter: address of board private structure | ||
1114 | **/ | ||
1115 | void igb_power_up_link(struct igb_adapter *adapter) | ||
1116 | { | ||
1117 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | ||
1118 | igb_power_up_phy_copper(&adapter->hw); | ||
1119 | else | ||
1120 | igb_power_up_serdes_link_82575(&adapter->hw); | ||
961 | } | 1121 | } |
962 | 1122 | ||
1123 | /** | ||
1124 | * igb_power_down_link - Power down the phy/serdes link | ||
1125 | * @adapter: address of board private structure | ||
1126 | */ | ||
1127 | static void igb_power_down_link(struct igb_adapter *adapter) | ||
1128 | { | ||
1129 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | ||
1130 | igb_power_down_phy_copper_82575(&adapter->hw); | ||
1131 | else | ||
1132 | igb_shutdown_serdes_link_82575(&adapter->hw); | ||
1133 | } | ||
963 | 1134 | ||
964 | /** | 1135 | /** |
965 | * igb_up - Open the interface and prepare it to handle traffic | 1136 | * igb_up - Open the interface and prepare it to handle traffic |
966 | * @adapter: board private structure | 1137 | * @adapter: board private structure |
967 | **/ | 1138 | **/ |
968 | |||
969 | int igb_up(struct igb_adapter *adapter) | 1139 | int igb_up(struct igb_adapter *adapter) |
970 | { | 1140 | { |
971 | struct e1000_hw *hw = &adapter->hw; | 1141 | struct e1000_hw *hw = &adapter->hw; |
@@ -976,30 +1146,39 @@ int igb_up(struct igb_adapter *adapter) | |||
976 | 1146 | ||
977 | clear_bit(__IGB_DOWN, &adapter->state); | 1147 | clear_bit(__IGB_DOWN, &adapter->state); |
978 | 1148 | ||
979 | for (i = 0; i < adapter->num_rx_queues; i++) | 1149 | for (i = 0; i < adapter->num_q_vectors; i++) { |
980 | napi_enable(&adapter->rx_ring[i].napi); | 1150 | struct igb_q_vector *q_vector = adapter->q_vector[i]; |
1151 | napi_enable(&q_vector->napi); | ||
1152 | } | ||
981 | if (adapter->msix_entries) | 1153 | if (adapter->msix_entries) |
982 | igb_configure_msix(adapter); | 1154 | igb_configure_msix(adapter); |
983 | 1155 | else | |
984 | igb_vmm_control(adapter); | 1156 | igb_assign_vector(adapter->q_vector[0], 0); |
985 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0); | ||
986 | igb_set_vmolr(hw, adapter->vfs_allocated_count); | ||
987 | 1157 | ||
988 | /* Clear any pending interrupts. */ | 1158 | /* Clear any pending interrupts. */ |
989 | rd32(E1000_ICR); | 1159 | rd32(E1000_ICR); |
990 | igb_irq_enable(adapter); | 1160 | igb_irq_enable(adapter); |
991 | 1161 | ||
1162 | /* notify VFs that reset has been completed */ | ||
1163 | if (adapter->vfs_allocated_count) { | ||
1164 | u32 reg_data = rd32(E1000_CTRL_EXT); | ||
1165 | reg_data |= E1000_CTRL_EXT_PFRSTD; | ||
1166 | wr32(E1000_CTRL_EXT, reg_data); | ||
1167 | } | ||
1168 | |||
992 | netif_tx_start_all_queues(adapter->netdev); | 1169 | netif_tx_start_all_queues(adapter->netdev); |
993 | 1170 | ||
994 | /* Fire a link change interrupt to start the watchdog. */ | 1171 | /* start the watchdog. */ |
995 | wr32(E1000_ICS, E1000_ICS_LSC); | 1172 | hw->mac.get_link_status = 1; |
1173 | schedule_work(&adapter->watchdog_task); | ||
1174 | |||
996 | return 0; | 1175 | return 0; |
997 | } | 1176 | } |
998 | 1177 | ||
999 | void igb_down(struct igb_adapter *adapter) | 1178 | void igb_down(struct igb_adapter *adapter) |
1000 | { | 1179 | { |
1001 | struct e1000_hw *hw = &adapter->hw; | ||
1002 | struct net_device *netdev = adapter->netdev; | 1180 | struct net_device *netdev = adapter->netdev; |
1181 | struct e1000_hw *hw = &adapter->hw; | ||
1003 | u32 tctl, rctl; | 1182 | u32 tctl, rctl; |
1004 | int i; | 1183 | int i; |
1005 | 1184 | ||
@@ -1022,15 +1201,16 @@ void igb_down(struct igb_adapter *adapter) | |||
1022 | wrfl(); | 1201 | wrfl(); |
1023 | msleep(10); | 1202 | msleep(10); |
1024 | 1203 | ||
1025 | for (i = 0; i < adapter->num_rx_queues; i++) | 1204 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1026 | napi_disable(&adapter->rx_ring[i].napi); | 1205 | struct igb_q_vector *q_vector = adapter->q_vector[i]; |
1206 | napi_disable(&q_vector->napi); | ||
1207 | } | ||
1027 | 1208 | ||
1028 | igb_irq_disable(adapter); | 1209 | igb_irq_disable(adapter); |
1029 | 1210 | ||
1030 | del_timer_sync(&adapter->watchdog_timer); | 1211 | del_timer_sync(&adapter->watchdog_timer); |
1031 | del_timer_sync(&adapter->phy_info_timer); | 1212 | del_timer_sync(&adapter->phy_info_timer); |
1032 | 1213 | ||
1033 | netdev->tx_queue_len = adapter->tx_queue_len; | ||
1034 | netif_carrier_off(netdev); | 1214 | netif_carrier_off(netdev); |
1035 | 1215 | ||
1036 | /* record the stats before reset*/ | 1216 | /* record the stats before reset*/ |
@@ -1062,6 +1242,7 @@ void igb_reinit_locked(struct igb_adapter *adapter) | |||
1062 | 1242 | ||
1063 | void igb_reset(struct igb_adapter *adapter) | 1243 | void igb_reset(struct igb_adapter *adapter) |
1064 | { | 1244 | { |
1245 | struct pci_dev *pdev = adapter->pdev; | ||
1065 | struct e1000_hw *hw = &adapter->hw; | 1246 | struct e1000_hw *hw = &adapter->hw; |
1066 | struct e1000_mac_info *mac = &hw->mac; | 1247 | struct e1000_mac_info *mac = &hw->mac; |
1067 | struct e1000_fc_info *fc = &hw->fc; | 1248 | struct e1000_fc_info *fc = &hw->fc; |
@@ -1072,8 +1253,13 @@ void igb_reset(struct igb_adapter *adapter) | |||
1072 | * To take effect CTRL.RST is required. | 1253 | * To take effect CTRL.RST is required. |
1073 | */ | 1254 | */ |
1074 | switch (mac->type) { | 1255 | switch (mac->type) { |
1256 | case e1000_82580: | ||
1257 | pba = rd32(E1000_RXPBS); | ||
1258 | pba = igb_rxpbs_adjust_82580(pba); | ||
1259 | break; | ||
1075 | case e1000_82576: | 1260 | case e1000_82576: |
1076 | pba = E1000_PBA_64K; | 1261 | pba = rd32(E1000_RXPBS); |
1262 | pba &= E1000_RXPBS_SIZE_MASK_82576; | ||
1077 | break; | 1263 | break; |
1078 | case e1000_82575: | 1264 | case e1000_82575: |
1079 | default: | 1265 | default: |
@@ -1133,13 +1319,8 @@ void igb_reset(struct igb_adapter *adapter) | |||
1133 | hwm = min(((pba << 10) * 9 / 10), | 1319 | hwm = min(((pba << 10) * 9 / 10), |
1134 | ((pba << 10) - 2 * adapter->max_frame_size)); | 1320 | ((pba << 10) - 2 * adapter->max_frame_size)); |
1135 | 1321 | ||
1136 | if (mac->type < e1000_82576) { | 1322 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ |
1137 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | 1323 | fc->low_water = fc->high_water - 16; |
1138 | fc->low_water = fc->high_water - 8; | ||
1139 | } else { | ||
1140 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | ||
1141 | fc->low_water = fc->high_water - 16; | ||
1142 | } | ||
1143 | fc->pause_time = 0xFFFF; | 1324 | fc->pause_time = 0xFFFF; |
1144 | fc->send_xon = 1; | 1325 | fc->send_xon = 1; |
1145 | fc->current_mode = fc->requested_mode; | 1326 | fc->current_mode = fc->requested_mode; |
@@ -1148,10 +1329,10 @@ void igb_reset(struct igb_adapter *adapter) | |||
1148 | if (adapter->vfs_allocated_count) { | 1329 | if (adapter->vfs_allocated_count) { |
1149 | int i; | 1330 | int i; |
1150 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | 1331 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) |
1151 | adapter->vf_data[i].clear_to_send = false; | 1332 | adapter->vf_data[i].flags = 0; |
1152 | 1333 | ||
1153 | /* ping all the active vfs to let them know we are going down */ | 1334 | /* ping all the active vfs to let them know we are going down */ |
1154 | igb_ping_all_vfs(adapter); | 1335 | igb_ping_all_vfs(adapter); |
1155 | 1336 | ||
1156 | /* disable transmits and receives */ | 1337 | /* disable transmits and receives */ |
1157 | wr32(E1000_VFRE, 0); | 1338 | wr32(E1000_VFRE, 0); |
@@ -1159,23 +1340,30 @@ void igb_reset(struct igb_adapter *adapter) | |||
1159 | } | 1340 | } |
1160 | 1341 | ||
1161 | /* Allow time for pending master requests to run */ | 1342 | /* Allow time for pending master requests to run */ |
1162 | adapter->hw.mac.ops.reset_hw(&adapter->hw); | 1343 | hw->mac.ops.reset_hw(hw); |
1163 | wr32(E1000_WUC, 0); | 1344 | wr32(E1000_WUC, 0); |
1164 | 1345 | ||
1165 | if (adapter->hw.mac.ops.init_hw(&adapter->hw)) | 1346 | if (hw->mac.ops.init_hw(hw)) |
1166 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | 1347 | dev_err(&pdev->dev, "Hardware Error\n"); |
1348 | |||
1349 | if (hw->mac.type == e1000_82580) { | ||
1350 | u32 reg = rd32(E1000_PCIEMISC); | ||
1351 | wr32(E1000_PCIEMISC, | ||
1352 | reg & ~E1000_PCIEMISC_LX_DECISION); | ||
1353 | } | ||
1354 | if (!netif_running(adapter->netdev)) | ||
1355 | igb_power_down_link(adapter); | ||
1167 | 1356 | ||
1168 | igb_update_mng_vlan(adapter); | 1357 | igb_update_mng_vlan(adapter); |
1169 | 1358 | ||
1170 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | 1359 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ |
1171 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | 1360 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); |
1172 | 1361 | ||
1173 | igb_reset_adaptive(&adapter->hw); | 1362 | igb_get_phy_info(hw); |
1174 | igb_get_phy_info(&adapter->hw); | ||
1175 | } | 1363 | } |
1176 | 1364 | ||
1177 | static const struct net_device_ops igb_netdev_ops = { | 1365 | static const struct net_device_ops igb_netdev_ops = { |
1178 | .ndo_open = igb_open, | 1366 | .ndo_open = igb_open, |
1179 | .ndo_stop = igb_close, | 1367 | .ndo_stop = igb_close, |
1180 | .ndo_start_xmit = igb_xmit_frame_adv, | 1368 | .ndo_start_xmit = igb_xmit_frame_adv, |
1181 | .ndo_get_stats = igb_get_stats, | 1369 | .ndo_get_stats = igb_get_stats, |
@@ -1189,6 +1377,10 @@ static const struct net_device_ops igb_netdev_ops = { | |||
1189 | .ndo_vlan_rx_register = igb_vlan_rx_register, | 1377 | .ndo_vlan_rx_register = igb_vlan_rx_register, |
1190 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, | 1378 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
1191 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | 1379 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, |
1380 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, | ||
1381 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | ||
1382 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | ||
1383 | .ndo_get_vf_config = igb_ndo_get_vf_config, | ||
1192 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1384 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1193 | .ndo_poll_controller = igb_netpoll, | 1385 | .ndo_poll_controller = igb_netpoll, |
1194 | #endif | 1386 | #endif |
@@ -1211,10 +1403,11 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1211 | struct net_device *netdev; | 1403 | struct net_device *netdev; |
1212 | struct igb_adapter *adapter; | 1404 | struct igb_adapter *adapter; |
1213 | struct e1000_hw *hw; | 1405 | struct e1000_hw *hw; |
1406 | u16 eeprom_data = 0; | ||
1407 | static int global_quad_port_a; /* global quad port a indication */ | ||
1214 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; | 1408 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1215 | unsigned long mmio_start, mmio_len; | 1409 | unsigned long mmio_start, mmio_len; |
1216 | int err, pci_using_dac; | 1410 | int err, pci_using_dac; |
1217 | u16 eeprom_data = 0; | ||
1218 | u16 eeprom_apme_mask = IGB_EEPROM_APME; | 1411 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
1219 | u32 part_num; | 1412 | u32 part_num; |
1220 | 1413 | ||
@@ -1291,8 +1484,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1291 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | 1484 | hw->subsystem_vendor_id = pdev->subsystem_vendor; |
1292 | hw->subsystem_device_id = pdev->subsystem_device; | 1485 | hw->subsystem_device_id = pdev->subsystem_device; |
1293 | 1486 | ||
1294 | /* setup the private structure */ | ||
1295 | hw->back = adapter; | ||
1296 | /* Copy the default MAC, PHY and NVM function pointers */ | 1487 | /* Copy the default MAC, PHY and NVM function pointers */ |
1297 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | 1488 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); |
1298 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | 1489 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); |
@@ -1302,46 +1493,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1302 | if (err) | 1493 | if (err) |
1303 | goto err_sw_init; | 1494 | goto err_sw_init; |
1304 | 1495 | ||
1305 | #ifdef CONFIG_PCI_IOV | ||
1306 | /* since iov functionality isn't critical to base device function we | ||
1307 | * can accept failure. If it fails we don't allow iov to be enabled */ | ||
1308 | if (hw->mac.type == e1000_82576) { | ||
1309 | /* 82576 supports a maximum of 7 VFs in addition to the PF */ | ||
1310 | unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs; | ||
1311 | int i; | ||
1312 | unsigned char mac_addr[ETH_ALEN]; | ||
1313 | |||
1314 | if (num_vfs) { | ||
1315 | adapter->vf_data = kcalloc(num_vfs, | ||
1316 | sizeof(struct vf_data_storage), | ||
1317 | GFP_KERNEL); | ||
1318 | if (!adapter->vf_data) { | ||
1319 | dev_err(&pdev->dev, | ||
1320 | "Could not allocate VF private data - " | ||
1321 | "IOV enable failed\n"); | ||
1322 | } else { | ||
1323 | err = pci_enable_sriov(pdev, num_vfs); | ||
1324 | if (!err) { | ||
1325 | adapter->vfs_allocated_count = num_vfs; | ||
1326 | dev_info(&pdev->dev, | ||
1327 | "%d vfs allocated\n", | ||
1328 | num_vfs); | ||
1329 | for (i = 0; | ||
1330 | i < adapter->vfs_allocated_count; | ||
1331 | i++) { | ||
1332 | random_ether_addr(mac_addr); | ||
1333 | igb_set_vf_mac(adapter, i, | ||
1334 | mac_addr); | ||
1335 | } | ||
1336 | } else { | ||
1337 | kfree(adapter->vf_data); | ||
1338 | adapter->vf_data = NULL; | ||
1339 | } | ||
1340 | } | ||
1341 | } | ||
1342 | } | ||
1343 | |||
1344 | #endif | ||
1345 | /* setup the private structure */ | 1496 | /* setup the private structure */ |
1346 | err = igb_sw_init(adapter); | 1497 | err = igb_sw_init(adapter); |
1347 | if (err) | 1498 | if (err) |
@@ -1349,18 +1500,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1349 | 1500 | ||
1350 | igb_get_bus_info_pcie(hw); | 1501 | igb_get_bus_info_pcie(hw); |
1351 | 1502 | ||
1352 | /* set flags */ | ||
1353 | switch (hw->mac.type) { | ||
1354 | case e1000_82575: | ||
1355 | adapter->flags |= IGB_FLAG_NEED_CTX_IDX; | ||
1356 | break; | ||
1357 | case e1000_82576: | ||
1358 | default: | ||
1359 | break; | ||
1360 | } | ||
1361 | |||
1362 | hw->phy.autoneg_wait_to_complete = false; | 1503 | hw->phy.autoneg_wait_to_complete = false; |
1363 | hw->mac.adaptive_ifs = true; | ||
1364 | 1504 | ||
1365 | /* Copper options */ | 1505 | /* Copper options */ |
1366 | if (hw->phy.media_type == e1000_media_type_copper) { | 1506 | if (hw->phy.media_type == e1000_media_type_copper) { |
@@ -1382,7 +1522,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1382 | netdev->features |= NETIF_F_IPV6_CSUM; | 1522 | netdev->features |= NETIF_F_IPV6_CSUM; |
1383 | netdev->features |= NETIF_F_TSO; | 1523 | netdev->features |= NETIF_F_TSO; |
1384 | netdev->features |= NETIF_F_TSO6; | 1524 | netdev->features |= NETIF_F_TSO6; |
1385 | |||
1386 | netdev->features |= NETIF_F_GRO; | 1525 | netdev->features |= NETIF_F_GRO; |
1387 | 1526 | ||
1388 | netdev->vlan_features |= NETIF_F_TSO; | 1527 | netdev->vlan_features |= NETIF_F_TSO; |
@@ -1394,10 +1533,10 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1394 | if (pci_using_dac) | 1533 | if (pci_using_dac) |
1395 | netdev->features |= NETIF_F_HIGHDMA; | 1534 | netdev->features |= NETIF_F_HIGHDMA; |
1396 | 1535 | ||
1397 | if (adapter->hw.mac.type == e1000_82576) | 1536 | if (hw->mac.type >= e1000_82576) |
1398 | netdev->features |= NETIF_F_SCTP_CSUM; | 1537 | netdev->features |= NETIF_F_SCTP_CSUM; |
1399 | 1538 | ||
1400 | adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw); | 1539 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
1401 | 1540 | ||
1402 | /* before reading the NVM, reset the controller to put the device in a | 1541 | /* before reading the NVM, reset the controller to put the device in a |
1403 | * known good starting state */ | 1542 | * known good starting state */ |
@@ -1439,9 +1578,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1439 | hw->fc.requested_mode = e1000_fc_default; | 1578 | hw->fc.requested_mode = e1000_fc_default; |
1440 | hw->fc.current_mode = e1000_fc_default; | 1579 | hw->fc.current_mode = e1000_fc_default; |
1441 | 1580 | ||
1442 | adapter->itr_setting = IGB_DEFAULT_ITR; | ||
1443 | adapter->itr = IGB_START_ITR; | ||
1444 | |||
1445 | igb_validate_mdi_setting(hw); | 1581 | igb_validate_mdi_setting(hw); |
1446 | 1582 | ||
1447 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, | 1583 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, |
@@ -1450,6 +1586,10 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1450 | 1586 | ||
1451 | if (hw->bus.func == 0) | 1587 | if (hw->bus.func == 0) |
1452 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); | 1588 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
1589 | else if (hw->mac.type == e1000_82580) | ||
1590 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | ||
1591 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | ||
1592 | &eeprom_data); | ||
1453 | else if (hw->bus.func == 1) | 1593 | else if (hw->bus.func == 1) |
1454 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | 1594 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); |
1455 | 1595 | ||
@@ -1472,6 +1612,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1472 | adapter->eeprom_wol = 0; | 1612 | adapter->eeprom_wol = 0; |
1473 | break; | 1613 | break; |
1474 | case E1000_DEV_ID_82576_QUAD_COPPER: | 1614 | case E1000_DEV_ID_82576_QUAD_COPPER: |
1615 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: | ||
1475 | /* if quad port adapter, disable WoL on all but port A */ | 1616 | /* if quad port adapter, disable WoL on all but port A */ |
1476 | if (global_quad_port_a != 0) | 1617 | if (global_quad_port_a != 0) |
1477 | adapter->eeprom_wol = 0; | 1618 | adapter->eeprom_wol = 0; |
@@ -1508,66 +1649,14 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1508 | dev_info(&pdev->dev, "DCA enabled\n"); | 1649 | dev_info(&pdev->dev, "DCA enabled\n"); |
1509 | igb_setup_dca(adapter); | 1650 | igb_setup_dca(adapter); |
1510 | } | 1651 | } |
1511 | #endif | ||
1512 | |||
1513 | /* | ||
1514 | * Initialize hardware timer: we keep it running just in case | ||
1515 | * that some program needs it later on. | ||
1516 | */ | ||
1517 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | ||
1518 | adapter->cycles.read = igb_read_clock; | ||
1519 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | ||
1520 | adapter->cycles.mult = 1; | ||
1521 | adapter->cycles.shift = IGB_TSYNC_SHIFT; | ||
1522 | wr32(E1000_TIMINCA, | ||
1523 | (1<<24) | | ||
1524 | IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE); | ||
1525 | #if 0 | ||
1526 | /* | ||
1527 | * Avoid rollover while we initialize by resetting the time counter. | ||
1528 | */ | ||
1529 | wr32(E1000_SYSTIML, 0x00000000); | ||
1530 | wr32(E1000_SYSTIMH, 0x00000000); | ||
1531 | #else | ||
1532 | /* | ||
1533 | * Set registers so that rollover occurs soon to test this. | ||
1534 | */ | ||
1535 | wr32(E1000_SYSTIML, 0x00000000); | ||
1536 | wr32(E1000_SYSTIMH, 0xFF800000); | ||
1537 | #endif | ||
1538 | wrfl(); | ||
1539 | timecounter_init(&adapter->clock, | ||
1540 | &adapter->cycles, | ||
1541 | ktime_to_ns(ktime_get_real())); | ||
1542 | |||
1543 | /* | ||
1544 | * Synchronize our NIC clock against system wall clock. NIC | ||
1545 | * time stamp reading requires ~3us per sample, each sample | ||
1546 | * was pretty stable even under load => only require 10 | ||
1547 | * samples for each offset comparison. | ||
1548 | */ | ||
1549 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | ||
1550 | adapter->compare.source = &adapter->clock; | ||
1551 | adapter->compare.target = ktime_get_real; | ||
1552 | adapter->compare.num_samples = 10; | ||
1553 | timecompare_update(&adapter->compare, 0); | ||
1554 | 1652 | ||
1555 | #ifdef DEBUG | ||
1556 | { | ||
1557 | char buffer[160]; | ||
1558 | printk(KERN_DEBUG | ||
1559 | "igb: %s: hw %p initialized timer\n", | ||
1560 | igb_get_time_str(adapter, buffer), | ||
1561 | &adapter->hw); | ||
1562 | } | ||
1563 | #endif | 1653 | #endif |
1564 | |||
1565 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); | 1654 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1566 | /* print bus type/speed/width info */ | 1655 | /* print bus type/speed/width info */ |
1567 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", | 1656 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
1568 | netdev->name, | 1657 | netdev->name, |
1569 | ((hw->bus.speed == e1000_bus_speed_2500) | 1658 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
1570 | ? "2.5Gb/s" : "unknown"), | 1659 | "unknown"), |
1571 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : | 1660 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
1572 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : | 1661 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : |
1573 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : | 1662 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : |
@@ -1594,15 +1683,14 @@ err_eeprom: | |||
1594 | 1683 | ||
1595 | if (hw->flash_address) | 1684 | if (hw->flash_address) |
1596 | iounmap(hw->flash_address); | 1685 | iounmap(hw->flash_address); |
1597 | |||
1598 | igb_free_queues(adapter); | ||
1599 | err_sw_init: | 1686 | err_sw_init: |
1687 | igb_clear_interrupt_scheme(adapter); | ||
1600 | iounmap(hw->hw_addr); | 1688 | iounmap(hw->hw_addr); |
1601 | err_ioremap: | 1689 | err_ioremap: |
1602 | free_netdev(netdev); | 1690 | free_netdev(netdev); |
1603 | err_alloc_etherdev: | 1691 | err_alloc_etherdev: |
1604 | pci_release_selected_regions(pdev, pci_select_bars(pdev, | 1692 | pci_release_selected_regions(pdev, |
1605 | IORESOURCE_MEM)); | 1693 | pci_select_bars(pdev, IORESOURCE_MEM)); |
1606 | err_pci_reg: | 1694 | err_pci_reg: |
1607 | err_dma: | 1695 | err_dma: |
1608 | pci_disable_device(pdev); | 1696 | pci_disable_device(pdev); |
@@ -1647,12 +1735,7 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
1647 | 1735 | ||
1648 | unregister_netdev(netdev); | 1736 | unregister_netdev(netdev); |
1649 | 1737 | ||
1650 | if (!igb_check_reset_block(&adapter->hw)) | 1738 | igb_clear_interrupt_scheme(adapter); |
1651 | igb_reset_phy(&adapter->hw); | ||
1652 | |||
1653 | igb_reset_interrupt_capability(adapter); | ||
1654 | |||
1655 | igb_free_queues(adapter); | ||
1656 | 1739 | ||
1657 | #ifdef CONFIG_PCI_IOV | 1740 | #ifdef CONFIG_PCI_IOV |
1658 | /* reclaim resources allocated to VFs */ | 1741 | /* reclaim resources allocated to VFs */ |
@@ -1668,11 +1751,12 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
1668 | dev_info(&pdev->dev, "IOV Disabled\n"); | 1751 | dev_info(&pdev->dev, "IOV Disabled\n"); |
1669 | } | 1752 | } |
1670 | #endif | 1753 | #endif |
1754 | |||
1671 | iounmap(hw->hw_addr); | 1755 | iounmap(hw->hw_addr); |
1672 | if (hw->flash_address) | 1756 | if (hw->flash_address) |
1673 | iounmap(hw->flash_address); | 1757 | iounmap(hw->flash_address); |
1674 | pci_release_selected_regions(pdev, pci_select_bars(pdev, | 1758 | pci_release_selected_regions(pdev, |
1675 | IORESOURCE_MEM)); | 1759 | pci_select_bars(pdev, IORESOURCE_MEM)); |
1676 | 1760 | ||
1677 | free_netdev(netdev); | 1761 | free_netdev(netdev); |
1678 | 1762 | ||
@@ -1682,6 +1766,160 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
1682 | } | 1766 | } |
1683 | 1767 | ||
1684 | /** | 1768 | /** |
1769 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space | ||
1770 | * @adapter: board private structure to initialize | ||
1771 | * | ||
1772 | * This function initializes the vf specific data storage and then attempts to | ||
1773 | * allocate the VFs. The reason for ordering it this way is because it is much | ||
1774 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | ||
1775 | * the memory for the VFs. | ||
1776 | **/ | ||
1777 | static void __devinit igb_probe_vfs(struct igb_adapter * adapter) | ||
1778 | { | ||
1779 | #ifdef CONFIG_PCI_IOV | ||
1780 | struct pci_dev *pdev = adapter->pdev; | ||
1781 | |||
1782 | if (adapter->vfs_allocated_count > 7) | ||
1783 | adapter->vfs_allocated_count = 7; | ||
1784 | |||
1785 | if (adapter->vfs_allocated_count) { | ||
1786 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | ||
1787 | sizeof(struct vf_data_storage), | ||
1788 | GFP_KERNEL); | ||
1789 | /* if allocation failed then we do not support SR-IOV */ | ||
1790 | if (!adapter->vf_data) { | ||
1791 | adapter->vfs_allocated_count = 0; | ||
1792 | dev_err(&pdev->dev, "Unable to allocate memory for VF " | ||
1793 | "Data Storage\n"); | ||
1794 | } | ||
1795 | } | ||
1796 | |||
1797 | if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) { | ||
1798 | kfree(adapter->vf_data); | ||
1799 | adapter->vf_data = NULL; | ||
1800 | #endif /* CONFIG_PCI_IOV */ | ||
1801 | adapter->vfs_allocated_count = 0; | ||
1802 | #ifdef CONFIG_PCI_IOV | ||
1803 | } else { | ||
1804 | unsigned char mac_addr[ETH_ALEN]; | ||
1805 | int i; | ||
1806 | dev_info(&pdev->dev, "%d vfs allocated\n", | ||
1807 | adapter->vfs_allocated_count); | ||
1808 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | ||
1809 | random_ether_addr(mac_addr); | ||
1810 | igb_set_vf_mac(adapter, i, mac_addr); | ||
1811 | } | ||
1812 | } | ||
1813 | #endif /* CONFIG_PCI_IOV */ | ||
1814 | } | ||
1815 | |||
1816 | |||
1817 | /** | ||
1818 | * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp | ||
1819 | * @adapter: board private structure to initialize | ||
1820 | * | ||
1821 | * igb_init_hw_timer initializes the function pointer and values for the hw | ||
1822 | * timer found in hardware. | ||
1823 | **/ | ||
1824 | static void igb_init_hw_timer(struct igb_adapter *adapter) | ||
1825 | { | ||
1826 | struct e1000_hw *hw = &adapter->hw; | ||
1827 | |||
1828 | switch (hw->mac.type) { | ||
1829 | case e1000_82580: | ||
1830 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | ||
1831 | adapter->cycles.read = igb_read_clock; | ||
1832 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | ||
1833 | adapter->cycles.mult = 1; | ||
1834 | /* | ||
1835 | * The 82580 timesync updates the system timer every 8ns by 8ns | ||
1836 | * and the value cannot be shifted. Instead we need to shift | ||
1837 | * the registers to generate a 64bit timer value. As a result | ||
1838 | * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by | ||
1839 | * 24 in order to generate a larger value for synchronization. | ||
1840 | */ | ||
1841 | adapter->cycles.shift = IGB_82580_TSYNC_SHIFT; | ||
1842 | /* disable system timer temporarily by setting bit 31 */ | ||
1843 | wr32(E1000_TSAUXC, 0x80000000); | ||
1844 | wrfl(); | ||
1845 | |||
1846 | /* Set registers so that rollover occurs soon to test this. */ | ||
1847 | wr32(E1000_SYSTIMR, 0x00000000); | ||
1848 | wr32(E1000_SYSTIML, 0x80000000); | ||
1849 | wr32(E1000_SYSTIMH, 0x000000FF); | ||
1850 | wrfl(); | ||
1851 | |||
1852 | /* enable system timer by clearing bit 31 */ | ||
1853 | wr32(E1000_TSAUXC, 0x0); | ||
1854 | wrfl(); | ||
1855 | |||
1856 | timecounter_init(&adapter->clock, | ||
1857 | &adapter->cycles, | ||
1858 | ktime_to_ns(ktime_get_real())); | ||
1859 | /* | ||
1860 | * Synchronize our NIC clock against system wall clock. NIC | ||
1861 | * time stamp reading requires ~3us per sample, each sample | ||
1862 | * was pretty stable even under load => only require 10 | ||
1863 | * samples for each offset comparison. | ||
1864 | */ | ||
1865 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | ||
1866 | adapter->compare.source = &adapter->clock; | ||
1867 | adapter->compare.target = ktime_get_real; | ||
1868 | adapter->compare.num_samples = 10; | ||
1869 | timecompare_update(&adapter->compare, 0); | ||
1870 | break; | ||
1871 | case e1000_82576: | ||
1872 | /* | ||
1873 | * Initialize hardware timer: we keep it running just in case | ||
1874 | * that some program needs it later on. | ||
1875 | */ | ||
1876 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | ||
1877 | adapter->cycles.read = igb_read_clock; | ||
1878 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | ||
1879 | adapter->cycles.mult = 1; | ||
1880 | /** | ||
1881 | * Scale the NIC clock cycle by a large factor so that | ||
1882 | * relatively small clock corrections can be added or | ||
1883 | * substracted at each clock tick. The drawbacks of a large | ||
1884 | * factor are a) that the clock register overflows more quickly | ||
1885 | * (not such a big deal) and b) that the increment per tick has | ||
1886 | * to fit into 24 bits. As a result we need to use a shift of | ||
1887 | * 19 so we can fit a value of 16 into the TIMINCA register. | ||
1888 | */ | ||
1889 | adapter->cycles.shift = IGB_82576_TSYNC_SHIFT; | ||
1890 | wr32(E1000_TIMINCA, | ||
1891 | (1 << E1000_TIMINCA_16NS_SHIFT) | | ||
1892 | (16 << IGB_82576_TSYNC_SHIFT)); | ||
1893 | |||
1894 | /* Set registers so that rollover occurs soon to test this. */ | ||
1895 | wr32(E1000_SYSTIML, 0x00000000); | ||
1896 | wr32(E1000_SYSTIMH, 0xFF800000); | ||
1897 | wrfl(); | ||
1898 | |||
1899 | timecounter_init(&adapter->clock, | ||
1900 | &adapter->cycles, | ||
1901 | ktime_to_ns(ktime_get_real())); | ||
1902 | /* | ||
1903 | * Synchronize our NIC clock against system wall clock. NIC | ||
1904 | * time stamp reading requires ~3us per sample, each sample | ||
1905 | * was pretty stable even under load => only require 10 | ||
1906 | * samples for each offset comparison. | ||
1907 | */ | ||
1908 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | ||
1909 | adapter->compare.source = &adapter->clock; | ||
1910 | adapter->compare.target = ktime_get_real; | ||
1911 | adapter->compare.num_samples = 10; | ||
1912 | timecompare_update(&adapter->compare, 0); | ||
1913 | break; | ||
1914 | case e1000_82575: | ||
1915 | /* 82575 does not support timesync */ | ||
1916 | default: | ||
1917 | break; | ||
1918 | } | ||
1919 | |||
1920 | } | ||
1921 | |||
1922 | /** | ||
1685 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | 1923 | * igb_sw_init - Initialize general software structures (struct igb_adapter) |
1686 | * @adapter: board private structure to initialize | 1924 | * @adapter: board private structure to initialize |
1687 | * | 1925 | * |
@@ -1699,20 +1937,37 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter) | |||
1699 | 1937 | ||
1700 | adapter->tx_ring_count = IGB_DEFAULT_TXD; | 1938 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
1701 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | 1939 | adapter->rx_ring_count = IGB_DEFAULT_RXD; |
1702 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | 1940 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; |
1703 | adapter->rx_ps_hdr_size = 0; /* disable packet split */ | 1941 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; |
1942 | |||
1704 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | 1943 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
1705 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | 1944 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
1706 | 1945 | ||
1707 | /* This call may decrease the number of queues depending on | 1946 | #ifdef CONFIG_PCI_IOV |
1708 | * interrupt mode. */ | 1947 | if (hw->mac.type == e1000_82576) |
1709 | igb_set_interrupt_capability(adapter); | 1948 | adapter->vfs_allocated_count = max_vfs; |
1949 | |||
1950 | #endif /* CONFIG_PCI_IOV */ | ||
1951 | adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); | ||
1952 | |||
1953 | /* | ||
1954 | * if rss_queues > 4 or vfs are going to be allocated with rss_queues | ||
1955 | * then we should combine the queues into a queue pair in order to | ||
1956 | * conserve interrupts due to limited supply | ||
1957 | */ | ||
1958 | if ((adapter->rss_queues > 4) || | ||
1959 | ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6))) | ||
1960 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | ||
1710 | 1961 | ||
1711 | if (igb_alloc_queues(adapter)) { | 1962 | /* This call may decrease the number of queues */ |
1963 | if (igb_init_interrupt_scheme(adapter)) { | ||
1712 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | 1964 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
1713 | return -ENOMEM; | 1965 | return -ENOMEM; |
1714 | } | 1966 | } |
1715 | 1967 | ||
1968 | igb_init_hw_timer(adapter); | ||
1969 | igb_probe_vfs(adapter); | ||
1970 | |||
1716 | /* Explicitly disable IRQ since the NIC can be in any state. */ | 1971 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
1717 | igb_irq_disable(adapter); | 1972 | igb_irq_disable(adapter); |
1718 | 1973 | ||
@@ -1755,12 +2010,7 @@ static int igb_open(struct net_device *netdev) | |||
1755 | if (err) | 2010 | if (err) |
1756 | goto err_setup_rx; | 2011 | goto err_setup_rx; |
1757 | 2012 | ||
1758 | /* e1000_power_up_phy(adapter); */ | 2013 | igb_power_up_link(adapter); |
1759 | |||
1760 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | ||
1761 | if ((adapter->hw.mng_cookie.status & | ||
1762 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) | ||
1763 | igb_update_mng_vlan(adapter); | ||
1764 | 2014 | ||
1765 | /* before we allocate an interrupt, we must be ready to handle it. | 2015 | /* before we allocate an interrupt, we must be ready to handle it. |
1766 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | 2016 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt |
@@ -1768,10 +2018,6 @@ static int igb_open(struct net_device *netdev) | |||
1768 | * clean_rx handler before we do so. */ | 2018 | * clean_rx handler before we do so. */ |
1769 | igb_configure(adapter); | 2019 | igb_configure(adapter); |
1770 | 2020 | ||
1771 | igb_vmm_control(adapter); | ||
1772 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0); | ||
1773 | igb_set_vmolr(hw, adapter->vfs_allocated_count); | ||
1774 | |||
1775 | err = igb_request_irq(adapter); | 2021 | err = igb_request_irq(adapter); |
1776 | if (err) | 2022 | if (err) |
1777 | goto err_req_irq; | 2023 | goto err_req_irq; |
@@ -1779,24 +2025,34 @@ static int igb_open(struct net_device *netdev) | |||
1779 | /* From here on the code is the same as igb_up() */ | 2025 | /* From here on the code is the same as igb_up() */ |
1780 | clear_bit(__IGB_DOWN, &adapter->state); | 2026 | clear_bit(__IGB_DOWN, &adapter->state); |
1781 | 2027 | ||
1782 | for (i = 0; i < adapter->num_rx_queues; i++) | 2028 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1783 | napi_enable(&adapter->rx_ring[i].napi); | 2029 | struct igb_q_vector *q_vector = adapter->q_vector[i]; |
2030 | napi_enable(&q_vector->napi); | ||
2031 | } | ||
1784 | 2032 | ||
1785 | /* Clear any pending interrupts. */ | 2033 | /* Clear any pending interrupts. */ |
1786 | rd32(E1000_ICR); | 2034 | rd32(E1000_ICR); |
1787 | 2035 | ||
1788 | igb_irq_enable(adapter); | 2036 | igb_irq_enable(adapter); |
1789 | 2037 | ||
2038 | /* notify VFs that reset has been completed */ | ||
2039 | if (adapter->vfs_allocated_count) { | ||
2040 | u32 reg_data = rd32(E1000_CTRL_EXT); | ||
2041 | reg_data |= E1000_CTRL_EXT_PFRSTD; | ||
2042 | wr32(E1000_CTRL_EXT, reg_data); | ||
2043 | } | ||
2044 | |||
1790 | netif_tx_start_all_queues(netdev); | 2045 | netif_tx_start_all_queues(netdev); |
1791 | 2046 | ||
1792 | /* Fire a link status change interrupt to start the watchdog. */ | 2047 | /* start the watchdog. */ |
1793 | wr32(E1000_ICS, E1000_ICS_LSC); | 2048 | hw->mac.get_link_status = 1; |
2049 | schedule_work(&adapter->watchdog_task); | ||
1794 | 2050 | ||
1795 | return 0; | 2051 | return 0; |
1796 | 2052 | ||
1797 | err_req_irq: | 2053 | err_req_irq: |
1798 | igb_release_hw_control(adapter); | 2054 | igb_release_hw_control(adapter); |
1799 | /* e1000_power_down_phy(adapter); */ | 2055 | igb_power_down_link(adapter); |
1800 | igb_free_all_rx_resources(adapter); | 2056 | igb_free_all_rx_resources(adapter); |
1801 | err_setup_rx: | 2057 | err_setup_rx: |
1802 | igb_free_all_tx_resources(adapter); | 2058 | igb_free_all_tx_resources(adapter); |
@@ -1829,28 +2085,18 @@ static int igb_close(struct net_device *netdev) | |||
1829 | igb_free_all_tx_resources(adapter); | 2085 | igb_free_all_tx_resources(adapter); |
1830 | igb_free_all_rx_resources(adapter); | 2086 | igb_free_all_rx_resources(adapter); |
1831 | 2087 | ||
1832 | /* kill manageability vlan ID if supported, but not if a vlan with | ||
1833 | * the same ID is registered on the host OS (let 8021q kill it) */ | ||
1834 | if ((adapter->hw.mng_cookie.status & | ||
1835 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | ||
1836 | !(adapter->vlgrp && | ||
1837 | vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) | ||
1838 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | ||
1839 | |||
1840 | return 0; | 2088 | return 0; |
1841 | } | 2089 | } |
1842 | 2090 | ||
1843 | /** | 2091 | /** |
1844 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | 2092 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) |
1845 | * @adapter: board private structure | ||
1846 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | 2093 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
1847 | * | 2094 | * |
1848 | * Return 0 on success, negative on failure | 2095 | * Return 0 on success, negative on failure |
1849 | **/ | 2096 | **/ |
1850 | int igb_setup_tx_resources(struct igb_adapter *adapter, | 2097 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
1851 | struct igb_ring *tx_ring) | ||
1852 | { | 2098 | { |
1853 | struct pci_dev *pdev = adapter->pdev; | 2099 | struct pci_dev *pdev = tx_ring->pdev; |
1854 | int size; | 2100 | int size; |
1855 | 2101 | ||
1856 | size = sizeof(struct igb_buffer) * tx_ring->count; | 2102 | size = sizeof(struct igb_buffer) * tx_ring->count; |
@@ -1863,20 +2109,20 @@ int igb_setup_tx_resources(struct igb_adapter *adapter, | |||
1863 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); | 2109 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
1864 | tx_ring->size = ALIGN(tx_ring->size, 4096); | 2110 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1865 | 2111 | ||
1866 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, | 2112 | tx_ring->desc = pci_alloc_consistent(pdev, |
2113 | tx_ring->size, | ||
1867 | &tx_ring->dma); | 2114 | &tx_ring->dma); |
1868 | 2115 | ||
1869 | if (!tx_ring->desc) | 2116 | if (!tx_ring->desc) |
1870 | goto err; | 2117 | goto err; |
1871 | 2118 | ||
1872 | tx_ring->adapter = adapter; | ||
1873 | tx_ring->next_to_use = 0; | 2119 | tx_ring->next_to_use = 0; |
1874 | tx_ring->next_to_clean = 0; | 2120 | tx_ring->next_to_clean = 0; |
1875 | return 0; | 2121 | return 0; |
1876 | 2122 | ||
1877 | err: | 2123 | err: |
1878 | vfree(tx_ring->buffer_info); | 2124 | vfree(tx_ring->buffer_info); |
1879 | dev_err(&adapter->pdev->dev, | 2125 | dev_err(&pdev->dev, |
1880 | "Unable to allocate memory for the transmit descriptor ring\n"); | 2126 | "Unable to allocate memory for the transmit descriptor ring\n"); |
1881 | return -ENOMEM; | 2127 | return -ENOMEM; |
1882 | } | 2128 | } |
@@ -1890,71 +2136,38 @@ err: | |||
1890 | **/ | 2136 | **/ |
1891 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | 2137 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) |
1892 | { | 2138 | { |
2139 | struct pci_dev *pdev = adapter->pdev; | ||
1893 | int i, err = 0; | 2140 | int i, err = 0; |
1894 | int r_idx; | ||
1895 | 2141 | ||
1896 | for (i = 0; i < adapter->num_tx_queues; i++) { | 2142 | for (i = 0; i < adapter->num_tx_queues; i++) { |
1897 | err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); | 2143 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
1898 | if (err) { | 2144 | if (err) { |
1899 | dev_err(&adapter->pdev->dev, | 2145 | dev_err(&pdev->dev, |
1900 | "Allocation for Tx Queue %u failed\n", i); | 2146 | "Allocation for Tx Queue %u failed\n", i); |
1901 | for (i--; i >= 0; i--) | 2147 | for (i--; i >= 0; i--) |
1902 | igb_free_tx_resources(&adapter->tx_ring[i]); | 2148 | igb_free_tx_resources(adapter->tx_ring[i]); |
1903 | break; | 2149 | break; |
1904 | } | 2150 | } |
1905 | } | 2151 | } |
1906 | 2152 | ||
1907 | for (i = 0; i < IGB_MAX_TX_QUEUES; i++) { | 2153 | for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) { |
1908 | r_idx = i % adapter->num_tx_queues; | 2154 | int r_idx = i % adapter->num_tx_queues; |
1909 | adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; | 2155 | adapter->multi_tx_table[i] = adapter->tx_ring[r_idx]; |
1910 | } | 2156 | } |
1911 | return err; | 2157 | return err; |
1912 | } | 2158 | } |
1913 | 2159 | ||
1914 | /** | 2160 | /** |
1915 | * igb_configure_tx - Configure transmit Unit after Reset | 2161 | * igb_setup_tctl - configure the transmit control registers |
1916 | * @adapter: board private structure | 2162 | * @adapter: Board private structure |
1917 | * | ||
1918 | * Configure the Tx unit of the MAC after a reset. | ||
1919 | **/ | 2163 | **/ |
1920 | static void igb_configure_tx(struct igb_adapter *adapter) | 2164 | void igb_setup_tctl(struct igb_adapter *adapter) |
1921 | { | 2165 | { |
1922 | u64 tdba; | ||
1923 | struct e1000_hw *hw = &adapter->hw; | 2166 | struct e1000_hw *hw = &adapter->hw; |
1924 | u32 tctl; | 2167 | u32 tctl; |
1925 | u32 txdctl, txctrl; | ||
1926 | int i, j; | ||
1927 | |||
1928 | for (i = 0; i < adapter->num_tx_queues; i++) { | ||
1929 | struct igb_ring *ring = &adapter->tx_ring[i]; | ||
1930 | j = ring->reg_idx; | ||
1931 | wr32(E1000_TDLEN(j), | ||
1932 | ring->count * sizeof(union e1000_adv_tx_desc)); | ||
1933 | tdba = ring->dma; | ||
1934 | wr32(E1000_TDBAL(j), | ||
1935 | tdba & 0x00000000ffffffffULL); | ||
1936 | wr32(E1000_TDBAH(j), tdba >> 32); | ||
1937 | |||
1938 | ring->head = E1000_TDH(j); | ||
1939 | ring->tail = E1000_TDT(j); | ||
1940 | writel(0, hw->hw_addr + ring->tail); | ||
1941 | writel(0, hw->hw_addr + ring->head); | ||
1942 | txdctl = rd32(E1000_TXDCTL(j)); | ||
1943 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | ||
1944 | wr32(E1000_TXDCTL(j), txdctl); | ||
1945 | |||
1946 | /* Turn off Relaxed Ordering on head write-backs. The | ||
1947 | * writebacks MUST be delivered in order or it will | ||
1948 | * completely screw up our bookeeping. | ||
1949 | */ | ||
1950 | txctrl = rd32(E1000_DCA_TXCTRL(j)); | ||
1951 | txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; | ||
1952 | wr32(E1000_DCA_TXCTRL(j), txctrl); | ||
1953 | } | ||
1954 | 2168 | ||
1955 | /* disable queue 0 to prevent tail bump w/o re-configuration */ | 2169 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
1956 | if (adapter->vfs_allocated_count) | 2170 | wr32(E1000_TXDCTL(0), 0); |
1957 | wr32(E1000_TXDCTL(0), 0); | ||
1958 | 2171 | ||
1959 | /* Program the Transmit Control Register */ | 2172 | /* Program the Transmit Control Register */ |
1960 | tctl = rd32(E1000_TCTL); | 2173 | tctl = rd32(E1000_TCTL); |
@@ -1964,9 +2177,6 @@ static void igb_configure_tx(struct igb_adapter *adapter) | |||
1964 | 2177 | ||
1965 | igb_config_collision_dist(hw); | 2178 | igb_config_collision_dist(hw); |
1966 | 2179 | ||
1967 | /* Setup Transmit Descriptor Settings for eop descriptor */ | ||
1968 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS; | ||
1969 | |||
1970 | /* Enable transmits */ | 2180 | /* Enable transmits */ |
1971 | tctl |= E1000_TCTL_EN; | 2181 | tctl |= E1000_TCTL_EN; |
1972 | 2182 | ||
@@ -1974,16 +2184,69 @@ static void igb_configure_tx(struct igb_adapter *adapter) | |||
1974 | } | 2184 | } |
1975 | 2185 | ||
1976 | /** | 2186 | /** |
1977 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | 2187 | * igb_configure_tx_ring - Configure transmit ring after Reset |
1978 | * @adapter: board private structure | 2188 | * @adapter: board private structure |
2189 | * @ring: tx ring to configure | ||
2190 | * | ||
2191 | * Configure a transmit ring after a reset. | ||
2192 | **/ | ||
2193 | void igb_configure_tx_ring(struct igb_adapter *adapter, | ||
2194 | struct igb_ring *ring) | ||
2195 | { | ||
2196 | struct e1000_hw *hw = &adapter->hw; | ||
2197 | u32 txdctl; | ||
2198 | u64 tdba = ring->dma; | ||
2199 | int reg_idx = ring->reg_idx; | ||
2200 | |||
2201 | /* disable the queue */ | ||
2202 | txdctl = rd32(E1000_TXDCTL(reg_idx)); | ||
2203 | wr32(E1000_TXDCTL(reg_idx), | ||
2204 | txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); | ||
2205 | wrfl(); | ||
2206 | mdelay(10); | ||
2207 | |||
2208 | wr32(E1000_TDLEN(reg_idx), | ||
2209 | ring->count * sizeof(union e1000_adv_tx_desc)); | ||
2210 | wr32(E1000_TDBAL(reg_idx), | ||
2211 | tdba & 0x00000000ffffffffULL); | ||
2212 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); | ||
2213 | |||
2214 | ring->head = hw->hw_addr + E1000_TDH(reg_idx); | ||
2215 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); | ||
2216 | writel(0, ring->head); | ||
2217 | writel(0, ring->tail); | ||
2218 | |||
2219 | txdctl |= IGB_TX_PTHRESH; | ||
2220 | txdctl |= IGB_TX_HTHRESH << 8; | ||
2221 | txdctl |= IGB_TX_WTHRESH << 16; | ||
2222 | |||
2223 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | ||
2224 | wr32(E1000_TXDCTL(reg_idx), txdctl); | ||
2225 | } | ||
2226 | |||
2227 | /** | ||
2228 | * igb_configure_tx - Configure transmit Unit after Reset | ||
2229 | * @adapter: board private structure | ||
2230 | * | ||
2231 | * Configure the Tx unit of the MAC after a reset. | ||
2232 | **/ | ||
2233 | static void igb_configure_tx(struct igb_adapter *adapter) | ||
2234 | { | ||
2235 | int i; | ||
2236 | |||
2237 | for (i = 0; i < adapter->num_tx_queues; i++) | ||
2238 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); | ||
2239 | } | ||
2240 | |||
2241 | /** | ||
2242 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | ||
1979 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | 2243 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
1980 | * | 2244 | * |
1981 | * Returns 0 on success, negative on failure | 2245 | * Returns 0 on success, negative on failure |
1982 | **/ | 2246 | **/ |
1983 | int igb_setup_rx_resources(struct igb_adapter *adapter, | 2247 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
1984 | struct igb_ring *rx_ring) | ||
1985 | { | 2248 | { |
1986 | struct pci_dev *pdev = adapter->pdev; | 2249 | struct pci_dev *pdev = rx_ring->pdev; |
1987 | int size, desc_len; | 2250 | int size, desc_len; |
1988 | 2251 | ||
1989 | size = sizeof(struct igb_buffer) * rx_ring->count; | 2252 | size = sizeof(struct igb_buffer) * rx_ring->count; |
@@ -2007,13 +2270,12 @@ int igb_setup_rx_resources(struct igb_adapter *adapter, | |||
2007 | rx_ring->next_to_clean = 0; | 2270 | rx_ring->next_to_clean = 0; |
2008 | rx_ring->next_to_use = 0; | 2271 | rx_ring->next_to_use = 0; |
2009 | 2272 | ||
2010 | rx_ring->adapter = adapter; | ||
2011 | |||
2012 | return 0; | 2273 | return 0; |
2013 | 2274 | ||
2014 | err: | 2275 | err: |
2015 | vfree(rx_ring->buffer_info); | 2276 | vfree(rx_ring->buffer_info); |
2016 | dev_err(&adapter->pdev->dev, "Unable to allocate memory for " | 2277 | rx_ring->buffer_info = NULL; |
2278 | dev_err(&pdev->dev, "Unable to allocate memory for " | ||
2017 | "the receive descriptor ring\n"); | 2279 | "the receive descriptor ring\n"); |
2018 | return -ENOMEM; | 2280 | return -ENOMEM; |
2019 | } | 2281 | } |
@@ -2027,15 +2289,16 @@ err: | |||
2027 | **/ | 2289 | **/ |
2028 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | 2290 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) |
2029 | { | 2291 | { |
2292 | struct pci_dev *pdev = adapter->pdev; | ||
2030 | int i, err = 0; | 2293 | int i, err = 0; |
2031 | 2294 | ||
2032 | for (i = 0; i < adapter->num_rx_queues; i++) { | 2295 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2033 | err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]); | 2296 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
2034 | if (err) { | 2297 | if (err) { |
2035 | dev_err(&adapter->pdev->dev, | 2298 | dev_err(&pdev->dev, |
2036 | "Allocation for Rx Queue %u failed\n", i); | 2299 | "Allocation for Rx Queue %u failed\n", i); |
2037 | for (i--; i >= 0; i--) | 2300 | for (i--; i >= 0; i--) |
2038 | igb_free_rx_resources(&adapter->rx_ring[i]); | 2301 | igb_free_rx_resources(adapter->rx_ring[i]); |
2039 | break; | 2302 | break; |
2040 | } | 2303 | } |
2041 | } | 2304 | } |
@@ -2044,15 +2307,122 @@ static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |||
2044 | } | 2307 | } |
2045 | 2308 | ||
2046 | /** | 2309 | /** |
2310 | * igb_setup_mrqc - configure the multiple receive queue control registers | ||
2311 | * @adapter: Board private structure | ||
2312 | **/ | ||
2313 | static void igb_setup_mrqc(struct igb_adapter *adapter) | ||
2314 | { | ||
2315 | struct e1000_hw *hw = &adapter->hw; | ||
2316 | u32 mrqc, rxcsum; | ||
2317 | u32 j, num_rx_queues, shift = 0, shift2 = 0; | ||
2318 | union e1000_reta { | ||
2319 | u32 dword; | ||
2320 | u8 bytes[4]; | ||
2321 | } reta; | ||
2322 | static const u8 rsshash[40] = { | ||
2323 | 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, | ||
2324 | 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, | ||
2325 | 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, | ||
2326 | 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa }; | ||
2327 | |||
2328 | /* Fill out hash function seeds */ | ||
2329 | for (j = 0; j < 10; j++) { | ||
2330 | u32 rsskey = rsshash[(j * 4)]; | ||
2331 | rsskey |= rsshash[(j * 4) + 1] << 8; | ||
2332 | rsskey |= rsshash[(j * 4) + 2] << 16; | ||
2333 | rsskey |= rsshash[(j * 4) + 3] << 24; | ||
2334 | array_wr32(E1000_RSSRK(0), j, rsskey); | ||
2335 | } | ||
2336 | |||
2337 | num_rx_queues = adapter->rss_queues; | ||
2338 | |||
2339 | if (adapter->vfs_allocated_count) { | ||
2340 | /* 82575 and 82576 supports 2 RSS queues for VMDq */ | ||
2341 | switch (hw->mac.type) { | ||
2342 | case e1000_82580: | ||
2343 | num_rx_queues = 1; | ||
2344 | shift = 0; | ||
2345 | break; | ||
2346 | case e1000_82576: | ||
2347 | shift = 3; | ||
2348 | num_rx_queues = 2; | ||
2349 | break; | ||
2350 | case e1000_82575: | ||
2351 | shift = 2; | ||
2352 | shift2 = 6; | ||
2353 | default: | ||
2354 | break; | ||
2355 | } | ||
2356 | } else { | ||
2357 | if (hw->mac.type == e1000_82575) | ||
2358 | shift = 6; | ||
2359 | } | ||
2360 | |||
2361 | for (j = 0; j < (32 * 4); j++) { | ||
2362 | reta.bytes[j & 3] = (j % num_rx_queues) << shift; | ||
2363 | if (shift2) | ||
2364 | reta.bytes[j & 3] |= num_rx_queues << shift2; | ||
2365 | if ((j & 3) == 3) | ||
2366 | wr32(E1000_RETA(j >> 2), reta.dword); | ||
2367 | } | ||
2368 | |||
2369 | /* | ||
2370 | * Disable raw packet checksumming so that RSS hash is placed in | ||
2371 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum | ||
2372 | * offloads as they are enabled by default | ||
2373 | */ | ||
2374 | rxcsum = rd32(E1000_RXCSUM); | ||
2375 | rxcsum |= E1000_RXCSUM_PCSD; | ||
2376 | |||
2377 | if (adapter->hw.mac.type >= e1000_82576) | ||
2378 | /* Enable Receive Checksum Offload for SCTP */ | ||
2379 | rxcsum |= E1000_RXCSUM_CRCOFL; | ||
2380 | |||
2381 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | ||
2382 | wr32(E1000_RXCSUM, rxcsum); | ||
2383 | |||
2384 | /* If VMDq is enabled then we set the appropriate mode for that, else | ||
2385 | * we default to RSS so that an RSS hash is calculated per packet even | ||
2386 | * if we are only using one queue */ | ||
2387 | if (adapter->vfs_allocated_count) { | ||
2388 | if (hw->mac.type > e1000_82575) { | ||
2389 | /* Set the default pool for the PF's first queue */ | ||
2390 | u32 vtctl = rd32(E1000_VT_CTL); | ||
2391 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | ||
2392 | E1000_VT_CTL_DISABLE_DEF_POOL); | ||
2393 | vtctl |= adapter->vfs_allocated_count << | ||
2394 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | ||
2395 | wr32(E1000_VT_CTL, vtctl); | ||
2396 | } | ||
2397 | if (adapter->rss_queues > 1) | ||
2398 | mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; | ||
2399 | else | ||
2400 | mrqc = E1000_MRQC_ENABLE_VMDQ; | ||
2401 | } else { | ||
2402 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | ||
2403 | } | ||
2404 | igb_vmm_control(adapter); | ||
2405 | |||
2406 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | ||
2407 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | ||
2408 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | ||
2409 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | ||
2410 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | ||
2411 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | ||
2412 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | ||
2413 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | ||
2414 | |||
2415 | wr32(E1000_MRQC, mrqc); | ||
2416 | } | ||
2417 | |||
2418 | /** | ||
2047 | * igb_setup_rctl - configure the receive control registers | 2419 | * igb_setup_rctl - configure the receive control registers |
2048 | * @adapter: Board private structure | 2420 | * @adapter: Board private structure |
2049 | **/ | 2421 | **/ |
2050 | static void igb_setup_rctl(struct igb_adapter *adapter) | 2422 | void igb_setup_rctl(struct igb_adapter *adapter) |
2051 | { | 2423 | { |
2052 | struct e1000_hw *hw = &adapter->hw; | 2424 | struct e1000_hw *hw = &adapter->hw; |
2053 | u32 rctl; | 2425 | u32 rctl; |
2054 | u32 srrctl = 0; | ||
2055 | int i; | ||
2056 | 2426 | ||
2057 | rctl = rd32(E1000_RCTL); | 2427 | rctl = rd32(E1000_RCTL); |
2058 | 2428 | ||
@@ -2069,75 +2439,45 @@ static void igb_setup_rctl(struct igb_adapter *adapter) | |||
2069 | */ | 2439 | */ |
2070 | rctl |= E1000_RCTL_SECRC; | 2440 | rctl |= E1000_RCTL_SECRC; |
2071 | 2441 | ||
2072 | /* | 2442 | /* disable store bad packets and clear size bits. */ |
2073 | * disable store bad packets and clear size bits. | ||
2074 | */ | ||
2075 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); | 2443 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
2076 | 2444 | ||
2077 | /* enable LPE when to prevent packets larger than max_frame_size */ | 2445 | /* enable LPE to prevent packets larger than max_frame_size */ |
2078 | rctl |= E1000_RCTL_LPE; | 2446 | rctl |= E1000_RCTL_LPE; |
2079 | 2447 | ||
2080 | /* Setup buffer sizes */ | 2448 | /* disable queue 0 to prevent tail write w/o re-config */ |
2081 | switch (adapter->rx_buffer_len) { | 2449 | wr32(E1000_RXDCTL(0), 0); |
2082 | case IGB_RXBUFFER_256: | ||
2083 | rctl |= E1000_RCTL_SZ_256; | ||
2084 | break; | ||
2085 | case IGB_RXBUFFER_512: | ||
2086 | rctl |= E1000_RCTL_SZ_512; | ||
2087 | break; | ||
2088 | default: | ||
2089 | srrctl = ALIGN(adapter->rx_buffer_len, 1024) | ||
2090 | >> E1000_SRRCTL_BSIZEPKT_SHIFT; | ||
2091 | break; | ||
2092 | } | ||
2093 | |||
2094 | /* 82575 and greater support packet-split where the protocol | ||
2095 | * header is placed in skb->data and the packet data is | ||
2096 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | ||
2097 | * In the case of a non-split, skb->data is linearly filled, | ||
2098 | * followed by the page buffers. Therefore, skb->data is | ||
2099 | * sized to hold the largest protocol header. | ||
2100 | */ | ||
2101 | /* allocations using alloc_page take too long for regular MTU | ||
2102 | * so only enable packet split for jumbo frames */ | ||
2103 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | ||
2104 | adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; | ||
2105 | srrctl |= adapter->rx_ps_hdr_size << | ||
2106 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; | ||
2107 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | ||
2108 | } else { | ||
2109 | adapter->rx_ps_hdr_size = 0; | ||
2110 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | ||
2111 | } | ||
2112 | 2450 | ||
2113 | /* Attention!!! For SR-IOV PF driver operations you must enable | 2451 | /* Attention!!! For SR-IOV PF driver operations you must enable |
2114 | * queue drop for all VF and PF queues to prevent head of line blocking | 2452 | * queue drop for all VF and PF queues to prevent head of line blocking |
2115 | * if an un-trusted VF does not provide descriptors to hardware. | 2453 | * if an un-trusted VF does not provide descriptors to hardware. |
2116 | */ | 2454 | */ |
2117 | if (adapter->vfs_allocated_count) { | 2455 | if (adapter->vfs_allocated_count) { |
2118 | u32 vmolr; | ||
2119 | |||
2120 | /* set all queue drop enable bits */ | 2456 | /* set all queue drop enable bits */ |
2121 | wr32(E1000_QDE, ALL_QUEUES); | 2457 | wr32(E1000_QDE, ALL_QUEUES); |
2122 | srrctl |= E1000_SRRCTL_DROP_EN; | 2458 | } |
2123 | 2459 | ||
2124 | /* disable queue 0 to prevent tail write w/o re-config */ | 2460 | wr32(E1000_RCTL, rctl); |
2125 | wr32(E1000_RXDCTL(0), 0); | 2461 | } |
2126 | 2462 | ||
2127 | vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count)); | 2463 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
2128 | if (rctl & E1000_RCTL_LPE) | 2464 | int vfn) |
2129 | vmolr |= E1000_VMOLR_LPE; | 2465 | { |
2130 | if (adapter->num_rx_queues > 1) | 2466 | struct e1000_hw *hw = &adapter->hw; |
2131 | vmolr |= E1000_VMOLR_RSSE; | 2467 | u32 vmolr; |
2132 | wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr); | ||
2133 | } | ||
2134 | 2468 | ||
2135 | for (i = 0; i < adapter->num_rx_queues; i++) { | 2469 | /* if it isn't the PF check to see if VFs are enabled and |
2136 | int j = adapter->rx_ring[i].reg_idx; | 2470 | * increase the size to support vlan tags */ |
2137 | wr32(E1000_SRRCTL(j), srrctl); | 2471 | if (vfn < adapter->vfs_allocated_count && |
2138 | } | 2472 | adapter->vf_data[vfn].vlans_enabled) |
2473 | size += VLAN_TAG_SIZE; | ||
2139 | 2474 | ||
2140 | wr32(E1000_RCTL, rctl); | 2475 | vmolr = rd32(E1000_VMOLR(vfn)); |
2476 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | ||
2477 | vmolr |= size | E1000_VMOLR_LPE; | ||
2478 | wr32(E1000_VMOLR(vfn), vmolr); | ||
2479 | |||
2480 | return 0; | ||
2141 | } | 2481 | } |
2142 | 2482 | ||
2143 | /** | 2483 | /** |
@@ -2159,33 +2499,114 @@ static void igb_rlpml_set(struct igb_adapter *adapter) | |||
2159 | * size and set the VMOLR RLPML to the size we need */ | 2499 | * size and set the VMOLR RLPML to the size we need */ |
2160 | if (pf_id) { | 2500 | if (pf_id) { |
2161 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | 2501 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); |
2162 | max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE; | 2502 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
2163 | } | 2503 | } |
2164 | 2504 | ||
2165 | wr32(E1000_RLPML, max_frame_size); | 2505 | wr32(E1000_RLPML, max_frame_size); |
2166 | } | 2506 | } |
2167 | 2507 | ||
2508 | static inline void igb_set_vmolr(struct igb_adapter *adapter, | ||
2509 | int vfn, bool aupe) | ||
2510 | { | ||
2511 | struct e1000_hw *hw = &adapter->hw; | ||
2512 | u32 vmolr; | ||
2513 | |||
2514 | /* | ||
2515 | * This register exists only on 82576 and newer so if we are older then | ||
2516 | * we should exit and do nothing | ||
2517 | */ | ||
2518 | if (hw->mac.type < e1000_82576) | ||
2519 | return; | ||
2520 | |||
2521 | vmolr = rd32(E1000_VMOLR(vfn)); | ||
2522 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ | ||
2523 | if (aupe) | ||
2524 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ | ||
2525 | else | ||
2526 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | ||
2527 | |||
2528 | /* clear all bits that might not be set */ | ||
2529 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | ||
2530 | |||
2531 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) | ||
2532 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ | ||
2533 | /* | ||
2534 | * for VMDq only allow the VFs and pool 0 to accept broadcast and | ||
2535 | * multicast packets | ||
2536 | */ | ||
2537 | if (vfn <= adapter->vfs_allocated_count) | ||
2538 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ | ||
2539 | |||
2540 | wr32(E1000_VMOLR(vfn), vmolr); | ||
2541 | } | ||
2542 | |||
2168 | /** | 2543 | /** |
2169 | * igb_configure_vt_default_pool - Configure VT default pool | 2544 | * igb_configure_rx_ring - Configure a receive ring after Reset |
2170 | * @adapter: board private structure | 2545 | * @adapter: board private structure |
2546 | * @ring: receive ring to be configured | ||
2171 | * | 2547 | * |
2172 | * Configure the default pool | 2548 | * Configure the Rx unit of the MAC after a reset. |
2173 | **/ | 2549 | **/ |
2174 | static void igb_configure_vt_default_pool(struct igb_adapter *adapter) | 2550 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
2551 | struct igb_ring *ring) | ||
2175 | { | 2552 | { |
2176 | struct e1000_hw *hw = &adapter->hw; | 2553 | struct e1000_hw *hw = &adapter->hw; |
2177 | u16 pf_id = adapter->vfs_allocated_count; | 2554 | u64 rdba = ring->dma; |
2178 | u32 vtctl; | 2555 | int reg_idx = ring->reg_idx; |
2556 | u32 srrctl, rxdctl; | ||
2557 | |||
2558 | /* disable the queue */ | ||
2559 | rxdctl = rd32(E1000_RXDCTL(reg_idx)); | ||
2560 | wr32(E1000_RXDCTL(reg_idx), | ||
2561 | rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE); | ||
2562 | |||
2563 | /* Set DMA base address registers */ | ||
2564 | wr32(E1000_RDBAL(reg_idx), | ||
2565 | rdba & 0x00000000ffffffffULL); | ||
2566 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | ||
2567 | wr32(E1000_RDLEN(reg_idx), | ||
2568 | ring->count * sizeof(union e1000_adv_rx_desc)); | ||
2569 | |||
2570 | /* initialize head and tail */ | ||
2571 | ring->head = hw->hw_addr + E1000_RDH(reg_idx); | ||
2572 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); | ||
2573 | writel(0, ring->head); | ||
2574 | writel(0, ring->tail); | ||
2575 | |||
2576 | /* set descriptor configuration */ | ||
2577 | if (ring->rx_buffer_len < IGB_RXBUFFER_1024) { | ||
2578 | srrctl = ALIGN(ring->rx_buffer_len, 64) << | ||
2579 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; | ||
2580 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 | ||
2581 | srrctl |= IGB_RXBUFFER_16384 >> | ||
2582 | E1000_SRRCTL_BSIZEPKT_SHIFT; | ||
2583 | #else | ||
2584 | srrctl |= (PAGE_SIZE / 2) >> | ||
2585 | E1000_SRRCTL_BSIZEPKT_SHIFT; | ||
2586 | #endif | ||
2587 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | ||
2588 | } else { | ||
2589 | srrctl = ALIGN(ring->rx_buffer_len, 1024) >> | ||
2590 | E1000_SRRCTL_BSIZEPKT_SHIFT; | ||
2591 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | ||
2592 | } | ||
2593 | /* Only set Drop Enable if we are supporting multiple queues */ | ||
2594 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | ||
2595 | srrctl |= E1000_SRRCTL_DROP_EN; | ||
2179 | 2596 | ||
2180 | /* not in sr-iov mode - do nothing */ | 2597 | wr32(E1000_SRRCTL(reg_idx), srrctl); |
2181 | if (!pf_id) | ||
2182 | return; | ||
2183 | 2598 | ||
2184 | vtctl = rd32(E1000_VT_CTL); | 2599 | /* set filtering for VMDQ pools */ |
2185 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | 2600 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
2186 | E1000_VT_CTL_DISABLE_DEF_POOL); | 2601 | |
2187 | vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT; | 2602 | /* enable receive descriptor fetching */ |
2188 | wr32(E1000_VT_CTL, vtctl); | 2603 | rxdctl = rd32(E1000_RXDCTL(reg_idx)); |
2604 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | ||
2605 | rxdctl &= 0xFFF00000; | ||
2606 | rxdctl |= IGB_RX_PTHRESH; | ||
2607 | rxdctl |= IGB_RX_HTHRESH << 8; | ||
2608 | rxdctl |= IGB_RX_WTHRESH << 16; | ||
2609 | wr32(E1000_RXDCTL(reg_idx), rxdctl); | ||
2189 | } | 2610 | } |
2190 | 2611 | ||
2191 | /** | 2612 | /** |
@@ -2196,112 +2617,19 @@ static void igb_configure_vt_default_pool(struct igb_adapter *adapter) | |||
2196 | **/ | 2617 | **/ |
2197 | static void igb_configure_rx(struct igb_adapter *adapter) | 2618 | static void igb_configure_rx(struct igb_adapter *adapter) |
2198 | { | 2619 | { |
2199 | u64 rdba; | ||
2200 | struct e1000_hw *hw = &adapter->hw; | ||
2201 | u32 rctl, rxcsum; | ||
2202 | u32 rxdctl; | ||
2203 | int i; | 2620 | int i; |
2204 | 2621 | ||
2205 | /* disable receives while setting up the descriptors */ | 2622 | /* set UTA to appropriate mode */ |
2206 | rctl = rd32(E1000_RCTL); | 2623 | igb_set_uta(adapter); |
2207 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | ||
2208 | wrfl(); | ||
2209 | mdelay(10); | ||
2210 | 2624 | ||
2211 | if (adapter->itr_setting > 3) | 2625 | /* set the correct pool for the PF default MAC address in entry 0 */ |
2212 | wr32(E1000_ITR, adapter->itr); | 2626 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, |
2627 | adapter->vfs_allocated_count); | ||
2213 | 2628 | ||
2214 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | 2629 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
2215 | * the Base and Length of the Rx Descriptor Ring */ | 2630 | * the Base and Length of the Rx Descriptor Ring */ |
2216 | for (i = 0; i < adapter->num_rx_queues; i++) { | 2631 | for (i = 0; i < adapter->num_rx_queues; i++) |
2217 | struct igb_ring *ring = &adapter->rx_ring[i]; | 2632 | igb_configure_rx_ring(adapter, adapter->rx_ring[i]); |
2218 | int j = ring->reg_idx; | ||
2219 | rdba = ring->dma; | ||
2220 | wr32(E1000_RDBAL(j), | ||
2221 | rdba & 0x00000000ffffffffULL); | ||
2222 | wr32(E1000_RDBAH(j), rdba >> 32); | ||
2223 | wr32(E1000_RDLEN(j), | ||
2224 | ring->count * sizeof(union e1000_adv_rx_desc)); | ||
2225 | |||
2226 | ring->head = E1000_RDH(j); | ||
2227 | ring->tail = E1000_RDT(j); | ||
2228 | writel(0, hw->hw_addr + ring->tail); | ||
2229 | writel(0, hw->hw_addr + ring->head); | ||
2230 | |||
2231 | rxdctl = rd32(E1000_RXDCTL(j)); | ||
2232 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | ||
2233 | rxdctl &= 0xFFF00000; | ||
2234 | rxdctl |= IGB_RX_PTHRESH; | ||
2235 | rxdctl |= IGB_RX_HTHRESH << 8; | ||
2236 | rxdctl |= IGB_RX_WTHRESH << 16; | ||
2237 | wr32(E1000_RXDCTL(j), rxdctl); | ||
2238 | } | ||
2239 | |||
2240 | if (adapter->num_rx_queues > 1) { | ||
2241 | u32 random[10]; | ||
2242 | u32 mrqc; | ||
2243 | u32 j, shift; | ||
2244 | union e1000_reta { | ||
2245 | u32 dword; | ||
2246 | u8 bytes[4]; | ||
2247 | } reta; | ||
2248 | |||
2249 | get_random_bytes(&random[0], 40); | ||
2250 | |||
2251 | if (hw->mac.type >= e1000_82576) | ||
2252 | shift = 0; | ||
2253 | else | ||
2254 | shift = 6; | ||
2255 | for (j = 0; j < (32 * 4); j++) { | ||
2256 | reta.bytes[j & 3] = | ||
2257 | adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift; | ||
2258 | if ((j & 3) == 3) | ||
2259 | writel(reta.dword, | ||
2260 | hw->hw_addr + E1000_RETA(0) + (j & ~3)); | ||
2261 | } | ||
2262 | if (adapter->vfs_allocated_count) | ||
2263 | mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; | ||
2264 | else | ||
2265 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | ||
2266 | |||
2267 | /* Fill out hash function seeds */ | ||
2268 | for (j = 0; j < 10; j++) | ||
2269 | array_wr32(E1000_RSSRK(0), j, random[j]); | ||
2270 | |||
2271 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | ||
2272 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | ||
2273 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | ||
2274 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | ||
2275 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | ||
2276 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | ||
2277 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | ||
2278 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | ||
2279 | |||
2280 | wr32(E1000_MRQC, mrqc); | ||
2281 | } else if (adapter->vfs_allocated_count) { | ||
2282 | /* Enable multi-queue for sr-iov */ | ||
2283 | wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ); | ||
2284 | } | ||
2285 | |||
2286 | /* Enable Receive Checksum Offload for TCP and UDP */ | ||
2287 | rxcsum = rd32(E1000_RXCSUM); | ||
2288 | /* Disable raw packet checksumming */ | ||
2289 | rxcsum |= E1000_RXCSUM_PCSD; | ||
2290 | |||
2291 | if (adapter->hw.mac.type == e1000_82576) | ||
2292 | /* Enable Receive Checksum Offload for SCTP */ | ||
2293 | rxcsum |= E1000_RXCSUM_CRCOFL; | ||
2294 | |||
2295 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | ||
2296 | wr32(E1000_RXCSUM, rxcsum); | ||
2297 | |||
2298 | /* Set the default pool for the PF's first queue */ | ||
2299 | igb_configure_vt_default_pool(adapter); | ||
2300 | |||
2301 | igb_rlpml_set(adapter); | ||
2302 | |||
2303 | /* Enable Receives */ | ||
2304 | wr32(E1000_RCTL, rctl); | ||
2305 | } | 2633 | } |
2306 | 2634 | ||
2307 | /** | 2635 | /** |
@@ -2312,14 +2640,17 @@ static void igb_configure_rx(struct igb_adapter *adapter) | |||
2312 | **/ | 2640 | **/ |
2313 | void igb_free_tx_resources(struct igb_ring *tx_ring) | 2641 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
2314 | { | 2642 | { |
2315 | struct pci_dev *pdev = tx_ring->adapter->pdev; | ||
2316 | |||
2317 | igb_clean_tx_ring(tx_ring); | 2643 | igb_clean_tx_ring(tx_ring); |
2318 | 2644 | ||
2319 | vfree(tx_ring->buffer_info); | 2645 | vfree(tx_ring->buffer_info); |
2320 | tx_ring->buffer_info = NULL; | 2646 | tx_ring->buffer_info = NULL; |
2321 | 2647 | ||
2322 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | 2648 | /* if not set, then don't free */ |
2649 | if (!tx_ring->desc) | ||
2650 | return; | ||
2651 | |||
2652 | pci_free_consistent(tx_ring->pdev, tx_ring->size, | ||
2653 | tx_ring->desc, tx_ring->dma); | ||
2323 | 2654 | ||
2324 | tx_ring->desc = NULL; | 2655 | tx_ring->desc = NULL; |
2325 | } | 2656 | } |
@@ -2335,21 +2666,33 @@ static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |||
2335 | int i; | 2666 | int i; |
2336 | 2667 | ||
2337 | for (i = 0; i < adapter->num_tx_queues; i++) | 2668 | for (i = 0; i < adapter->num_tx_queues; i++) |
2338 | igb_free_tx_resources(&adapter->tx_ring[i]); | 2669 | igb_free_tx_resources(adapter->tx_ring[i]); |
2339 | } | 2670 | } |
2340 | 2671 | ||
2341 | static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, | 2672 | void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring, |
2342 | struct igb_buffer *buffer_info) | 2673 | struct igb_buffer *buffer_info) |
2343 | { | 2674 | { |
2344 | buffer_info->dma = 0; | 2675 | if (buffer_info->dma) { |
2676 | if (buffer_info->mapped_as_page) | ||
2677 | pci_unmap_page(tx_ring->pdev, | ||
2678 | buffer_info->dma, | ||
2679 | buffer_info->length, | ||
2680 | PCI_DMA_TODEVICE); | ||
2681 | else | ||
2682 | pci_unmap_single(tx_ring->pdev, | ||
2683 | buffer_info->dma, | ||
2684 | buffer_info->length, | ||
2685 | PCI_DMA_TODEVICE); | ||
2686 | buffer_info->dma = 0; | ||
2687 | } | ||
2345 | if (buffer_info->skb) { | 2688 | if (buffer_info->skb) { |
2346 | skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb, | ||
2347 | DMA_TO_DEVICE); | ||
2348 | dev_kfree_skb_any(buffer_info->skb); | 2689 | dev_kfree_skb_any(buffer_info->skb); |
2349 | buffer_info->skb = NULL; | 2690 | buffer_info->skb = NULL; |
2350 | } | 2691 | } |
2351 | buffer_info->time_stamp = 0; | 2692 | buffer_info->time_stamp = 0; |
2352 | /* buffer_info must be completely set up in the transmit path */ | 2693 | buffer_info->length = 0; |
2694 | buffer_info->next_to_watch = 0; | ||
2695 | buffer_info->mapped_as_page = false; | ||
2353 | } | 2696 | } |
2354 | 2697 | ||
2355 | /** | 2698 | /** |
@@ -2358,7 +2701,6 @@ static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, | |||
2358 | **/ | 2701 | **/ |
2359 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) | 2702 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
2360 | { | 2703 | { |
2361 | struct igb_adapter *adapter = tx_ring->adapter; | ||
2362 | struct igb_buffer *buffer_info; | 2704 | struct igb_buffer *buffer_info; |
2363 | unsigned long size; | 2705 | unsigned long size; |
2364 | unsigned int i; | 2706 | unsigned int i; |
@@ -2369,21 +2711,17 @@ static void igb_clean_tx_ring(struct igb_ring *tx_ring) | |||
2369 | 2711 | ||
2370 | for (i = 0; i < tx_ring->count; i++) { | 2712 | for (i = 0; i < tx_ring->count; i++) { |
2371 | buffer_info = &tx_ring->buffer_info[i]; | 2713 | buffer_info = &tx_ring->buffer_info[i]; |
2372 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | 2714 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
2373 | } | 2715 | } |
2374 | 2716 | ||
2375 | size = sizeof(struct igb_buffer) * tx_ring->count; | 2717 | size = sizeof(struct igb_buffer) * tx_ring->count; |
2376 | memset(tx_ring->buffer_info, 0, size); | 2718 | memset(tx_ring->buffer_info, 0, size); |
2377 | 2719 | ||
2378 | /* Zero out the descriptor ring */ | 2720 | /* Zero out the descriptor ring */ |
2379 | |||
2380 | memset(tx_ring->desc, 0, tx_ring->size); | 2721 | memset(tx_ring->desc, 0, tx_ring->size); |
2381 | 2722 | ||
2382 | tx_ring->next_to_use = 0; | 2723 | tx_ring->next_to_use = 0; |
2383 | tx_ring->next_to_clean = 0; | 2724 | tx_ring->next_to_clean = 0; |
2384 | |||
2385 | writel(0, adapter->hw.hw_addr + tx_ring->head); | ||
2386 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | ||
2387 | } | 2725 | } |
2388 | 2726 | ||
2389 | /** | 2727 | /** |
@@ -2395,7 +2733,7 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |||
2395 | int i; | 2733 | int i; |
2396 | 2734 | ||
2397 | for (i = 0; i < adapter->num_tx_queues; i++) | 2735 | for (i = 0; i < adapter->num_tx_queues; i++) |
2398 | igb_clean_tx_ring(&adapter->tx_ring[i]); | 2736 | igb_clean_tx_ring(adapter->tx_ring[i]); |
2399 | } | 2737 | } |
2400 | 2738 | ||
2401 | /** | 2739 | /** |
@@ -2406,14 +2744,17 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |||
2406 | **/ | 2744 | **/ |
2407 | void igb_free_rx_resources(struct igb_ring *rx_ring) | 2745 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
2408 | { | 2746 | { |
2409 | struct pci_dev *pdev = rx_ring->adapter->pdev; | ||
2410 | |||
2411 | igb_clean_rx_ring(rx_ring); | 2747 | igb_clean_rx_ring(rx_ring); |
2412 | 2748 | ||
2413 | vfree(rx_ring->buffer_info); | 2749 | vfree(rx_ring->buffer_info); |
2414 | rx_ring->buffer_info = NULL; | 2750 | rx_ring->buffer_info = NULL; |
2415 | 2751 | ||
2416 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | 2752 | /* if not set, then don't free */ |
2753 | if (!rx_ring->desc) | ||
2754 | return; | ||
2755 | |||
2756 | pci_free_consistent(rx_ring->pdev, rx_ring->size, | ||
2757 | rx_ring->desc, rx_ring->dma); | ||
2417 | 2758 | ||
2418 | rx_ring->desc = NULL; | 2759 | rx_ring->desc = NULL; |
2419 | } | 2760 | } |
@@ -2429,7 +2770,7 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |||
2429 | int i; | 2770 | int i; |
2430 | 2771 | ||
2431 | for (i = 0; i < adapter->num_rx_queues; i++) | 2772 | for (i = 0; i < adapter->num_rx_queues; i++) |
2432 | igb_free_rx_resources(&adapter->rx_ring[i]); | 2773 | igb_free_rx_resources(adapter->rx_ring[i]); |
2433 | } | 2774 | } |
2434 | 2775 | ||
2435 | /** | 2776 | /** |
@@ -2438,26 +2779,21 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |||
2438 | **/ | 2779 | **/ |
2439 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) | 2780 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
2440 | { | 2781 | { |
2441 | struct igb_adapter *adapter = rx_ring->adapter; | ||
2442 | struct igb_buffer *buffer_info; | 2782 | struct igb_buffer *buffer_info; |
2443 | struct pci_dev *pdev = adapter->pdev; | ||
2444 | unsigned long size; | 2783 | unsigned long size; |
2445 | unsigned int i; | 2784 | unsigned int i; |
2446 | 2785 | ||
2447 | if (!rx_ring->buffer_info) | 2786 | if (!rx_ring->buffer_info) |
2448 | return; | 2787 | return; |
2788 | |||
2449 | /* Free all the Rx ring sk_buffs */ | 2789 | /* Free all the Rx ring sk_buffs */ |
2450 | for (i = 0; i < rx_ring->count; i++) { | 2790 | for (i = 0; i < rx_ring->count; i++) { |
2451 | buffer_info = &rx_ring->buffer_info[i]; | 2791 | buffer_info = &rx_ring->buffer_info[i]; |
2452 | if (buffer_info->dma) { | 2792 | if (buffer_info->dma) { |
2453 | if (adapter->rx_ps_hdr_size) | 2793 | pci_unmap_single(rx_ring->pdev, |
2454 | pci_unmap_single(pdev, buffer_info->dma, | 2794 | buffer_info->dma, |
2455 | adapter->rx_ps_hdr_size, | 2795 | rx_ring->rx_buffer_len, |
2456 | PCI_DMA_FROMDEVICE); | 2796 | PCI_DMA_FROMDEVICE); |
2457 | else | ||
2458 | pci_unmap_single(pdev, buffer_info->dma, | ||
2459 | adapter->rx_buffer_len, | ||
2460 | PCI_DMA_FROMDEVICE); | ||
2461 | buffer_info->dma = 0; | 2797 | buffer_info->dma = 0; |
2462 | } | 2798 | } |
2463 | 2799 | ||
@@ -2465,14 +2801,16 @@ static void igb_clean_rx_ring(struct igb_ring *rx_ring) | |||
2465 | dev_kfree_skb(buffer_info->skb); | 2801 | dev_kfree_skb(buffer_info->skb); |
2466 | buffer_info->skb = NULL; | 2802 | buffer_info->skb = NULL; |
2467 | } | 2803 | } |
2804 | if (buffer_info->page_dma) { | ||
2805 | pci_unmap_page(rx_ring->pdev, | ||
2806 | buffer_info->page_dma, | ||
2807 | PAGE_SIZE / 2, | ||
2808 | PCI_DMA_FROMDEVICE); | ||
2809 | buffer_info->page_dma = 0; | ||
2810 | } | ||
2468 | if (buffer_info->page) { | 2811 | if (buffer_info->page) { |
2469 | if (buffer_info->page_dma) | ||
2470 | pci_unmap_page(pdev, buffer_info->page_dma, | ||
2471 | PAGE_SIZE / 2, | ||
2472 | PCI_DMA_FROMDEVICE); | ||
2473 | put_page(buffer_info->page); | 2812 | put_page(buffer_info->page); |
2474 | buffer_info->page = NULL; | 2813 | buffer_info->page = NULL; |
2475 | buffer_info->page_dma = 0; | ||
2476 | buffer_info->page_offset = 0; | 2814 | buffer_info->page_offset = 0; |
2477 | } | 2815 | } |
2478 | } | 2816 | } |
@@ -2485,9 +2823,6 @@ static void igb_clean_rx_ring(struct igb_ring *rx_ring) | |||
2485 | 2823 | ||
2486 | rx_ring->next_to_clean = 0; | 2824 | rx_ring->next_to_clean = 0; |
2487 | rx_ring->next_to_use = 0; | 2825 | rx_ring->next_to_use = 0; |
2488 | |||
2489 | writel(0, adapter->hw.hw_addr + rx_ring->head); | ||
2490 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | ||
2491 | } | 2826 | } |
2492 | 2827 | ||
2493 | /** | 2828 | /** |
@@ -2499,7 +2834,7 @@ static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |||
2499 | int i; | 2834 | int i; |
2500 | 2835 | ||
2501 | for (i = 0; i < adapter->num_rx_queues; i++) | 2836 | for (i = 0; i < adapter->num_rx_queues; i++) |
2502 | igb_clean_rx_ring(&adapter->rx_ring[i]); | 2837 | igb_clean_rx_ring(adapter->rx_ring[i]); |
2503 | } | 2838 | } |
2504 | 2839 | ||
2505 | /** | 2840 | /** |
@@ -2521,61 +2856,83 @@ static int igb_set_mac(struct net_device *netdev, void *p) | |||
2521 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | 2856 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
2522 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); | 2857 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
2523 | 2858 | ||
2524 | igb_rar_set(hw, hw->mac.addr, 0); | 2859 | /* set the correct pool for the new PF MAC address in entry 0 */ |
2525 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0); | 2860 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, |
2861 | adapter->vfs_allocated_count); | ||
2526 | 2862 | ||
2527 | return 0; | 2863 | return 0; |
2528 | } | 2864 | } |
2529 | 2865 | ||
2530 | /** | 2866 | /** |
2531 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set | 2867 | * igb_write_mc_addr_list - write multicast addresses to MTA |
2532 | * @netdev: network interface device structure | 2868 | * @netdev: network interface device structure |
2533 | * | 2869 | * |
2534 | * The set_rx_mode entry point is called whenever the unicast or multicast | 2870 | * Writes multicast address list to the MTA hash table. |
2535 | * address lists or the network interface flags are updated. This routine is | 2871 | * Returns: -ENOMEM on failure |
2536 | * responsible for configuring the hardware for proper unicast, multicast, | 2872 | * 0 on no addresses written |
2537 | * promiscuous mode, and all-multi behavior. | 2873 | * X on writing X addresses to MTA |
2538 | **/ | 2874 | **/ |
2539 | static void igb_set_rx_mode(struct net_device *netdev) | 2875 | static int igb_write_mc_addr_list(struct net_device *netdev) |
2540 | { | 2876 | { |
2541 | struct igb_adapter *adapter = netdev_priv(netdev); | 2877 | struct igb_adapter *adapter = netdev_priv(netdev); |
2542 | struct e1000_hw *hw = &adapter->hw; | 2878 | struct e1000_hw *hw = &adapter->hw; |
2543 | unsigned int rar_entries = hw->mac.rar_entry_count - | 2879 | struct dev_mc_list *mc_ptr; |
2544 | (adapter->vfs_allocated_count + 1); | 2880 | u8 *mta_list; |
2545 | struct dev_mc_list *mc_ptr = netdev->mc_list; | ||
2546 | u8 *mta_list = NULL; | ||
2547 | u32 rctl; | ||
2548 | int i; | 2881 | int i; |
2549 | 2882 | ||
2550 | /* Check for Promiscuous and All Multicast modes */ | 2883 | if (netdev_mc_empty(netdev)) { |
2551 | rctl = rd32(E1000_RCTL); | 2884 | /* nothing to program, so clear mc list */ |
2885 | igb_update_mc_addr_list(hw, NULL, 0); | ||
2886 | igb_restore_vf_multicasts(adapter); | ||
2887 | return 0; | ||
2888 | } | ||
2552 | 2889 | ||
2553 | if (netdev->flags & IFF_PROMISC) { | 2890 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
2554 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | 2891 | if (!mta_list) |
2555 | rctl &= ~E1000_RCTL_VFE; | 2892 | return -ENOMEM; |
2556 | } else { | ||
2557 | if (netdev->flags & IFF_ALLMULTI) | ||
2558 | rctl |= E1000_RCTL_MPE; | ||
2559 | else | ||
2560 | rctl &= ~E1000_RCTL_MPE; | ||
2561 | 2893 | ||
2562 | if (netdev->uc.count > rar_entries) | 2894 | /* The shared function expects a packed array of only addresses. */ |
2563 | rctl |= E1000_RCTL_UPE; | 2895 | i = 0; |
2564 | else | 2896 | netdev_for_each_mc_addr(mc_ptr, netdev) |
2565 | rctl &= ~E1000_RCTL_UPE; | 2897 | memcpy(mta_list + (i++ * ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); |
2566 | rctl |= E1000_RCTL_VFE; | 2898 | |
2567 | } | 2899 | igb_update_mc_addr_list(hw, mta_list, i); |
2568 | wr32(E1000_RCTL, rctl); | 2900 | kfree(mta_list); |
2901 | |||
2902 | return netdev_mc_count(netdev); | ||
2903 | } | ||
2904 | |||
2905 | /** | ||
2906 | * igb_write_uc_addr_list - write unicast addresses to RAR table | ||
2907 | * @netdev: network interface device structure | ||
2908 | * | ||
2909 | * Writes unicast address list to the RAR table. | ||
2910 | * Returns: -ENOMEM on failure/insufficient address space | ||
2911 | * 0 on no addresses written | ||
2912 | * X on writing X addresses to the RAR table | ||
2913 | **/ | ||
2914 | static int igb_write_uc_addr_list(struct net_device *netdev) | ||
2915 | { | ||
2916 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
2917 | struct e1000_hw *hw = &adapter->hw; | ||
2918 | unsigned int vfn = adapter->vfs_allocated_count; | ||
2919 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | ||
2920 | int count = 0; | ||
2921 | |||
2922 | /* return ENOMEM indicating insufficient memory for addresses */ | ||
2923 | if (netdev_uc_count(netdev) > rar_entries) | ||
2924 | return -ENOMEM; | ||
2569 | 2925 | ||
2570 | if (netdev->uc.count && rar_entries) { | 2926 | if (!netdev_uc_empty(netdev) && rar_entries) { |
2571 | struct netdev_hw_addr *ha; | 2927 | struct netdev_hw_addr *ha; |
2572 | list_for_each_entry(ha, &netdev->uc.list, list) { | 2928 | |
2929 | netdev_for_each_uc_addr(ha, netdev) { | ||
2573 | if (!rar_entries) | 2930 | if (!rar_entries) |
2574 | break; | 2931 | break; |
2575 | igb_rar_set(hw, ha->addr, rar_entries); | 2932 | igb_rar_set_qsel(adapter, ha->addr, |
2576 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, | 2933 | rar_entries--, |
2577 | rar_entries); | 2934 | vfn); |
2578 | rar_entries--; | 2935 | count++; |
2579 | } | 2936 | } |
2580 | } | 2937 | } |
2581 | /* write the addresses in reverse order to avoid write combining */ | 2938 | /* write the addresses in reverse order to avoid write combining */ |
@@ -2585,29 +2942,79 @@ static void igb_set_rx_mode(struct net_device *netdev) | |||
2585 | } | 2942 | } |
2586 | wrfl(); | 2943 | wrfl(); |
2587 | 2944 | ||
2588 | if (!netdev->mc_count) { | 2945 | return count; |
2589 | /* nothing to program, so clear mc list */ | 2946 | } |
2590 | igb_update_mc_addr_list(hw, NULL, 0); | 2947 | |
2591 | igb_restore_vf_multicasts(adapter); | 2948 | /** |
2592 | return; | 2949 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set |
2950 | * @netdev: network interface device structure | ||
2951 | * | ||
2952 | * The set_rx_mode entry point is called whenever the unicast or multicast | ||
2953 | * address lists or the network interface flags are updated. This routine is | ||
2954 | * responsible for configuring the hardware for proper unicast, multicast, | ||
2955 | * promiscuous mode, and all-multi behavior. | ||
2956 | **/ | ||
2957 | static void igb_set_rx_mode(struct net_device *netdev) | ||
2958 | { | ||
2959 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
2960 | struct e1000_hw *hw = &adapter->hw; | ||
2961 | unsigned int vfn = adapter->vfs_allocated_count; | ||
2962 | u32 rctl, vmolr = 0; | ||
2963 | int count; | ||
2964 | |||
2965 | /* Check for Promiscuous and All Multicast modes */ | ||
2966 | rctl = rd32(E1000_RCTL); | ||
2967 | |||
2968 | /* clear the effected bits */ | ||
2969 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | ||
2970 | |||
2971 | if (netdev->flags & IFF_PROMISC) { | ||
2972 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | ||
2973 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | ||
2974 | } else { | ||
2975 | if (netdev->flags & IFF_ALLMULTI) { | ||
2976 | rctl |= E1000_RCTL_MPE; | ||
2977 | vmolr |= E1000_VMOLR_MPME; | ||
2978 | } else { | ||
2979 | /* | ||
2980 | * Write addresses to the MTA, if the attempt fails | ||
2981 | * then we should just turn on promiscous mode so | ||
2982 | * that we can at least receive multicast traffic | ||
2983 | */ | ||
2984 | count = igb_write_mc_addr_list(netdev); | ||
2985 | if (count < 0) { | ||
2986 | rctl |= E1000_RCTL_MPE; | ||
2987 | vmolr |= E1000_VMOLR_MPME; | ||
2988 | } else if (count) { | ||
2989 | vmolr |= E1000_VMOLR_ROMPE; | ||
2990 | } | ||
2991 | } | ||
2992 | /* | ||
2993 | * Write addresses to available RAR registers, if there is not | ||
2994 | * sufficient space to store all the addresses then enable | ||
2995 | * unicast promiscous mode | ||
2996 | */ | ||
2997 | count = igb_write_uc_addr_list(netdev); | ||
2998 | if (count < 0) { | ||
2999 | rctl |= E1000_RCTL_UPE; | ||
3000 | vmolr |= E1000_VMOLR_ROPE; | ||
3001 | } | ||
3002 | rctl |= E1000_RCTL_VFE; | ||
2593 | } | 3003 | } |
3004 | wr32(E1000_RCTL, rctl); | ||
2594 | 3005 | ||
2595 | mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); | 3006 | /* |
2596 | if (!mta_list) { | 3007 | * In order to support SR-IOV and eventually VMDq it is necessary to set |
2597 | dev_err(&adapter->pdev->dev, | 3008 | * the VMOLR to enable the appropriate modes. Without this workaround |
2598 | "failed to allocate multicast filter list\n"); | 3009 | * we will have issues with VLAN tag stripping not being done for frames |
3010 | * that are only arriving because we are the default pool | ||
3011 | */ | ||
3012 | if (hw->mac.type < e1000_82576) | ||
2599 | return; | 3013 | return; |
2600 | } | ||
2601 | 3014 | ||
2602 | /* The shared function expects a packed array of only addresses. */ | 3015 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
2603 | for (i = 0; i < netdev->mc_count; i++) { | 3016 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); |
2604 | if (!mc_ptr) | 3017 | wr32(E1000_VMOLR(vfn), vmolr); |
2605 | break; | ||
2606 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | ||
2607 | mc_ptr = mc_ptr->next; | ||
2608 | } | ||
2609 | igb_update_mc_addr_list(hw, mta_list, i); | ||
2610 | kfree(mta_list); | ||
2611 | igb_restore_vf_multicasts(adapter); | 3018 | igb_restore_vf_multicasts(adapter); |
2612 | } | 3019 | } |
2613 | 3020 | ||
@@ -2623,7 +3030,7 @@ static void igb_update_phy_info(unsigned long data) | |||
2623 | * igb_has_link - check shared code for link and determine up/down | 3030 | * igb_has_link - check shared code for link and determine up/down |
2624 | * @adapter: pointer to driver private info | 3031 | * @adapter: pointer to driver private info |
2625 | **/ | 3032 | **/ |
2626 | static bool igb_has_link(struct igb_adapter *adapter) | 3033 | bool igb_has_link(struct igb_adapter *adapter) |
2627 | { | 3034 | { |
2628 | struct e1000_hw *hw = &adapter->hw; | 3035 | struct e1000_hw *hw = &adapter->hw; |
2629 | bool link_active = false; | 3036 | bool link_active = false; |
@@ -2669,49 +3076,41 @@ static void igb_watchdog(unsigned long data) | |||
2669 | static void igb_watchdog_task(struct work_struct *work) | 3076 | static void igb_watchdog_task(struct work_struct *work) |
2670 | { | 3077 | { |
2671 | struct igb_adapter *adapter = container_of(work, | 3078 | struct igb_adapter *adapter = container_of(work, |
2672 | struct igb_adapter, watchdog_task); | 3079 | struct igb_adapter, |
3080 | watchdog_task); | ||
2673 | struct e1000_hw *hw = &adapter->hw; | 3081 | struct e1000_hw *hw = &adapter->hw; |
2674 | struct net_device *netdev = adapter->netdev; | 3082 | struct net_device *netdev = adapter->netdev; |
2675 | struct igb_ring *tx_ring = adapter->tx_ring; | ||
2676 | u32 link; | 3083 | u32 link; |
2677 | u32 eics = 0; | ||
2678 | int i; | 3084 | int i; |
2679 | 3085 | ||
2680 | link = igb_has_link(adapter); | 3086 | link = igb_has_link(adapter); |
2681 | if ((netif_carrier_ok(netdev)) && link) | ||
2682 | goto link_up; | ||
2683 | |||
2684 | if (link) { | 3087 | if (link) { |
2685 | if (!netif_carrier_ok(netdev)) { | 3088 | if (!netif_carrier_ok(netdev)) { |
2686 | u32 ctrl; | 3089 | u32 ctrl; |
2687 | hw->mac.ops.get_speed_and_duplex(&adapter->hw, | 3090 | hw->mac.ops.get_speed_and_duplex(hw, |
2688 | &adapter->link_speed, | 3091 | &adapter->link_speed, |
2689 | &adapter->link_duplex); | 3092 | &adapter->link_duplex); |
2690 | 3093 | ||
2691 | ctrl = rd32(E1000_CTRL); | 3094 | ctrl = rd32(E1000_CTRL); |
2692 | /* Links status message must follow this format */ | 3095 | /* Links status message must follow this format */ |
2693 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | 3096 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " |
2694 | "Flow Control: %s\n", | 3097 | "Flow Control: %s\n", |
2695 | netdev->name, | 3098 | netdev->name, |
2696 | adapter->link_speed, | 3099 | adapter->link_speed, |
2697 | adapter->link_duplex == FULL_DUPLEX ? | 3100 | adapter->link_duplex == FULL_DUPLEX ? |
2698 | "Full Duplex" : "Half Duplex", | 3101 | "Full Duplex" : "Half Duplex", |
2699 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & | 3102 | ((ctrl & E1000_CTRL_TFCE) && |
2700 | E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & | 3103 | (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" : |
2701 | E1000_CTRL_RFCE) ? "RX" : ((ctrl & | 3104 | ((ctrl & E1000_CTRL_RFCE) ? "RX" : |
2702 | E1000_CTRL_TFCE) ? "TX" : "None"))); | 3105 | ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None"))); |
2703 | 3106 | ||
2704 | /* tweak tx_queue_len according to speed/duplex and | 3107 | /* adjust timeout factor according to speed/duplex */ |
2705 | * adjust the timeout factor */ | ||
2706 | netdev->tx_queue_len = adapter->tx_queue_len; | ||
2707 | adapter->tx_timeout_factor = 1; | 3108 | adapter->tx_timeout_factor = 1; |
2708 | switch (adapter->link_speed) { | 3109 | switch (adapter->link_speed) { |
2709 | case SPEED_10: | 3110 | case SPEED_10: |
2710 | netdev->tx_queue_len = 10; | ||
2711 | adapter->tx_timeout_factor = 14; | 3111 | adapter->tx_timeout_factor = 14; |
2712 | break; | 3112 | break; |
2713 | case SPEED_100: | 3113 | case SPEED_100: |
2714 | netdev->tx_queue_len = 100; | ||
2715 | /* maybe add some timeout factor ? */ | 3114 | /* maybe add some timeout factor ? */ |
2716 | break; | 3115 | break; |
2717 | } | 3116 | } |
@@ -2743,46 +3142,39 @@ static void igb_watchdog_task(struct work_struct *work) | |||
2743 | } | 3142 | } |
2744 | } | 3143 | } |
2745 | 3144 | ||
2746 | link_up: | ||
2747 | igb_update_stats(adapter); | 3145 | igb_update_stats(adapter); |
2748 | 3146 | ||
2749 | hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; | 3147 | for (i = 0; i < adapter->num_tx_queues; i++) { |
2750 | adapter->tpt_old = adapter->stats.tpt; | 3148 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
2751 | hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old; | 3149 | if (!netif_carrier_ok(netdev)) { |
2752 | adapter->colc_old = adapter->stats.colc; | ||
2753 | |||
2754 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; | ||
2755 | adapter->gorc_old = adapter->stats.gorc; | ||
2756 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | ||
2757 | adapter->gotc_old = adapter->stats.gotc; | ||
2758 | |||
2759 | igb_update_adaptive(&adapter->hw); | ||
2760 | |||
2761 | if (!netif_carrier_ok(netdev)) { | ||
2762 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { | ||
2763 | /* We've lost link, so the controller stops DMA, | 3150 | /* We've lost link, so the controller stops DMA, |
2764 | * but we've got queued Tx work that's never going | 3151 | * but we've got queued Tx work that's never going |
2765 | * to get done, so reset controller to flush Tx. | 3152 | * to get done, so reset controller to flush Tx. |
2766 | * (Do the reset outside of interrupt context). */ | 3153 | * (Do the reset outside of interrupt context). */ |
2767 | adapter->tx_timeout_count++; | 3154 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
2768 | schedule_work(&adapter->reset_task); | 3155 | adapter->tx_timeout_count++; |
2769 | /* return immediately since reset is imminent */ | 3156 | schedule_work(&adapter->reset_task); |
2770 | return; | 3157 | /* return immediately since reset is imminent */ |
3158 | return; | ||
3159 | } | ||
2771 | } | 3160 | } |
3161 | |||
3162 | /* Force detection of hung controller every watchdog period */ | ||
3163 | tx_ring->detect_tx_hung = true; | ||
2772 | } | 3164 | } |
2773 | 3165 | ||
2774 | /* Cause software interrupt to ensure rx ring is cleaned */ | 3166 | /* Cause software interrupt to ensure rx ring is cleaned */ |
2775 | if (adapter->msix_entries) { | 3167 | if (adapter->msix_entries) { |
2776 | for (i = 0; i < adapter->num_rx_queues; i++) | 3168 | u32 eics = 0; |
2777 | eics |= adapter->rx_ring[i].eims_value; | 3169 | for (i = 0; i < adapter->num_q_vectors; i++) { |
3170 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | ||
3171 | eics |= q_vector->eims_value; | ||
3172 | } | ||
2778 | wr32(E1000_EICS, eics); | 3173 | wr32(E1000_EICS, eics); |
2779 | } else { | 3174 | } else { |
2780 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | 3175 | wr32(E1000_ICS, E1000_ICS_RXDMT0); |
2781 | } | 3176 | } |
2782 | 3177 | ||
2783 | /* Force detection of hung controller every watchdog period */ | ||
2784 | tx_ring->detect_tx_hung = true; | ||
2785 | |||
2786 | /* Reset the timer */ | 3178 | /* Reset the timer */ |
2787 | if (!test_bit(__IGB_DOWN, &adapter->state)) | 3179 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2788 | mod_timer(&adapter->watchdog_timer, | 3180 | mod_timer(&adapter->watchdog_timer, |
@@ -2796,7 +3188,6 @@ enum latency_range { | |||
2796 | latency_invalid = 255 | 3188 | latency_invalid = 255 |
2797 | }; | 3189 | }; |
2798 | 3190 | ||
2799 | |||
2800 | /** | 3191 | /** |
2801 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | 3192 | * igb_update_ring_itr - update the dynamic ITR value based on packet size |
2802 | * | 3193 | * |
@@ -2811,25 +3202,37 @@ enum latency_range { | |||
2811 | * parameter (see igb_param.c) | 3202 | * parameter (see igb_param.c) |
2812 | * NOTE: This function is called only when operating in a multiqueue | 3203 | * NOTE: This function is called only when operating in a multiqueue |
2813 | * receive environment. | 3204 | * receive environment. |
2814 | * @rx_ring: pointer to ring | 3205 | * @q_vector: pointer to q_vector |
2815 | **/ | 3206 | **/ |
2816 | static void igb_update_ring_itr(struct igb_ring *rx_ring) | 3207 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
2817 | { | 3208 | { |
2818 | int new_val = rx_ring->itr_val; | 3209 | int new_val = q_vector->itr_val; |
2819 | int avg_wire_size = 0; | 3210 | int avg_wire_size = 0; |
2820 | struct igb_adapter *adapter = rx_ring->adapter; | 3211 | struct igb_adapter *adapter = q_vector->adapter; |
2821 | |||
2822 | if (!rx_ring->total_packets) | ||
2823 | goto clear_counts; /* no packets, so don't do anything */ | ||
2824 | 3212 | ||
2825 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 | 3213 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
2826 | * ints/sec - ITR timer value of 120 ticks. | 3214 | * ints/sec - ITR timer value of 120 ticks. |
2827 | */ | 3215 | */ |
2828 | if (adapter->link_speed != SPEED_1000) { | 3216 | if (adapter->link_speed != SPEED_1000) { |
2829 | new_val = 120; | 3217 | new_val = 976; |
2830 | goto set_itr_val; | 3218 | goto set_itr_val; |
2831 | } | 3219 | } |
2832 | avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets; | 3220 | |
3221 | if (q_vector->rx_ring && q_vector->rx_ring->total_packets) { | ||
3222 | struct igb_ring *ring = q_vector->rx_ring; | ||
3223 | avg_wire_size = ring->total_bytes / ring->total_packets; | ||
3224 | } | ||
3225 | |||
3226 | if (q_vector->tx_ring && q_vector->tx_ring->total_packets) { | ||
3227 | struct igb_ring *ring = q_vector->tx_ring; | ||
3228 | avg_wire_size = max_t(u32, avg_wire_size, | ||
3229 | (ring->total_bytes / | ||
3230 | ring->total_packets)); | ||
3231 | } | ||
3232 | |||
3233 | /* if avg_wire_size isn't set no work was done */ | ||
3234 | if (!avg_wire_size) | ||
3235 | goto clear_counts; | ||
2833 | 3236 | ||
2834 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ | 3237 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
2835 | avg_wire_size += 24; | 3238 | avg_wire_size += 24; |
@@ -2843,14 +3246,24 @@ static void igb_update_ring_itr(struct igb_ring *rx_ring) | |||
2843 | else | 3246 | else |
2844 | new_val = avg_wire_size / 2; | 3247 | new_val = avg_wire_size / 2; |
2845 | 3248 | ||
3249 | /* when in itr mode 3 do not exceed 20K ints/sec */ | ||
3250 | if (adapter->rx_itr_setting == 3 && new_val < 196) | ||
3251 | new_val = 196; | ||
3252 | |||
2846 | set_itr_val: | 3253 | set_itr_val: |
2847 | if (new_val != rx_ring->itr_val) { | 3254 | if (new_val != q_vector->itr_val) { |
2848 | rx_ring->itr_val = new_val; | 3255 | q_vector->itr_val = new_val; |
2849 | rx_ring->set_itr = 1; | 3256 | q_vector->set_itr = 1; |
2850 | } | 3257 | } |
2851 | clear_counts: | 3258 | clear_counts: |
2852 | rx_ring->total_bytes = 0; | 3259 | if (q_vector->rx_ring) { |
2853 | rx_ring->total_packets = 0; | 3260 | q_vector->rx_ring->total_bytes = 0; |
3261 | q_vector->rx_ring->total_packets = 0; | ||
3262 | } | ||
3263 | if (q_vector->tx_ring) { | ||
3264 | q_vector->tx_ring->total_bytes = 0; | ||
3265 | q_vector->tx_ring->total_packets = 0; | ||
3266 | } | ||
2854 | } | 3267 | } |
2855 | 3268 | ||
2856 | /** | 3269 | /** |
@@ -2867,7 +3280,7 @@ clear_counts: | |||
2867 | * NOTE: These calculations are only valid when operating in a single- | 3280 | * NOTE: These calculations are only valid when operating in a single- |
2868 | * queue environment. | 3281 | * queue environment. |
2869 | * @adapter: pointer to adapter | 3282 | * @adapter: pointer to adapter |
2870 | * @itr_setting: current adapter->itr | 3283 | * @itr_setting: current q_vector->itr_val |
2871 | * @packets: the number of packets during this measurement interval | 3284 | * @packets: the number of packets during this measurement interval |
2872 | * @bytes: the number of bytes during this measurement interval | 3285 | * @bytes: the number of bytes during this measurement interval |
2873 | **/ | 3286 | **/ |
@@ -2919,8 +3332,9 @@ update_itr_done: | |||
2919 | 3332 | ||
2920 | static void igb_set_itr(struct igb_adapter *adapter) | 3333 | static void igb_set_itr(struct igb_adapter *adapter) |
2921 | { | 3334 | { |
3335 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | ||
2922 | u16 current_itr; | 3336 | u16 current_itr; |
2923 | u32 new_itr = adapter->itr; | 3337 | u32 new_itr = q_vector->itr_val; |
2924 | 3338 | ||
2925 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | 3339 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ |
2926 | if (adapter->link_speed != SPEED_1000) { | 3340 | if (adapter->link_speed != SPEED_1000) { |
@@ -2931,21 +3345,17 @@ static void igb_set_itr(struct igb_adapter *adapter) | |||
2931 | 3345 | ||
2932 | adapter->rx_itr = igb_update_itr(adapter, | 3346 | adapter->rx_itr = igb_update_itr(adapter, |
2933 | adapter->rx_itr, | 3347 | adapter->rx_itr, |
2934 | adapter->rx_ring->total_packets, | 3348 | q_vector->rx_ring->total_packets, |
2935 | adapter->rx_ring->total_bytes); | 3349 | q_vector->rx_ring->total_bytes); |
2936 | 3350 | ||
2937 | if (adapter->rx_ring->buddy) { | 3351 | adapter->tx_itr = igb_update_itr(adapter, |
2938 | adapter->tx_itr = igb_update_itr(adapter, | 3352 | adapter->tx_itr, |
2939 | adapter->tx_itr, | 3353 | q_vector->tx_ring->total_packets, |
2940 | adapter->tx_ring->total_packets, | 3354 | q_vector->tx_ring->total_bytes); |
2941 | adapter->tx_ring->total_bytes); | 3355 | current_itr = max(adapter->rx_itr, adapter->tx_itr); |
2942 | current_itr = max(adapter->rx_itr, adapter->tx_itr); | ||
2943 | } else { | ||
2944 | current_itr = adapter->rx_itr; | ||
2945 | } | ||
2946 | 3356 | ||
2947 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ | 3357 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
2948 | if (adapter->itr_setting == 3 && current_itr == lowest_latency) | 3358 | if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency) |
2949 | current_itr = low_latency; | 3359 | current_itr = low_latency; |
2950 | 3360 | ||
2951 | switch (current_itr) { | 3361 | switch (current_itr) { |
@@ -2964,20 +3374,19 @@ static void igb_set_itr(struct igb_adapter *adapter) | |||
2964 | } | 3374 | } |
2965 | 3375 | ||
2966 | set_itr_now: | 3376 | set_itr_now: |
2967 | adapter->rx_ring->total_bytes = 0; | 3377 | q_vector->rx_ring->total_bytes = 0; |
2968 | adapter->rx_ring->total_packets = 0; | 3378 | q_vector->rx_ring->total_packets = 0; |
2969 | if (adapter->rx_ring->buddy) { | 3379 | q_vector->tx_ring->total_bytes = 0; |
2970 | adapter->rx_ring->buddy->total_bytes = 0; | 3380 | q_vector->tx_ring->total_packets = 0; |
2971 | adapter->rx_ring->buddy->total_packets = 0; | ||
2972 | } | ||
2973 | 3381 | ||
2974 | if (new_itr != adapter->itr) { | 3382 | if (new_itr != q_vector->itr_val) { |
2975 | /* this attempts to bias the interrupt rate towards Bulk | 3383 | /* this attempts to bias the interrupt rate towards Bulk |
2976 | * by adding intermediate steps when interrupt rate is | 3384 | * by adding intermediate steps when interrupt rate is |
2977 | * increasing */ | 3385 | * increasing */ |
2978 | new_itr = new_itr > adapter->itr ? | 3386 | new_itr = new_itr > q_vector->itr_val ? |
2979 | max((new_itr * adapter->itr) / | 3387 | max((new_itr * q_vector->itr_val) / |
2980 | (new_itr + (adapter->itr >> 2)), new_itr) : | 3388 | (new_itr + (q_vector->itr_val >> 2)), |
3389 | new_itr) : | ||
2981 | new_itr; | 3390 | new_itr; |
2982 | /* Don't write the value here; it resets the adapter's | 3391 | /* Don't write the value here; it resets the adapter's |
2983 | * internal timer, and causes us to delay far longer than | 3392 | * internal timer, and causes us to delay far longer than |
@@ -2985,25 +3394,22 @@ set_itr_now: | |||
2985 | * value at the beginning of the next interrupt so the timing | 3394 | * value at the beginning of the next interrupt so the timing |
2986 | * ends up being correct. | 3395 | * ends up being correct. |
2987 | */ | 3396 | */ |
2988 | adapter->itr = new_itr; | 3397 | q_vector->itr_val = new_itr; |
2989 | adapter->rx_ring->itr_val = new_itr; | 3398 | q_vector->set_itr = 1; |
2990 | adapter->rx_ring->set_itr = 1; | ||
2991 | } | 3399 | } |
2992 | 3400 | ||
2993 | return; | 3401 | return; |
2994 | } | 3402 | } |
2995 | 3403 | ||
2996 | |||
2997 | #define IGB_TX_FLAGS_CSUM 0x00000001 | 3404 | #define IGB_TX_FLAGS_CSUM 0x00000001 |
2998 | #define IGB_TX_FLAGS_VLAN 0x00000002 | 3405 | #define IGB_TX_FLAGS_VLAN 0x00000002 |
2999 | #define IGB_TX_FLAGS_TSO 0x00000004 | 3406 | #define IGB_TX_FLAGS_TSO 0x00000004 |
3000 | #define IGB_TX_FLAGS_IPV4 0x00000008 | 3407 | #define IGB_TX_FLAGS_IPV4 0x00000008 |
3001 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 | 3408 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 |
3002 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 | 3409 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
3003 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | 3410 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 |
3004 | 3411 | ||
3005 | static inline int igb_tso_adv(struct igb_adapter *adapter, | 3412 | static inline int igb_tso_adv(struct igb_ring *tx_ring, |
3006 | struct igb_ring *tx_ring, | ||
3007 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) | 3413 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) |
3008 | { | 3414 | { |
3009 | struct e1000_adv_tx_context_desc *context_desc; | 3415 | struct e1000_adv_tx_context_desc *context_desc; |
@@ -3011,8 +3417,8 @@ static inline int igb_tso_adv(struct igb_adapter *adapter, | |||
3011 | int err; | 3417 | int err; |
3012 | struct igb_buffer *buffer_info; | 3418 | struct igb_buffer *buffer_info; |
3013 | u32 info = 0, tu_cmd = 0; | 3419 | u32 info = 0, tu_cmd = 0; |
3014 | u32 mss_l4len_idx, l4len; | 3420 | u32 mss_l4len_idx; |
3015 | *hdr_len = 0; | 3421 | u8 l4len; |
3016 | 3422 | ||
3017 | if (skb_header_cloned(skb)) { | 3423 | if (skb_header_cloned(skb)) { |
3018 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | 3424 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
@@ -3031,7 +3437,7 @@ static inline int igb_tso_adv(struct igb_adapter *adapter, | |||
3031 | iph->daddr, 0, | 3437 | iph->daddr, 0, |
3032 | IPPROTO_TCP, | 3438 | IPPROTO_TCP, |
3033 | 0); | 3439 | 0); |
3034 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | 3440 | } else if (skb_is_gso_v6(skb)) { |
3035 | ipv6_hdr(skb)->payload_len = 0; | 3441 | ipv6_hdr(skb)->payload_len = 0; |
3036 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | 3442 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, |
3037 | &ipv6_hdr(skb)->daddr, | 3443 | &ipv6_hdr(skb)->daddr, |
@@ -3065,8 +3471,8 @@ static inline int igb_tso_adv(struct igb_adapter *adapter, | |||
3065 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | 3471 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); |
3066 | 3472 | ||
3067 | /* For 82575, context index must be unique per ring. */ | 3473 | /* For 82575, context index must be unique per ring. */ |
3068 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) | 3474 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) |
3069 | mss_l4len_idx |= tx_ring->queue_index << 4; | 3475 | mss_l4len_idx |= tx_ring->reg_idx << 4; |
3070 | 3476 | ||
3071 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | 3477 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
3072 | context_desc->seqnum_seed = 0; | 3478 | context_desc->seqnum_seed = 0; |
@@ -3083,14 +3489,14 @@ static inline int igb_tso_adv(struct igb_adapter *adapter, | |||
3083 | return true; | 3489 | return true; |
3084 | } | 3490 | } |
3085 | 3491 | ||
3086 | static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | 3492 | static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring, |
3087 | struct igb_ring *tx_ring, | 3493 | struct sk_buff *skb, u32 tx_flags) |
3088 | struct sk_buff *skb, u32 tx_flags) | ||
3089 | { | 3494 | { |
3090 | struct e1000_adv_tx_context_desc *context_desc; | 3495 | struct e1000_adv_tx_context_desc *context_desc; |
3091 | unsigned int i; | 3496 | struct pci_dev *pdev = tx_ring->pdev; |
3092 | struct igb_buffer *buffer_info; | 3497 | struct igb_buffer *buffer_info; |
3093 | u32 info = 0, tu_cmd = 0; | 3498 | u32 info = 0, tu_cmd = 0; |
3499 | unsigned int i; | ||
3094 | 3500 | ||
3095 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | 3501 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || |
3096 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | 3502 | (tx_flags & IGB_TX_FLAGS_VLAN)) { |
@@ -3100,6 +3506,7 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |||
3100 | 3506 | ||
3101 | if (tx_flags & IGB_TX_FLAGS_VLAN) | 3507 | if (tx_flags & IGB_TX_FLAGS_VLAN) |
3102 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | 3508 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); |
3509 | |||
3103 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | 3510 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); |
3104 | if (skb->ip_summed == CHECKSUM_PARTIAL) | 3511 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
3105 | info |= skb_network_header_len(skb); | 3512 | info |= skb_network_header_len(skb); |
@@ -3137,7 +3544,7 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |||
3137 | break; | 3544 | break; |
3138 | default: | 3545 | default: |
3139 | if (unlikely(net_ratelimit())) | 3546 | if (unlikely(net_ratelimit())) |
3140 | dev_warn(&adapter->pdev->dev, | 3547 | dev_warn(&pdev->dev, |
3141 | "partial checksum but proto=%x!\n", | 3548 | "partial checksum but proto=%x!\n", |
3142 | skb->protocol); | 3549 | skb->protocol); |
3143 | break; | 3550 | break; |
@@ -3146,11 +3553,9 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |||
3146 | 3553 | ||
3147 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | 3554 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); |
3148 | context_desc->seqnum_seed = 0; | 3555 | context_desc->seqnum_seed = 0; |
3149 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) | 3556 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) |
3150 | context_desc->mss_l4len_idx = | 3557 | context_desc->mss_l4len_idx = |
3151 | cpu_to_le32(tx_ring->queue_index << 4); | 3558 | cpu_to_le32(tx_ring->reg_idx << 4); |
3152 | else | ||
3153 | context_desc->mss_l4len_idx = 0; | ||
3154 | 3559 | ||
3155 | buffer_info->time_stamp = jiffies; | 3560 | buffer_info->time_stamp = jiffies; |
3156 | buffer_info->next_to_watch = i; | 3561 | buffer_info->next_to_watch = i; |
@@ -3169,36 +3574,32 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |||
3169 | #define IGB_MAX_TXD_PWR 16 | 3574 | #define IGB_MAX_TXD_PWR 16 |
3170 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | 3575 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) |
3171 | 3576 | ||
3172 | static inline int igb_tx_map_adv(struct igb_adapter *adapter, | 3577 | static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb, |
3173 | struct igb_ring *tx_ring, struct sk_buff *skb, | ||
3174 | unsigned int first) | 3578 | unsigned int first) |
3175 | { | 3579 | { |
3176 | struct igb_buffer *buffer_info; | 3580 | struct igb_buffer *buffer_info; |
3581 | struct pci_dev *pdev = tx_ring->pdev; | ||
3177 | unsigned int len = skb_headlen(skb); | 3582 | unsigned int len = skb_headlen(skb); |
3178 | unsigned int count = 0, i; | 3583 | unsigned int count = 0, i; |
3179 | unsigned int f; | 3584 | unsigned int f; |
3180 | dma_addr_t *map; | ||
3181 | 3585 | ||
3182 | i = tx_ring->next_to_use; | 3586 | i = tx_ring->next_to_use; |
3183 | 3587 | ||
3184 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { | ||
3185 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | ||
3186 | return 0; | ||
3187 | } | ||
3188 | |||
3189 | map = skb_shinfo(skb)->dma_maps; | ||
3190 | |||
3191 | buffer_info = &tx_ring->buffer_info[i]; | 3588 | buffer_info = &tx_ring->buffer_info[i]; |
3192 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | 3589 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); |
3193 | buffer_info->length = len; | 3590 | buffer_info->length = len; |
3194 | /* set time_stamp *before* dma to help avoid a possible race */ | 3591 | /* set time_stamp *before* dma to help avoid a possible race */ |
3195 | buffer_info->time_stamp = jiffies; | 3592 | buffer_info->time_stamp = jiffies; |
3196 | buffer_info->next_to_watch = i; | 3593 | buffer_info->next_to_watch = i; |
3197 | buffer_info->dma = skb_shinfo(skb)->dma_head; | 3594 | buffer_info->dma = pci_map_single(pdev, skb->data, len, |
3595 | PCI_DMA_TODEVICE); | ||
3596 | if (pci_dma_mapping_error(pdev, buffer_info->dma)) | ||
3597 | goto dma_error; | ||
3198 | 3598 | ||
3199 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | 3599 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { |
3200 | struct skb_frag_struct *frag; | 3600 | struct skb_frag_struct *frag; |
3201 | 3601 | ||
3602 | count++; | ||
3202 | i++; | 3603 | i++; |
3203 | if (i == tx_ring->count) | 3604 | if (i == tx_ring->count) |
3204 | i = 0; | 3605 | i = 0; |
@@ -3211,25 +3612,53 @@ static inline int igb_tx_map_adv(struct igb_adapter *adapter, | |||
3211 | buffer_info->length = len; | 3612 | buffer_info->length = len; |
3212 | buffer_info->time_stamp = jiffies; | 3613 | buffer_info->time_stamp = jiffies; |
3213 | buffer_info->next_to_watch = i; | 3614 | buffer_info->next_to_watch = i; |
3214 | buffer_info->dma = map[count]; | 3615 | buffer_info->mapped_as_page = true; |
3215 | count++; | 3616 | buffer_info->dma = pci_map_page(pdev, |
3617 | frag->page, | ||
3618 | frag->page_offset, | ||
3619 | len, | ||
3620 | PCI_DMA_TODEVICE); | ||
3621 | if (pci_dma_mapping_error(pdev, buffer_info->dma)) | ||
3622 | goto dma_error; | ||
3623 | |||
3216 | } | 3624 | } |
3217 | 3625 | ||
3218 | tx_ring->buffer_info[i].skb = skb; | 3626 | tx_ring->buffer_info[i].skb = skb; |
3627 | tx_ring->buffer_info[i].gso_segs = skb_shinfo(skb)->gso_segs ?: 1; | ||
3219 | tx_ring->buffer_info[first].next_to_watch = i; | 3628 | tx_ring->buffer_info[first].next_to_watch = i; |
3220 | 3629 | ||
3221 | return count + 1; | 3630 | return ++count; |
3631 | |||
3632 | dma_error: | ||
3633 | dev_err(&pdev->dev, "TX DMA map failed\n"); | ||
3634 | |||
3635 | /* clear timestamp and dma mappings for failed buffer_info mapping */ | ||
3636 | buffer_info->dma = 0; | ||
3637 | buffer_info->time_stamp = 0; | ||
3638 | buffer_info->length = 0; | ||
3639 | buffer_info->next_to_watch = 0; | ||
3640 | buffer_info->mapped_as_page = false; | ||
3641 | |||
3642 | /* clear timestamp and dma mappings for remaining portion of packet */ | ||
3643 | while (count--) { | ||
3644 | if (i == 0) | ||
3645 | i = tx_ring->count; | ||
3646 | i--; | ||
3647 | buffer_info = &tx_ring->buffer_info[i]; | ||
3648 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); | ||
3649 | } | ||
3650 | |||
3651 | return 0; | ||
3222 | } | 3652 | } |
3223 | 3653 | ||
3224 | static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | 3654 | static inline void igb_tx_queue_adv(struct igb_ring *tx_ring, |
3225 | struct igb_ring *tx_ring, | 3655 | u32 tx_flags, int count, u32 paylen, |
3226 | int tx_flags, int count, u32 paylen, | ||
3227 | u8 hdr_len) | 3656 | u8 hdr_len) |
3228 | { | 3657 | { |
3229 | union e1000_adv_tx_desc *tx_desc = NULL; | 3658 | union e1000_adv_tx_desc *tx_desc; |
3230 | struct igb_buffer *buffer_info; | 3659 | struct igb_buffer *buffer_info; |
3231 | u32 olinfo_status = 0, cmd_type_len; | 3660 | u32 olinfo_status = 0, cmd_type_len; |
3232 | unsigned int i; | 3661 | unsigned int i = tx_ring->next_to_use; |
3233 | 3662 | ||
3234 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | 3663 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | |
3235 | E1000_ADVTXD_DCMD_DEXT); | 3664 | E1000_ADVTXD_DCMD_DEXT); |
@@ -3254,27 +3683,28 @@ static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | |||
3254 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | 3683 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; |
3255 | } | 3684 | } |
3256 | 3685 | ||
3257 | if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) && | 3686 | if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) && |
3258 | (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | | 3687 | (tx_flags & (IGB_TX_FLAGS_CSUM | |
3688 | IGB_TX_FLAGS_TSO | | ||
3259 | IGB_TX_FLAGS_VLAN))) | 3689 | IGB_TX_FLAGS_VLAN))) |
3260 | olinfo_status |= tx_ring->queue_index << 4; | 3690 | olinfo_status |= tx_ring->reg_idx << 4; |
3261 | 3691 | ||
3262 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | 3692 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); |
3263 | 3693 | ||
3264 | i = tx_ring->next_to_use; | 3694 | do { |
3265 | while (count--) { | ||
3266 | buffer_info = &tx_ring->buffer_info[i]; | 3695 | buffer_info = &tx_ring->buffer_info[i]; |
3267 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | 3696 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); |
3268 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | 3697 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); |
3269 | tx_desc->read.cmd_type_len = | 3698 | tx_desc->read.cmd_type_len = |
3270 | cpu_to_le32(cmd_type_len | buffer_info->length); | 3699 | cpu_to_le32(cmd_type_len | buffer_info->length); |
3271 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | 3700 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
3701 | count--; | ||
3272 | i++; | 3702 | i++; |
3273 | if (i == tx_ring->count) | 3703 | if (i == tx_ring->count) |
3274 | i = 0; | 3704 | i = 0; |
3275 | } | 3705 | } while (count > 0); |
3276 | 3706 | ||
3277 | tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd); | 3707 | tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD); |
3278 | /* Force memory writes to complete before letting h/w | 3708 | /* Force memory writes to complete before letting h/w |
3279 | * know there are new descriptors to fetch. (Only | 3709 | * know there are new descriptors to fetch. (Only |
3280 | * applicable for weak-ordered memory model archs, | 3710 | * applicable for weak-ordered memory model archs, |
@@ -3282,16 +3712,15 @@ static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | |||
3282 | wmb(); | 3712 | wmb(); |
3283 | 3713 | ||
3284 | tx_ring->next_to_use = i; | 3714 | tx_ring->next_to_use = i; |
3285 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | 3715 | writel(i, tx_ring->tail); |
3286 | /* we need this if more than one processor can write to our tail | 3716 | /* we need this if more than one processor can write to our tail |
3287 | * at a time, it syncronizes IO on IA64/Altix systems */ | 3717 | * at a time, it syncronizes IO on IA64/Altix systems */ |
3288 | mmiowb(); | 3718 | mmiowb(); |
3289 | } | 3719 | } |
3290 | 3720 | ||
3291 | static int __igb_maybe_stop_tx(struct net_device *netdev, | 3721 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
3292 | struct igb_ring *tx_ring, int size) | ||
3293 | { | 3722 | { |
3294 | struct igb_adapter *adapter = netdev_priv(netdev); | 3723 | struct net_device *netdev = tx_ring->netdev; |
3295 | 3724 | ||
3296 | netif_stop_subqueue(netdev, tx_ring->queue_index); | 3725 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
3297 | 3726 | ||
@@ -3307,66 +3736,43 @@ static int __igb_maybe_stop_tx(struct net_device *netdev, | |||
3307 | 3736 | ||
3308 | /* A reprieve! */ | 3737 | /* A reprieve! */ |
3309 | netif_wake_subqueue(netdev, tx_ring->queue_index); | 3738 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
3310 | ++adapter->restart_queue; | 3739 | tx_ring->tx_stats.restart_queue++; |
3311 | return 0; | 3740 | return 0; |
3312 | } | 3741 | } |
3313 | 3742 | ||
3314 | static int igb_maybe_stop_tx(struct net_device *netdev, | 3743 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
3315 | struct igb_ring *tx_ring, int size) | ||
3316 | { | 3744 | { |
3317 | if (igb_desc_unused(tx_ring) >= size) | 3745 | if (igb_desc_unused(tx_ring) >= size) |
3318 | return 0; | 3746 | return 0; |
3319 | return __igb_maybe_stop_tx(netdev, tx_ring, size); | 3747 | return __igb_maybe_stop_tx(tx_ring, size); |
3320 | } | 3748 | } |
3321 | 3749 | ||
3322 | static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb, | 3750 | netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb, |
3323 | struct net_device *netdev, | 3751 | struct igb_ring *tx_ring) |
3324 | struct igb_ring *tx_ring) | ||
3325 | { | 3752 | { |
3326 | struct igb_adapter *adapter = netdev_priv(netdev); | 3753 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); |
3327 | unsigned int first; | 3754 | int tso = 0, count; |
3328 | unsigned int tx_flags = 0; | 3755 | u32 tx_flags = 0; |
3756 | u16 first; | ||
3329 | u8 hdr_len = 0; | 3757 | u8 hdr_len = 0; |
3330 | int count = 0; | 3758 | union skb_shared_tx *shtx = skb_tx(skb); |
3331 | int tso = 0; | ||
3332 | union skb_shared_tx *shtx; | ||
3333 | |||
3334 | if (test_bit(__IGB_DOWN, &adapter->state)) { | ||
3335 | dev_kfree_skb_any(skb); | ||
3336 | return NETDEV_TX_OK; | ||
3337 | } | ||
3338 | |||
3339 | if (skb->len <= 0) { | ||
3340 | dev_kfree_skb_any(skb); | ||
3341 | return NETDEV_TX_OK; | ||
3342 | } | ||
3343 | 3759 | ||
3344 | /* need: 1 descriptor per page, | 3760 | /* need: 1 descriptor per page, |
3345 | * + 2 desc gap to keep tail from touching head, | 3761 | * + 2 desc gap to keep tail from touching head, |
3346 | * + 1 desc for skb->data, | 3762 | * + 1 desc for skb->data, |
3347 | * + 1 desc for context descriptor, | 3763 | * + 1 desc for context descriptor, |
3348 | * otherwise try next time */ | 3764 | * otherwise try next time */ |
3349 | if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { | 3765 | if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { |
3350 | /* this is a hard error */ | 3766 | /* this is a hard error */ |
3351 | return NETDEV_TX_BUSY; | 3767 | return NETDEV_TX_BUSY; |
3352 | } | 3768 | } |
3353 | 3769 | ||
3354 | /* | ||
3355 | * TODO: check that there currently is no other packet with | ||
3356 | * time stamping in the queue | ||
3357 | * | ||
3358 | * When doing time stamping, keep the connection to the socket | ||
3359 | * a while longer: it is still needed by skb_hwtstamp_tx(), | ||
3360 | * called either in igb_tx_hwtstamp() or by our caller when | ||
3361 | * doing software time stamping. | ||
3362 | */ | ||
3363 | shtx = skb_tx(skb); | ||
3364 | if (unlikely(shtx->hardware)) { | 3770 | if (unlikely(shtx->hardware)) { |
3365 | shtx->in_progress = 1; | 3771 | shtx->in_progress = 1; |
3366 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | 3772 | tx_flags |= IGB_TX_FLAGS_TSTAMP; |
3367 | } | 3773 | } |
3368 | 3774 | ||
3369 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | 3775 | if (vlan_tx_tag_present(skb) && adapter->vlgrp) { |
3370 | tx_flags |= IGB_TX_FLAGS_VLAN; | 3776 | tx_flags |= IGB_TX_FLAGS_VLAN; |
3371 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | 3777 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); |
3372 | } | 3778 | } |
@@ -3375,37 +3781,38 @@ static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb, | |||
3375 | tx_flags |= IGB_TX_FLAGS_IPV4; | 3781 | tx_flags |= IGB_TX_FLAGS_IPV4; |
3376 | 3782 | ||
3377 | first = tx_ring->next_to_use; | 3783 | first = tx_ring->next_to_use; |
3378 | tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, | 3784 | if (skb_is_gso(skb)) { |
3379 | &hdr_len) : 0; | 3785 | tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len); |
3380 | 3786 | ||
3381 | if (tso < 0) { | 3787 | if (tso < 0) { |
3382 | dev_kfree_skb_any(skb); | 3788 | dev_kfree_skb_any(skb); |
3383 | return NETDEV_TX_OK; | 3789 | return NETDEV_TX_OK; |
3790 | } | ||
3384 | } | 3791 | } |
3385 | 3792 | ||
3386 | if (tso) | 3793 | if (tso) |
3387 | tx_flags |= IGB_TX_FLAGS_TSO; | 3794 | tx_flags |= IGB_TX_FLAGS_TSO; |
3388 | else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) && | 3795 | else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) && |
3389 | (skb->ip_summed == CHECKSUM_PARTIAL)) | 3796 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
3390 | tx_flags |= IGB_TX_FLAGS_CSUM; | 3797 | tx_flags |= IGB_TX_FLAGS_CSUM; |
3391 | 3798 | ||
3392 | /* | 3799 | /* |
3393 | * count reflects descriptors mapped, if 0 then mapping error | 3800 | * count reflects descriptors mapped, if 0 or less then mapping error |
3394 | * has occured and we need to rewind the descriptor queue | 3801 | * has occured and we need to rewind the descriptor queue |
3395 | */ | 3802 | */ |
3396 | count = igb_tx_map_adv(adapter, tx_ring, skb, first); | 3803 | count = igb_tx_map_adv(tx_ring, skb, first); |
3397 | 3804 | if (!count) { | |
3398 | if (count) { | ||
3399 | igb_tx_queue_adv(adapter, tx_ring, tx_flags, count, | ||
3400 | skb->len, hdr_len); | ||
3401 | /* Make sure there is space in the ring for the next send. */ | ||
3402 | igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); | ||
3403 | } else { | ||
3404 | dev_kfree_skb_any(skb); | 3805 | dev_kfree_skb_any(skb); |
3405 | tx_ring->buffer_info[first].time_stamp = 0; | 3806 | tx_ring->buffer_info[first].time_stamp = 0; |
3406 | tx_ring->next_to_use = first; | 3807 | tx_ring->next_to_use = first; |
3808 | return NETDEV_TX_OK; | ||
3407 | } | 3809 | } |
3408 | 3810 | ||
3811 | igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len); | ||
3812 | |||
3813 | /* Make sure there is space in the ring for the next send. */ | ||
3814 | igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); | ||
3815 | |||
3409 | return NETDEV_TX_OK; | 3816 | return NETDEV_TX_OK; |
3410 | } | 3817 | } |
3411 | 3818 | ||
@@ -3414,8 +3821,18 @@ static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, | |||
3414 | { | 3821 | { |
3415 | struct igb_adapter *adapter = netdev_priv(netdev); | 3822 | struct igb_adapter *adapter = netdev_priv(netdev); |
3416 | struct igb_ring *tx_ring; | 3823 | struct igb_ring *tx_ring; |
3417 | |||
3418 | int r_idx = 0; | 3824 | int r_idx = 0; |
3825 | |||
3826 | if (test_bit(__IGB_DOWN, &adapter->state)) { | ||
3827 | dev_kfree_skb_any(skb); | ||
3828 | return NETDEV_TX_OK; | ||
3829 | } | ||
3830 | |||
3831 | if (skb->len <= 0) { | ||
3832 | dev_kfree_skb_any(skb); | ||
3833 | return NETDEV_TX_OK; | ||
3834 | } | ||
3835 | |||
3419 | r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); | 3836 | r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); |
3420 | tx_ring = adapter->multi_tx_table[r_idx]; | 3837 | tx_ring = adapter->multi_tx_table[r_idx]; |
3421 | 3838 | ||
@@ -3423,7 +3840,7 @@ static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, | |||
3423 | * to a flow. Right now, performance is impacted slightly negatively | 3840 | * to a flow. Right now, performance is impacted slightly negatively |
3424 | * if using multiple tx queues. If the stack breaks away from a | 3841 | * if using multiple tx queues. If the stack breaks away from a |
3425 | * single qdisc implementation, we can look at this again. */ | 3842 | * single qdisc implementation, we can look at this again. */ |
3426 | return igb_xmit_frame_ring_adv(skb, netdev, tx_ring); | 3843 | return igb_xmit_frame_ring_adv(skb, tx_ring); |
3427 | } | 3844 | } |
3428 | 3845 | ||
3429 | /** | 3846 | /** |
@@ -3437,6 +3854,10 @@ static void igb_tx_timeout(struct net_device *netdev) | |||
3437 | 3854 | ||
3438 | /* Do the reset outside of interrupt context */ | 3855 | /* Do the reset outside of interrupt context */ |
3439 | adapter->tx_timeout_count++; | 3856 | adapter->tx_timeout_count++; |
3857 | |||
3858 | if (hw->mac.type == e1000_82580) | ||
3859 | hw->dev_spec._82575.global_device_reset = true; | ||
3860 | |||
3440 | schedule_work(&adapter->reset_task); | 3861 | schedule_work(&adapter->reset_task); |
3441 | wr32(E1000_EICS, | 3862 | wr32(E1000_EICS, |
3442 | (adapter->eims_enable_mask & ~adapter->eims_other)); | 3863 | (adapter->eims_enable_mask & ~adapter->eims_other)); |
@@ -3459,10 +3880,8 @@ static void igb_reset_task(struct work_struct *work) | |||
3459 | **/ | 3880 | **/ |
3460 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) | 3881 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) |
3461 | { | 3882 | { |
3462 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
3463 | |||
3464 | /* only return the current stats */ | 3883 | /* only return the current stats */ |
3465 | return &adapter->net_stats; | 3884 | return &netdev->stats; |
3466 | } | 3885 | } |
3467 | 3886 | ||
3468 | /** | 3887 | /** |
@@ -3475,16 +3894,17 @@ static struct net_device_stats *igb_get_stats(struct net_device *netdev) | |||
3475 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | 3894 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) |
3476 | { | 3895 | { |
3477 | struct igb_adapter *adapter = netdev_priv(netdev); | 3896 | struct igb_adapter *adapter = netdev_priv(netdev); |
3897 | struct pci_dev *pdev = adapter->pdev; | ||
3478 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | 3898 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
3899 | u32 rx_buffer_len, i; | ||
3479 | 3900 | ||
3480 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | 3901 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
3481 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | 3902 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
3482 | dev_err(&adapter->pdev->dev, "Invalid MTU setting\n"); | ||
3483 | return -EINVAL; | 3903 | return -EINVAL; |
3484 | } | 3904 | } |
3485 | 3905 | ||
3486 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { | 3906 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
3487 | dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n"); | 3907 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
3488 | return -EINVAL; | 3908 | return -EINVAL; |
3489 | } | 3909 | } |
3490 | 3910 | ||
@@ -3493,8 +3913,6 @@ static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |||
3493 | 3913 | ||
3494 | /* igb_down has a dependency on max_frame_size */ | 3914 | /* igb_down has a dependency on max_frame_size */ |
3495 | adapter->max_frame_size = max_frame; | 3915 | adapter->max_frame_size = max_frame; |
3496 | if (netif_running(netdev)) | ||
3497 | igb_down(adapter); | ||
3498 | 3916 | ||
3499 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN | 3917 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN |
3500 | * means we reserve 2 more, this pushes us to allocate from the next | 3918 | * means we reserve 2 more, this pushes us to allocate from the next |
@@ -3502,35 +3920,23 @@ static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |||
3502 | * i.e. RXBUFFER_2048 --> size-4096 slab | 3920 | * i.e. RXBUFFER_2048 --> size-4096 slab |
3503 | */ | 3921 | */ |
3504 | 3922 | ||
3505 | if (max_frame <= IGB_RXBUFFER_256) | 3923 | if (max_frame <= IGB_RXBUFFER_1024) |
3506 | adapter->rx_buffer_len = IGB_RXBUFFER_256; | 3924 | rx_buffer_len = IGB_RXBUFFER_1024; |
3507 | else if (max_frame <= IGB_RXBUFFER_512) | 3925 | else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE) |
3508 | adapter->rx_buffer_len = IGB_RXBUFFER_512; | 3926 | rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
3509 | else if (max_frame <= IGB_RXBUFFER_1024) | ||
3510 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | ||
3511 | else if (max_frame <= IGB_RXBUFFER_2048) | ||
3512 | adapter->rx_buffer_len = IGB_RXBUFFER_2048; | ||
3513 | else | 3927 | else |
3514 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 | 3928 | rx_buffer_len = IGB_RXBUFFER_128; |
3515 | adapter->rx_buffer_len = IGB_RXBUFFER_16384; | ||
3516 | #else | ||
3517 | adapter->rx_buffer_len = PAGE_SIZE / 2; | ||
3518 | #endif | ||
3519 | 3929 | ||
3520 | /* if sr-iov is enabled we need to force buffer size to 1K or larger */ | 3930 | if (netif_running(netdev)) |
3521 | if (adapter->vfs_allocated_count && | 3931 | igb_down(adapter); |
3522 | (adapter->rx_buffer_len < IGB_RXBUFFER_1024)) | ||
3523 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | ||
3524 | |||
3525 | /* adjust allocation if LPE protects us, and we aren't using SBP */ | ||
3526 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || | ||
3527 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) | ||
3528 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | ||
3529 | 3932 | ||
3530 | dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n", | 3933 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
3531 | netdev->mtu, new_mtu); | 3934 | netdev->mtu, new_mtu); |
3532 | netdev->mtu = new_mtu; | 3935 | netdev->mtu = new_mtu; |
3533 | 3936 | ||
3937 | for (i = 0; i < adapter->num_rx_queues; i++) | ||
3938 | adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len; | ||
3939 | |||
3534 | if (netif_running(netdev)) | 3940 | if (netif_running(netdev)) |
3535 | igb_up(adapter); | 3941 | igb_up(adapter); |
3536 | else | 3942 | else |
@@ -3548,9 +3954,13 @@ static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |||
3548 | 3954 | ||
3549 | void igb_update_stats(struct igb_adapter *adapter) | 3955 | void igb_update_stats(struct igb_adapter *adapter) |
3550 | { | 3956 | { |
3957 | struct net_device_stats *net_stats = igb_get_stats(adapter->netdev); | ||
3551 | struct e1000_hw *hw = &adapter->hw; | 3958 | struct e1000_hw *hw = &adapter->hw; |
3552 | struct pci_dev *pdev = adapter->pdev; | 3959 | struct pci_dev *pdev = adapter->pdev; |
3960 | u32 reg, mpc; | ||
3553 | u16 phy_tmp; | 3961 | u16 phy_tmp; |
3962 | int i; | ||
3963 | u64 bytes, packets; | ||
3554 | 3964 | ||
3555 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | 3965 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF |
3556 | 3966 | ||
@@ -3563,6 +3973,31 @@ void igb_update_stats(struct igb_adapter *adapter) | |||
3563 | if (pci_channel_offline(pdev)) | 3973 | if (pci_channel_offline(pdev)) |
3564 | return; | 3974 | return; |
3565 | 3975 | ||
3976 | bytes = 0; | ||
3977 | packets = 0; | ||
3978 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
3979 | u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF; | ||
3980 | struct igb_ring *ring = adapter->rx_ring[i]; | ||
3981 | ring->rx_stats.drops += rqdpc_tmp; | ||
3982 | net_stats->rx_fifo_errors += rqdpc_tmp; | ||
3983 | bytes += ring->rx_stats.bytes; | ||
3984 | packets += ring->rx_stats.packets; | ||
3985 | } | ||
3986 | |||
3987 | net_stats->rx_bytes = bytes; | ||
3988 | net_stats->rx_packets = packets; | ||
3989 | |||
3990 | bytes = 0; | ||
3991 | packets = 0; | ||
3992 | for (i = 0; i < adapter->num_tx_queues; i++) { | ||
3993 | struct igb_ring *ring = adapter->tx_ring[i]; | ||
3994 | bytes += ring->tx_stats.bytes; | ||
3995 | packets += ring->tx_stats.packets; | ||
3996 | } | ||
3997 | net_stats->tx_bytes = bytes; | ||
3998 | net_stats->tx_packets = packets; | ||
3999 | |||
4000 | /* read stats registers */ | ||
3566 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); | 4001 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
3567 | adapter->stats.gprc += rd32(E1000_GPRC); | 4002 | adapter->stats.gprc += rd32(E1000_GPRC); |
3568 | adapter->stats.gorc += rd32(E1000_GORCL); | 4003 | adapter->stats.gorc += rd32(E1000_GORCL); |
@@ -3580,7 +4015,9 @@ void igb_update_stats(struct igb_adapter *adapter) | |||
3580 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | 4015 | adapter->stats.symerrs += rd32(E1000_SYMERRS); |
3581 | adapter->stats.sec += rd32(E1000_SEC); | 4016 | adapter->stats.sec += rd32(E1000_SEC); |
3582 | 4017 | ||
3583 | adapter->stats.mpc += rd32(E1000_MPC); | 4018 | mpc = rd32(E1000_MPC); |
4019 | adapter->stats.mpc += mpc; | ||
4020 | net_stats->rx_fifo_errors += mpc; | ||
3584 | adapter->stats.scc += rd32(E1000_SCC); | 4021 | adapter->stats.scc += rd32(E1000_SCC); |
3585 | adapter->stats.ecol += rd32(E1000_ECOL); | 4022 | adapter->stats.ecol += rd32(E1000_ECOL); |
3586 | adapter->stats.mcc += rd32(E1000_MCC); | 4023 | adapter->stats.mcc += rd32(E1000_MCC); |
@@ -3613,16 +4050,17 @@ void igb_update_stats(struct igb_adapter *adapter) | |||
3613 | adapter->stats.mptc += rd32(E1000_MPTC); | 4050 | adapter->stats.mptc += rd32(E1000_MPTC); |
3614 | adapter->stats.bptc += rd32(E1000_BPTC); | 4051 | adapter->stats.bptc += rd32(E1000_BPTC); |
3615 | 4052 | ||
3616 | /* used for adaptive IFS */ | 4053 | adapter->stats.tpt += rd32(E1000_TPT); |
3617 | 4054 | adapter->stats.colc += rd32(E1000_COLC); | |
3618 | hw->mac.tx_packet_delta = rd32(E1000_TPT); | ||
3619 | adapter->stats.tpt += hw->mac.tx_packet_delta; | ||
3620 | hw->mac.collision_delta = rd32(E1000_COLC); | ||
3621 | adapter->stats.colc += hw->mac.collision_delta; | ||
3622 | 4055 | ||
3623 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | 4056 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); |
3624 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | 4057 | /* read internal phy specific stats */ |
3625 | adapter->stats.tncrs += rd32(E1000_TNCRS); | 4058 | reg = rd32(E1000_CTRL_EXT); |
4059 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | ||
4060 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | ||
4061 | adapter->stats.tncrs += rd32(E1000_TNCRS); | ||
4062 | } | ||
4063 | |||
3626 | adapter->stats.tsctc += rd32(E1000_TSCTC); | 4064 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
3627 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | 4065 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); |
3628 | 4066 | ||
@@ -3637,56 +4075,29 @@ void igb_update_stats(struct igb_adapter *adapter) | |||
3637 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | 4075 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); |
3638 | 4076 | ||
3639 | /* Fill out the OS statistics structure */ | 4077 | /* Fill out the OS statistics structure */ |
3640 | adapter->net_stats.multicast = adapter->stats.mprc; | 4078 | net_stats->multicast = adapter->stats.mprc; |
3641 | adapter->net_stats.collisions = adapter->stats.colc; | 4079 | net_stats->collisions = adapter->stats.colc; |
3642 | 4080 | ||
3643 | /* Rx Errors */ | 4081 | /* Rx Errors */ |
3644 | 4082 | ||
3645 | if (hw->mac.type != e1000_82575) { | ||
3646 | u32 rqdpc_tmp; | ||
3647 | u64 rqdpc_total = 0; | ||
3648 | int i; | ||
3649 | /* Read out drops stats per RX queue. Notice RQDPC (Receive | ||
3650 | * Queue Drop Packet Count) stats only gets incremented, if | ||
3651 | * the DROP_EN but it set (in the SRRCTL register for that | ||
3652 | * queue). If DROP_EN bit is NOT set, then the some what | ||
3653 | * equivalent count is stored in RNBC (not per queue basis). | ||
3654 | * Also note the drop count is due to lack of available | ||
3655 | * descriptors. | ||
3656 | */ | ||
3657 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
3658 | rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF; | ||
3659 | adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp; | ||
3660 | rqdpc_total += adapter->rx_ring[i].rx_stats.drops; | ||
3661 | } | ||
3662 | adapter->net_stats.rx_fifo_errors = rqdpc_total; | ||
3663 | } | ||
3664 | |||
3665 | /* Note RNBC (Receive No Buffers Count) is an not an exact | ||
3666 | * drop count as the hardware FIFO might save the day. Thats | ||
3667 | * one of the reason for saving it in rx_fifo_errors, as its | ||
3668 | * potentially not a true drop. | ||
3669 | */ | ||
3670 | adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc; | ||
3671 | |||
3672 | /* RLEC on some newer hardware can be incorrect so build | 4083 | /* RLEC on some newer hardware can be incorrect so build |
3673 | * our own version based on RUC and ROC */ | 4084 | * our own version based on RUC and ROC */ |
3674 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + | 4085 | net_stats->rx_errors = adapter->stats.rxerrc + |
3675 | adapter->stats.crcerrs + adapter->stats.algnerrc + | 4086 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
3676 | adapter->stats.ruc + adapter->stats.roc + | 4087 | adapter->stats.ruc + adapter->stats.roc + |
3677 | adapter->stats.cexterr; | 4088 | adapter->stats.cexterr; |
3678 | adapter->net_stats.rx_length_errors = adapter->stats.ruc + | 4089 | net_stats->rx_length_errors = adapter->stats.ruc + |
3679 | adapter->stats.roc; | 4090 | adapter->stats.roc; |
3680 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | 4091 | net_stats->rx_crc_errors = adapter->stats.crcerrs; |
3681 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; | 4092 | net_stats->rx_frame_errors = adapter->stats.algnerrc; |
3682 | adapter->net_stats.rx_missed_errors = adapter->stats.mpc; | 4093 | net_stats->rx_missed_errors = adapter->stats.mpc; |
3683 | 4094 | ||
3684 | /* Tx Errors */ | 4095 | /* Tx Errors */ |
3685 | adapter->net_stats.tx_errors = adapter->stats.ecol + | 4096 | net_stats->tx_errors = adapter->stats.ecol + |
3686 | adapter->stats.latecol; | 4097 | adapter->stats.latecol; |
3687 | adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; | 4098 | net_stats->tx_aborted_errors = adapter->stats.ecol; |
3688 | adapter->net_stats.tx_window_errors = adapter->stats.latecol; | 4099 | net_stats->tx_window_errors = adapter->stats.latecol; |
3689 | adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; | 4100 | net_stats->tx_carrier_errors = adapter->stats.tncrs; |
3690 | 4101 | ||
3691 | /* Tx Dropped needs to be maintained elsewhere */ | 4102 | /* Tx Dropped needs to be maintained elsewhere */ |
3692 | 4103 | ||
@@ -3707,14 +4118,15 @@ void igb_update_stats(struct igb_adapter *adapter) | |||
3707 | 4118 | ||
3708 | static irqreturn_t igb_msix_other(int irq, void *data) | 4119 | static irqreturn_t igb_msix_other(int irq, void *data) |
3709 | { | 4120 | { |
3710 | struct net_device *netdev = data; | 4121 | struct igb_adapter *adapter = data; |
3711 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
3712 | struct e1000_hw *hw = &adapter->hw; | 4122 | struct e1000_hw *hw = &adapter->hw; |
3713 | u32 icr = rd32(E1000_ICR); | 4123 | u32 icr = rd32(E1000_ICR); |
3714 | |||
3715 | /* reading ICR causes bit 31 of EICR to be cleared */ | 4124 | /* reading ICR causes bit 31 of EICR to be cleared */ |
3716 | 4125 | ||
3717 | if(icr & E1000_ICR_DOUTSYNC) { | 4126 | if (icr & E1000_ICR_DRSTA) |
4127 | schedule_work(&adapter->reset_task); | ||
4128 | |||
4129 | if (icr & E1000_ICR_DOUTSYNC) { | ||
3718 | /* HW is reporting DMA is out of sync */ | 4130 | /* HW is reporting DMA is out of sync */ |
3719 | adapter->stats.doosync++; | 4131 | adapter->stats.doosync++; |
3720 | } | 4132 | } |
@@ -3730,125 +4142,91 @@ static irqreturn_t igb_msix_other(int irq, void *data) | |||
3730 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | 4142 | mod_timer(&adapter->watchdog_timer, jiffies + 1); |
3731 | } | 4143 | } |
3732 | 4144 | ||
3733 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB); | 4145 | if (adapter->vfs_allocated_count) |
4146 | wr32(E1000_IMS, E1000_IMS_LSC | | ||
4147 | E1000_IMS_VMMB | | ||
4148 | E1000_IMS_DOUTSYNC); | ||
4149 | else | ||
4150 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); | ||
3734 | wr32(E1000_EIMS, adapter->eims_other); | 4151 | wr32(E1000_EIMS, adapter->eims_other); |
3735 | 4152 | ||
3736 | return IRQ_HANDLED; | 4153 | return IRQ_HANDLED; |
3737 | } | 4154 | } |
3738 | 4155 | ||
3739 | static irqreturn_t igb_msix_tx(int irq, void *data) | 4156 | static void igb_write_itr(struct igb_q_vector *q_vector) |
3740 | { | 4157 | { |
3741 | struct igb_ring *tx_ring = data; | 4158 | struct igb_adapter *adapter = q_vector->adapter; |
3742 | struct igb_adapter *adapter = tx_ring->adapter; | 4159 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
3743 | struct e1000_hw *hw = &adapter->hw; | ||
3744 | 4160 | ||
3745 | #ifdef CONFIG_IGB_DCA | 4161 | if (!q_vector->set_itr) |
3746 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) | 4162 | return; |
3747 | igb_update_tx_dca(tx_ring); | ||
3748 | #endif | ||
3749 | 4163 | ||
3750 | tx_ring->total_bytes = 0; | 4164 | if (!itr_val) |
3751 | tx_ring->total_packets = 0; | 4165 | itr_val = 0x4; |
3752 | 4166 | ||
3753 | /* auto mask will automatically reenable the interrupt when we write | 4167 | if (adapter->hw.mac.type == e1000_82575) |
3754 | * EICS */ | 4168 | itr_val |= itr_val << 16; |
3755 | if (!igb_clean_tx_irq(tx_ring)) | ||
3756 | /* Ring was not completely cleaned, so fire another interrupt */ | ||
3757 | wr32(E1000_EICS, tx_ring->eims_value); | ||
3758 | else | 4169 | else |
3759 | wr32(E1000_EIMS, tx_ring->eims_value); | 4170 | itr_val |= 0x8000000; |
3760 | 4171 | ||
3761 | return IRQ_HANDLED; | 4172 | writel(itr_val, q_vector->itr_register); |
3762 | } | 4173 | q_vector->set_itr = 0; |
3763 | |||
3764 | static void igb_write_itr(struct igb_ring *ring) | ||
3765 | { | ||
3766 | struct e1000_hw *hw = &ring->adapter->hw; | ||
3767 | if ((ring->adapter->itr_setting & 3) && ring->set_itr) { | ||
3768 | switch (hw->mac.type) { | ||
3769 | case e1000_82576: | ||
3770 | wr32(ring->itr_register, ring->itr_val | | ||
3771 | 0x80000000); | ||
3772 | break; | ||
3773 | default: | ||
3774 | wr32(ring->itr_register, ring->itr_val | | ||
3775 | (ring->itr_val << 16)); | ||
3776 | break; | ||
3777 | } | ||
3778 | ring->set_itr = 0; | ||
3779 | } | ||
3780 | } | 4174 | } |
3781 | 4175 | ||
3782 | static irqreturn_t igb_msix_rx(int irq, void *data) | 4176 | static irqreturn_t igb_msix_ring(int irq, void *data) |
3783 | { | 4177 | { |
3784 | struct igb_ring *rx_ring = data; | 4178 | struct igb_q_vector *q_vector = data; |
3785 | 4179 | ||
3786 | /* Write the ITR value calculated at the end of the | 4180 | /* Write the ITR value calculated from the previous interrupt. */ |
3787 | * previous interrupt. | 4181 | igb_write_itr(q_vector); |
3788 | */ | ||
3789 | 4182 | ||
3790 | igb_write_itr(rx_ring); | 4183 | napi_schedule(&q_vector->napi); |
3791 | 4184 | ||
3792 | if (napi_schedule_prep(&rx_ring->napi)) | 4185 | return IRQ_HANDLED; |
3793 | __napi_schedule(&rx_ring->napi); | ||
3794 | |||
3795 | #ifdef CONFIG_IGB_DCA | ||
3796 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) | ||
3797 | igb_update_rx_dca(rx_ring); | ||
3798 | #endif | ||
3799 | return IRQ_HANDLED; | ||
3800 | } | 4186 | } |
3801 | 4187 | ||
3802 | #ifdef CONFIG_IGB_DCA | 4188 | #ifdef CONFIG_IGB_DCA |
3803 | static void igb_update_rx_dca(struct igb_ring *rx_ring) | 4189 | static void igb_update_dca(struct igb_q_vector *q_vector) |
3804 | { | 4190 | { |
3805 | u32 dca_rxctrl; | 4191 | struct igb_adapter *adapter = q_vector->adapter; |
3806 | struct igb_adapter *adapter = rx_ring->adapter; | ||
3807 | struct e1000_hw *hw = &adapter->hw; | 4192 | struct e1000_hw *hw = &adapter->hw; |
3808 | int cpu = get_cpu(); | 4193 | int cpu = get_cpu(); |
3809 | int q = rx_ring->reg_idx; | ||
3810 | 4194 | ||
3811 | if (rx_ring->cpu != cpu) { | 4195 | if (q_vector->cpu == cpu) |
3812 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | 4196 | goto out_no_update; |
3813 | if (hw->mac.type == e1000_82576) { | 4197 | |
3814 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | 4198 | if (q_vector->tx_ring) { |
3815 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | 4199 | int q = q_vector->tx_ring->reg_idx; |
3816 | E1000_DCA_RXCTRL_CPUID_SHIFT; | 4200 | u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); |
4201 | if (hw->mac.type == e1000_82575) { | ||
4202 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | ||
4203 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | ||
3817 | } else { | 4204 | } else { |
4205 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; | ||
4206 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | ||
4207 | E1000_DCA_TXCTRL_CPUID_SHIFT; | ||
4208 | } | ||
4209 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; | ||
4210 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | ||
4211 | } | ||
4212 | if (q_vector->rx_ring) { | ||
4213 | int q = q_vector->rx_ring->reg_idx; | ||
4214 | u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | ||
4215 | if (hw->mac.type == e1000_82575) { | ||
3818 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | 4216 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; |
3819 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | 4217 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
4218 | } else { | ||
4219 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | ||
4220 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | ||
4221 | E1000_DCA_RXCTRL_CPUID_SHIFT; | ||
3820 | } | 4222 | } |
3821 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; | 4223 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
3822 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | 4224 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; |
3823 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | 4225 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; |
3824 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | 4226 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); |
3825 | rx_ring->cpu = cpu; | ||
3826 | } | ||
3827 | put_cpu(); | ||
3828 | } | ||
3829 | |||
3830 | static void igb_update_tx_dca(struct igb_ring *tx_ring) | ||
3831 | { | ||
3832 | u32 dca_txctrl; | ||
3833 | struct igb_adapter *adapter = tx_ring->adapter; | ||
3834 | struct e1000_hw *hw = &adapter->hw; | ||
3835 | int cpu = get_cpu(); | ||
3836 | int q = tx_ring->reg_idx; | ||
3837 | |||
3838 | if (tx_ring->cpu != cpu) { | ||
3839 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | ||
3840 | if (hw->mac.type == e1000_82576) { | ||
3841 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; | ||
3842 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | ||
3843 | E1000_DCA_TXCTRL_CPUID_SHIFT; | ||
3844 | } else { | ||
3845 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | ||
3846 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | ||
3847 | } | ||
3848 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; | ||
3849 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | ||
3850 | tx_ring->cpu = cpu; | ||
3851 | } | 4227 | } |
4228 | q_vector->cpu = cpu; | ||
4229 | out_no_update: | ||
3852 | put_cpu(); | 4230 | put_cpu(); |
3853 | } | 4231 | } |
3854 | 4232 | ||
@@ -3863,13 +4241,9 @@ static void igb_setup_dca(struct igb_adapter *adapter) | |||
3863 | /* Always use CB2 mode, difference is masked in the CB driver. */ | 4241 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
3864 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | 4242 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
3865 | 4243 | ||
3866 | for (i = 0; i < adapter->num_tx_queues; i++) { | 4244 | for (i = 0; i < adapter->num_q_vectors; i++) { |
3867 | adapter->tx_ring[i].cpu = -1; | 4245 | adapter->q_vector[i]->cpu = -1; |
3868 | igb_update_tx_dca(&adapter->tx_ring[i]); | 4246 | igb_update_dca(adapter->q_vector[i]); |
3869 | } | ||
3870 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
3871 | adapter->rx_ring[i].cpu = -1; | ||
3872 | igb_update_rx_dca(&adapter->rx_ring[i]); | ||
3873 | } | 4247 | } |
3874 | } | 4248 | } |
3875 | 4249 | ||
@@ -3877,6 +4251,7 @@ static int __igb_notify_dca(struct device *dev, void *data) | |||
3877 | { | 4251 | { |
3878 | struct net_device *netdev = dev_get_drvdata(dev); | 4252 | struct net_device *netdev = dev_get_drvdata(dev); |
3879 | struct igb_adapter *adapter = netdev_priv(netdev); | 4253 | struct igb_adapter *adapter = netdev_priv(netdev); |
4254 | struct pci_dev *pdev = adapter->pdev; | ||
3880 | struct e1000_hw *hw = &adapter->hw; | 4255 | struct e1000_hw *hw = &adapter->hw; |
3881 | unsigned long event = *(unsigned long *)data; | 4256 | unsigned long event = *(unsigned long *)data; |
3882 | 4257 | ||
@@ -3885,12 +4260,9 @@ static int __igb_notify_dca(struct device *dev, void *data) | |||
3885 | /* if already enabled, don't do it again */ | 4260 | /* if already enabled, don't do it again */ |
3886 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) | 4261 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
3887 | break; | 4262 | break; |
3888 | /* Always use CB2 mode, difference is masked | ||
3889 | * in the CB driver. */ | ||
3890 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | ||
3891 | if (dca_add_requester(dev) == 0) { | 4263 | if (dca_add_requester(dev) == 0) { |
3892 | adapter->flags |= IGB_FLAG_DCA_ENABLED; | 4264 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
3893 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); | 4265 | dev_info(&pdev->dev, "DCA enabled\n"); |
3894 | igb_setup_dca(adapter); | 4266 | igb_setup_dca(adapter); |
3895 | break; | 4267 | break; |
3896 | } | 4268 | } |
@@ -3898,9 +4270,9 @@ static int __igb_notify_dca(struct device *dev, void *data) | |||
3898 | case DCA_PROVIDER_REMOVE: | 4270 | case DCA_PROVIDER_REMOVE: |
3899 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { | 4271 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
3900 | /* without this a class_device is left | 4272 | /* without this a class_device is left |
3901 | * hanging around in the sysfs model */ | 4273 | * hanging around in the sysfs model */ |
3902 | dca_remove_requester(dev); | 4274 | dca_remove_requester(dev); |
3903 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); | 4275 | dev_info(&pdev->dev, "DCA disabled\n"); |
3904 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; | 4276 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
3905 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); | 4277 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
3906 | } | 4278 | } |
@@ -3930,12 +4302,51 @@ static void igb_ping_all_vfs(struct igb_adapter *adapter) | |||
3930 | 4302 | ||
3931 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | 4303 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { |
3932 | ping = E1000_PF_CONTROL_MSG; | 4304 | ping = E1000_PF_CONTROL_MSG; |
3933 | if (adapter->vf_data[i].clear_to_send) | 4305 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
3934 | ping |= E1000_VT_MSGTYPE_CTS; | 4306 | ping |= E1000_VT_MSGTYPE_CTS; |
3935 | igb_write_mbx(hw, &ping, 1, i); | 4307 | igb_write_mbx(hw, &ping, 1, i); |
3936 | } | 4308 | } |
3937 | } | 4309 | } |
3938 | 4310 | ||
4311 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | ||
4312 | { | ||
4313 | struct e1000_hw *hw = &adapter->hw; | ||
4314 | u32 vmolr = rd32(E1000_VMOLR(vf)); | ||
4315 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | ||
4316 | |||
4317 | vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC | | ||
4318 | IGB_VF_FLAG_MULTI_PROMISC); | ||
4319 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | ||
4320 | |||
4321 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | ||
4322 | vmolr |= E1000_VMOLR_MPME; | ||
4323 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; | ||
4324 | } else { | ||
4325 | /* | ||
4326 | * if we have hashes and we are clearing a multicast promisc | ||
4327 | * flag we need to write the hashes to the MTA as this step | ||
4328 | * was previously skipped | ||
4329 | */ | ||
4330 | if (vf_data->num_vf_mc_hashes > 30) { | ||
4331 | vmolr |= E1000_VMOLR_MPME; | ||
4332 | } else if (vf_data->num_vf_mc_hashes) { | ||
4333 | int j; | ||
4334 | vmolr |= E1000_VMOLR_ROMPE; | ||
4335 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | ||
4336 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | ||
4337 | } | ||
4338 | } | ||
4339 | |||
4340 | wr32(E1000_VMOLR(vf), vmolr); | ||
4341 | |||
4342 | /* there are flags left unprocessed, likely not supported */ | ||
4343 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | ||
4344 | return -EINVAL; | ||
4345 | |||
4346 | return 0; | ||
4347 | |||
4348 | } | ||
4349 | |||
3939 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, | 4350 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
3940 | u32 *msgbuf, u32 vf) | 4351 | u32 *msgbuf, u32 vf) |
3941 | { | 4352 | { |
@@ -3944,18 +4355,17 @@ static int igb_set_vf_multicasts(struct igb_adapter *adapter, | |||
3944 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | 4355 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
3945 | int i; | 4356 | int i; |
3946 | 4357 | ||
3947 | /* only up to 30 hash values supported */ | 4358 | /* salt away the number of multicast addresses assigned |
3948 | if (n > 30) | ||
3949 | n = 30; | ||
3950 | |||
3951 | /* salt away the number of multi cast addresses assigned | ||
3952 | * to this VF for later use to restore when the PF multi cast | 4359 | * to this VF for later use to restore when the PF multi cast |
3953 | * list changes | 4360 | * list changes |
3954 | */ | 4361 | */ |
3955 | vf_data->num_vf_mc_hashes = n; | 4362 | vf_data->num_vf_mc_hashes = n; |
3956 | 4363 | ||
3957 | /* VFs are limited to using the MTA hash table for their multicast | 4364 | /* only up to 30 hash values supported */ |
3958 | * addresses */ | 4365 | if (n > 30) |
4366 | n = 30; | ||
4367 | |||
4368 | /* store the hashes for later use */ | ||
3959 | for (i = 0; i < n; i++) | 4369 | for (i = 0; i < n; i++) |
3960 | vf_data->vf_mc_hashes[i] = hash_list[i]; | 4370 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
3961 | 4371 | ||
@@ -3972,9 +4382,20 @@ static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |||
3972 | int i, j; | 4382 | int i, j; |
3973 | 4383 | ||
3974 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | 4384 | for (i = 0; i < adapter->vfs_allocated_count; i++) { |
4385 | u32 vmolr = rd32(E1000_VMOLR(i)); | ||
4386 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | ||
4387 | |||
3975 | vf_data = &adapter->vf_data[i]; | 4388 | vf_data = &adapter->vf_data[i]; |
3976 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | 4389 | |
3977 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | 4390 | if ((vf_data->num_vf_mc_hashes > 30) || |
4391 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | ||
4392 | vmolr |= E1000_VMOLR_MPME; | ||
4393 | } else if (vf_data->num_vf_mc_hashes) { | ||
4394 | vmolr |= E1000_VMOLR_ROMPE; | ||
4395 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | ||
4396 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | ||
4397 | } | ||
4398 | wr32(E1000_VMOLR(i), vmolr); | ||
3978 | } | 4399 | } |
3979 | } | 4400 | } |
3980 | 4401 | ||
@@ -4012,7 +4433,11 @@ static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |||
4012 | struct e1000_hw *hw = &adapter->hw; | 4433 | struct e1000_hw *hw = &adapter->hw; |
4013 | u32 reg, i; | 4434 | u32 reg, i; |
4014 | 4435 | ||
4015 | /* It is an error to call this function when VFs are not enabled */ | 4436 | /* The vlvf table only exists on 82576 hardware and newer */ |
4437 | if (hw->mac.type < e1000_82576) | ||
4438 | return -1; | ||
4439 | |||
4440 | /* we only need to do this if VMDq is enabled */ | ||
4016 | if (!adapter->vfs_allocated_count) | 4441 | if (!adapter->vfs_allocated_count) |
4017 | return -1; | 4442 | return -1; |
4018 | 4443 | ||
@@ -4042,16 +4467,12 @@ static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |||
4042 | 4467 | ||
4043 | /* if !enabled we need to set this up in vfta */ | 4468 | /* if !enabled we need to set this up in vfta */ |
4044 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | 4469 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { |
4045 | /* add VID to filter table, if bit already set | 4470 | /* add VID to filter table */ |
4046 | * PF must have added it outside of table */ | 4471 | igb_vfta_set(hw, vid, true); |
4047 | if (igb_vfta_set(hw, vid, true)) | ||
4048 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + | ||
4049 | adapter->vfs_allocated_count); | ||
4050 | reg |= E1000_VLVF_VLANID_ENABLE; | 4472 | reg |= E1000_VLVF_VLANID_ENABLE; |
4051 | } | 4473 | } |
4052 | reg &= ~E1000_VLVF_VLANID_MASK; | 4474 | reg &= ~E1000_VLVF_VLANID_MASK; |
4053 | reg |= vid; | 4475 | reg |= vid; |
4054 | |||
4055 | wr32(E1000_VLVF(i), reg); | 4476 | wr32(E1000_VLVF(i), reg); |
4056 | 4477 | ||
4057 | /* do not modify RLPML for PF devices */ | 4478 | /* do not modify RLPML for PF devices */ |
@@ -4067,8 +4488,8 @@ static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |||
4067 | reg |= size; | 4488 | reg |= size; |
4068 | wr32(E1000_VMOLR(vf), reg); | 4489 | wr32(E1000_VMOLR(vf), reg); |
4069 | } | 4490 | } |
4070 | adapter->vf_data[vf].vlans_enabled++; | ||
4071 | 4491 | ||
4492 | adapter->vf_data[vf].vlans_enabled++; | ||
4072 | return 0; | 4493 | return 0; |
4073 | } | 4494 | } |
4074 | } else { | 4495 | } else { |
@@ -4096,10 +4517,57 @@ static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |||
4096 | reg |= size; | 4517 | reg |= size; |
4097 | wr32(E1000_VMOLR(vf), reg); | 4518 | wr32(E1000_VMOLR(vf), reg); |
4098 | } | 4519 | } |
4099 | return 0; | ||
4100 | } | 4520 | } |
4101 | } | 4521 | } |
4102 | return -1; | 4522 | return 0; |
4523 | } | ||
4524 | |||
4525 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | ||
4526 | { | ||
4527 | struct e1000_hw *hw = &adapter->hw; | ||
4528 | |||
4529 | if (vid) | ||
4530 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | ||
4531 | else | ||
4532 | wr32(E1000_VMVIR(vf), 0); | ||
4533 | } | ||
4534 | |||
4535 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | ||
4536 | int vf, u16 vlan, u8 qos) | ||
4537 | { | ||
4538 | int err = 0; | ||
4539 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
4540 | |||
4541 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | ||
4542 | return -EINVAL; | ||
4543 | if (vlan || qos) { | ||
4544 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | ||
4545 | if (err) | ||
4546 | goto out; | ||
4547 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | ||
4548 | igb_set_vmolr(adapter, vf, !vlan); | ||
4549 | adapter->vf_data[vf].pf_vlan = vlan; | ||
4550 | adapter->vf_data[vf].pf_qos = qos; | ||
4551 | dev_info(&adapter->pdev->dev, | ||
4552 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | ||
4553 | if (test_bit(__IGB_DOWN, &adapter->state)) { | ||
4554 | dev_warn(&adapter->pdev->dev, | ||
4555 | "The VF VLAN has been set," | ||
4556 | " but the PF device is not up.\n"); | ||
4557 | dev_warn(&adapter->pdev->dev, | ||
4558 | "Bring the PF device up before" | ||
4559 | " attempting to use the VF device.\n"); | ||
4560 | } | ||
4561 | } else { | ||
4562 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | ||
4563 | false, vf); | ||
4564 | igb_set_vmvir(adapter, vlan, vf); | ||
4565 | igb_set_vmolr(adapter, vf, true); | ||
4566 | adapter->vf_data[vf].pf_vlan = 0; | ||
4567 | adapter->vf_data[vf].pf_qos = 0; | ||
4568 | } | ||
4569 | out: | ||
4570 | return err; | ||
4103 | } | 4571 | } |
4104 | 4572 | ||
4105 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | 4573 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
@@ -4110,18 +4578,23 @@ static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |||
4110 | return igb_vlvf_set(adapter, vid, add, vf); | 4578 | return igb_vlvf_set(adapter, vid, add, vf); |
4111 | } | 4579 | } |
4112 | 4580 | ||
4113 | static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) | 4581 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4114 | { | 4582 | { |
4115 | struct e1000_hw *hw = &adapter->hw; | 4583 | /* clear flags */ |
4116 | 4584 | adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC); | |
4117 | /* disable mailbox functionality for vf */ | 4585 | adapter->vf_data[vf].last_nack = jiffies; |
4118 | adapter->vf_data[vf].clear_to_send = false; | ||
4119 | 4586 | ||
4120 | /* reset offloads to defaults */ | 4587 | /* reset offloads to defaults */ |
4121 | igb_set_vmolr(hw, vf); | 4588 | igb_set_vmolr(adapter, vf, true); |
4122 | 4589 | ||
4123 | /* reset vlans for device */ | 4590 | /* reset vlans for device */ |
4124 | igb_clear_vf_vfta(adapter, vf); | 4591 | igb_clear_vf_vfta(adapter, vf); |
4592 | if (adapter->vf_data[vf].pf_vlan) | ||
4593 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | ||
4594 | adapter->vf_data[vf].pf_vlan, | ||
4595 | adapter->vf_data[vf].pf_qos); | ||
4596 | else | ||
4597 | igb_clear_vf_vfta(adapter, vf); | ||
4125 | 4598 | ||
4126 | /* reset multicast table array for vf */ | 4599 | /* reset multicast table array for vf */ |
4127 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | 4600 | adapter->vf_data[vf].num_vf_mc_hashes = 0; |
@@ -4130,7 +4603,19 @@ static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) | |||
4130 | igb_set_rx_mode(adapter->netdev); | 4603 | igb_set_rx_mode(adapter->netdev); |
4131 | } | 4604 | } |
4132 | 4605 | ||
4133 | static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | 4606 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
4607 | { | ||
4608 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | ||
4609 | |||
4610 | /* generate a new mac address as we were hotplug removed/added */ | ||
4611 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) | ||
4612 | random_ether_addr(vf_mac); | ||
4613 | |||
4614 | /* process remaining reset events */ | ||
4615 | igb_vf_reset(adapter, vf); | ||
4616 | } | ||
4617 | |||
4618 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | ||
4134 | { | 4619 | { |
4135 | struct e1000_hw *hw = &adapter->hw; | 4620 | struct e1000_hw *hw = &adapter->hw; |
4136 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | 4621 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; |
@@ -4139,11 +4624,10 @@ static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |||
4139 | u8 *addr = (u8 *)(&msgbuf[1]); | 4624 | u8 *addr = (u8 *)(&msgbuf[1]); |
4140 | 4625 | ||
4141 | /* process all the same items cleared in a function level reset */ | 4626 | /* process all the same items cleared in a function level reset */ |
4142 | igb_vf_reset_event(adapter, vf); | 4627 | igb_vf_reset(adapter, vf); |
4143 | 4628 | ||
4144 | /* set vf mac address */ | 4629 | /* set vf mac address */ |
4145 | igb_rar_set(hw, vf_mac, rar_entry); | 4630 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4146 | igb_set_rah_pool(hw, vf, rar_entry); | ||
4147 | 4631 | ||
4148 | /* enable transmit and receive for vf */ | 4632 | /* enable transmit and receive for vf */ |
4149 | reg = rd32(E1000_VFTE); | 4633 | reg = rd32(E1000_VFTE); |
@@ -4151,8 +4635,7 @@ static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |||
4151 | reg = rd32(E1000_VFRE); | 4635 | reg = rd32(E1000_VFRE); |
4152 | wr32(E1000_VFRE, reg | (1 << vf)); | 4636 | wr32(E1000_VFRE, reg | (1 << vf)); |
4153 | 4637 | ||
4154 | /* enable mailbox functionality for vf */ | 4638 | adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS; |
4155 | adapter->vf_data[vf].clear_to_send = true; | ||
4156 | 4639 | ||
4157 | /* reply to reset with ack and vf mac address */ | 4640 | /* reply to reset with ack and vf mac address */ |
4158 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | 4641 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; |
@@ -4162,66 +4645,51 @@ static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |||
4162 | 4645 | ||
4163 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | 4646 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) |
4164 | { | 4647 | { |
4165 | unsigned char *addr = (char *)&msg[1]; | 4648 | unsigned char *addr = (char *)&msg[1]; |
4166 | int err = -1; | 4649 | int err = -1; |
4167 | 4650 | ||
4168 | if (is_valid_ether_addr(addr)) | 4651 | if (is_valid_ether_addr(addr)) |
4169 | err = igb_set_vf_mac(adapter, vf, addr); | 4652 | err = igb_set_vf_mac(adapter, vf, addr); |
4170 | |||
4171 | return err; | ||
4172 | 4653 | ||
4654 | return err; | ||
4173 | } | 4655 | } |
4174 | 4656 | ||
4175 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | 4657 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) |
4176 | { | 4658 | { |
4177 | struct e1000_hw *hw = &adapter->hw; | 4659 | struct e1000_hw *hw = &adapter->hw; |
4660 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | ||
4178 | u32 msg = E1000_VT_MSGTYPE_NACK; | 4661 | u32 msg = E1000_VT_MSGTYPE_NACK; |
4179 | 4662 | ||
4180 | /* if device isn't clear to send it shouldn't be reading either */ | 4663 | /* if device isn't clear to send it shouldn't be reading either */ |
4181 | if (!adapter->vf_data[vf].clear_to_send) | 4664 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
4665 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | ||
4182 | igb_write_mbx(hw, &msg, 1, vf); | 4666 | igb_write_mbx(hw, &msg, 1, vf); |
4183 | } | 4667 | vf_data->last_nack = jiffies; |
4184 | |||
4185 | |||
4186 | static void igb_msg_task(struct igb_adapter *adapter) | ||
4187 | { | ||
4188 | struct e1000_hw *hw = &adapter->hw; | ||
4189 | u32 vf; | ||
4190 | |||
4191 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | ||
4192 | /* process any reset requests */ | ||
4193 | if (!igb_check_for_rst(hw, vf)) { | ||
4194 | adapter->vf_data[vf].clear_to_send = false; | ||
4195 | igb_vf_reset_event(adapter, vf); | ||
4196 | } | ||
4197 | |||
4198 | /* process any messages pending */ | ||
4199 | if (!igb_check_for_msg(hw, vf)) | ||
4200 | igb_rcv_msg_from_vf(adapter, vf); | ||
4201 | |||
4202 | /* process any acks */ | ||
4203 | if (!igb_check_for_ack(hw, vf)) | ||
4204 | igb_rcv_ack_from_vf(adapter, vf); | ||
4205 | |||
4206 | } | 4668 | } |
4207 | } | 4669 | } |
4208 | 4670 | ||
4209 | static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) | 4671 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4210 | { | 4672 | { |
4211 | u32 mbx_size = E1000_VFMAILBOX_SIZE; | 4673 | struct pci_dev *pdev = adapter->pdev; |
4212 | u32 msgbuf[mbx_size]; | 4674 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; |
4213 | struct e1000_hw *hw = &adapter->hw; | 4675 | struct e1000_hw *hw = &adapter->hw; |
4676 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | ||
4214 | s32 retval; | 4677 | s32 retval; |
4215 | 4678 | ||
4216 | retval = igb_read_mbx(hw, msgbuf, mbx_size, vf); | 4679 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4217 | 4680 | ||
4218 | if (retval) | 4681 | if (retval) { |
4219 | dev_err(&adapter->pdev->dev, | 4682 | /* if receive failed revoke VF CTS stats and restart init */ |
4220 | "Error receiving message from VF\n"); | 4683 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
4684 | vf_data->flags &= ~IGB_VF_FLAG_CTS; | ||
4685 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | ||
4686 | return; | ||
4687 | goto out; | ||
4688 | } | ||
4221 | 4689 | ||
4222 | /* this is a message we already processed, do nothing */ | 4690 | /* this is a message we already processed, do nothing */ |
4223 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | 4691 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) |
4224 | return retval; | 4692 | return; |
4225 | 4693 | ||
4226 | /* | 4694 | /* |
4227 | * until the vf completes a reset it should not be | 4695 | * until the vf completes a reset it should not be |
@@ -4230,20 +4698,23 @@ static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) | |||
4230 | 4698 | ||
4231 | if (msgbuf[0] == E1000_VF_RESET) { | 4699 | if (msgbuf[0] == E1000_VF_RESET) { |
4232 | igb_vf_reset_msg(adapter, vf); | 4700 | igb_vf_reset_msg(adapter, vf); |
4233 | 4701 | return; | |
4234 | return retval; | ||
4235 | } | 4702 | } |
4236 | 4703 | ||
4237 | if (!adapter->vf_data[vf].clear_to_send) { | 4704 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
4238 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | 4705 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
4239 | igb_write_mbx(hw, msgbuf, 1, vf); | 4706 | return; |
4240 | return retval; | 4707 | retval = -1; |
4708 | goto out; | ||
4241 | } | 4709 | } |
4242 | 4710 | ||
4243 | switch ((msgbuf[0] & 0xFFFF)) { | 4711 | switch ((msgbuf[0] & 0xFFFF)) { |
4244 | case E1000_VF_SET_MAC_ADDR: | 4712 | case E1000_VF_SET_MAC_ADDR: |
4245 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | 4713 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); |
4246 | break; | 4714 | break; |
4715 | case E1000_VF_SET_PROMISC: | ||
4716 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | ||
4717 | break; | ||
4247 | case E1000_VF_SET_MULTICAST: | 4718 | case E1000_VF_SET_MULTICAST: |
4248 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | 4719 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); |
4249 | break; | 4720 | break; |
@@ -4251,25 +4722,73 @@ static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) | |||
4251 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | 4722 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); |
4252 | break; | 4723 | break; |
4253 | case E1000_VF_SET_VLAN: | 4724 | case E1000_VF_SET_VLAN: |
4254 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | 4725 | if (adapter->vf_data[vf].pf_vlan) |
4726 | retval = -1; | ||
4727 | else | ||
4728 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | ||
4255 | break; | 4729 | break; |
4256 | default: | 4730 | default: |
4257 | dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); | 4731 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4258 | retval = -1; | 4732 | retval = -1; |
4259 | break; | 4733 | break; |
4260 | } | 4734 | } |
4261 | 4735 | ||
4736 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; | ||
4737 | out: | ||
4262 | /* notify the VF of the results of what it sent us */ | 4738 | /* notify the VF of the results of what it sent us */ |
4263 | if (retval) | 4739 | if (retval) |
4264 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | 4740 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; |
4265 | else | 4741 | else |
4266 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | 4742 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; |
4267 | 4743 | ||
4268 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; | ||
4269 | |||
4270 | igb_write_mbx(hw, msgbuf, 1, vf); | 4744 | igb_write_mbx(hw, msgbuf, 1, vf); |
4745 | } | ||
4271 | 4746 | ||
4272 | return retval; | 4747 | static void igb_msg_task(struct igb_adapter *adapter) |
4748 | { | ||
4749 | struct e1000_hw *hw = &adapter->hw; | ||
4750 | u32 vf; | ||
4751 | |||
4752 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | ||
4753 | /* process any reset requests */ | ||
4754 | if (!igb_check_for_rst(hw, vf)) | ||
4755 | igb_vf_reset_event(adapter, vf); | ||
4756 | |||
4757 | /* process any messages pending */ | ||
4758 | if (!igb_check_for_msg(hw, vf)) | ||
4759 | igb_rcv_msg_from_vf(adapter, vf); | ||
4760 | |||
4761 | /* process any acks */ | ||
4762 | if (!igb_check_for_ack(hw, vf)) | ||
4763 | igb_rcv_ack_from_vf(adapter, vf); | ||
4764 | } | ||
4765 | } | ||
4766 | |||
4767 | /** | ||
4768 | * igb_set_uta - Set unicast filter table address | ||
4769 | * @adapter: board private structure | ||
4770 | * | ||
4771 | * The unicast table address is a register array of 32-bit registers. | ||
4772 | * The table is meant to be used in a way similar to how the MTA is used | ||
4773 | * however due to certain limitations in the hardware it is necessary to | ||
4774 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous | ||
4775 | * enable bit to allow vlan tag stripping when promiscous mode is enabled | ||
4776 | **/ | ||
4777 | static void igb_set_uta(struct igb_adapter *adapter) | ||
4778 | { | ||
4779 | struct e1000_hw *hw = &adapter->hw; | ||
4780 | int i; | ||
4781 | |||
4782 | /* The UTA table only exists on 82576 hardware and newer */ | ||
4783 | if (hw->mac.type < e1000_82576) | ||
4784 | return; | ||
4785 | |||
4786 | /* we only need to do this if VMDq is enabled */ | ||
4787 | if (!adapter->vfs_allocated_count) | ||
4788 | return; | ||
4789 | |||
4790 | for (i = 0; i < hw->mac.uta_reg_count; i++) | ||
4791 | array_wr32(E1000_UTA, i, ~0); | ||
4273 | } | 4792 | } |
4274 | 4793 | ||
4275 | /** | 4794 | /** |
@@ -4279,15 +4798,18 @@ static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) | |||
4279 | **/ | 4798 | **/ |
4280 | static irqreturn_t igb_intr_msi(int irq, void *data) | 4799 | static irqreturn_t igb_intr_msi(int irq, void *data) |
4281 | { | 4800 | { |
4282 | struct net_device *netdev = data; | 4801 | struct igb_adapter *adapter = data; |
4283 | struct igb_adapter *adapter = netdev_priv(netdev); | 4802 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
4284 | struct e1000_hw *hw = &adapter->hw; | 4803 | struct e1000_hw *hw = &adapter->hw; |
4285 | /* read ICR disables interrupts using IAM */ | 4804 | /* read ICR disables interrupts using IAM */ |
4286 | u32 icr = rd32(E1000_ICR); | 4805 | u32 icr = rd32(E1000_ICR); |
4287 | 4806 | ||
4288 | igb_write_itr(adapter->rx_ring); | 4807 | igb_write_itr(q_vector); |
4808 | |||
4809 | if (icr & E1000_ICR_DRSTA) | ||
4810 | schedule_work(&adapter->reset_task); | ||
4289 | 4811 | ||
4290 | if(icr & E1000_ICR_DOUTSYNC) { | 4812 | if (icr & E1000_ICR_DOUTSYNC) { |
4291 | /* HW is reporting DMA is out of sync */ | 4813 | /* HW is reporting DMA is out of sync */ |
4292 | adapter->stats.doosync++; | 4814 | adapter->stats.doosync++; |
4293 | } | 4815 | } |
@@ -4298,7 +4820,7 @@ static irqreturn_t igb_intr_msi(int irq, void *data) | |||
4298 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | 4820 | mod_timer(&adapter->watchdog_timer, jiffies + 1); |
4299 | } | 4821 | } |
4300 | 4822 | ||
4301 | napi_schedule(&adapter->rx_ring[0].napi); | 4823 | napi_schedule(&q_vector->napi); |
4302 | 4824 | ||
4303 | return IRQ_HANDLED; | 4825 | return IRQ_HANDLED; |
4304 | } | 4826 | } |
@@ -4310,8 +4832,8 @@ static irqreturn_t igb_intr_msi(int irq, void *data) | |||
4310 | **/ | 4832 | **/ |
4311 | static irqreturn_t igb_intr(int irq, void *data) | 4833 | static irqreturn_t igb_intr(int irq, void *data) |
4312 | { | 4834 | { |
4313 | struct net_device *netdev = data; | 4835 | struct igb_adapter *adapter = data; |
4314 | struct igb_adapter *adapter = netdev_priv(netdev); | 4836 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
4315 | struct e1000_hw *hw = &adapter->hw; | 4837 | struct e1000_hw *hw = &adapter->hw; |
4316 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | 4838 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No |
4317 | * need for the IMC write */ | 4839 | * need for the IMC write */ |
@@ -4319,14 +4841,17 @@ static irqreturn_t igb_intr(int irq, void *data) | |||
4319 | if (!icr) | 4841 | if (!icr) |
4320 | return IRQ_NONE; /* Not our interrupt */ | 4842 | return IRQ_NONE; /* Not our interrupt */ |
4321 | 4843 | ||
4322 | igb_write_itr(adapter->rx_ring); | 4844 | igb_write_itr(q_vector); |
4323 | 4845 | ||
4324 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | 4846 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is |
4325 | * not set, then the adapter didn't send an interrupt */ | 4847 | * not set, then the adapter didn't send an interrupt */ |
4326 | if (!(icr & E1000_ICR_INT_ASSERTED)) | 4848 | if (!(icr & E1000_ICR_INT_ASSERTED)) |
4327 | return IRQ_NONE; | 4849 | return IRQ_NONE; |
4328 | 4850 | ||
4329 | if(icr & E1000_ICR_DOUTSYNC) { | 4851 | if (icr & E1000_ICR_DRSTA) |
4852 | schedule_work(&adapter->reset_task); | ||
4853 | |||
4854 | if (icr & E1000_ICR_DOUTSYNC) { | ||
4330 | /* HW is reporting DMA is out of sync */ | 4855 | /* HW is reporting DMA is out of sync */ |
4331 | adapter->stats.doosync++; | 4856 | adapter->stats.doosync++; |
4332 | } | 4857 | } |
@@ -4338,26 +4863,27 @@ static irqreturn_t igb_intr(int irq, void *data) | |||
4338 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | 4863 | mod_timer(&adapter->watchdog_timer, jiffies + 1); |
4339 | } | 4864 | } |
4340 | 4865 | ||
4341 | napi_schedule(&adapter->rx_ring[0].napi); | 4866 | napi_schedule(&q_vector->napi); |
4342 | 4867 | ||
4343 | return IRQ_HANDLED; | 4868 | return IRQ_HANDLED; |
4344 | } | 4869 | } |
4345 | 4870 | ||
4346 | static inline void igb_rx_irq_enable(struct igb_ring *rx_ring) | 4871 | static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
4347 | { | 4872 | { |
4348 | struct igb_adapter *adapter = rx_ring->adapter; | 4873 | struct igb_adapter *adapter = q_vector->adapter; |
4349 | struct e1000_hw *hw = &adapter->hw; | 4874 | struct e1000_hw *hw = &adapter->hw; |
4350 | 4875 | ||
4351 | if (adapter->itr_setting & 3) { | 4876 | if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) || |
4352 | if (adapter->num_rx_queues == 1) | 4877 | (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) { |
4878 | if (!adapter->msix_entries) | ||
4353 | igb_set_itr(adapter); | 4879 | igb_set_itr(adapter); |
4354 | else | 4880 | else |
4355 | igb_update_ring_itr(rx_ring); | 4881 | igb_update_ring_itr(q_vector); |
4356 | } | 4882 | } |
4357 | 4883 | ||
4358 | if (!test_bit(__IGB_DOWN, &adapter->state)) { | 4884 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
4359 | if (adapter->msix_entries) | 4885 | if (adapter->msix_entries) |
4360 | wr32(E1000_EIMS, rx_ring->eims_value); | 4886 | wr32(E1000_EIMS, q_vector->eims_value); |
4361 | else | 4887 | else |
4362 | igb_irq_enable(adapter); | 4888 | igb_irq_enable(adapter); |
4363 | } | 4889 | } |
@@ -4370,76 +4896,101 @@ static inline void igb_rx_irq_enable(struct igb_ring *rx_ring) | |||
4370 | **/ | 4896 | **/ |
4371 | static int igb_poll(struct napi_struct *napi, int budget) | 4897 | static int igb_poll(struct napi_struct *napi, int budget) |
4372 | { | 4898 | { |
4373 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); | 4899 | struct igb_q_vector *q_vector = container_of(napi, |
4374 | int work_done = 0; | 4900 | struct igb_q_vector, |
4901 | napi); | ||
4902 | int tx_clean_complete = 1, work_done = 0; | ||
4375 | 4903 | ||
4376 | #ifdef CONFIG_IGB_DCA | 4904 | #ifdef CONFIG_IGB_DCA |
4377 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) | 4905 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
4378 | igb_update_rx_dca(rx_ring); | 4906 | igb_update_dca(q_vector); |
4379 | #endif | 4907 | #endif |
4380 | igb_clean_rx_irq_adv(rx_ring, &work_done, budget); | 4908 | if (q_vector->tx_ring) |
4909 | tx_clean_complete = igb_clean_tx_irq(q_vector); | ||
4381 | 4910 | ||
4382 | if (rx_ring->buddy) { | 4911 | if (q_vector->rx_ring) |
4383 | #ifdef CONFIG_IGB_DCA | 4912 | igb_clean_rx_irq_adv(q_vector, &work_done, budget); |
4384 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) | 4913 | |
4385 | igb_update_tx_dca(rx_ring->buddy); | 4914 | if (!tx_clean_complete) |
4386 | #endif | 4915 | work_done = budget; |
4387 | if (!igb_clean_tx_irq(rx_ring->buddy)) | ||
4388 | work_done = budget; | ||
4389 | } | ||
4390 | 4916 | ||
4391 | /* If not enough Rx work done, exit the polling mode */ | 4917 | /* If not enough Rx work done, exit the polling mode */ |
4392 | if (work_done < budget) { | 4918 | if (work_done < budget) { |
4393 | napi_complete(napi); | 4919 | napi_complete(napi); |
4394 | igb_rx_irq_enable(rx_ring); | 4920 | igb_ring_irq_enable(q_vector); |
4395 | } | 4921 | } |
4396 | 4922 | ||
4397 | return work_done; | 4923 | return work_done; |
4398 | } | 4924 | } |
4399 | 4925 | ||
4400 | /** | 4926 | /** |
4401 | * igb_hwtstamp - utility function which checks for TX time stamp | 4927 | * igb_systim_to_hwtstamp - convert system time value to hw timestamp |
4402 | * @adapter: board private structure | 4928 | * @adapter: board private structure |
4929 | * @shhwtstamps: timestamp structure to update | ||
4930 | * @regval: unsigned 64bit system time value. | ||
4931 | * | ||
4932 | * We need to convert the system time value stored in the RX/TXSTMP registers | ||
4933 | * into a hwtstamp which can be used by the upper level timestamping functions | ||
4934 | */ | ||
4935 | static void igb_systim_to_hwtstamp(struct igb_adapter *adapter, | ||
4936 | struct skb_shared_hwtstamps *shhwtstamps, | ||
4937 | u64 regval) | ||
4938 | { | ||
4939 | u64 ns; | ||
4940 | |||
4941 | /* | ||
4942 | * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to | ||
4943 | * 24 to match clock shift we setup earlier. | ||
4944 | */ | ||
4945 | if (adapter->hw.mac.type == e1000_82580) | ||
4946 | regval <<= IGB_82580_TSYNC_SHIFT; | ||
4947 | |||
4948 | ns = timecounter_cyc2time(&adapter->clock, regval); | ||
4949 | timecompare_update(&adapter->compare, ns); | ||
4950 | memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); | ||
4951 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | ||
4952 | shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns); | ||
4953 | } | ||
4954 | |||
4955 | /** | ||
4956 | * igb_tx_hwtstamp - utility function which checks for TX time stamp | ||
4957 | * @q_vector: pointer to q_vector containing needed info | ||
4403 | * @skb: packet that was just sent | 4958 | * @skb: packet that was just sent |
4404 | * | 4959 | * |
4405 | * If we were asked to do hardware stamping and such a time stamp is | 4960 | * If we were asked to do hardware stamping and such a time stamp is |
4406 | * available, then it must have been for this skb here because we only | 4961 | * available, then it must have been for this skb here because we only |
4407 | * allow only one such packet into the queue. | 4962 | * allow only one such packet into the queue. |
4408 | */ | 4963 | */ |
4409 | static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb) | 4964 | static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb) |
4410 | { | 4965 | { |
4966 | struct igb_adapter *adapter = q_vector->adapter; | ||
4411 | union skb_shared_tx *shtx = skb_tx(skb); | 4967 | union skb_shared_tx *shtx = skb_tx(skb); |
4412 | struct e1000_hw *hw = &adapter->hw; | 4968 | struct e1000_hw *hw = &adapter->hw; |
4969 | struct skb_shared_hwtstamps shhwtstamps; | ||
4970 | u64 regval; | ||
4413 | 4971 | ||
4414 | if (unlikely(shtx->hardware)) { | 4972 | /* if skb does not support hw timestamp or TX stamp not valid exit */ |
4415 | u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID; | 4973 | if (likely(!shtx->hardware) || |
4416 | if (valid) { | 4974 | !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID)) |
4417 | u64 regval = rd32(E1000_TXSTMPL); | 4975 | return; |
4418 | u64 ns; | 4976 | |
4419 | struct skb_shared_hwtstamps shhwtstamps; | 4977 | regval = rd32(E1000_TXSTMPL); |
4420 | 4978 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
4421 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | 4979 | |
4422 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | 4980 | igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
4423 | ns = timecounter_cyc2time(&adapter->clock, | 4981 | skb_tstamp_tx(skb, &shhwtstamps); |
4424 | regval); | ||
4425 | timecompare_update(&adapter->compare, ns); | ||
4426 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | ||
4427 | shhwtstamps.syststamp = | ||
4428 | timecompare_transform(&adapter->compare, ns); | ||
4429 | skb_tstamp_tx(skb, &shhwtstamps); | ||
4430 | } | ||
4431 | } | ||
4432 | } | 4982 | } |
4433 | 4983 | ||
4434 | /** | 4984 | /** |
4435 | * igb_clean_tx_irq - Reclaim resources after transmit completes | 4985 | * igb_clean_tx_irq - Reclaim resources after transmit completes |
4436 | * @adapter: board private structure | 4986 | * @q_vector: pointer to q_vector containing needed info |
4437 | * returns true if ring is completely cleaned | 4987 | * returns true if ring is completely cleaned |
4438 | **/ | 4988 | **/ |
4439 | static bool igb_clean_tx_irq(struct igb_ring *tx_ring) | 4989 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
4440 | { | 4990 | { |
4441 | struct igb_adapter *adapter = tx_ring->adapter; | 4991 | struct igb_adapter *adapter = q_vector->adapter; |
4442 | struct net_device *netdev = adapter->netdev; | 4992 | struct igb_ring *tx_ring = q_vector->tx_ring; |
4993 | struct net_device *netdev = tx_ring->netdev; | ||
4443 | struct e1000_hw *hw = &adapter->hw; | 4994 | struct e1000_hw *hw = &adapter->hw; |
4444 | struct igb_buffer *buffer_info; | 4995 | struct igb_buffer *buffer_info; |
4445 | struct sk_buff *skb; | 4996 | struct sk_buff *skb; |
@@ -4463,17 +5014,17 @@ static bool igb_clean_tx_irq(struct igb_ring *tx_ring) | |||
4463 | if (skb) { | 5014 | if (skb) { |
4464 | unsigned int segs, bytecount; | 5015 | unsigned int segs, bytecount; |
4465 | /* gso_segs is currently only valid for tcp */ | 5016 | /* gso_segs is currently only valid for tcp */ |
4466 | segs = skb_shinfo(skb)->gso_segs ?: 1; | 5017 | segs = buffer_info->gso_segs; |
4467 | /* multiply data chunks by size of headers */ | 5018 | /* multiply data chunks by size of headers */ |
4468 | bytecount = ((segs - 1) * skb_headlen(skb)) + | 5019 | bytecount = ((segs - 1) * skb_headlen(skb)) + |
4469 | skb->len; | 5020 | skb->len; |
4470 | total_packets += segs; | 5021 | total_packets += segs; |
4471 | total_bytes += bytecount; | 5022 | total_bytes += bytecount; |
4472 | 5023 | ||
4473 | igb_tx_hwtstamp(adapter, skb); | 5024 | igb_tx_hwtstamp(q_vector, skb); |
4474 | } | 5025 | } |
4475 | 5026 | ||
4476 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | 5027 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
4477 | tx_desc->wb.status = 0; | 5028 | tx_desc->wb.status = 0; |
4478 | 5029 | ||
4479 | i++; | 5030 | i++; |
@@ -4496,7 +5047,7 @@ static bool igb_clean_tx_irq(struct igb_ring *tx_ring) | |||
4496 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && | 5047 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
4497 | !(test_bit(__IGB_DOWN, &adapter->state))) { | 5048 | !(test_bit(__IGB_DOWN, &adapter->state))) { |
4498 | netif_wake_subqueue(netdev, tx_ring->queue_index); | 5049 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
4499 | ++adapter->restart_queue; | 5050 | tx_ring->tx_stats.restart_queue++; |
4500 | } | 5051 | } |
4501 | } | 5052 | } |
4502 | 5053 | ||
@@ -4506,12 +5057,11 @@ static bool igb_clean_tx_irq(struct igb_ring *tx_ring) | |||
4506 | tx_ring->detect_tx_hung = false; | 5057 | tx_ring->detect_tx_hung = false; |
4507 | if (tx_ring->buffer_info[i].time_stamp && | 5058 | if (tx_ring->buffer_info[i].time_stamp && |
4508 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | 5059 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + |
4509 | (adapter->tx_timeout_factor * HZ)) | 5060 | (adapter->tx_timeout_factor * HZ)) && |
4510 | && !(rd32(E1000_STATUS) & | 5061 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { |
4511 | E1000_STATUS_TXOFF)) { | ||
4512 | 5062 | ||
4513 | /* detected Tx unit hang */ | 5063 | /* detected Tx unit hang */ |
4514 | dev_err(&adapter->pdev->dev, | 5064 | dev_err(&tx_ring->pdev->dev, |
4515 | "Detected Tx Unit Hang\n" | 5065 | "Detected Tx Unit Hang\n" |
4516 | " Tx Queue <%d>\n" | 5066 | " Tx Queue <%d>\n" |
4517 | " TDH <%x>\n" | 5067 | " TDH <%x>\n" |
@@ -4524,11 +5074,11 @@ static bool igb_clean_tx_irq(struct igb_ring *tx_ring) | |||
4524 | " jiffies <%lx>\n" | 5074 | " jiffies <%lx>\n" |
4525 | " desc.status <%x>\n", | 5075 | " desc.status <%x>\n", |
4526 | tx_ring->queue_index, | 5076 | tx_ring->queue_index, |
4527 | readl(adapter->hw.hw_addr + tx_ring->head), | 5077 | readl(tx_ring->head), |
4528 | readl(adapter->hw.hw_addr + tx_ring->tail), | 5078 | readl(tx_ring->tail), |
4529 | tx_ring->next_to_use, | 5079 | tx_ring->next_to_use, |
4530 | tx_ring->next_to_clean, | 5080 | tx_ring->next_to_clean, |
4531 | tx_ring->buffer_info[i].time_stamp, | 5081 | tx_ring->buffer_info[eop].time_stamp, |
4532 | eop, | 5082 | eop, |
4533 | jiffies, | 5083 | jiffies, |
4534 | eop_desc->wb.status); | 5084 | eop_desc->wb.status); |
@@ -4539,43 +5089,38 @@ static bool igb_clean_tx_irq(struct igb_ring *tx_ring) | |||
4539 | tx_ring->total_packets += total_packets; | 5089 | tx_ring->total_packets += total_packets; |
4540 | tx_ring->tx_stats.bytes += total_bytes; | 5090 | tx_ring->tx_stats.bytes += total_bytes; |
4541 | tx_ring->tx_stats.packets += total_packets; | 5091 | tx_ring->tx_stats.packets += total_packets; |
4542 | adapter->net_stats.tx_bytes += total_bytes; | ||
4543 | adapter->net_stats.tx_packets += total_packets; | ||
4544 | return (count < tx_ring->count); | 5092 | return (count < tx_ring->count); |
4545 | } | 5093 | } |
4546 | 5094 | ||
4547 | /** | 5095 | /** |
4548 | * igb_receive_skb - helper function to handle rx indications | 5096 | * igb_receive_skb - helper function to handle rx indications |
4549 | * @ring: pointer to receive ring receving this packet | 5097 | * @q_vector: structure containing interrupt and ring information |
4550 | * @status: descriptor status field as written by hardware | 5098 | * @skb: packet to send up |
4551 | * @rx_desc: receive descriptor containing vlan and type information. | 5099 | * @vlan_tag: vlan tag for packet |
4552 | * @skb: pointer to sk_buff to be indicated to stack | ||
4553 | **/ | 5100 | **/ |
4554 | static void igb_receive_skb(struct igb_ring *ring, u8 status, | 5101 | static void igb_receive_skb(struct igb_q_vector *q_vector, |
4555 | union e1000_adv_rx_desc * rx_desc, | 5102 | struct sk_buff *skb, |
4556 | struct sk_buff *skb) | 5103 | u16 vlan_tag) |
4557 | { | 5104 | { |
4558 | struct igb_adapter * adapter = ring->adapter; | 5105 | struct igb_adapter *adapter = q_vector->adapter; |
4559 | bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP)); | 5106 | |
4560 | 5107 | if (vlan_tag && adapter->vlgrp) | |
4561 | skb_record_rx_queue(skb, ring->queue_index); | 5108 | vlan_gro_receive(&q_vector->napi, adapter->vlgrp, |
4562 | if (vlan_extracted) | 5109 | vlan_tag, skb); |
4563 | vlan_gro_receive(&ring->napi, adapter->vlgrp, | ||
4564 | le16_to_cpu(rx_desc->wb.upper.vlan), | ||
4565 | skb); | ||
4566 | else | 5110 | else |
4567 | napi_gro_receive(&ring->napi, skb); | 5111 | napi_gro_receive(&q_vector->napi, skb); |
4568 | } | 5112 | } |
4569 | 5113 | ||
4570 | static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, | 5114 | static inline void igb_rx_checksum_adv(struct igb_ring *ring, |
4571 | u32 status_err, struct sk_buff *skb) | 5115 | u32 status_err, struct sk_buff *skb) |
4572 | { | 5116 | { |
4573 | skb->ip_summed = CHECKSUM_NONE; | 5117 | skb->ip_summed = CHECKSUM_NONE; |
4574 | 5118 | ||
4575 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | 5119 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ |
4576 | if ((status_err & E1000_RXD_STAT_IXSM) || | 5120 | if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) || |
4577 | (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED)) | 5121 | (status_err & E1000_RXD_STAT_IXSM)) |
4578 | return; | 5122 | return; |
5123 | |||
4579 | /* TCP/UDP checksum error bit is set */ | 5124 | /* TCP/UDP checksum error bit is set */ |
4580 | if (status_err & | 5125 | if (status_err & |
4581 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | 5126 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { |
@@ -4584,9 +5129,10 @@ static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, | |||
4584 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) | 5129 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) |
4585 | * packets, (aka let the stack check the crc32c) | 5130 | * packets, (aka let the stack check the crc32c) |
4586 | */ | 5131 | */ |
4587 | if (!((adapter->hw.mac.type == e1000_82576) && | 5132 | if ((skb->len == 60) && |
4588 | (skb->len == 60))) | 5133 | (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) |
4589 | adapter->hw_csum_err++; | 5134 | ring->rx_stats.csum_err++; |
5135 | |||
4590 | /* let the stack verify checksum errors */ | 5136 | /* let the stack verify checksum errors */ |
4591 | return; | 5137 | return; |
4592 | } | 5138 | } |
@@ -4594,11 +5140,38 @@ static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, | |||
4594 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | 5140 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) |
4595 | skb->ip_summed = CHECKSUM_UNNECESSARY; | 5141 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
4596 | 5142 | ||
4597 | dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err); | 5143 | dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err); |
4598 | adapter->hw_csum_good++; | ||
4599 | } | 5144 | } |
4600 | 5145 | ||
4601 | static inline u16 igb_get_hlen(struct igb_adapter *adapter, | 5146 | static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr, |
5147 | struct sk_buff *skb) | ||
5148 | { | ||
5149 | struct igb_adapter *adapter = q_vector->adapter; | ||
5150 | struct e1000_hw *hw = &adapter->hw; | ||
5151 | u64 regval; | ||
5152 | |||
5153 | /* | ||
5154 | * If this bit is set, then the RX registers contain the time stamp. No | ||
5155 | * other packet will be time stamped until we read these registers, so | ||
5156 | * read the registers to make them available again. Because only one | ||
5157 | * packet can be time stamped at a time, we know that the register | ||
5158 | * values must belong to this one here and therefore we don't need to | ||
5159 | * compare any of the additional attributes stored for it. | ||
5160 | * | ||
5161 | * If nothing went wrong, then it should have a skb_shared_tx that we | ||
5162 | * can turn into a skb_shared_hwtstamps. | ||
5163 | */ | ||
5164 | if (likely(!(staterr & E1000_RXDADV_STAT_TS))) | ||
5165 | return; | ||
5166 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) | ||
5167 | return; | ||
5168 | |||
5169 | regval = rd32(E1000_RXSTMPL); | ||
5170 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | ||
5171 | |||
5172 | igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | ||
5173 | } | ||
5174 | static inline u16 igb_get_hlen(struct igb_ring *rx_ring, | ||
4602 | union e1000_adv_rx_desc *rx_desc) | 5175 | union e1000_adv_rx_desc *rx_desc) |
4603 | { | 5176 | { |
4604 | /* HW will not DMA in data larger than the given buffer, even if it | 5177 | /* HW will not DMA in data larger than the given buffer, even if it |
@@ -4607,27 +5180,28 @@ static inline u16 igb_get_hlen(struct igb_adapter *adapter, | |||
4607 | */ | 5180 | */ |
4608 | u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | 5181 | u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & |
4609 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | 5182 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; |
4610 | if (hlen > adapter->rx_ps_hdr_size) | 5183 | if (hlen > rx_ring->rx_buffer_len) |
4611 | hlen = adapter->rx_ps_hdr_size; | 5184 | hlen = rx_ring->rx_buffer_len; |
4612 | return hlen; | 5185 | return hlen; |
4613 | } | 5186 | } |
4614 | 5187 | ||
4615 | static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, | 5188 | static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector, |
4616 | int *work_done, int budget) | 5189 | int *work_done, int budget) |
4617 | { | 5190 | { |
4618 | struct igb_adapter *adapter = rx_ring->adapter; | 5191 | struct igb_ring *rx_ring = q_vector->rx_ring; |
4619 | struct net_device *netdev = adapter->netdev; | 5192 | struct net_device *netdev = rx_ring->netdev; |
4620 | struct e1000_hw *hw = &adapter->hw; | 5193 | struct pci_dev *pdev = rx_ring->pdev; |
4621 | struct pci_dev *pdev = adapter->pdev; | ||
4622 | union e1000_adv_rx_desc *rx_desc , *next_rxd; | 5194 | union e1000_adv_rx_desc *rx_desc , *next_rxd; |
4623 | struct igb_buffer *buffer_info , *next_buffer; | 5195 | struct igb_buffer *buffer_info , *next_buffer; |
4624 | struct sk_buff *skb; | 5196 | struct sk_buff *skb; |
4625 | bool cleaned = false; | 5197 | bool cleaned = false; |
4626 | int cleaned_count = 0; | 5198 | int cleaned_count = 0; |
5199 | int current_node = numa_node_id(); | ||
4627 | unsigned int total_bytes = 0, total_packets = 0; | 5200 | unsigned int total_bytes = 0, total_packets = 0; |
4628 | unsigned int i; | 5201 | unsigned int i; |
4629 | u32 staterr; | 5202 | u32 staterr; |
4630 | u16 length; | 5203 | u16 length; |
5204 | u16 vlan_tag; | ||
4631 | 5205 | ||
4632 | i = rx_ring->next_to_clean; | 5206 | i = rx_ring->next_to_clean; |
4633 | buffer_info = &rx_ring->buffer_info[i]; | 5207 | buffer_info = &rx_ring->buffer_info[i]; |
@@ -4646,6 +5220,7 @@ static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, | |||
4646 | i++; | 5220 | i++; |
4647 | if (i == rx_ring->count) | 5221 | if (i == rx_ring->count) |
4648 | i = 0; | 5222 | i = 0; |
5223 | |||
4649 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); | 5224 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); |
4650 | prefetch(next_rxd); | 5225 | prefetch(next_rxd); |
4651 | next_buffer = &rx_ring->buffer_info[i]; | 5226 | next_buffer = &rx_ring->buffer_info[i]; |
@@ -4654,23 +5229,16 @@ static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, | |||
4654 | cleaned = true; | 5229 | cleaned = true; |
4655 | cleaned_count++; | 5230 | cleaned_count++; |
4656 | 5231 | ||
4657 | /* this is the fast path for the non-packet split case */ | ||
4658 | if (!adapter->rx_ps_hdr_size) { | ||
4659 | pci_unmap_single(pdev, buffer_info->dma, | ||
4660 | adapter->rx_buffer_len, | ||
4661 | PCI_DMA_FROMDEVICE); | ||
4662 | buffer_info->dma = 0; | ||
4663 | skb_put(skb, length); | ||
4664 | goto send_up; | ||
4665 | } | ||
4666 | |||
4667 | if (buffer_info->dma) { | 5232 | if (buffer_info->dma) { |
4668 | u16 hlen = igb_get_hlen(adapter, rx_desc); | ||
4669 | pci_unmap_single(pdev, buffer_info->dma, | 5233 | pci_unmap_single(pdev, buffer_info->dma, |
4670 | adapter->rx_ps_hdr_size, | 5234 | rx_ring->rx_buffer_len, |
4671 | PCI_DMA_FROMDEVICE); | 5235 | PCI_DMA_FROMDEVICE); |
4672 | buffer_info->dma = 0; | 5236 | buffer_info->dma = 0; |
4673 | skb_put(skb, hlen); | 5237 | if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) { |
5238 | skb_put(skb, length); | ||
5239 | goto send_up; | ||
5240 | } | ||
5241 | skb_put(skb, igb_get_hlen(rx_ring, rx_desc)); | ||
4674 | } | 5242 | } |
4675 | 5243 | ||
4676 | if (length) { | 5244 | if (length) { |
@@ -4683,15 +5251,14 @@ static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, | |||
4683 | buffer_info->page_offset, | 5251 | buffer_info->page_offset, |
4684 | length); | 5252 | length); |
4685 | 5253 | ||
4686 | if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) || | 5254 | if ((page_count(buffer_info->page) != 1) || |
4687 | (page_count(buffer_info->page) != 1)) | 5255 | (page_to_nid(buffer_info->page) != current_node)) |
4688 | buffer_info->page = NULL; | 5256 | buffer_info->page = NULL; |
4689 | else | 5257 | else |
4690 | get_page(buffer_info->page); | 5258 | get_page(buffer_info->page); |
4691 | 5259 | ||
4692 | skb->len += length; | 5260 | skb->len += length; |
4693 | skb->data_len += length; | 5261 | skb->data_len += length; |
4694 | |||
4695 | skb->truesize += length; | 5262 | skb->truesize += length; |
4696 | } | 5263 | } |
4697 | 5264 | ||
@@ -4703,60 +5270,24 @@ static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, | |||
4703 | goto next_desc; | 5270 | goto next_desc; |
4704 | } | 5271 | } |
4705 | send_up: | 5272 | send_up: |
4706 | /* | ||
4707 | * If this bit is set, then the RX registers contain | ||
4708 | * the time stamp. No other packet will be time | ||
4709 | * stamped until we read these registers, so read the | ||
4710 | * registers to make them available again. Because | ||
4711 | * only one packet can be time stamped at a time, we | ||
4712 | * know that the register values must belong to this | ||
4713 | * one here and therefore we don't need to compare | ||
4714 | * any of the additional attributes stored for it. | ||
4715 | * | ||
4716 | * If nothing went wrong, then it should have a | ||
4717 | * skb_shared_tx that we can turn into a | ||
4718 | * skb_shared_hwtstamps. | ||
4719 | * | ||
4720 | * TODO: can time stamping be triggered (thus locking | ||
4721 | * the registers) without the packet reaching this point | ||
4722 | * here? In that case RX time stamping would get stuck. | ||
4723 | * | ||
4724 | * TODO: in "time stamp all packets" mode this bit is | ||
4725 | * not set. Need a global flag for this mode and then | ||
4726 | * always read the registers. Cannot be done without | ||
4727 | * a race condition. | ||
4728 | */ | ||
4729 | if (unlikely(staterr & E1000_RXD_STAT_TS)) { | ||
4730 | u64 regval; | ||
4731 | u64 ns; | ||
4732 | struct skb_shared_hwtstamps *shhwtstamps = | ||
4733 | skb_hwtstamps(skb); | ||
4734 | |||
4735 | WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID), | ||
4736 | "igb: no RX time stamp available for time stamped packet"); | ||
4737 | regval = rd32(E1000_RXSTMPL); | ||
4738 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | ||
4739 | ns = timecounter_cyc2time(&adapter->clock, regval); | ||
4740 | timecompare_update(&adapter->compare, ns); | ||
4741 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | ||
4742 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | ||
4743 | shhwtstamps->syststamp = | ||
4744 | timecompare_transform(&adapter->compare, ns); | ||
4745 | } | ||
4746 | |||
4747 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { | 5273 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
4748 | dev_kfree_skb_irq(skb); | 5274 | dev_kfree_skb_irq(skb); |
4749 | goto next_desc; | 5275 | goto next_desc; |
4750 | } | 5276 | } |
4751 | 5277 | ||
5278 | igb_rx_hwtstamp(q_vector, staterr, skb); | ||
4752 | total_bytes += skb->len; | 5279 | total_bytes += skb->len; |
4753 | total_packets++; | 5280 | total_packets++; |
4754 | 5281 | ||
4755 | igb_rx_checksum_adv(adapter, staterr, skb); | 5282 | igb_rx_checksum_adv(rx_ring, staterr, skb); |
4756 | 5283 | ||
4757 | skb->protocol = eth_type_trans(skb, netdev); | 5284 | skb->protocol = eth_type_trans(skb, netdev); |
5285 | skb_record_rx_queue(skb, rx_ring->queue_index); | ||
4758 | 5286 | ||
4759 | igb_receive_skb(rx_ring, staterr, rx_desc, skb); | 5287 | vlan_tag = ((staterr & E1000_RXD_STAT_VP) ? |
5288 | le16_to_cpu(rx_desc->wb.upper.vlan) : 0); | ||
5289 | |||
5290 | igb_receive_skb(q_vector, skb, vlan_tag); | ||
4760 | 5291 | ||
4761 | next_desc: | 5292 | next_desc: |
4762 | rx_desc->wb.upper.status_error = 0; | 5293 | rx_desc->wb.upper.status_error = 0; |
@@ -4783,8 +5314,6 @@ next_desc: | |||
4783 | rx_ring->total_bytes += total_bytes; | 5314 | rx_ring->total_bytes += total_bytes; |
4784 | rx_ring->rx_stats.packets += total_packets; | 5315 | rx_ring->rx_stats.packets += total_packets; |
4785 | rx_ring->rx_stats.bytes += total_bytes; | 5316 | rx_ring->rx_stats.bytes += total_bytes; |
4786 | adapter->net_stats.rx_bytes += total_bytes; | ||
4787 | adapter->net_stats.rx_packets += total_packets; | ||
4788 | return cleaned; | 5317 | return cleaned; |
4789 | } | 5318 | } |
4790 | 5319 | ||
@@ -4792,12 +5321,9 @@ next_desc: | |||
4792 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | 5321 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split |
4793 | * @adapter: address of board private structure | 5322 | * @adapter: address of board private structure |
4794 | **/ | 5323 | **/ |
4795 | static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, | 5324 | void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count) |
4796 | int cleaned_count) | ||
4797 | { | 5325 | { |
4798 | struct igb_adapter *adapter = rx_ring->adapter; | 5326 | struct net_device *netdev = rx_ring->netdev; |
4799 | struct net_device *netdev = adapter->netdev; | ||
4800 | struct pci_dev *pdev = adapter->pdev; | ||
4801 | union e1000_adv_rx_desc *rx_desc; | 5327 | union e1000_adv_rx_desc *rx_desc; |
4802 | struct igb_buffer *buffer_info; | 5328 | struct igb_buffer *buffer_info; |
4803 | struct sk_buff *skb; | 5329 | struct sk_buff *skb; |
@@ -4807,19 +5333,16 @@ static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, | |||
4807 | i = rx_ring->next_to_use; | 5333 | i = rx_ring->next_to_use; |
4808 | buffer_info = &rx_ring->buffer_info[i]; | 5334 | buffer_info = &rx_ring->buffer_info[i]; |
4809 | 5335 | ||
4810 | if (adapter->rx_ps_hdr_size) | 5336 | bufsz = rx_ring->rx_buffer_len; |
4811 | bufsz = adapter->rx_ps_hdr_size; | ||
4812 | else | ||
4813 | bufsz = adapter->rx_buffer_len; | ||
4814 | 5337 | ||
4815 | while (cleaned_count--) { | 5338 | while (cleaned_count--) { |
4816 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | 5339 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); |
4817 | 5340 | ||
4818 | if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) { | 5341 | if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) { |
4819 | if (!buffer_info->page) { | 5342 | if (!buffer_info->page) { |
4820 | buffer_info->page = alloc_page(GFP_ATOMIC); | 5343 | buffer_info->page = netdev_alloc_page(netdev); |
4821 | if (!buffer_info->page) { | 5344 | if (!buffer_info->page) { |
4822 | adapter->alloc_rx_buff_failed++; | 5345 | rx_ring->rx_stats.alloc_failed++; |
4823 | goto no_buffers; | 5346 | goto no_buffers; |
4824 | } | 5347 | } |
4825 | buffer_info->page_offset = 0; | 5348 | buffer_info->page_offset = 0; |
@@ -4827,39 +5350,48 @@ static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, | |||
4827 | buffer_info->page_offset ^= PAGE_SIZE / 2; | 5350 | buffer_info->page_offset ^= PAGE_SIZE / 2; |
4828 | } | 5351 | } |
4829 | buffer_info->page_dma = | 5352 | buffer_info->page_dma = |
4830 | pci_map_page(pdev, buffer_info->page, | 5353 | pci_map_page(rx_ring->pdev, buffer_info->page, |
4831 | buffer_info->page_offset, | 5354 | buffer_info->page_offset, |
4832 | PAGE_SIZE / 2, | 5355 | PAGE_SIZE / 2, |
4833 | PCI_DMA_FROMDEVICE); | 5356 | PCI_DMA_FROMDEVICE); |
5357 | if (pci_dma_mapping_error(rx_ring->pdev, | ||
5358 | buffer_info->page_dma)) { | ||
5359 | buffer_info->page_dma = 0; | ||
5360 | rx_ring->rx_stats.alloc_failed++; | ||
5361 | goto no_buffers; | ||
5362 | } | ||
4834 | } | 5363 | } |
4835 | 5364 | ||
4836 | if (!buffer_info->skb) { | 5365 | skb = buffer_info->skb; |
4837 | skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN); | 5366 | if (!skb) { |
5367 | skb = netdev_alloc_skb_ip_align(netdev, bufsz); | ||
4838 | if (!skb) { | 5368 | if (!skb) { |
4839 | adapter->alloc_rx_buff_failed++; | 5369 | rx_ring->rx_stats.alloc_failed++; |
4840 | goto no_buffers; | 5370 | goto no_buffers; |
4841 | } | 5371 | } |
4842 | 5372 | ||
4843 | /* Make buffer alignment 2 beyond a 16 byte boundary | ||
4844 | * this will result in a 16 byte aligned IP header after | ||
4845 | * the 14 byte MAC header is removed | ||
4846 | */ | ||
4847 | skb_reserve(skb, NET_IP_ALIGN); | ||
4848 | |||
4849 | buffer_info->skb = skb; | 5373 | buffer_info->skb = skb; |
4850 | buffer_info->dma = pci_map_single(pdev, skb->data, | 5374 | } |
5375 | if (!buffer_info->dma) { | ||
5376 | buffer_info->dma = pci_map_single(rx_ring->pdev, | ||
5377 | skb->data, | ||
4851 | bufsz, | 5378 | bufsz, |
4852 | PCI_DMA_FROMDEVICE); | 5379 | PCI_DMA_FROMDEVICE); |
5380 | if (pci_dma_mapping_error(rx_ring->pdev, | ||
5381 | buffer_info->dma)) { | ||
5382 | buffer_info->dma = 0; | ||
5383 | rx_ring->rx_stats.alloc_failed++; | ||
5384 | goto no_buffers; | ||
5385 | } | ||
4853 | } | 5386 | } |
4854 | /* Refresh the desc even if buffer_addrs didn't change because | 5387 | /* Refresh the desc even if buffer_addrs didn't change because |
4855 | * each write-back erases this info. */ | 5388 | * each write-back erases this info. */ |
4856 | if (adapter->rx_ps_hdr_size) { | 5389 | if (bufsz < IGB_RXBUFFER_1024) { |
4857 | rx_desc->read.pkt_addr = | 5390 | rx_desc->read.pkt_addr = |
4858 | cpu_to_le64(buffer_info->page_dma); | 5391 | cpu_to_le64(buffer_info->page_dma); |
4859 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | 5392 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); |
4860 | } else { | 5393 | } else { |
4861 | rx_desc->read.pkt_addr = | 5394 | rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma); |
4862 | cpu_to_le64(buffer_info->dma); | ||
4863 | rx_desc->read.hdr_addr = 0; | 5395 | rx_desc->read.hdr_addr = 0; |
4864 | } | 5396 | } |
4865 | 5397 | ||
@@ -4882,7 +5414,7 @@ no_buffers: | |||
4882 | * applicable for weak-ordered memory model archs, | 5414 | * applicable for weak-ordered memory model archs, |
4883 | * such as IA-64). */ | 5415 | * such as IA-64). */ |
4884 | wmb(); | 5416 | wmb(); |
4885 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | 5417 | writel(i, rx_ring->tail); |
4886 | } | 5418 | } |
4887 | } | 5419 | } |
4888 | 5420 | ||
@@ -4941,13 +5473,11 @@ static int igb_hwtstamp_ioctl(struct net_device *netdev, | |||
4941 | struct igb_adapter *adapter = netdev_priv(netdev); | 5473 | struct igb_adapter *adapter = netdev_priv(netdev); |
4942 | struct e1000_hw *hw = &adapter->hw; | 5474 | struct e1000_hw *hw = &adapter->hw; |
4943 | struct hwtstamp_config config; | 5475 | struct hwtstamp_config config; |
4944 | u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; | 5476 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
4945 | u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED; | 5477 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; |
4946 | u32 tsync_rx_ctl_type = 0; | ||
4947 | u32 tsync_rx_cfg = 0; | 5478 | u32 tsync_rx_cfg = 0; |
4948 | int is_l4 = 0; | 5479 | bool is_l4 = false; |
4949 | int is_l2 = 0; | 5480 | bool is_l2 = false; |
4950 | short port = 319; /* PTP */ | ||
4951 | u32 regval; | 5481 | u32 regval; |
4952 | 5482 | ||
4953 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | 5483 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) |
@@ -4959,10 +5489,8 @@ static int igb_hwtstamp_ioctl(struct net_device *netdev, | |||
4959 | 5489 | ||
4960 | switch (config.tx_type) { | 5490 | switch (config.tx_type) { |
4961 | case HWTSTAMP_TX_OFF: | 5491 | case HWTSTAMP_TX_OFF: |
4962 | tsync_tx_ctl_bit = 0; | 5492 | tsync_tx_ctl = 0; |
4963 | break; | ||
4964 | case HWTSTAMP_TX_ON: | 5493 | case HWTSTAMP_TX_ON: |
4965 | tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; | ||
4966 | break; | 5494 | break; |
4967 | default: | 5495 | default: |
4968 | return -ERANGE; | 5496 | return -ERANGE; |
@@ -4970,7 +5498,7 @@ static int igb_hwtstamp_ioctl(struct net_device *netdev, | |||
4970 | 5498 | ||
4971 | switch (config.rx_filter) { | 5499 | switch (config.rx_filter) { |
4972 | case HWTSTAMP_FILTER_NONE: | 5500 | case HWTSTAMP_FILTER_NONE: |
4973 | tsync_rx_ctl_bit = 0; | 5501 | tsync_rx_ctl = 0; |
4974 | break; | 5502 | break; |
4975 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | 5503 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
4976 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | 5504 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
@@ -4981,86 +5509,97 @@ static int igb_hwtstamp_ioctl(struct net_device *netdev, | |||
4981 | * possible to time stamp both Sync and Delay_Req messages | 5509 | * possible to time stamp both Sync and Delay_Req messages |
4982 | * => fall back to time stamping all packets | 5510 | * => fall back to time stamping all packets |
4983 | */ | 5511 | */ |
4984 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL; | 5512 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
4985 | config.rx_filter = HWTSTAMP_FILTER_ALL; | 5513 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
4986 | break; | 5514 | break; |
4987 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | 5515 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
4988 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | 5516 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
4989 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | 5517 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; |
4990 | is_l4 = 1; | 5518 | is_l4 = true; |
4991 | break; | 5519 | break; |
4992 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | 5520 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
4993 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | 5521 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
4994 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | 5522 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; |
4995 | is_l4 = 1; | 5523 | is_l4 = true; |
4996 | break; | 5524 | break; |
4997 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | 5525 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
4998 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | 5526 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
4999 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | 5527 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
5000 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; | 5528 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; |
5001 | is_l2 = 1; | 5529 | is_l2 = true; |
5002 | is_l4 = 1; | 5530 | is_l4 = true; |
5003 | config.rx_filter = HWTSTAMP_FILTER_SOME; | 5531 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
5004 | break; | 5532 | break; |
5005 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | 5533 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
5006 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | 5534 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
5007 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | 5535 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
5008 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; | 5536 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; |
5009 | is_l2 = 1; | 5537 | is_l2 = true; |
5010 | is_l4 = 1; | 5538 | is_l4 = true; |
5011 | config.rx_filter = HWTSTAMP_FILTER_SOME; | 5539 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
5012 | break; | 5540 | break; |
5013 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | 5541 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
5014 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | 5542 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
5015 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | 5543 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
5016 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2; | 5544 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
5017 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | 5545 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
5018 | is_l2 = 1; | 5546 | is_l2 = true; |
5019 | break; | 5547 | break; |
5020 | default: | 5548 | default: |
5021 | return -ERANGE; | 5549 | return -ERANGE; |
5022 | } | 5550 | } |
5023 | 5551 | ||
5552 | if (hw->mac.type == e1000_82575) { | ||
5553 | if (tsync_rx_ctl | tsync_tx_ctl) | ||
5554 | return -EINVAL; | ||
5555 | return 0; | ||
5556 | } | ||
5557 | |||
5024 | /* enable/disable TX */ | 5558 | /* enable/disable TX */ |
5025 | regval = rd32(E1000_TSYNCTXCTL); | 5559 | regval = rd32(E1000_TSYNCTXCTL); |
5026 | regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit; | 5560 | regval &= ~E1000_TSYNCTXCTL_ENABLED; |
5561 | regval |= tsync_tx_ctl; | ||
5027 | wr32(E1000_TSYNCTXCTL, regval); | 5562 | wr32(E1000_TSYNCTXCTL, regval); |
5028 | 5563 | ||
5029 | /* enable/disable RX, define which PTP packets are time stamped */ | 5564 | /* enable/disable RX */ |
5030 | regval = rd32(E1000_TSYNCRXCTL); | 5565 | regval = rd32(E1000_TSYNCRXCTL); |
5031 | regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit; | 5566 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); |
5032 | regval = (regval & ~0xE) | tsync_rx_ctl_type; | 5567 | regval |= tsync_rx_ctl; |
5033 | wr32(E1000_TSYNCRXCTL, regval); | 5568 | wr32(E1000_TSYNCRXCTL, regval); |
5034 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | ||
5035 | 5569 | ||
5036 | /* | 5570 | /* define which PTP packets are time stamped */ |
5037 | * Ethertype Filter Queue Filter[0][15:0] = 0x88F7 | 5571 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); |
5038 | * (Ethertype to filter on) | ||
5039 | * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter) | ||
5040 | * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping) | ||
5041 | */ | ||
5042 | wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0); | ||
5043 | |||
5044 | /* L4 Queue Filter[0]: only filter by source and destination port */ | ||
5045 | wr32(E1000_SPQF0, htons(port)); | ||
5046 | wr32(E1000_IMIREXT(0), is_l4 ? | ||
5047 | ((1<<12) | (1<<19) /* bypass size and control flags */) : 0); | ||
5048 | wr32(E1000_IMIR(0), is_l4 ? | ||
5049 | (htons(port) | ||
5050 | | (0<<16) /* immediate interrupt disabled */ | ||
5051 | | 0 /* (1<<17) bit cleared: do not bypass | ||
5052 | destination port check */) | ||
5053 | : 0); | ||
5054 | wr32(E1000_FTQF0, is_l4 ? | ||
5055 | (0x11 /* UDP */ | ||
5056 | | (1<<15) /* VF not compared */ | ||
5057 | | (1<<27) /* Enable Timestamping */ | ||
5058 | | (7<<28) /* only source port filter enabled, | ||
5059 | source/target address and protocol | ||
5060 | masked */) | ||
5061 | : ((1<<15) | (15<<28) /* all mask bits set = filter not | ||
5062 | enabled */)); | ||
5063 | 5572 | ||
5573 | /* define ethertype filter for timestamped packets */ | ||
5574 | if (is_l2) | ||
5575 | wr32(E1000_ETQF(3), | ||
5576 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | ||
5577 | E1000_ETQF_1588 | /* enable timestamping */ | ||
5578 | ETH_P_1588)); /* 1588 eth protocol type */ | ||
5579 | else | ||
5580 | wr32(E1000_ETQF(3), 0); | ||
5581 | |||
5582 | #define PTP_PORT 319 | ||
5583 | /* L4 Queue Filter[3]: filter by destination port and protocol */ | ||
5584 | if (is_l4) { | ||
5585 | u32 ftqf = (IPPROTO_UDP /* UDP */ | ||
5586 | | E1000_FTQF_VF_BP /* VF not compared */ | ||
5587 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | ||
5588 | | E1000_FTQF_MASK); /* mask all inputs */ | ||
5589 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | ||
5590 | |||
5591 | wr32(E1000_IMIR(3), htons(PTP_PORT)); | ||
5592 | wr32(E1000_IMIREXT(3), | ||
5593 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | ||
5594 | if (hw->mac.type == e1000_82576) { | ||
5595 | /* enable source port check */ | ||
5596 | wr32(E1000_SPQF(3), htons(PTP_PORT)); | ||
5597 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; | ||
5598 | } | ||
5599 | wr32(E1000_FTQF(3), ftqf); | ||
5600 | } else { | ||
5601 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | ||
5602 | } | ||
5064 | wrfl(); | 5603 | wrfl(); |
5065 | 5604 | ||
5066 | adapter->hwtstamp_config = config; | 5605 | adapter->hwtstamp_config = config; |
@@ -5137,21 +5676,15 @@ static void igb_vlan_rx_register(struct net_device *netdev, | |||
5137 | ctrl |= E1000_CTRL_VME; | 5676 | ctrl |= E1000_CTRL_VME; |
5138 | wr32(E1000_CTRL, ctrl); | 5677 | wr32(E1000_CTRL, ctrl); |
5139 | 5678 | ||
5140 | /* enable VLAN receive filtering */ | 5679 | /* Disable CFI check */ |
5141 | rctl = rd32(E1000_RCTL); | 5680 | rctl = rd32(E1000_RCTL); |
5142 | rctl &= ~E1000_RCTL_CFIEN; | 5681 | rctl &= ~E1000_RCTL_CFIEN; |
5143 | wr32(E1000_RCTL, rctl); | 5682 | wr32(E1000_RCTL, rctl); |
5144 | igb_update_mng_vlan(adapter); | ||
5145 | } else { | 5683 | } else { |
5146 | /* disable VLAN tag insert/strip */ | 5684 | /* disable VLAN tag insert/strip */ |
5147 | ctrl = rd32(E1000_CTRL); | 5685 | ctrl = rd32(E1000_CTRL); |
5148 | ctrl &= ~E1000_CTRL_VME; | 5686 | ctrl &= ~E1000_CTRL_VME; |
5149 | wr32(E1000_CTRL, ctrl); | 5687 | wr32(E1000_CTRL, ctrl); |
5150 | |||
5151 | if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { | ||
5152 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | ||
5153 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | ||
5154 | } | ||
5155 | } | 5688 | } |
5156 | 5689 | ||
5157 | igb_rlpml_set(adapter); | 5690 | igb_rlpml_set(adapter); |
@@ -5166,16 +5699,11 @@ static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |||
5166 | struct e1000_hw *hw = &adapter->hw; | 5699 | struct e1000_hw *hw = &adapter->hw; |
5167 | int pf_id = adapter->vfs_allocated_count; | 5700 | int pf_id = adapter->vfs_allocated_count; |
5168 | 5701 | ||
5169 | if ((hw->mng_cookie.status & | 5702 | /* attempt to add filter to vlvf array */ |
5170 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | 5703 | igb_vlvf_set(adapter, vid, true, pf_id); |
5171 | (vid == adapter->mng_vlan_id)) | ||
5172 | return; | ||
5173 | |||
5174 | /* add vid to vlvf if sr-iov is enabled, | ||
5175 | * if that fails add directly to filter table */ | ||
5176 | if (igb_vlvf_set(adapter, vid, true, pf_id)) | ||
5177 | igb_vfta_set(hw, vid, true); | ||
5178 | 5704 | ||
5705 | /* add the filter since PF can receive vlans w/o entry in vlvf */ | ||
5706 | igb_vfta_set(hw, vid, true); | ||
5179 | } | 5707 | } |
5180 | 5708 | ||
5181 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | 5709 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
@@ -5183,6 +5711,7 @@ static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |||
5183 | struct igb_adapter *adapter = netdev_priv(netdev); | 5711 | struct igb_adapter *adapter = netdev_priv(netdev); |
5184 | struct e1000_hw *hw = &adapter->hw; | 5712 | struct e1000_hw *hw = &adapter->hw; |
5185 | int pf_id = adapter->vfs_allocated_count; | 5713 | int pf_id = adapter->vfs_allocated_count; |
5714 | s32 err; | ||
5186 | 5715 | ||
5187 | igb_irq_disable(adapter); | 5716 | igb_irq_disable(adapter); |
5188 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | 5717 | vlan_group_set_device(adapter->vlgrp, vid, NULL); |
@@ -5190,17 +5719,11 @@ static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |||
5190 | if (!test_bit(__IGB_DOWN, &adapter->state)) | 5719 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
5191 | igb_irq_enable(adapter); | 5720 | igb_irq_enable(adapter); |
5192 | 5721 | ||
5193 | if ((adapter->hw.mng_cookie.status & | 5722 | /* remove vlan from VLVF table array */ |
5194 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | 5723 | err = igb_vlvf_set(adapter, vid, false, pf_id); |
5195 | (vid == adapter->mng_vlan_id)) { | ||
5196 | /* release control to f/w */ | ||
5197 | igb_release_hw_control(adapter); | ||
5198 | return; | ||
5199 | } | ||
5200 | 5724 | ||
5201 | /* remove vid from vlvf if sr-iov is enabled, | 5725 | /* if vid was not present in VLVF just remove it from table */ |
5202 | * if not in vlvf remove from vfta */ | 5726 | if (err) |
5203 | if (igb_vlvf_set(adapter, vid, false, pf_id)) | ||
5204 | igb_vfta_set(hw, vid, false); | 5727 | igb_vfta_set(hw, vid, false); |
5205 | } | 5728 | } |
5206 | 5729 | ||
@@ -5220,6 +5743,7 @@ static void igb_restore_vlan(struct igb_adapter *adapter) | |||
5220 | 5743 | ||
5221 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | 5744 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) |
5222 | { | 5745 | { |
5746 | struct pci_dev *pdev = adapter->pdev; | ||
5223 | struct e1000_mac_info *mac = &adapter->hw.mac; | 5747 | struct e1000_mac_info *mac = &adapter->hw.mac; |
5224 | 5748 | ||
5225 | mac->autoneg = 0; | 5749 | mac->autoneg = 0; |
@@ -5243,8 +5767,7 @@ int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |||
5243 | break; | 5767 | break; |
5244 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | 5768 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ |
5245 | default: | 5769 | default: |
5246 | dev_err(&adapter->pdev->dev, | 5770 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); |
5247 | "Unsupported Speed/Duplex configuration\n"); | ||
5248 | return -EINVAL; | 5771 | return -EINVAL; |
5249 | } | 5772 | } |
5250 | return 0; | 5773 | return 0; |
@@ -5266,9 +5789,7 @@ static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake) | |||
5266 | if (netif_running(netdev)) | 5789 | if (netif_running(netdev)) |
5267 | igb_close(netdev); | 5790 | igb_close(netdev); |
5268 | 5791 | ||
5269 | igb_reset_interrupt_capability(adapter); | 5792 | igb_clear_interrupt_scheme(adapter); |
5270 | |||
5271 | igb_free_queues(adapter); | ||
5272 | 5793 | ||
5273 | #ifdef CONFIG_PM | 5794 | #ifdef CONFIG_PM |
5274 | retval = pci_save_state(pdev); | 5795 | retval = pci_save_state(pdev); |
@@ -5300,7 +5821,7 @@ static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake) | |||
5300 | wr32(E1000_CTRL, ctrl); | 5821 | wr32(E1000_CTRL, ctrl); |
5301 | 5822 | ||
5302 | /* Allow time for pending master requests to run */ | 5823 | /* Allow time for pending master requests to run */ |
5303 | igb_disable_pcie_master(&adapter->hw); | 5824 | igb_disable_pcie_master(hw); |
5304 | 5825 | ||
5305 | wr32(E1000_WUC, E1000_WUC_PME_EN); | 5826 | wr32(E1000_WUC, E1000_WUC_PME_EN); |
5306 | wr32(E1000_WUFC, wufc); | 5827 | wr32(E1000_WUFC, wufc); |
@@ -5311,7 +5832,9 @@ static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake) | |||
5311 | 5832 | ||
5312 | *enable_wake = wufc || adapter->en_mng_pt; | 5833 | *enable_wake = wufc || adapter->en_mng_pt; |
5313 | if (!*enable_wake) | 5834 | if (!*enable_wake) |
5314 | igb_shutdown_serdes_link_82575(hw); | 5835 | igb_power_down_link(adapter); |
5836 | else | ||
5837 | igb_power_up_link(adapter); | ||
5315 | 5838 | ||
5316 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | 5839 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
5317 | * would have already happened in close and is redundant. */ | 5840 | * would have already happened in close and is redundant. */ |
@@ -5351,6 +5874,7 @@ static int igb_resume(struct pci_dev *pdev) | |||
5351 | 5874 | ||
5352 | pci_set_power_state(pdev, PCI_D0); | 5875 | pci_set_power_state(pdev, PCI_D0); |
5353 | pci_restore_state(pdev); | 5876 | pci_restore_state(pdev); |
5877 | pci_save_state(pdev); | ||
5354 | 5878 | ||
5355 | err = pci_enable_device_mem(pdev); | 5879 | err = pci_enable_device_mem(pdev); |
5356 | if (err) { | 5880 | if (err) { |
@@ -5363,15 +5887,11 @@ static int igb_resume(struct pci_dev *pdev) | |||
5363 | pci_enable_wake(pdev, PCI_D3hot, 0); | 5887 | pci_enable_wake(pdev, PCI_D3hot, 0); |
5364 | pci_enable_wake(pdev, PCI_D3cold, 0); | 5888 | pci_enable_wake(pdev, PCI_D3cold, 0); |
5365 | 5889 | ||
5366 | igb_set_interrupt_capability(adapter); | 5890 | if (igb_init_interrupt_scheme(adapter)) { |
5367 | |||
5368 | if (igb_alloc_queues(adapter)) { | ||
5369 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | 5891 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
5370 | return -ENOMEM; | 5892 | return -ENOMEM; |
5371 | } | 5893 | } |
5372 | 5894 | ||
5373 | /* e1000_power_up_phy(adapter); */ | ||
5374 | |||
5375 | igb_reset(adapter); | 5895 | igb_reset(adapter); |
5376 | 5896 | ||
5377 | /* let the f/w know that the h/w is now under the control of the | 5897 | /* let the f/w know that the h/w is now under the control of the |
@@ -5417,22 +5937,16 @@ static void igb_netpoll(struct net_device *netdev) | |||
5417 | int i; | 5937 | int i; |
5418 | 5938 | ||
5419 | if (!adapter->msix_entries) { | 5939 | if (!adapter->msix_entries) { |
5940 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | ||
5420 | igb_irq_disable(adapter); | 5941 | igb_irq_disable(adapter); |
5421 | napi_schedule(&adapter->rx_ring[0].napi); | 5942 | napi_schedule(&q_vector->napi); |
5422 | return; | 5943 | return; |
5423 | } | 5944 | } |
5424 | 5945 | ||
5425 | for (i = 0; i < adapter->num_tx_queues; i++) { | 5946 | for (i = 0; i < adapter->num_q_vectors; i++) { |
5426 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | 5947 | struct igb_q_vector *q_vector = adapter->q_vector[i]; |
5427 | wr32(E1000_EIMC, tx_ring->eims_value); | 5948 | wr32(E1000_EIMC, q_vector->eims_value); |
5428 | igb_clean_tx_irq(tx_ring); | 5949 | napi_schedule(&q_vector->napi); |
5429 | wr32(E1000_EIMS, tx_ring->eims_value); | ||
5430 | } | ||
5431 | |||
5432 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
5433 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | ||
5434 | wr32(E1000_EIMC, rx_ring->eims_value); | ||
5435 | napi_schedule(&rx_ring->napi); | ||
5436 | } | 5950 | } |
5437 | } | 5951 | } |
5438 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | 5952 | #endif /* CONFIG_NET_POLL_CONTROLLER */ |
@@ -5486,6 +6000,7 @@ static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |||
5486 | } else { | 6000 | } else { |
5487 | pci_set_master(pdev); | 6001 | pci_set_master(pdev); |
5488 | pci_restore_state(pdev); | 6002 | pci_restore_state(pdev); |
6003 | pci_save_state(pdev); | ||
5489 | 6004 | ||
5490 | pci_enable_wake(pdev, PCI_D3hot, 0); | 6005 | pci_enable_wake(pdev, PCI_D3hot, 0); |
5491 | pci_enable_wake(pdev, PCI_D3cold, 0); | 6006 | pci_enable_wake(pdev, PCI_D3cold, 0); |
@@ -5532,6 +6047,33 @@ static void igb_io_resume(struct pci_dev *pdev) | |||
5532 | igb_get_hw_control(adapter); | 6047 | igb_get_hw_control(adapter); |
5533 | } | 6048 | } |
5534 | 6049 | ||
6050 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, | ||
6051 | u8 qsel) | ||
6052 | { | ||
6053 | u32 rar_low, rar_high; | ||
6054 | struct e1000_hw *hw = &adapter->hw; | ||
6055 | |||
6056 | /* HW expects these in little endian so we reverse the byte order | ||
6057 | * from network order (big endian) to little endian | ||
6058 | */ | ||
6059 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | ||
6060 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | ||
6061 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | ||
6062 | |||
6063 | /* Indicate to hardware the Address is Valid. */ | ||
6064 | rar_high |= E1000_RAH_AV; | ||
6065 | |||
6066 | if (hw->mac.type == e1000_82575) | ||
6067 | rar_high |= E1000_RAH_POOL_1 * qsel; | ||
6068 | else | ||
6069 | rar_high |= E1000_RAH_POOL_1 << qsel; | ||
6070 | |||
6071 | wr32(E1000_RAL(index), rar_low); | ||
6072 | wrfl(); | ||
6073 | wr32(E1000_RAH(index), rar_high); | ||
6074 | wrfl(); | ||
6075 | } | ||
6076 | |||
5535 | static int igb_set_vf_mac(struct igb_adapter *adapter, | 6077 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
5536 | int vf, unsigned char *mac_addr) | 6078 | int vf, unsigned char *mac_addr) |
5537 | { | 6079 | { |
@@ -5542,28 +6084,74 @@ static int igb_set_vf_mac(struct igb_adapter *adapter, | |||
5542 | 6084 | ||
5543 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); | 6085 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
5544 | 6086 | ||
5545 | igb_rar_set(hw, mac_addr, rar_entry); | 6087 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
5546 | igb_set_rah_pool(hw, vf, rar_entry); | 6088 | |
6089 | return 0; | ||
6090 | } | ||
6091 | |||
6092 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) | ||
6093 | { | ||
6094 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
6095 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | ||
6096 | return -EINVAL; | ||
6097 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | ||
6098 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | ||
6099 | dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" | ||
6100 | " change effective."); | ||
6101 | if (test_bit(__IGB_DOWN, &adapter->state)) { | ||
6102 | dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," | ||
6103 | " but the PF device is not up.\n"); | ||
6104 | dev_warn(&adapter->pdev->dev, "Bring the PF device up before" | ||
6105 | " attempting to use the VF device.\n"); | ||
6106 | } | ||
6107 | return igb_set_vf_mac(adapter, vf, mac); | ||
6108 | } | ||
5547 | 6109 | ||
6110 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) | ||
6111 | { | ||
6112 | return -EOPNOTSUPP; | ||
6113 | } | ||
6114 | |||
6115 | static int igb_ndo_get_vf_config(struct net_device *netdev, | ||
6116 | int vf, struct ifla_vf_info *ivi) | ||
6117 | { | ||
6118 | struct igb_adapter *adapter = netdev_priv(netdev); | ||
6119 | if (vf >= adapter->vfs_allocated_count) | ||
6120 | return -EINVAL; | ||
6121 | ivi->vf = vf; | ||
6122 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | ||
6123 | ivi->tx_rate = 0; | ||
6124 | ivi->vlan = adapter->vf_data[vf].pf_vlan; | ||
6125 | ivi->qos = adapter->vf_data[vf].pf_qos; | ||
5548 | return 0; | 6126 | return 0; |
5549 | } | 6127 | } |
5550 | 6128 | ||
5551 | static void igb_vmm_control(struct igb_adapter *adapter) | 6129 | static void igb_vmm_control(struct igb_adapter *adapter) |
5552 | { | 6130 | { |
5553 | struct e1000_hw *hw = &adapter->hw; | 6131 | struct e1000_hw *hw = &adapter->hw; |
5554 | u32 reg_data; | 6132 | u32 reg; |
5555 | 6133 | ||
5556 | if (!adapter->vfs_allocated_count) | 6134 | /* replication is not supported for 82575 */ |
6135 | if (hw->mac.type == e1000_82575) | ||
5557 | return; | 6136 | return; |
5558 | 6137 | ||
5559 | /* VF's need PF reset indication before they | 6138 | /* enable replication vlan tag stripping */ |
5560 | * can send/receive mail */ | 6139 | reg = rd32(E1000_RPLOLR); |
5561 | reg_data = rd32(E1000_CTRL_EXT); | 6140 | reg |= E1000_RPLOLR_STRVLAN; |
5562 | reg_data |= E1000_CTRL_EXT_PFRSTD; | 6141 | wr32(E1000_RPLOLR, reg); |
5563 | wr32(E1000_CTRL_EXT, reg_data); | ||
5564 | 6142 | ||
5565 | igb_vmdq_set_loopback_pf(hw, true); | 6143 | /* notify HW that the MAC is adding vlan tags */ |
5566 | igb_vmdq_set_replication_pf(hw, true); | 6144 | reg = rd32(E1000_DTXCTL); |
6145 | reg |= E1000_DTXCTL_VLAN_ADDED; | ||
6146 | wr32(E1000_DTXCTL, reg); | ||
6147 | |||
6148 | if (adapter->vfs_allocated_count) { | ||
6149 | igb_vmdq_set_loopback_pf(hw, true); | ||
6150 | igb_vmdq_set_replication_pf(hw, true); | ||
6151 | } else { | ||
6152 | igb_vmdq_set_loopback_pf(hw, false); | ||
6153 | igb_vmdq_set_replication_pf(hw, false); | ||
6154 | } | ||
5567 | } | 6155 | } |
5568 | 6156 | ||
5569 | /* igb_main.c */ | 6157 | /* igb_main.c */ |