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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-02 01:48:13 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-27 03:58:30 -0400
commitff5a3b509e4ec96a2a4c57052a2d96e855778a24 (patch)
treecf7b81e65c03ab1cbadd949742aed7146cb80dd0 /drivers/net/hippi
parent224cf5ad14c038b13c119dff29422f178a306f54 (diff)
hippi: Move the HIPPI driver
Move the HIPPI driver into drivers/net/hippi/ and make the necessary Kconfig and Makefile changes. CC: Jes Sorensen <jes@wildopensource.com> CC: Jes Sorensen <jes@trained-monkey.org> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/hippi')
-rw-r--r--drivers/net/hippi/Kconfig39
-rw-r--r--drivers/net/hippi/Makefile5
-rw-r--r--drivers/net/hippi/rrunner.c1716
-rw-r--r--drivers/net/hippi/rrunner.h846
4 files changed, 2606 insertions, 0 deletions
diff --git a/drivers/net/hippi/Kconfig b/drivers/net/hippi/Kconfig
new file mode 100644
index 000000000000..7393eb732ee6
--- /dev/null
+++ b/drivers/net/hippi/Kconfig
@@ -0,0 +1,39 @@
1#
2# HIPPI network device configuration
3#
4
5config HIPPI
6 bool "HIPPI driver support (EXPERIMENTAL)"
7 depends on EXPERIMENTAL && INET && PCI
8 ---help---
9 HIgh Performance Parallel Interface (HIPPI) is a 800Mbit/sec and
10 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
11 can run over copper (25m) or fiber (300m on multi-mode or 10km on
12 single-mode). HIPPI networks are commonly used for clusters and to
13 connect to super computers. If you are connected to a HIPPI network
14 and have a HIPPI network card in your computer that you want to use
15 under Linux, say Y here (you must also remember to enable the driver
16 for your HIPPI card below). Most people will say N here.
17
18if HIPPI
19
20config ROADRUNNER
21 tristate "Essential RoadRunner HIPPI PCI adapter support (EXPERIMENTAL)"
22 depends on PCI
23 ---help---
24 Say Y here if this is your PCI HIPPI network card.
25
26 To compile this driver as a module, choose M here: the module
27 will be called rrunner. If unsure, say N.
28
29config ROADRUNNER_LARGE_RINGS
30 bool "Use large TX/RX rings (EXPERIMENTAL)"
31 depends on ROADRUNNER
32 ---help---
33 If you say Y here, the RoadRunner driver will preallocate up to 2 MB
34 of additional memory to allow for fastest operation, both for
35 transmitting and receiving. This memory cannot be used by any other
36 kernel code or by user space programs. Say Y here only if you have
37 the memory.
38
39endif /* HIPPI */
diff --git a/drivers/net/hippi/Makefile b/drivers/net/hippi/Makefile
new file mode 100644
index 000000000000..b95d629baee5
--- /dev/null
+++ b/drivers/net/hippi/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the HIPPI network device drivers.
3#
4
5obj-$(CONFIG_ROADRUNNER) += rrunner.o
diff --git a/drivers/net/hippi/rrunner.c b/drivers/net/hippi/rrunner.c
new file mode 100644
index 000000000000..e68c941926f1
--- /dev/null
+++ b/drivers/net/hippi/rrunner.c
@@ -0,0 +1,1716 @@
1/*
2 * rrunner.c: Linux driver for the Essential RoadRunner HIPPI board.
3 *
4 * Copyright (C) 1998-2002 by Jes Sorensen, <jes@wildopensource.com>.
5 *
6 * Thanks to Essential Communication for providing us with hardware
7 * and very comprehensive documentation without which I would not have
8 * been able to write this driver. A special thank you to John Gibbon
9 * for sorting out the legal issues, with the NDA, allowing the code to
10 * be released under the GPL.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * Thanks to Jayaram Bhat from ODS/Essential for fixing some of the
18 * stupid bugs in my code.
19 *
20 * Softnet support and various other patches from Val Henson of
21 * ODS/Essential.
22 *
23 * PCI DMA mapping code partly based on work by Francois Romieu.
24 */
25
26
27#define DEBUG 1
28#define RX_DMA_SKBUFF 1
29#define PKT_COPY_THRESHOLD 512
30
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/ioport.h>
35#include <linux/pci.h>
36#include <linux/kernel.h>
37#include <linux/netdevice.h>
38#include <linux/hippidevice.h>
39#include <linux/skbuff.h>
40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/mm.h>
43#include <linux/slab.h>
44#include <net/sock.h>
45
46#include <asm/system.h>
47#include <asm/cache.h>
48#include <asm/byteorder.h>
49#include <asm/io.h>
50#include <asm/irq.h>
51#include <asm/uaccess.h>
52
53#define rr_if_busy(dev) netif_queue_stopped(dev)
54#define rr_if_running(dev) netif_running(dev)
55
56#include "rrunner.h"
57
58#define RUN_AT(x) (jiffies + (x))
59
60
61MODULE_AUTHOR("Jes Sorensen <jes@wildopensource.com>");
62MODULE_DESCRIPTION("Essential RoadRunner HIPPI driver");
63MODULE_LICENSE("GPL");
64
65static char version[] __devinitdata = "rrunner.c: v0.50 11/11/2002 Jes Sorensen (jes@wildopensource.com)\n";
66
67
68static const struct net_device_ops rr_netdev_ops = {
69 .ndo_open = rr_open,
70 .ndo_stop = rr_close,
71 .ndo_do_ioctl = rr_ioctl,
72 .ndo_start_xmit = rr_start_xmit,
73 .ndo_change_mtu = hippi_change_mtu,
74 .ndo_set_mac_address = hippi_mac_addr,
75};
76
77/*
78 * Implementation notes:
79 *
80 * The DMA engine only allows for DMA within physical 64KB chunks of
81 * memory. The current approach of the driver (and stack) is to use
82 * linear blocks of memory for the skbuffs. However, as the data block
83 * is always the first part of the skb and skbs are 2^n aligned so we
84 * are guarantted to get the whole block within one 64KB align 64KB
85 * chunk.
86 *
87 * On the long term, relying on being able to allocate 64KB linear
88 * chunks of memory is not feasible and the skb handling code and the
89 * stack will need to know about I/O vectors or something similar.
90 */
91
92static int __devinit rr_init_one(struct pci_dev *pdev,
93 const struct pci_device_id *ent)
94{
95 struct net_device *dev;
96 static int version_disp;
97 u8 pci_latency;
98 struct rr_private *rrpriv;
99 void *tmpptr;
100 dma_addr_t ring_dma;
101 int ret = -ENOMEM;
102
103 dev = alloc_hippi_dev(sizeof(struct rr_private));
104 if (!dev)
105 goto out3;
106
107 ret = pci_enable_device(pdev);
108 if (ret) {
109 ret = -ENODEV;
110 goto out2;
111 }
112
113 rrpriv = netdev_priv(dev);
114
115 SET_NETDEV_DEV(dev, &pdev->dev);
116
117 if (pci_request_regions(pdev, "rrunner")) {
118 ret = -EIO;
119 goto out;
120 }
121
122 pci_set_drvdata(pdev, dev);
123
124 rrpriv->pci_dev = pdev;
125
126 spin_lock_init(&rrpriv->lock);
127
128 dev->irq = pdev->irq;
129 dev->netdev_ops = &rr_netdev_ops;
130
131 dev->base_addr = pci_resource_start(pdev, 0);
132
133 /* display version info if adapter is found */
134 if (!version_disp) {
135 /* set display flag to TRUE so that */
136 /* we only display this string ONCE */
137 version_disp = 1;
138 printk(version);
139 }
140
141 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
142 if (pci_latency <= 0x58){
143 pci_latency = 0x58;
144 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, pci_latency);
145 }
146
147 pci_set_master(pdev);
148
149 printk(KERN_INFO "%s: Essential RoadRunner serial HIPPI "
150 "at 0x%08lx, irq %i, PCI latency %i\n", dev->name,
151 dev->base_addr, dev->irq, pci_latency);
152
153 /*
154 * Remap the regs into kernel space.
155 */
156
157 rrpriv->regs = ioremap(dev->base_addr, 0x1000);
158
159 if (!rrpriv->regs){
160 printk(KERN_ERR "%s: Unable to map I/O register, "
161 "RoadRunner will be disabled.\n", dev->name);
162 ret = -EIO;
163 goto out;
164 }
165
166 tmpptr = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
167 rrpriv->tx_ring = tmpptr;
168 rrpriv->tx_ring_dma = ring_dma;
169
170 if (!tmpptr) {
171 ret = -ENOMEM;
172 goto out;
173 }
174
175 tmpptr = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
176 rrpriv->rx_ring = tmpptr;
177 rrpriv->rx_ring_dma = ring_dma;
178
179 if (!tmpptr) {
180 ret = -ENOMEM;
181 goto out;
182 }
183
184 tmpptr = pci_alloc_consistent(pdev, EVT_RING_SIZE, &ring_dma);
185 rrpriv->evt_ring = tmpptr;
186 rrpriv->evt_ring_dma = ring_dma;
187
188 if (!tmpptr) {
189 ret = -ENOMEM;
190 goto out;
191 }
192
193 /*
194 * Don't access any register before this point!
195 */
196#ifdef __BIG_ENDIAN
197 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
198 &rrpriv->regs->HostCtrl);
199#endif
200 /*
201 * Need to add a case for little-endian 64-bit hosts here.
202 */
203
204 rr_init(dev);
205
206 dev->base_addr = 0;
207
208 ret = register_netdev(dev);
209 if (ret)
210 goto out;
211 return 0;
212
213 out:
214 if (rrpriv->rx_ring)
215 pci_free_consistent(pdev, RX_TOTAL_SIZE, rrpriv->rx_ring,
216 rrpriv->rx_ring_dma);
217 if (rrpriv->tx_ring)
218 pci_free_consistent(pdev, TX_TOTAL_SIZE, rrpriv->tx_ring,
219 rrpriv->tx_ring_dma);
220 if (rrpriv->regs)
221 iounmap(rrpriv->regs);
222 if (pdev) {
223 pci_release_regions(pdev);
224 pci_set_drvdata(pdev, NULL);
225 }
226 out2:
227 free_netdev(dev);
228 out3:
229 return ret;
230}
231
232static void __devexit rr_remove_one (struct pci_dev *pdev)
233{
234 struct net_device *dev = pci_get_drvdata(pdev);
235
236 if (dev) {
237 struct rr_private *rr = netdev_priv(dev);
238
239 if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)){
240 printk(KERN_ERR "%s: trying to unload running NIC\n",
241 dev->name);
242 writel(HALT_NIC, &rr->regs->HostCtrl);
243 }
244
245 pci_free_consistent(pdev, EVT_RING_SIZE, rr->evt_ring,
246 rr->evt_ring_dma);
247 pci_free_consistent(pdev, RX_TOTAL_SIZE, rr->rx_ring,
248 rr->rx_ring_dma);
249 pci_free_consistent(pdev, TX_TOTAL_SIZE, rr->tx_ring,
250 rr->tx_ring_dma);
251 unregister_netdev(dev);
252 iounmap(rr->regs);
253 free_netdev(dev);
254 pci_release_regions(pdev);
255 pci_disable_device(pdev);
256 pci_set_drvdata(pdev, NULL);
257 }
258}
259
260
261/*
262 * Commands are considered to be slow, thus there is no reason to
263 * inline this.
264 */
265static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
266{
267 struct rr_regs __iomem *regs;
268 u32 idx;
269
270 regs = rrpriv->regs;
271 /*
272 * This is temporary - it will go away in the final version.
273 * We probably also want to make this function inline.
274 */
275 if (readl(&regs->HostCtrl) & NIC_HALTED){
276 printk("issuing command for halted NIC, code 0x%x, "
277 "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));
278 if (readl(&regs->Mode) & FATAL_ERR)
279 printk("error codes Fail1 %02x, Fail2 %02x\n",
280 readl(&regs->Fail1), readl(&regs->Fail2));
281 }
282
283 idx = rrpriv->info->cmd_ctrl.pi;
284
285 writel(*(u32*)(cmd), &regs->CmdRing[idx]);
286 wmb();
287
288 idx = (idx - 1) % CMD_RING_ENTRIES;
289 rrpriv->info->cmd_ctrl.pi = idx;
290 wmb();
291
292 if (readl(&regs->Mode) & FATAL_ERR)
293 printk("error code %02x\n", readl(&regs->Fail1));
294}
295
296
297/*
298 * Reset the board in a sensible manner. The NIC is already halted
299 * when we get here and a spin-lock is held.
300 */
301static int rr_reset(struct net_device *dev)
302{
303 struct rr_private *rrpriv;
304 struct rr_regs __iomem *regs;
305 u32 start_pc;
306 int i;
307
308 rrpriv = netdev_priv(dev);
309 regs = rrpriv->regs;
310
311 rr_load_firmware(dev);
312
313 writel(0x01000000, &regs->TX_state);
314 writel(0xff800000, &regs->RX_state);
315 writel(0, &regs->AssistState);
316 writel(CLEAR_INTA, &regs->LocalCtrl);
317 writel(0x01, &regs->BrkPt);
318 writel(0, &regs->Timer);
319 writel(0, &regs->TimerRef);
320 writel(RESET_DMA, &regs->DmaReadState);
321 writel(RESET_DMA, &regs->DmaWriteState);
322 writel(0, &regs->DmaWriteHostHi);
323 writel(0, &regs->DmaWriteHostLo);
324 writel(0, &regs->DmaReadHostHi);
325 writel(0, &regs->DmaReadHostLo);
326 writel(0, &regs->DmaReadLen);
327 writel(0, &regs->DmaWriteLen);
328 writel(0, &regs->DmaWriteLcl);
329 writel(0, &regs->DmaWriteIPchecksum);
330 writel(0, &regs->DmaReadLcl);
331 writel(0, &regs->DmaReadIPchecksum);
332 writel(0, &regs->PciState);
333#if (BITS_PER_LONG == 64) && defined __LITTLE_ENDIAN
334 writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);
335#elif (BITS_PER_LONG == 64)
336 writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);
337#else
338 writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);
339#endif
340
341#if 0
342 /*
343 * Don't worry, this is just black magic.
344 */
345 writel(0xdf000, &regs->RxBase);
346 writel(0xdf000, &regs->RxPrd);
347 writel(0xdf000, &regs->RxCon);
348 writel(0xce000, &regs->TxBase);
349 writel(0xce000, &regs->TxPrd);
350 writel(0xce000, &regs->TxCon);
351 writel(0, &regs->RxIndPro);
352 writel(0, &regs->RxIndCon);
353 writel(0, &regs->RxIndRef);
354 writel(0, &regs->TxIndPro);
355 writel(0, &regs->TxIndCon);
356 writel(0, &regs->TxIndRef);
357 writel(0xcc000, &regs->pad10[0]);
358 writel(0, &regs->DrCmndPro);
359 writel(0, &regs->DrCmndCon);
360 writel(0, &regs->DwCmndPro);
361 writel(0, &regs->DwCmndCon);
362 writel(0, &regs->DwCmndRef);
363 writel(0, &regs->DrDataPro);
364 writel(0, &regs->DrDataCon);
365 writel(0, &regs->DrDataRef);
366 writel(0, &regs->DwDataPro);
367 writel(0, &regs->DwDataCon);
368 writel(0, &regs->DwDataRef);
369#endif
370
371 writel(0xffffffff, &regs->MbEvent);
372 writel(0, &regs->Event);
373
374 writel(0, &regs->TxPi);
375 writel(0, &regs->IpRxPi);
376
377 writel(0, &regs->EvtCon);
378 writel(0, &regs->EvtPrd);
379
380 rrpriv->info->evt_ctrl.pi = 0;
381
382 for (i = 0; i < CMD_RING_ENTRIES; i++)
383 writel(0, &regs->CmdRing[i]);
384
385/*
386 * Why 32 ? is this not cache line size dependent?
387 */
388 writel(RBURST_64|WBURST_64, &regs->PciState);
389 wmb();
390
391 start_pc = rr_read_eeprom_word(rrpriv,
392 offsetof(struct eeprom, rncd_info.FwStart));
393
394#if (DEBUG > 1)
395 printk("%s: Executing firmware at address 0x%06x\n",
396 dev->name, start_pc);
397#endif
398
399 writel(start_pc + 0x800, &regs->Pc);
400 wmb();
401 udelay(5);
402
403 writel(start_pc, &regs->Pc);
404 wmb();
405
406 return 0;
407}
408
409
410/*
411 * Read a string from the EEPROM.
412 */
413static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
414 unsigned long offset,
415 unsigned char *buf,
416 unsigned long length)
417{
418 struct rr_regs __iomem *regs = rrpriv->regs;
419 u32 misc, io, host, i;
420
421 io = readl(&regs->ExtIo);
422 writel(0, &regs->ExtIo);
423 misc = readl(&regs->LocalCtrl);
424 writel(0, &regs->LocalCtrl);
425 host = readl(&regs->HostCtrl);
426 writel(host | HALT_NIC, &regs->HostCtrl);
427 mb();
428
429 for (i = 0; i < length; i++){
430 writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
431 mb();
432 buf[i] = (readl(&regs->WinData) >> 24) & 0xff;
433 mb();
434 }
435
436 writel(host, &regs->HostCtrl);
437 writel(misc, &regs->LocalCtrl);
438 writel(io, &regs->ExtIo);
439 mb();
440 return i;
441}
442
443
444/*
445 * Shortcut to read one word (4 bytes) out of the EEPROM and convert
446 * it to our CPU byte-order.
447 */
448static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
449 size_t offset)
450{
451 __be32 word;
452
453 if ((rr_read_eeprom(rrpriv, offset,
454 (unsigned char *)&word, 4) == 4))
455 return be32_to_cpu(word);
456 return 0;
457}
458
459
460/*
461 * Write a string to the EEPROM.
462 *
463 * This is only called when the firmware is not running.
464 */
465static unsigned int write_eeprom(struct rr_private *rrpriv,
466 unsigned long offset,
467 unsigned char *buf,
468 unsigned long length)
469{
470 struct rr_regs __iomem *regs = rrpriv->regs;
471 u32 misc, io, data, i, j, ready, error = 0;
472
473 io = readl(&regs->ExtIo);
474 writel(0, &regs->ExtIo);
475 misc = readl(&regs->LocalCtrl);
476 writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);
477 mb();
478
479 for (i = 0; i < length; i++){
480 writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
481 mb();
482 data = buf[i] << 24;
483 /*
484 * Only try to write the data if it is not the same
485 * value already.
486 */
487 if ((readl(&regs->WinData) & 0xff000000) != data){
488 writel(data, &regs->WinData);
489 ready = 0;
490 j = 0;
491 mb();
492 while(!ready){
493 udelay(20);
494 if ((readl(&regs->WinData) & 0xff000000) ==
495 data)
496 ready = 1;
497 mb();
498 if (j++ > 5000){
499 printk("data mismatch: %08x, "
500 "WinData %08x\n", data,
501 readl(&regs->WinData));
502 ready = 1;
503 error = 1;
504 }
505 }
506 }
507 }
508
509 writel(misc, &regs->LocalCtrl);
510 writel(io, &regs->ExtIo);
511 mb();
512
513 return error;
514}
515
516
517static int __devinit rr_init(struct net_device *dev)
518{
519 struct rr_private *rrpriv;
520 struct rr_regs __iomem *regs;
521 u32 sram_size, rev;
522
523 rrpriv = netdev_priv(dev);
524 regs = rrpriv->regs;
525
526 rev = readl(&regs->FwRev);
527 rrpriv->fw_rev = rev;
528 if (rev > 0x00020024)
529 printk(" Firmware revision: %i.%i.%i\n", (rev >> 16),
530 ((rev >> 8) & 0xff), (rev & 0xff));
531 else if (rev >= 0x00020000) {
532 printk(" Firmware revision: %i.%i.%i (2.0.37 or "
533 "later is recommended)\n", (rev >> 16),
534 ((rev >> 8) & 0xff), (rev & 0xff));
535 }else{
536 printk(" Firmware revision too old: %i.%i.%i, please "
537 "upgrade to 2.0.37 or later.\n",
538 (rev >> 16), ((rev >> 8) & 0xff), (rev & 0xff));
539 }
540
541#if (DEBUG > 2)
542 printk(" Maximum receive rings %i\n", readl(&regs->MaxRxRng));
543#endif
544
545 /*
546 * Read the hardware address from the eeprom. The HW address
547 * is not really necessary for HIPPI but awfully convenient.
548 * The pointer arithmetic to put it in dev_addr is ugly, but
549 * Donald Becker does it this way for the GigE version of this
550 * card and it's shorter and more portable than any
551 * other method I've seen. -VAL
552 */
553
554 *(__be16 *)(dev->dev_addr) =
555 htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
556 *(__be32 *)(dev->dev_addr+2) =
557 htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
558
559 printk(" MAC: %pM\n", dev->dev_addr);
560
561 sram_size = rr_read_eeprom_word(rrpriv, 8);
562 printk(" SRAM size 0x%06x\n", sram_size);
563
564 return 0;
565}
566
567
568static int rr_init1(struct net_device *dev)
569{
570 struct rr_private *rrpriv;
571 struct rr_regs __iomem *regs;
572 unsigned long myjif, flags;
573 struct cmd cmd;
574 u32 hostctrl;
575 int ecode = 0;
576 short i;
577
578 rrpriv = netdev_priv(dev);
579 regs = rrpriv->regs;
580
581 spin_lock_irqsave(&rrpriv->lock, flags);
582
583 hostctrl = readl(&regs->HostCtrl);
584 writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);
585 wmb();
586
587 if (hostctrl & PARITY_ERR){
588 printk("%s: Parity error halting NIC - this is serious!\n",
589 dev->name);
590 spin_unlock_irqrestore(&rrpriv->lock, flags);
591 ecode = -EFAULT;
592 goto error;
593 }
594
595 set_rxaddr(regs, rrpriv->rx_ctrl_dma);
596 set_infoaddr(regs, rrpriv->info_dma);
597
598 rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
599 rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
600 rrpriv->info->evt_ctrl.mode = 0;
601 rrpriv->info->evt_ctrl.pi = 0;
602 set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
603
604 rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
605 rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
606 rrpriv->info->cmd_ctrl.mode = 0;
607 rrpriv->info->cmd_ctrl.pi = 15;
608
609 for (i = 0; i < CMD_RING_ENTRIES; i++) {
610 writel(0, &regs->CmdRing[i]);
611 }
612
613 for (i = 0; i < TX_RING_ENTRIES; i++) {
614 rrpriv->tx_ring[i].size = 0;
615 set_rraddr(&rrpriv->tx_ring[i].addr, 0);
616 rrpriv->tx_skbuff[i] = NULL;
617 }
618 rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
619 rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
620 rrpriv->info->tx_ctrl.mode = 0;
621 rrpriv->info->tx_ctrl.pi = 0;
622 set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
623
624 /*
625 * Set dirty_tx before we start receiving interrupts, otherwise
626 * the interrupt handler might think it is supposed to process
627 * tx ints before we are up and running, which may cause a null
628 * pointer access in the int handler.
629 */
630 rrpriv->tx_full = 0;
631 rrpriv->cur_rx = 0;
632 rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
633
634 rr_reset(dev);
635
636 /* Tuning values */
637 writel(0x5000, &regs->ConRetry);
638 writel(0x100, &regs->ConRetryTmr);
639 writel(0x500000, &regs->ConTmout);
640 writel(0x60, &regs->IntrTmr);
641 writel(0x500000, &regs->TxDataMvTimeout);
642 writel(0x200000, &regs->RxDataMvTimeout);
643 writel(0x80, &regs->WriteDmaThresh);
644 writel(0x80, &regs->ReadDmaThresh);
645
646 rrpriv->fw_running = 0;
647 wmb();
648
649 hostctrl &= ~(HALT_NIC | INVALID_INST_B | PARITY_ERR);
650 writel(hostctrl, &regs->HostCtrl);
651 wmb();
652
653 spin_unlock_irqrestore(&rrpriv->lock, flags);
654
655 for (i = 0; i < RX_RING_ENTRIES; i++) {
656 struct sk_buff *skb;
657 dma_addr_t addr;
658
659 rrpriv->rx_ring[i].mode = 0;
660 skb = alloc_skb(dev->mtu + HIPPI_HLEN, GFP_ATOMIC);
661 if (!skb) {
662 printk(KERN_WARNING "%s: Unable to allocate memory "
663 "for receive ring - halting NIC\n", dev->name);
664 ecode = -ENOMEM;
665 goto error;
666 }
667 rrpriv->rx_skbuff[i] = skb;
668 addr = pci_map_single(rrpriv->pci_dev, skb->data,
669 dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
670 /*
671 * Sanity test to see if we conflict with the DMA
672 * limitations of the Roadrunner.
673 */
674 if ((((unsigned long)skb->data) & 0xfff) > ~65320)
675 printk("skb alloc error\n");
676
677 set_rraddr(&rrpriv->rx_ring[i].addr, addr);
678 rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
679 }
680
681 rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
682 rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
683 rrpriv->rx_ctrl[4].mode = 8;
684 rrpriv->rx_ctrl[4].pi = 0;
685 wmb();
686 set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
687
688 udelay(1000);
689
690 /*
691 * Now start the FirmWare.
692 */
693 cmd.code = C_START_FW;
694 cmd.ring = 0;
695 cmd.index = 0;
696
697 rr_issue_cmd(rrpriv, &cmd);
698
699 /*
700 * Give the FirmWare time to chew on the `get running' command.
701 */
702 myjif = jiffies + 5 * HZ;
703 while (time_before(jiffies, myjif) && !rrpriv->fw_running)
704 cpu_relax();
705
706 netif_start_queue(dev);
707
708 return ecode;
709
710 error:
711 /*
712 * We might have gotten here because we are out of memory,
713 * make sure we release everything we allocated before failing
714 */
715 for (i = 0; i < RX_RING_ENTRIES; i++) {
716 struct sk_buff *skb = rrpriv->rx_skbuff[i];
717
718 if (skb) {
719 pci_unmap_single(rrpriv->pci_dev,
720 rrpriv->rx_ring[i].addr.addrlo,
721 dev->mtu + HIPPI_HLEN,
722 PCI_DMA_FROMDEVICE);
723 rrpriv->rx_ring[i].size = 0;
724 set_rraddr(&rrpriv->rx_ring[i].addr, 0);
725 dev_kfree_skb(skb);
726 rrpriv->rx_skbuff[i] = NULL;
727 }
728 }
729 return ecode;
730}
731
732
733/*
734 * All events are considered to be slow (RX/TX ints do not generate
735 * events) and are handled here, outside the main interrupt handler,
736 * to reduce the size of the handler.
737 */
738static u32 rr_handle_event(struct net_device *dev, u32 prodidx, u32 eidx)
739{
740 struct rr_private *rrpriv;
741 struct rr_regs __iomem *regs;
742 u32 tmp;
743
744 rrpriv = netdev_priv(dev);
745 regs = rrpriv->regs;
746
747 while (prodidx != eidx){
748 switch (rrpriv->evt_ring[eidx].code){
749 case E_NIC_UP:
750 tmp = readl(&regs->FwRev);
751 printk(KERN_INFO "%s: Firmware revision %i.%i.%i "
752 "up and running\n", dev->name,
753 (tmp >> 16), ((tmp >> 8) & 0xff), (tmp & 0xff));
754 rrpriv->fw_running = 1;
755 writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);
756 wmb();
757 break;
758 case E_LINK_ON:
759 printk(KERN_INFO "%s: Optical link ON\n", dev->name);
760 break;
761 case E_LINK_OFF:
762 printk(KERN_INFO "%s: Optical link OFF\n", dev->name);
763 break;
764 case E_RX_IDLE:
765 printk(KERN_WARNING "%s: RX data not moving\n",
766 dev->name);
767 goto drop;
768 case E_WATCHDOG:
769 printk(KERN_INFO "%s: The watchdog is here to see "
770 "us\n", dev->name);
771 break;
772 case E_INTERN_ERR:
773 printk(KERN_ERR "%s: HIPPI Internal NIC error\n",
774 dev->name);
775 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
776 &regs->HostCtrl);
777 wmb();
778 break;
779 case E_HOST_ERR:
780 printk(KERN_ERR "%s: Host software error\n",
781 dev->name);
782 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
783 &regs->HostCtrl);
784 wmb();
785 break;
786 /*
787 * TX events.
788 */
789 case E_CON_REJ:
790 printk(KERN_WARNING "%s: Connection rejected\n",
791 dev->name);
792 dev->stats.tx_aborted_errors++;
793 break;
794 case E_CON_TMOUT:
795 printk(KERN_WARNING "%s: Connection timeout\n",
796 dev->name);
797 break;
798 case E_DISC_ERR:
799 printk(KERN_WARNING "%s: HIPPI disconnect error\n",
800 dev->name);
801 dev->stats.tx_aborted_errors++;
802 break;
803 case E_INT_PRTY:
804 printk(KERN_ERR "%s: HIPPI Internal Parity error\n",
805 dev->name);
806 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
807 &regs->HostCtrl);
808 wmb();
809 break;
810 case E_TX_IDLE:
811 printk(KERN_WARNING "%s: Transmitter idle\n",
812 dev->name);
813 break;
814 case E_TX_LINK_DROP:
815 printk(KERN_WARNING "%s: Link lost during transmit\n",
816 dev->name);
817 dev->stats.tx_aborted_errors++;
818 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
819 &regs->HostCtrl);
820 wmb();
821 break;
822 case E_TX_INV_RNG:
823 printk(KERN_ERR "%s: Invalid send ring block\n",
824 dev->name);
825 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
826 &regs->HostCtrl);
827 wmb();
828 break;
829 case E_TX_INV_BUF:
830 printk(KERN_ERR "%s: Invalid send buffer address\n",
831 dev->name);
832 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
833 &regs->HostCtrl);
834 wmb();
835 break;
836 case E_TX_INV_DSC:
837 printk(KERN_ERR "%s: Invalid descriptor address\n",
838 dev->name);
839 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
840 &regs->HostCtrl);
841 wmb();
842 break;
843 /*
844 * RX events.
845 */
846 case E_RX_RNG_OUT:
847 printk(KERN_INFO "%s: Receive ring full\n", dev->name);
848 break;
849
850 case E_RX_PAR_ERR:
851 printk(KERN_WARNING "%s: Receive parity error\n",
852 dev->name);
853 goto drop;
854 case E_RX_LLRC_ERR:
855 printk(KERN_WARNING "%s: Receive LLRC error\n",
856 dev->name);
857 goto drop;
858 case E_PKT_LN_ERR:
859 printk(KERN_WARNING "%s: Receive packet length "
860 "error\n", dev->name);
861 goto drop;
862 case E_DTA_CKSM_ERR:
863 printk(KERN_WARNING "%s: Data checksum error\n",
864 dev->name);
865 goto drop;
866 case E_SHT_BST:
867 printk(KERN_WARNING "%s: Unexpected short burst "
868 "error\n", dev->name);
869 goto drop;
870 case E_STATE_ERR:
871 printk(KERN_WARNING "%s: Recv. state transition"
872 " error\n", dev->name);
873 goto drop;
874 case E_UNEXP_DATA:
875 printk(KERN_WARNING "%s: Unexpected data error\n",
876 dev->name);
877 goto drop;
878 case E_LST_LNK_ERR:
879 printk(KERN_WARNING "%s: Link lost error\n",
880 dev->name);
881 goto drop;
882 case E_FRM_ERR:
883 printk(KERN_WARNING "%s: Framming Error\n",
884 dev->name);
885 goto drop;
886 case E_FLG_SYN_ERR:
887 printk(KERN_WARNING "%s: Flag sync. lost during "
888 "packet\n", dev->name);
889 goto drop;
890 case E_RX_INV_BUF:
891 printk(KERN_ERR "%s: Invalid receive buffer "
892 "address\n", dev->name);
893 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
894 &regs->HostCtrl);
895 wmb();
896 break;
897 case E_RX_INV_DSC:
898 printk(KERN_ERR "%s: Invalid receive descriptor "
899 "address\n", dev->name);
900 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
901 &regs->HostCtrl);
902 wmb();
903 break;
904 case E_RNG_BLK:
905 printk(KERN_ERR "%s: Invalid ring block\n",
906 dev->name);
907 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
908 &regs->HostCtrl);
909 wmb();
910 break;
911 drop:
912 /* Label packet to be dropped.
913 * Actual dropping occurs in rx
914 * handling.
915 *
916 * The index of packet we get to drop is
917 * the index of the packet following
918 * the bad packet. -kbf
919 */
920 {
921 u16 index = rrpriv->evt_ring[eidx].index;
922 index = (index + (RX_RING_ENTRIES - 1)) %
923 RX_RING_ENTRIES;
924 rrpriv->rx_ring[index].mode |=
925 (PACKET_BAD | PACKET_END);
926 }
927 break;
928 default:
929 printk(KERN_WARNING "%s: Unhandled event 0x%02x\n",
930 dev->name, rrpriv->evt_ring[eidx].code);
931 }
932 eidx = (eidx + 1) % EVT_RING_ENTRIES;
933 }
934
935 rrpriv->info->evt_ctrl.pi = eidx;
936 wmb();
937 return eidx;
938}
939
940
941static void rx_int(struct net_device *dev, u32 rxlimit, u32 index)
942{
943 struct rr_private *rrpriv = netdev_priv(dev);
944 struct rr_regs __iomem *regs = rrpriv->regs;
945
946 do {
947 struct rx_desc *desc;
948 u32 pkt_len;
949
950 desc = &(rrpriv->rx_ring[index]);
951 pkt_len = desc->size;
952#if (DEBUG > 2)
953 printk("index %i, rxlimit %i\n", index, rxlimit);
954 printk("len %x, mode %x\n", pkt_len, desc->mode);
955#endif
956 if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
957 dev->stats.rx_dropped++;
958 goto defer;
959 }
960
961 if (pkt_len > 0){
962 struct sk_buff *skb, *rx_skb;
963
964 rx_skb = rrpriv->rx_skbuff[index];
965
966 if (pkt_len < PKT_COPY_THRESHOLD) {
967 skb = alloc_skb(pkt_len, GFP_ATOMIC);
968 if (skb == NULL){
969 printk(KERN_WARNING "%s: Unable to allocate skb (%i bytes), deferring packet\n", dev->name, pkt_len);
970 dev->stats.rx_dropped++;
971 goto defer;
972 } else {
973 pci_dma_sync_single_for_cpu(rrpriv->pci_dev,
974 desc->addr.addrlo,
975 pkt_len,
976 PCI_DMA_FROMDEVICE);
977
978 memcpy(skb_put(skb, pkt_len),
979 rx_skb->data, pkt_len);
980
981 pci_dma_sync_single_for_device(rrpriv->pci_dev,
982 desc->addr.addrlo,
983 pkt_len,
984 PCI_DMA_FROMDEVICE);
985 }
986 }else{
987 struct sk_buff *newskb;
988
989 newskb = alloc_skb(dev->mtu + HIPPI_HLEN,
990 GFP_ATOMIC);
991 if (newskb){
992 dma_addr_t addr;
993
994 pci_unmap_single(rrpriv->pci_dev,
995 desc->addr.addrlo, dev->mtu +
996 HIPPI_HLEN, PCI_DMA_FROMDEVICE);
997 skb = rx_skb;
998 skb_put(skb, pkt_len);
999 rrpriv->rx_skbuff[index] = newskb;
1000 addr = pci_map_single(rrpriv->pci_dev,
1001 newskb->data,
1002 dev->mtu + HIPPI_HLEN,
1003 PCI_DMA_FROMDEVICE);
1004 set_rraddr(&desc->addr, addr);
1005 } else {
1006 printk("%s: Out of memory, deferring "
1007 "packet\n", dev->name);
1008 dev->stats.rx_dropped++;
1009 goto defer;
1010 }
1011 }
1012 skb->protocol = hippi_type_trans(skb, dev);
1013
1014 netif_rx(skb); /* send it up */
1015
1016 dev->stats.rx_packets++;
1017 dev->stats.rx_bytes += pkt_len;
1018 }
1019 defer:
1020 desc->mode = 0;
1021 desc->size = dev->mtu + HIPPI_HLEN;
1022
1023 if ((index & 7) == 7)
1024 writel(index, &regs->IpRxPi);
1025
1026 index = (index + 1) % RX_RING_ENTRIES;
1027 } while(index != rxlimit);
1028
1029 rrpriv->cur_rx = index;
1030 wmb();
1031}
1032
1033
1034static irqreturn_t rr_interrupt(int irq, void *dev_id)
1035{
1036 struct rr_private *rrpriv;
1037 struct rr_regs __iomem *regs;
1038 struct net_device *dev = (struct net_device *)dev_id;
1039 u32 prodidx, rxindex, eidx, txcsmr, rxlimit, txcon;
1040
1041 rrpriv = netdev_priv(dev);
1042 regs = rrpriv->regs;
1043
1044 if (!(readl(&regs->HostCtrl) & RR_INT))
1045 return IRQ_NONE;
1046
1047 spin_lock(&rrpriv->lock);
1048
1049 prodidx = readl(&regs->EvtPrd);
1050 txcsmr = (prodidx >> 8) & 0xff;
1051 rxlimit = (prodidx >> 16) & 0xff;
1052 prodidx &= 0xff;
1053
1054#if (DEBUG > 2)
1055 printk("%s: interrupt, prodidx = %i, eidx = %i\n", dev->name,
1056 prodidx, rrpriv->info->evt_ctrl.pi);
1057#endif
1058 /*
1059 * Order here is important. We must handle events
1060 * before doing anything else in order to catch
1061 * such things as LLRC errors, etc -kbf
1062 */
1063
1064 eidx = rrpriv->info->evt_ctrl.pi;
1065 if (prodidx != eidx)
1066 eidx = rr_handle_event(dev, prodidx, eidx);
1067
1068 rxindex = rrpriv->cur_rx;
1069 if (rxindex != rxlimit)
1070 rx_int(dev, rxlimit, rxindex);
1071
1072 txcon = rrpriv->dirty_tx;
1073 if (txcsmr != txcon) {
1074 do {
1075 /* Due to occational firmware TX producer/consumer out
1076 * of sync. error need to check entry in ring -kbf
1077 */
1078 if(rrpriv->tx_skbuff[txcon]){
1079 struct tx_desc *desc;
1080 struct sk_buff *skb;
1081
1082 desc = &(rrpriv->tx_ring[txcon]);
1083 skb = rrpriv->tx_skbuff[txcon];
1084
1085 dev->stats.tx_packets++;
1086 dev->stats.tx_bytes += skb->len;
1087
1088 pci_unmap_single(rrpriv->pci_dev,
1089 desc->addr.addrlo, skb->len,
1090 PCI_DMA_TODEVICE);
1091 dev_kfree_skb_irq(skb);
1092
1093 rrpriv->tx_skbuff[txcon] = NULL;
1094 desc->size = 0;
1095 set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
1096 desc->mode = 0;
1097 }
1098 txcon = (txcon + 1) % TX_RING_ENTRIES;
1099 } while (txcsmr != txcon);
1100 wmb();
1101
1102 rrpriv->dirty_tx = txcon;
1103 if (rrpriv->tx_full && rr_if_busy(dev) &&
1104 (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
1105 != rrpriv->dirty_tx)){
1106 rrpriv->tx_full = 0;
1107 netif_wake_queue(dev);
1108 }
1109 }
1110
1111 eidx |= ((txcsmr << 8) | (rxlimit << 16));
1112 writel(eidx, &regs->EvtCon);
1113 wmb();
1114
1115 spin_unlock(&rrpriv->lock);
1116 return IRQ_HANDLED;
1117}
1118
1119static inline void rr_raz_tx(struct rr_private *rrpriv,
1120 struct net_device *dev)
1121{
1122 int i;
1123
1124 for (i = 0; i < TX_RING_ENTRIES; i++) {
1125 struct sk_buff *skb = rrpriv->tx_skbuff[i];
1126
1127 if (skb) {
1128 struct tx_desc *desc = &(rrpriv->tx_ring[i]);
1129
1130 pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
1131 skb->len, PCI_DMA_TODEVICE);
1132 desc->size = 0;
1133 set_rraddr(&desc->addr, 0);
1134 dev_kfree_skb(skb);
1135 rrpriv->tx_skbuff[i] = NULL;
1136 }
1137 }
1138}
1139
1140
1141static inline void rr_raz_rx(struct rr_private *rrpriv,
1142 struct net_device *dev)
1143{
1144 int i;
1145
1146 for (i = 0; i < RX_RING_ENTRIES; i++) {
1147 struct sk_buff *skb = rrpriv->rx_skbuff[i];
1148
1149 if (skb) {
1150 struct rx_desc *desc = &(rrpriv->rx_ring[i]);
1151
1152 pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
1153 dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
1154 desc->size = 0;
1155 set_rraddr(&desc->addr, 0);
1156 dev_kfree_skb(skb);
1157 rrpriv->rx_skbuff[i] = NULL;
1158 }
1159 }
1160}
1161
1162static void rr_timer(unsigned long data)
1163{
1164 struct net_device *dev = (struct net_device *)data;
1165 struct rr_private *rrpriv = netdev_priv(dev);
1166 struct rr_regs __iomem *regs = rrpriv->regs;
1167 unsigned long flags;
1168
1169 if (readl(&regs->HostCtrl) & NIC_HALTED){
1170 printk("%s: Restarting nic\n", dev->name);
1171 memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
1172 memset(rrpriv->info, 0, sizeof(struct rr_info));
1173 wmb();
1174
1175 rr_raz_tx(rrpriv, dev);
1176 rr_raz_rx(rrpriv, dev);
1177
1178 if (rr_init1(dev)) {
1179 spin_lock_irqsave(&rrpriv->lock, flags);
1180 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
1181 &regs->HostCtrl);
1182 spin_unlock_irqrestore(&rrpriv->lock, flags);
1183 }
1184 }
1185 rrpriv->timer.expires = RUN_AT(5*HZ);
1186 add_timer(&rrpriv->timer);
1187}
1188
1189
1190static int rr_open(struct net_device *dev)
1191{
1192 struct rr_private *rrpriv = netdev_priv(dev);
1193 struct pci_dev *pdev = rrpriv->pci_dev;
1194 struct rr_regs __iomem *regs;
1195 int ecode = 0;
1196 unsigned long flags;
1197 dma_addr_t dma_addr;
1198
1199 regs = rrpriv->regs;
1200
1201 if (rrpriv->fw_rev < 0x00020000) {
1202 printk(KERN_WARNING "%s: trying to configure device with "
1203 "obsolete firmware\n", dev->name);
1204 ecode = -EBUSY;
1205 goto error;
1206 }
1207
1208 rrpriv->rx_ctrl = pci_alloc_consistent(pdev,
1209 256 * sizeof(struct ring_ctrl),
1210 &dma_addr);
1211 if (!rrpriv->rx_ctrl) {
1212 ecode = -ENOMEM;
1213 goto error;
1214 }
1215 rrpriv->rx_ctrl_dma = dma_addr;
1216 memset(rrpriv->rx_ctrl, 0, 256*sizeof(struct ring_ctrl));
1217
1218 rrpriv->info = pci_alloc_consistent(pdev, sizeof(struct rr_info),
1219 &dma_addr);
1220 if (!rrpriv->info) {
1221 ecode = -ENOMEM;
1222 goto error;
1223 }
1224 rrpriv->info_dma = dma_addr;
1225 memset(rrpriv->info, 0, sizeof(struct rr_info));
1226 wmb();
1227
1228 spin_lock_irqsave(&rrpriv->lock, flags);
1229 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
1230 readl(&regs->HostCtrl);
1231 spin_unlock_irqrestore(&rrpriv->lock, flags);
1232
1233 if (request_irq(dev->irq, rr_interrupt, IRQF_SHARED, dev->name, dev)) {
1234 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1235 dev->name, dev->irq);
1236 ecode = -EAGAIN;
1237 goto error;
1238 }
1239
1240 if ((ecode = rr_init1(dev)))
1241 goto error;
1242
1243 /* Set the timer to switch to check for link beat and perhaps switch
1244 to an alternate media type. */
1245 init_timer(&rrpriv->timer);
1246 rrpriv->timer.expires = RUN_AT(5*HZ); /* 5 sec. watchdog */
1247 rrpriv->timer.data = (unsigned long)dev;
1248 rrpriv->timer.function = rr_timer; /* timer handler */
1249 add_timer(&rrpriv->timer);
1250
1251 netif_start_queue(dev);
1252
1253 return ecode;
1254
1255 error:
1256 spin_lock_irqsave(&rrpriv->lock, flags);
1257 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
1258 spin_unlock_irqrestore(&rrpriv->lock, flags);
1259
1260 if (rrpriv->info) {
1261 pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
1262 rrpriv->info_dma);
1263 rrpriv->info = NULL;
1264 }
1265 if (rrpriv->rx_ctrl) {
1266 pci_free_consistent(pdev, sizeof(struct ring_ctrl),
1267 rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
1268 rrpriv->rx_ctrl = NULL;
1269 }
1270
1271 netif_stop_queue(dev);
1272
1273 return ecode;
1274}
1275
1276
1277static void rr_dump(struct net_device *dev)
1278{
1279 struct rr_private *rrpriv;
1280 struct rr_regs __iomem *regs;
1281 u32 index, cons;
1282 short i;
1283 int len;
1284
1285 rrpriv = netdev_priv(dev);
1286 regs = rrpriv->regs;
1287
1288 printk("%s: dumping NIC TX rings\n", dev->name);
1289
1290 printk("RxPrd %08x, TxPrd %02x, EvtPrd %08x, TxPi %02x, TxCtrlPi %02x\n",
1291 readl(&regs->RxPrd), readl(&regs->TxPrd),
1292 readl(&regs->EvtPrd), readl(&regs->TxPi),
1293 rrpriv->info->tx_ctrl.pi);
1294
1295 printk("Error code 0x%x\n", readl(&regs->Fail1));
1296
1297 index = (((readl(&regs->EvtPrd) >> 8) & 0xff) - 1) % TX_RING_ENTRIES;
1298 cons = rrpriv->dirty_tx;
1299 printk("TX ring index %i, TX consumer %i\n",
1300 index, cons);
1301
1302 if (rrpriv->tx_skbuff[index]){
1303 len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
1304 printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
1305 for (i = 0; i < len; i++){
1306 if (!(i & 7))
1307 printk("\n");
1308 printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
1309 }
1310 printk("\n");
1311 }
1312
1313 if (rrpriv->tx_skbuff[cons]){
1314 len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
1315 printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
1316 printk("mode 0x%x, size 0x%x,\n phys %08Lx, skbuff-addr %08lx, truesize 0x%x\n",
1317 rrpriv->tx_ring[cons].mode,
1318 rrpriv->tx_ring[cons].size,
1319 (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
1320 (unsigned long)rrpriv->tx_skbuff[cons]->data,
1321 (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
1322 for (i = 0; i < len; i++){
1323 if (!(i & 7))
1324 printk("\n");
1325 printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
1326 }
1327 printk("\n");
1328 }
1329
1330 printk("dumping TX ring info:\n");
1331 for (i = 0; i < TX_RING_ENTRIES; i++)
1332 printk("mode 0x%x, size 0x%x, phys-addr %08Lx\n",
1333 rrpriv->tx_ring[i].mode,
1334 rrpriv->tx_ring[i].size,
1335 (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
1336
1337}
1338
1339
1340static int rr_close(struct net_device *dev)
1341{
1342 struct rr_private *rrpriv;
1343 struct rr_regs __iomem *regs;
1344 unsigned long flags;
1345 u32 tmp;
1346 short i;
1347
1348 netif_stop_queue(dev);
1349
1350 rrpriv = netdev_priv(dev);
1351 regs = rrpriv->regs;
1352
1353 /*
1354 * Lock to make sure we are not cleaning up while another CPU
1355 * is handling interrupts.
1356 */
1357 spin_lock_irqsave(&rrpriv->lock, flags);
1358
1359 tmp = readl(&regs->HostCtrl);
1360 if (tmp & NIC_HALTED){
1361 printk("%s: NIC already halted\n", dev->name);
1362 rr_dump(dev);
1363 }else{
1364 tmp |= HALT_NIC | RR_CLEAR_INT;
1365 writel(tmp, &regs->HostCtrl);
1366 readl(&regs->HostCtrl);
1367 }
1368
1369 rrpriv->fw_running = 0;
1370
1371 del_timer_sync(&rrpriv->timer);
1372
1373 writel(0, &regs->TxPi);
1374 writel(0, &regs->IpRxPi);
1375
1376 writel(0, &regs->EvtCon);
1377 writel(0, &regs->EvtPrd);
1378
1379 for (i = 0; i < CMD_RING_ENTRIES; i++)
1380 writel(0, &regs->CmdRing[i]);
1381
1382 rrpriv->info->tx_ctrl.entries = 0;
1383 rrpriv->info->cmd_ctrl.pi = 0;
1384 rrpriv->info->evt_ctrl.pi = 0;
1385 rrpriv->rx_ctrl[4].entries = 0;
1386
1387 rr_raz_tx(rrpriv, dev);
1388 rr_raz_rx(rrpriv, dev);
1389
1390 pci_free_consistent(rrpriv->pci_dev, 256 * sizeof(struct ring_ctrl),
1391 rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
1392 rrpriv->rx_ctrl = NULL;
1393
1394 pci_free_consistent(rrpriv->pci_dev, sizeof(struct rr_info),
1395 rrpriv->info, rrpriv->info_dma);
1396 rrpriv->info = NULL;
1397
1398 free_irq(dev->irq, dev);
1399 spin_unlock_irqrestore(&rrpriv->lock, flags);
1400
1401 return 0;
1402}
1403
1404
1405static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
1406 struct net_device *dev)
1407{
1408 struct rr_private *rrpriv = netdev_priv(dev);
1409 struct rr_regs __iomem *regs = rrpriv->regs;
1410 struct hippi_cb *hcb = (struct hippi_cb *) skb->cb;
1411 struct ring_ctrl *txctrl;
1412 unsigned long flags;
1413 u32 index, len = skb->len;
1414 u32 *ifield;
1415 struct sk_buff *new_skb;
1416
1417 if (readl(&regs->Mode) & FATAL_ERR)
1418 printk("error codes Fail1 %02x, Fail2 %02x\n",
1419 readl(&regs->Fail1), readl(&regs->Fail2));
1420
1421 /*
1422 * We probably need to deal with tbusy here to prevent overruns.
1423 */
1424
1425 if (skb_headroom(skb) < 8){
1426 printk("incoming skb too small - reallocating\n");
1427 if (!(new_skb = dev_alloc_skb(len + 8))) {
1428 dev_kfree_skb(skb);
1429 netif_wake_queue(dev);
1430 return NETDEV_TX_OK;
1431 }
1432 skb_reserve(new_skb, 8);
1433 skb_put(new_skb, len);
1434 skb_copy_from_linear_data(skb, new_skb->data, len);
1435 dev_kfree_skb(skb);
1436 skb = new_skb;
1437 }
1438
1439 ifield = (u32 *)skb_push(skb, 8);
1440
1441 ifield[0] = 0;
1442 ifield[1] = hcb->ifield;
1443
1444 /*
1445 * We don't need the lock before we are actually going to start
1446 * fiddling with the control blocks.
1447 */
1448 spin_lock_irqsave(&rrpriv->lock, flags);
1449
1450 txctrl = &rrpriv->info->tx_ctrl;
1451
1452 index = txctrl->pi;
1453
1454 rrpriv->tx_skbuff[index] = skb;
1455 set_rraddr(&rrpriv->tx_ring[index].addr, pci_map_single(
1456 rrpriv->pci_dev, skb->data, len + 8, PCI_DMA_TODEVICE));
1457 rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
1458 rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
1459 txctrl->pi = (index + 1) % TX_RING_ENTRIES;
1460 wmb();
1461 writel(txctrl->pi, &regs->TxPi);
1462
1463 if (txctrl->pi == rrpriv->dirty_tx){
1464 rrpriv->tx_full = 1;
1465 netif_stop_queue(dev);
1466 }
1467
1468 spin_unlock_irqrestore(&rrpriv->lock, flags);
1469
1470 return NETDEV_TX_OK;
1471}
1472
1473
1474/*
1475 * Read the firmware out of the EEPROM and put it into the SRAM
1476 * (or from user space - later)
1477 *
1478 * This operation requires the NIC to be halted and is performed with
1479 * interrupts disabled and with the spinlock hold.
1480 */
1481static int rr_load_firmware(struct net_device *dev)
1482{
1483 struct rr_private *rrpriv;
1484 struct rr_regs __iomem *regs;
1485 size_t eptr, segptr;
1486 int i, j;
1487 u32 localctrl, sptr, len, tmp;
1488 u32 p2len, p2size, nr_seg, revision, io, sram_size;
1489
1490 rrpriv = netdev_priv(dev);
1491 regs = rrpriv->regs;
1492
1493 if (dev->flags & IFF_UP)
1494 return -EBUSY;
1495
1496 if (!(readl(&regs->HostCtrl) & NIC_HALTED)){
1497 printk("%s: Trying to load firmware to a running NIC.\n",
1498 dev->name);
1499 return -EBUSY;
1500 }
1501
1502 localctrl = readl(&regs->LocalCtrl);
1503 writel(0, &regs->LocalCtrl);
1504
1505 writel(0, &regs->EvtPrd);
1506 writel(0, &regs->RxPrd);
1507 writel(0, &regs->TxPrd);
1508
1509 /*
1510 * First wipe the entire SRAM, otherwise we might run into all
1511 * kinds of trouble ... sigh, this took almost all afternoon
1512 * to track down ;-(
1513 */
1514 io = readl(&regs->ExtIo);
1515 writel(0, &regs->ExtIo);
1516 sram_size = rr_read_eeprom_word(rrpriv, 8);
1517
1518 for (i = 200; i < sram_size / 4; i++){
1519 writel(i * 4, &regs->WinBase);
1520 mb();
1521 writel(0, &regs->WinData);
1522 mb();
1523 }
1524 writel(io, &regs->ExtIo);
1525 mb();
1526
1527 eptr = rr_read_eeprom_word(rrpriv,
1528 offsetof(struct eeprom, rncd_info.AddrRunCodeSegs));
1529 eptr = ((eptr & 0x1fffff) >> 3);
1530
1531 p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
1532 p2len = (p2len << 2);
1533 p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
1534 p2size = ((p2size & 0x1fffff) >> 3);
1535
1536 if ((eptr < p2size) || (eptr > (p2size + p2len))){
1537 printk("%s: eptr is invalid\n", dev->name);
1538 goto out;
1539 }
1540
1541 revision = rr_read_eeprom_word(rrpriv,
1542 offsetof(struct eeprom, manf.HeaderFmt));
1543
1544 if (revision != 1){
1545 printk("%s: invalid firmware format (%i)\n",
1546 dev->name, revision);
1547 goto out;
1548 }
1549
1550 nr_seg = rr_read_eeprom_word(rrpriv, eptr);
1551 eptr +=4;
1552#if (DEBUG > 1)
1553 printk("%s: nr_seg %i\n", dev->name, nr_seg);
1554#endif
1555
1556 for (i = 0; i < nr_seg; i++){
1557 sptr = rr_read_eeprom_word(rrpriv, eptr);
1558 eptr += 4;
1559 len = rr_read_eeprom_word(rrpriv, eptr);
1560 eptr += 4;
1561 segptr = rr_read_eeprom_word(rrpriv, eptr);
1562 segptr = ((segptr & 0x1fffff) >> 3);
1563 eptr += 4;
1564#if (DEBUG > 1)
1565 printk("%s: segment %i, sram address %06x, length %04x, segptr %06x\n",
1566 dev->name, i, sptr, len, segptr);
1567#endif
1568 for (j = 0; j < len; j++){
1569 tmp = rr_read_eeprom_word(rrpriv, segptr);
1570 writel(sptr, &regs->WinBase);
1571 mb();
1572 writel(tmp, &regs->WinData);
1573 mb();
1574 segptr += 4;
1575 sptr += 4;
1576 }
1577 }
1578
1579out:
1580 writel(localctrl, &regs->LocalCtrl);
1581 mb();
1582 return 0;
1583}
1584
1585
1586static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1587{
1588 struct rr_private *rrpriv;
1589 unsigned char *image, *oldimage;
1590 unsigned long flags;
1591 unsigned int i;
1592 int error = -EOPNOTSUPP;
1593
1594 rrpriv = netdev_priv(dev);
1595
1596 switch(cmd){
1597 case SIOCRRGFW:
1598 if (!capable(CAP_SYS_RAWIO)){
1599 return -EPERM;
1600 }
1601
1602 image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
1603 if (!image){
1604 printk(KERN_ERR "%s: Unable to allocate memory "
1605 "for EEPROM image\n", dev->name);
1606 return -ENOMEM;
1607 }
1608
1609
1610 if (rrpriv->fw_running){
1611 printk("%s: Firmware already running\n", dev->name);
1612 error = -EPERM;
1613 goto gf_out;
1614 }
1615
1616 spin_lock_irqsave(&rrpriv->lock, flags);
1617 i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
1618 spin_unlock_irqrestore(&rrpriv->lock, flags);
1619 if (i != EEPROM_BYTES){
1620 printk(KERN_ERR "%s: Error reading EEPROM\n",
1621 dev->name);
1622 error = -EFAULT;
1623 goto gf_out;
1624 }
1625 error = copy_to_user(rq->ifr_data, image, EEPROM_BYTES);
1626 if (error)
1627 error = -EFAULT;
1628 gf_out:
1629 kfree(image);
1630 return error;
1631
1632 case SIOCRRPFW:
1633 if (!capable(CAP_SYS_RAWIO)){
1634 return -EPERM;
1635 }
1636
1637 image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
1638 oldimage = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
1639 if (!image || !oldimage) {
1640 printk(KERN_ERR "%s: Unable to allocate memory "
1641 "for EEPROM image\n", dev->name);
1642 error = -ENOMEM;
1643 goto wf_out;
1644 }
1645
1646 error = copy_from_user(image, rq->ifr_data, EEPROM_BYTES);
1647 if (error) {
1648 error = -EFAULT;
1649 goto wf_out;
1650 }
1651
1652 if (rrpriv->fw_running){
1653 printk("%s: Firmware already running\n", dev->name);
1654 error = -EPERM;
1655 goto wf_out;
1656 }
1657
1658 printk("%s: Updating EEPROM firmware\n", dev->name);
1659
1660 spin_lock_irqsave(&rrpriv->lock, flags);
1661 error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
1662 if (error)
1663 printk(KERN_ERR "%s: Error writing EEPROM\n",
1664 dev->name);
1665
1666 i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
1667 spin_unlock_irqrestore(&rrpriv->lock, flags);
1668
1669 if (i != EEPROM_BYTES)
1670 printk(KERN_ERR "%s: Error reading back EEPROM "
1671 "image\n", dev->name);
1672
1673 error = memcmp(image, oldimage, EEPROM_BYTES);
1674 if (error){
1675 printk(KERN_ERR "%s: Error verifying EEPROM image\n",
1676 dev->name);
1677 error = -EFAULT;
1678 }
1679 wf_out:
1680 kfree(oldimage);
1681 kfree(image);
1682 return error;
1683
1684 case SIOCRRID:
1685 return put_user(0x52523032, (int __user *)rq->ifr_data);
1686 default:
1687 return error;
1688 }
1689}
1690
1691static DEFINE_PCI_DEVICE_TABLE(rr_pci_tbl) = {
1692 { PCI_VENDOR_ID_ESSENTIAL, PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER,
1693 PCI_ANY_ID, PCI_ANY_ID, },
1694 { 0,}
1695};
1696MODULE_DEVICE_TABLE(pci, rr_pci_tbl);
1697
1698static struct pci_driver rr_driver = {
1699 .name = "rrunner",
1700 .id_table = rr_pci_tbl,
1701 .probe = rr_init_one,
1702 .remove = __devexit_p(rr_remove_one),
1703};
1704
1705static int __init rr_init_module(void)
1706{
1707 return pci_register_driver(&rr_driver);
1708}
1709
1710static void __exit rr_cleanup_module(void)
1711{
1712 pci_unregister_driver(&rr_driver);
1713}
1714
1715module_init(rr_init_module);
1716module_exit(rr_cleanup_module);
diff --git a/drivers/net/hippi/rrunner.h b/drivers/net/hippi/rrunner.h
new file mode 100644
index 000000000000..28169043ae49
--- /dev/null
+++ b/drivers/net/hippi/rrunner.h
@@ -0,0 +1,846 @@
1#ifndef _RRUNNER_H_
2#define _RRUNNER_H_
3
4#include <linux/interrupt.h>
5
6#if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64))
7#error "BITS_PER_LONG not defined or not valid"
8#endif
9
10
11struct rr_regs {
12
13 u32 pad0[16];
14
15 u32 HostCtrl;
16 u32 LocalCtrl;
17 u32 Pc;
18 u32 BrkPt;
19
20/* Timer increments every 0.97 micro-seconds (unsigned int) */
21 u32 Timer_Hi;
22 u32 Timer;
23 u32 TimerRef;
24 u32 PciState;
25
26 u32 Event;
27 u32 MbEvent;
28
29 u32 WinBase;
30 u32 WinData;
31 u32 RX_state;
32 u32 TX_state;
33
34 u32 Overhead;
35 u32 ExtIo;
36
37 u32 DmaWriteHostHi;
38 u32 DmaWriteHostLo;
39
40 u32 pad1[2];
41
42 u32 DmaReadHostHi;
43 u32 DmaReadHostLo;
44
45 u32 pad2;
46
47 u32 DmaReadLen;
48 u32 DmaWriteState;
49
50 u32 DmaWriteLcl;
51 u32 DmaWriteIPchecksum;
52 u32 DmaWriteLen;
53 u32 DmaReadState;
54 u32 DmaReadLcl;
55 u32 DmaReadIPchecksum;
56 u32 pad3;
57
58 u32 RxBase;
59 u32 RxPrd;
60 u32 RxCon;
61
62 u32 pad4;
63
64 u32 TxBase;
65 u32 TxPrd;
66 u32 TxCon;
67
68 u32 pad5;
69
70 u32 RxIndPro;
71 u32 RxIndCon;
72 u32 RxIndRef;
73
74 u32 pad6;
75
76 u32 TxIndPro;
77 u32 TxIndCon;
78 u32 TxIndRef;
79
80 u32 pad7[17];
81
82 u32 DrCmndPro;
83 u32 DrCmndCon;
84 u32 DrCmndRef;
85
86 u32 pad8;
87
88 u32 DwCmndPro;
89 u32 DwCmndCon;
90 u32 DwCmndRef;
91
92 u32 AssistState;
93
94 u32 DrDataPro;
95 u32 DrDataCon;
96 u32 DrDataRef;
97
98 u32 pad9;
99
100 u32 DwDataPro;
101 u32 DwDataCon;
102 u32 DwDataRef;
103
104 u32 pad10[33];
105
106 u32 EvtCon;
107
108 u32 pad11[5];
109
110 u32 TxPi;
111 u32 IpRxPi;
112
113 u32 pad11a[8];
114
115 u32 CmdRing[16];
116
117/* The ULA is in two registers the high order two bytes of the first
118 * word contain the RunCode features.
119 * ula0 res res byte0 byte1
120 * ula1 byte2 byte3 byte4 byte5
121 */
122 u32 Ula0;
123 u32 Ula1;
124
125 u32 RxRingHi;
126 u32 RxRingLo;
127
128 u32 InfoPtrHi;
129 u32 InfoPtrLo;
130
131 u32 Mode;
132
133 u32 ConRetry;
134 u32 ConRetryTmr;
135
136 u32 ConTmout;
137 u32 CtatTmr;
138
139 u32 MaxRxRng;
140
141 u32 IntrTmr;
142 u32 TxDataMvTimeout;
143 u32 RxDataMvTimeout;
144
145 u32 EvtPrd;
146 u32 TraceIdx;
147
148 u32 Fail1;
149 u32 Fail2;
150
151 u32 DrvPrm;
152
153 u32 FilterLA;
154
155 u32 FwRev;
156 u32 FwRes1;
157 u32 FwRes2;
158 u32 FwRes3;
159
160 u32 WriteDmaThresh;
161 u32 ReadDmaThresh;
162
163 u32 pad12[325];
164 u32 Window[512];
165};
166
167/*
168 * Host control register bits.
169 */
170
171#define RR_INT 0x01
172#define RR_CLEAR_INT 0x02
173#define NO_SWAP 0x04000004
174#define NO_SWAP1 0x00000004
175#define PCI_RESET_NIC 0x08
176#define HALT_NIC 0x10
177#define SSTEP_NIC 0x20
178#define MEM_READ_MULTI 0x40
179#define NIC_HALTED 0x100
180#define HALT_INST 0x200
181#define PARITY_ERR 0x400
182#define INVALID_INST_B 0x800
183#define RR_REV_2 0x20000000
184#define RR_REV_MASK 0xf0000000
185
186/*
187 * Local control register bits.
188 */
189
190#define INTA_STATE 0x01
191#define CLEAR_INTA 0x02
192#define FAST_EEPROM_ACCESS 0x08
193#define ENABLE_EXTRA_SRAM 0x100
194#define ENABLE_EXTRA_DESC 0x200
195#define ENABLE_PARITY 0x400
196#define FORCE_DMA_PARITY_ERROR 0x800
197#define ENABLE_EEPROM_WRITE 0x1000
198#define ENABLE_DATA_CACHE 0x2000
199#define SRAM_LO_PARITY_ERR 0x4000
200#define SRAM_HI_PARITY_ERR 0x8000
201
202/*
203 * PCI state bits.
204 */
205
206#define FORCE_PCI_RESET 0x01
207#define PROVIDE_LENGTH 0x02
208#define MASK_DMA_READ_MAX 0x1C
209#define RBURST_DISABLE 0x00
210#define RBURST_4 0x04
211#define RBURST_16 0x08
212#define RBURST_32 0x0C
213#define RBURST_64 0x10
214#define RBURST_128 0x14
215#define RBURST_256 0x18
216#define RBURST_1024 0x1C
217#define MASK_DMA_WRITE_MAX 0xE0
218#define WBURST_DISABLE 0x00
219#define WBURST_4 0x20
220#define WBURST_16 0x40
221#define WBURST_32 0x60
222#define WBURST_64 0x80
223#define WBURST_128 0xa0
224#define WBURST_256 0xc0
225#define WBURST_1024 0xe0
226#define MASK_MIN_DMA 0xFF00
227#define FIFO_RETRY_ENABLE 0x10000
228
229/*
230 * Event register
231 */
232
233#define DMA_WRITE_DONE 0x10000
234#define DMA_READ_DONE 0x20000
235#define DMA_WRITE_ERR 0x40000
236#define DMA_READ_ERR 0x80000
237
238/*
239 * Receive state
240 *
241 * RoadRunner HIPPI Receive State Register controls and monitors the
242 * HIPPI receive interface in the NIC. Look at err bits when a HIPPI
243 * receive Error Event occurs.
244 */
245
246#define ENABLE_NEW_CON 0x01
247#define RESET_RECV 0x02
248#define RECV_ALL 0x00
249#define RECV_1K 0x20
250#define RECV_2K 0x40
251#define RECV_4K 0x60
252#define RECV_8K 0x80
253#define RECV_16K 0xa0
254#define RECV_32K 0xc0
255#define RECV_64K 0xe0
256
257/*
258 * Transmit status.
259 */
260
261#define ENA_XMIT 0x01
262#define PERM_CON 0x02
263
264/*
265 * DMA write state
266 */
267
268#define RESET_DMA 0x01
269#define NO_SWAP_DMA 0x02
270#define DMA_ACTIVE 0x04
271#define THRESH_MASK 0x1F
272#define DMA_ERROR_MASK 0xff000000
273
274/*
275 * Gooddies stored in the ULA registers.
276 */
277
278#define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */
279#define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */
280#define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */
281#define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */
282#define LONG_TX_WHAT_BIT 0x00400000
283#define LONG_RX_WHAT_BIT 0x00800000
284#define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */
285
286/*
287 * Mode status
288 */
289
290#define EVENT_OVFL 0x80000000
291#define FATAL_ERR 0x40000000
292#define LOOP_BACK 0x01
293#define MODE_PH 0x02
294#define MODE_FP 0x00
295#define PTR64BIT 0x04
296#define PTR32BIT 0x00
297#define PTR_WD_SWAP 0x08
298#define PTR_WD_NOSWAP 0x00
299#define POST_WARN_EVENT 0x10
300#define ERR_TERM 0x20
301#define DIRECT_CONN 0x40
302#define NO_NIC_WATCHDOG 0x80
303#define SWAP_DATA 0x100
304#define SWAP_CONTROL 0x200
305#define NIC_HALT_ON_ERR 0x400
306#define NIC_NO_RESTART 0x800
307#define HALF_DUP_TX 0x1000
308#define HALF_DUP_RX 0x2000
309
310
311/*
312 * Error codes
313 */
314
315/* Host Error Codes - values of fail1 */
316#define ERR_UNKNOWN_MBOX 0x1001
317#define ERR_UNKNOWN_CMD 0x1002
318#define ERR_MAX_RING 0x1003
319#define ERR_RING_CLOSED 0x1004
320#define ERR_RING_OPEN 0x1005
321/* Firmware internal errors */
322#define ERR_EVENT_RING_FULL 0x01
323#define ERR_DW_PEND_CMND_FULL 0x02
324#define ERR_DR_PEND_CMND_FULL 0x03
325#define ERR_DW_PEND_DATA_FULL 0x04
326#define ERR_DR_PEND_DATA_FULL 0x05
327#define ERR_ILLEGAL_JUMP 0x06
328#define ERR_UNIMPLEMENTED 0x07
329#define ERR_TX_INFO_FULL 0x08
330#define ERR_RX_INFO_FULL 0x09
331#define ERR_ILLEGAL_MODE 0x0A
332#define ERR_MAIN_TIMEOUT 0x0B
333#define ERR_EVENT_BITS 0x0C
334#define ERR_UNPEND_FULL 0x0D
335#define ERR_TIMER_QUEUE_FULL 0x0E
336#define ERR_TIMER_QUEUE_EMPTY 0x0F
337#define ERR_TIMER_NO_FREE 0x10
338#define ERR_INTR_START 0x11
339#define ERR_BAD_STARTUP 0x12
340#define ERR_NO_PKT_END 0x13
341#define ERR_HALTED_ON_ERR 0x14
342/* Hardware NIC Errors */
343#define ERR_WRITE_DMA 0x0101
344#define ERR_READ_DMA 0x0102
345#define ERR_EXT_SERIAL 0x0103
346#define ERR_TX_INT_PARITY 0x0104
347
348
349/*
350 * Event definitions
351 */
352
353#define EVT_RING_ENTRIES 64
354#define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
355
356struct event {
357#ifdef __LITTLE_ENDIAN
358 u16 index;
359 u8 ring;
360 u8 code;
361#else
362 u8 code;
363 u8 ring;
364 u16 index;
365#endif
366 u32 timestamp;
367};
368
369/*
370 * General Events
371 */
372
373#define E_NIC_UP 0x01
374#define E_WATCHDOG 0x02
375
376#define E_STAT_UPD 0x04
377#define E_INVAL_CMD 0x05
378#define E_SET_CMD_CONS 0x06
379#define E_LINK_ON 0x07
380#define E_LINK_OFF 0x08
381#define E_INTERN_ERR 0x09
382#define E_HOST_ERR 0x0A
383#define E_STATS_UPDATE 0x0B
384#define E_REJECTING 0x0C
385
386/*
387 * Send Events
388 */
389#define E_CON_REJ 0x13
390#define E_CON_TMOUT 0x14
391#define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */
392#define E_DISC_ERR 0x16
393#define E_INT_PRTY 0x17
394#define E_TX_IDLE 0x18
395#define E_TX_LINK_DROP 0x19
396#define E_TX_INV_RNG 0x1A
397#define E_TX_INV_BUF 0x1B
398#define E_TX_INV_DSC 0x1C
399
400/*
401 * Destination Events
402 */
403/*
404 * General Receive events
405 */
406#define E_VAL_RNG 0x20
407#define E_RX_RNG_ENER 0x21
408#define E_INV_RNG 0x22
409#define E_RX_RNG_SPC 0x23
410#define E_RX_RNG_OUT 0x24
411#define E_PKT_DISCARD 0x25
412#define E_INFO_EVT 0x27
413
414/*
415 * Data corrupted events
416 */
417#define E_RX_PAR_ERR 0x2B
418#define E_RX_LLRC_ERR 0x2C
419#define E_IP_CKSM_ERR 0x2D
420#define E_DTA_CKSM_ERR 0x2E
421#define E_SHT_BST 0x2F
422
423/*
424 * Data lost events
425 */
426#define E_LST_LNK_ERR 0x30
427#define E_FLG_SYN_ERR 0x31
428#define E_FRM_ERR 0x32
429#define E_RX_IDLE 0x33
430#define E_PKT_LN_ERR 0x34
431#define E_STATE_ERR 0x35
432#define E_UNEXP_DATA 0x3C
433
434/*
435 * Fatal events
436 */
437#define E_RX_INV_BUF 0x36
438#define E_RX_INV_DSC 0x37
439#define E_RNG_BLK 0x38
440
441/*
442 * Warning events
443 */
444#define E_RX_TO 0x39
445#define E_BFR_SPC 0x3A
446#define E_INV_ULP 0x3B
447
448#define E_NOT_IMPLEMENTED 0x40
449
450
451/*
452 * Commands
453 */
454
455#define CMD_RING_ENTRIES 16
456
457struct cmd {
458#ifdef __LITTLE_ENDIAN
459 u16 index;
460 u8 ring;
461 u8 code;
462#else
463 u8 code;
464 u8 ring;
465 u16 index;
466#endif
467};
468
469#define C_START_FW 0x01
470#define C_UPD_STAT 0x02
471#define C_WATCHDOG 0x05
472#define C_DEL_RNG 0x09
473#define C_NEW_RNG 0x0A
474#define C_CONN 0x0D
475
476
477/*
478 * Mode bits
479 */
480
481#define PACKET_BAD 0x01 /* Packet had link-layer error */
482#define INTERRUPT 0x02
483#define TX_IP_CKSUM 0x04
484#define PACKET_END 0x08
485#define PACKET_START 0x10
486#define SAME_IFIELD 0x80
487
488
489typedef struct {
490#if (BITS_PER_LONG == 64)
491 u64 addrlo;
492#else
493 u32 addrhi;
494 u32 addrlo;
495#endif
496} rraddr;
497
498
499static inline void set_rraddr(rraddr *ra, dma_addr_t addr)
500{
501 unsigned long baddr = addr;
502#if (BITS_PER_LONG == 64)
503 ra->addrlo = baddr;
504#else
505 /* Don't bother setting zero every time */
506 ra->addrlo = baddr;
507#endif
508 mb();
509}
510
511
512static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
513{
514 unsigned long baddr = addr;
515#if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
516 writel(baddr & 0xffffffff, &regs->RxRingHi);
517 writel(baddr >> 32, &regs->RxRingLo);
518#elif (BITS_PER_LONG == 64)
519 writel(baddr >> 32, &regs->RxRingHi);
520 writel(baddr & 0xffffffff, &regs->RxRingLo);
521#else
522 writel(0, &regs->RxRingHi);
523 writel(baddr, &regs->RxRingLo);
524#endif
525 mb();
526}
527
528
529static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
530{
531 unsigned long baddr = addr;
532#if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
533 writel(baddr & 0xffffffff, &regs->InfoPtrHi);
534 writel(baddr >> 32, &regs->InfoPtrLo);
535#elif (BITS_PER_LONG == 64)
536 writel(baddr >> 32, &regs->InfoPtrHi);
537 writel(baddr & 0xffffffff, &regs->InfoPtrLo);
538#else
539 writel(0, &regs->InfoPtrHi);
540 writel(baddr, &regs->InfoPtrLo);
541#endif
542 mb();
543}
544
545
546/*
547 * TX ring
548 */
549
550#ifdef CONFIG_ROADRUNNER_LARGE_RINGS
551#define TX_RING_ENTRIES 32
552#else
553#define TX_RING_ENTRIES 16
554#endif
555#define TX_TOTAL_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc))
556
557struct tx_desc{
558 rraddr addr;
559 u32 res;
560#ifdef __LITTLE_ENDIAN
561 u16 size;
562 u8 pad;
563 u8 mode;
564#else
565 u8 mode;
566 u8 pad;
567 u16 size;
568#endif
569};
570
571
572#ifdef CONFIG_ROADRUNNER_LARGE_RINGS
573#define RX_RING_ENTRIES 32
574#else
575#define RX_RING_ENTRIES 16
576#endif
577#define RX_TOTAL_SIZE (RX_RING_ENTRIES * sizeof(struct rx_desc))
578
579struct rx_desc{
580 rraddr addr;
581 u32 res;
582#ifdef __LITTLE_ENDIAN
583 u16 size;
584 u8 pad;
585 u8 mode;
586#else
587 u8 mode;
588 u8 pad;
589 u16 size;
590#endif
591};
592
593
594/*
595 * ioctl's
596 */
597
598#define SIOCRRPFW SIOCDEVPRIVATE /* put firmware */
599#define SIOCRRGFW SIOCDEVPRIVATE+1 /* get firmware */
600#define SIOCRRID SIOCDEVPRIVATE+2 /* identify */
601
602
603struct seg_hdr {
604 u32 seg_start;
605 u32 seg_len;
606 u32 seg_eestart;
607};
608
609
610#define EEPROM_BASE 0x80000000
611#define EEPROM_WORDS 8192
612#define EEPROM_BYTES (EEPROM_WORDS * sizeof(u32))
613
614struct eeprom_boot {
615 u32 key1;
616 u32 key2;
617 u32 sram_size;
618 struct seg_hdr loader;
619 u32 init_chksum;
620 u32 reserved1;
621};
622
623struct eeprom_manf {
624 u32 HeaderFmt;
625 u32 Firmware;
626 u32 BoardRevision;
627 u32 RoadrunnerRev;
628 char OpticsPart[8];
629 u32 OpticsRev;
630 u32 pad1;
631 char SramPart[8];
632 u32 SramRev;
633 u32 pad2;
634 char EepromPart[8];
635 u32 EepromRev;
636 u32 EepromSize;
637 char PalPart[8];
638 u32 PalRev;
639 u32 pad3;
640 char PalCodeFile[12];
641 u32 PalCodeRev;
642 char BoardULA[8];
643 char SerialNo[8];
644 char MfgDate[8];
645 char MfgTime[8];
646 char ModifyDate[8];
647 u32 ModCount;
648 u32 pad4[13];
649};
650
651
652struct eeprom_phase_info {
653 char phase1File[12];
654 u32 phase1Rev;
655 char phase1Date[8];
656 char phase2File[12];
657 u32 phase2Rev;
658 char phase2Date[8];
659 u32 reserved7[4];
660};
661
662struct eeprom_rncd_info {
663 u32 FwStart;
664 u32 FwRev;
665 char FwDate[8];
666 u32 AddrRunCodeSegs;
667 u32 FileNames;
668 char File[13][8];
669};
670
671
672/* Phase 1 region (starts are word offset 0x80) */
673struct phase1_hdr{
674 u32 jump;
675 u32 noop;
676 struct seg_hdr phase2Seg;
677};
678
679struct eeprom {
680 struct eeprom_boot boot;
681 u32 pad1[8];
682 struct eeprom_manf manf;
683 struct eeprom_phase_info phase_info;
684 struct eeprom_rncd_info rncd_info;
685 u32 pad2[15];
686 u32 hdr_checksum;
687 struct phase1_hdr phase1;
688};
689
690
691struct rr_stats {
692 u32 NicTimeStamp;
693 u32 RngCreated;
694 u32 RngDeleted;
695 u32 IntrGen;
696 u32 NEvtOvfl;
697 u32 InvCmd;
698 u32 DmaReadErrs;
699 u32 DmaWriteErrs;
700 u32 StatUpdtT;
701 u32 StatUpdtC;
702 u32 WatchDog;
703 u32 Trace;
704
705 /* Serial HIPPI */
706 u32 LnkRdyEst;
707 u32 GLinkErr;
708 u32 AltFlgErr;
709 u32 OvhdBit8Sync;
710 u32 RmtSerPrtyErr;
711 u32 RmtParPrtyErr;
712 u32 RmtLoopBk;
713 u32 pad1;
714
715 /* HIPPI tx */
716 u32 ConEst;
717 u32 ConRejS;
718 u32 ConRetry;
719 u32 ConTmOut;
720 u32 SndConDiscon;
721 u32 SndParErr;
722 u32 PktSnt;
723 u32 pad2[2];
724 u32 ShFBstSnt;
725 u64 BytSent;
726 u32 TxTimeout;
727 u32 pad3[3];
728
729 /* HIPPI rx */
730 u32 ConAcc;
731 u32 ConRejdiPrty;
732 u32 ConRejd64b;
733 u32 ConRejdBuf;
734 u32 RxConDiscon;
735 u32 RxConNoData;
736 u32 PktRx;
737 u32 pad4[2];
738 u32 ShFBstRx;
739 u64 BytRx;
740 u32 RxParErr;
741 u32 RxLLRCerr;
742 u32 RxBstSZerr;
743 u32 RxStateErr;
744 u32 RxRdyErr;
745 u32 RxInvULP;
746 u32 RxSpcBuf;
747 u32 RxSpcDesc;
748 u32 RxRngSpc;
749 u32 RxRngFull;
750 u32 RxPktLenErr;
751 u32 RxCksmErr;
752 u32 RxPktDrp;
753 u32 RngLowSpc;
754 u32 RngDataClose;
755 u32 RxTimeout;
756 u32 RxIdle;
757};
758
759
760/*
761 * This struct is shared with the NIC firmware.
762 */
763struct ring_ctrl {
764 rraddr rngptr;
765#ifdef __LITTLE_ENDIAN
766 u16 entries;
767 u8 pad;
768 u8 entry_size;
769 u16 pi;
770 u16 mode;
771#else
772 u8 entry_size;
773 u8 pad;
774 u16 entries;
775 u16 mode;
776 u16 pi;
777#endif
778};
779
780struct rr_info {
781 union {
782 struct rr_stats stats;
783 u32 stati[128];
784 } s;
785 struct ring_ctrl evt_ctrl;
786 struct ring_ctrl cmd_ctrl;
787 struct ring_ctrl tx_ctrl;
788 u8 pad[464];
789 u8 trace[3072];
790};
791
792/*
793 * The linux structure for the RoadRunner.
794 *
795 * RX/TX descriptors are put first to make sure they are properly
796 * aligned and do not cross cache-line boundaries.
797 */
798
799struct rr_private
800{
801 struct rx_desc *rx_ring;
802 struct tx_desc *tx_ring;
803 struct event *evt_ring;
804 dma_addr_t tx_ring_dma;
805 dma_addr_t rx_ring_dma;
806 dma_addr_t evt_ring_dma;
807 /* Alignment ok ? */
808 struct sk_buff *rx_skbuff[RX_RING_ENTRIES];
809 struct sk_buff *tx_skbuff[TX_RING_ENTRIES];
810 struct rr_regs __iomem *regs; /* Register base */
811 struct ring_ctrl *rx_ctrl; /* Receive ring control */
812 struct rr_info *info; /* Shared info page */
813 dma_addr_t rx_ctrl_dma;
814 dma_addr_t info_dma;
815 spinlock_t lock;
816 struct timer_list timer;
817 u32 cur_rx, cur_cmd, cur_evt;
818 u32 dirty_rx, dirty_tx;
819 u32 tx_full;
820 u32 fw_rev;
821 volatile short fw_running;
822 struct pci_dev *pci_dev;
823};
824
825
826/*
827 * Prototypes
828 */
829static int rr_init(struct net_device *dev);
830static int rr_init1(struct net_device *dev);
831static irqreturn_t rr_interrupt(int irq, void *dev_id);
832
833static int rr_open(struct net_device *dev);
834static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
835 struct net_device *dev);
836static int rr_close(struct net_device *dev);
837static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
838static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
839 unsigned long offset,
840 unsigned char *buf,
841 unsigned long length);
842static u32 rr_read_eeprom_word(struct rr_private *rrpriv, size_t offset);
843static int rr_load_firmware(struct net_device *dev);
844static inline void rr_raz_tx(struct rr_private *, struct net_device *);
845static inline void rr_raz_rx(struct rr_private *, struct net_device *);
846#endif /* _RRUNNER_H_ */
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