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authorYuval Mintz <yuvalmin@broadcom.com>2012-12-01 23:05:45 -0500
committerDavid S. Miller <davem@davemloft.net>2012-12-02 20:22:59 -0500
commitd6d99a3f7e9169ef351340b217b48accab78e849 (patch)
treeba007398f5f1903a79f82e1cc753870f4b1282fa /drivers/net/ethernet
parentd317966bd3249ee7cd912931ab013c49cb77b9a4 (diff)
bnx2x: revised and corrected SPIO access
Changed naming convention of SPIO macros, and prevented access to invalid SPIOs. Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c43
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h10
2 files changed, 30 insertions, 23 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index b4659c4b6fbd..5a22e19d2d98 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -2032,40 +2032,39 @@ int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 return 0; 2032 return 0;
2033} 2033}
2034 2034
2035static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2035static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2036{ 2036{
2037 u32 spio_mask = (1 << spio_num);
2038 u32 spio_reg; 2037 u32 spio_reg;
2039 2038
2040 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2039 /* Only 2 SPIOs are configurable */
2041 (spio_num > MISC_REGISTERS_SPIO_7)) { 2040 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2042 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2041 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2043 return -EINVAL; 2042 return -EINVAL;
2044 } 2043 }
2045 2044
2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2047 /* read SPIO and mask except the float bits */ 2046 /* read SPIO and mask except the float bits */
2048 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2047 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2049 2048
2050 switch (mode) { 2049 switch (mode) {
2051 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2050 case MISC_SPIO_OUTPUT_LOW:
2052 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); 2051 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2053 /* clear FLOAT and set CLR */ 2052 /* clear FLOAT and set CLR */
2054 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2053 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2055 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2054 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2056 break; 2055 break;
2057 2056
2058 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2057 case MISC_SPIO_OUTPUT_HIGH:
2059 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); 2058 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2060 /* clear FLOAT and set SET */ 2059 /* clear FLOAT and set SET */
2061 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2060 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2062 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2061 spio_reg |= (spio << MISC_SPIO_SET_POS);
2063 break; 2062 break;
2064 2063
2065 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2064 case MISC_SPIO_INPUT_HI_Z:
2066 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); 2065 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2067 /* set FLOAT */ 2066 /* set FLOAT */
2068 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2067 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2069 break; 2068 break;
2070 2069
2071 default: 2070 default:
@@ -6196,18 +6195,16 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6196 return; 6195 return;
6197 6196
6198 /* Fan failure is indicated by SPIO 5 */ 6197 /* Fan failure is indicated by SPIO 5 */
6199 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 6198 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6200 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6201 6199
6202 /* set to active low mode */ 6200 /* set to active low mode */
6203 val = REG_RD(bp, MISC_REG_SPIO_INT); 6201 val = REG_RD(bp, MISC_REG_SPIO_INT);
6204 val |= ((1 << MISC_REGISTERS_SPIO_5) << 6202 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6205 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6206 REG_WR(bp, MISC_REG_SPIO_INT, val); 6203 REG_WR(bp, MISC_REG_SPIO_INT, val);
6207 6204
6208 /* enable interrupt to signal the IGU */ 6205 /* enable interrupt to signal the IGU */
6209 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6206 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6210 val |= (1 << MISC_REGISTERS_SPIO_5); 6207 val |= MISC_SPIO_SPIO5;
6211 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 6208 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6212} 6209}
6213 6210
@@ -6969,7 +6966,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
6969 6966
6970 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6967 /* If SPIO5 is set to generate interrupts, enable it for this port */
6971 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6968 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6972 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6969 if (val & MISC_SPIO_SPIO5) {
6973 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6970 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6974 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6971 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6975 val = REG_RD(bp, reg_addr); 6972 val = REG_RD(bp, reg_addr);
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index f8d432af2563..87cf37c71b30 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -5942,6 +5942,16 @@
5942#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5942#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5943#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5943#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5944#define MISC_REGISTERS_SPIO_SET_POS 8 5944#define MISC_REGISTERS_SPIO_SET_POS 8
5945#define MISC_SPIO_CLR_POS 16
5946#define MISC_SPIO_FLOAT (0xffL<<24)
5947#define MISC_SPIO_FLOAT_POS 24
5948#define MISC_SPIO_INPUT_HI_Z 2
5949#define MISC_SPIO_INT_OLD_SET_POS 16
5950#define MISC_SPIO_OUTPUT_HIGH 1
5951#define MISC_SPIO_OUTPUT_LOW 0
5952#define MISC_SPIO_SET_POS 8
5953#define MISC_SPIO_SPIO4 0x10
5954#define MISC_SPIO_SPIO5 0x20
5945#define HW_LOCK_MAX_RESOURCE_VALUE 31 5955#define HW_LOCK_MAX_RESOURCE_VALUE 31
5946#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13 5956#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13
5947#define HW_LOCK_RESOURCE_DRV_FLAGS 10 5957#define HW_LOCK_RESOURCE_DRV_FLAGS 10