ixgbe: Update layout of ixgbe_ring structure to improve cache performance

This change makes it so that only the 2nd cache line in the ring structure
should see frequent updates.  The advantage to this is that it should
reduce the amount of cross CPU cache bouncing since only the 2nd cache line
will be changing between most network transactions.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
index 468cb9048dc8..862041419635 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
@@ -208,15 +208,18 @@ enum ixgbe_ring_state_t {
         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 struct ixgbe_ring {
         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
+        struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
+        struct net_device *netdev;      /* netdev ring belongs to */
+        struct device *dev;             /* device for DMA mapping */
         void *desc;                     /* descriptor ring memory */
-        struct device *dev;             /* device for DMA mapping */
-        struct net_device *netdev;      /* netdev ring belongs to */
         union {
                 struct ixgbe_tx_buffer *tx_buffer_info;
                 struct ixgbe_rx_buffer *rx_buffer_info;
         };
         unsigned long state;
         u8 __iomem *tail;
+        dma_addr_t dma;                 /* phys. address of descriptor ring */
+        unsigned int size;              /* length in bytes */
 
         u16 count;                      /* amount of descriptors */
 
@@ -226,17 +229,17 @@ struct ixgbe_ring {
                                          * associated with this ring, which is
                                          * different for DCB and RSS modes
                                          */
+        u16 next_to_use;
+        u16 next_to_clean;
+
         union {
+                u16 next_to_alloc;
                 struct {
                         u8 atr_sample_rate;
                         u8 atr_count;
                 };
-                u16 next_to_alloc;
         };
 
-        u16 next_to_use;
-        u16 next_to_clean;
-
         u8 dcb_tc;
         struct ixgbe_queue_stats stats;
         struct u64_stats_sync syncp;
@@ -244,9 +247,6 @@ struct ixgbe_ring {
                 struct ixgbe_tx_queue_stats tx_stats;
                 struct ixgbe_rx_queue_stats rx_stats;
         };
-        unsigned int size;              /* length in bytes */
-        dma_addr_t dma;                 /* phys. address of descriptor ring */
-        struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 } ____cacheline_internodealigned_in_smp;
 
 enum ixgbe_ring_f_enum {